TPS62865, TPS62867
SLUSDN8 – MARCH 2021
TPS62865/TPS62867 2.4-V to 5.5-V Input, 4-A and 6-A Synchronous Step-Down
Converter in 1.5-mm × 2.5-mm QFN Package
1 Features
3 Description
•
•
•
•
•
•
•
The TPS62865 and TPS62867 devices are highfrequency synchronous step-down converters which
provide an efficient, flexible, and high power-density
solution. At medium to heavy loads, the converters
operate in PWM mode and automatically enter Power
Save Mode operation at light load to maintain high
efficiency over the entire load current range. The
devices can also be forced in PWM mode operation
to minimize output voltage ripple. Together with
its DCS-control architecture, excellent load transient
performance and tight output voltage accuracy are
achieved. The devices feature a Power Good signal
and an internal soft start circuit. The devices are able
to operate in 100% mode. For fault protection, the
devices incorporate a HICCUP short circuit protection
as well as a thermal shutdown.
•
•
•
•
•
•
•
•
•
•
•
DCS-Control topology for fast transient response
11-mΩ and 10.5-mΩ internal power MOSFETs
1% output voltage accuracy
4-µA operating quiescent current
2.4-V to 5.5-V input voltage range
0.6-V to VIN output voltage range
Fixed (selectable by external resistor) and
adjustable output voltage versions
2.4-MHz switching frequency
Forced PWM or power save mode
Output voltage discharge
100% duty cycle mode
Hiccup short-circuit protection
Power good indicator with window comparator
Thermal shutdown
Solution sizes down to 30 mm2 possible
Available in 1.5-mm × 2.5-mm QFN with 0.5-mm
pitch
Create a custom design using the TPS62865 with
the WEBENCH® Power Designer
Create a custom design using the TPS62867 with
the WEBENCH® Power Designer
2 Applications
•
•
•
•
•
•
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
QFN (9)
1.5 × 2.5 × 1 mm
TPS62865
TPS62867
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Core supply for FPGAs, CPUs, ASICs, or video
chipsets
Machine vision cameras
IP network cameras
Solid-state drives
Optical modules
Multifunction printers
L1
0.22 µH
VIN
2.4 V to 5.5 V
R3
C1, C2
2×10 µF
VIN
SW
EN
VOS
VOUT
0.9 V
L1
0.22 µH
VIN
2.4 V to 5.5 V
C3, C4
2×22 µF
R3
C1, C2
2×10 µF
VIN
SW
EN
VOS
PG
PG
FB
VSET/MODE
PGND
PG
VSET/MODE
R2
AGND
Typical Application Schematics - Adjustable
Output Voltage
C3, C4
2×22 µF
FB
R1
PG
VOUT
1.8 V
PGND
AGND
R4
133 k
Typical Application Schematics - Fixed Output
Voltage
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ....................................... 4
7.2 ESD Ratings .............................................................. 4
7.3 Recommended Operating Conditions ........................4
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................6
7.6 Typical Characteristics................................................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
10 Power Supply Recommendations..............................19
11 Layout........................................................................... 20
11.1 Layout Guidelines................................................... 20
11.2 Layout Example...................................................... 20
12 Device and Documentation Support..........................22
12.1 Device Support....................................................... 22
12.2 Documentation Support.......................................... 22
12.3 Support Resources................................................. 22
12.4 Trademarks............................................................. 22
12.5 Electrostatic Discharge Caution..............................22
12.6 Glossary..................................................................23
13 Mechanical, Packaging, and Orderable
Information.................................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
March 2021
*
Initial Release
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
5 Device Options
(1)
PART NUMBER(1)
OUTPUT CURRENT
TPS62865
4A
TPS62867
6A
For all available packages, see the orderable addendum at the end of the data sheet.
PGND
AGND
FB
VOS
6 Pin Configuration and Functions
1
9
8
2
7
4
5
6
PG
VSET/MODE
3
EN
VIN
SW
Not to scale
Figure 6-1. 9-Pin RQY QFN Package (Top View)
Table 6-1. Pin Functions
PIN
DESCRIPTION
NAME
NO.
AGND
1
Analog ground pin
FB
9
Feedback pin. For the fixed output voltage versions, the pin must be connected to the output directly.
VOS
8
Output voltage sense pin. This pin must be directly connected to the output capacitor.
PGND
2
Power ground pin
SW
7
Switch pin of the power stage
VIN
3
Power supply input voltage pin
EN
4
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables
the device. Do not leave floating.
VSET/MODE
6
Voltage Set pin
In fixed output voltage applications, connect a resistor between this pin and GND to set the output
voltage (see Table 8-2). After start-up, connect this pin to a high level to enable forced-PWM operation,
or to a low level to enable power-save mode.
In adjustable output voltage applications, connect this pin to a high level to enable forced-PWM
operation, or to a low level to enable power-save mode operation.
PG
5
Power-good open-drain output pin. The pullup resistor can be connected to voltages up to 5.5 V. If
unused, leave it floating.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
3
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
7 Specifications
7.1 Absolute Maximum Ratings
See (1)
MIN
Voltage(2)
VIN, EN, VOS, FB, PG, VSET/MODE
–0.3
6
SW (DC)
–0.3
VIN + 0.3
–2.5
10
SW (AC, less than 10
ISINK_PG
MAX
ns)(3)
Sink current at PG
UNIT
V
1
mA
TJ
Junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltage values are with respect to network ground terminal.
While switching
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
VIN
Supply Voltage Range
VOUT
SR
IOUT
TJ
(1)
4
NOM
MAX
2.4
5.5
Output Voltage Range
0.6
VIN
Slew rate at VIN(1)
–10
4
Output current, TPS62867
6
–40
V
V
mV/µs
Output current, TPS62865
Junction temperature
UNIT
125
A
°C
The falling slew rate of VIN must be limited if VIN goes below VUVLO.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
7.4 Thermal Information
TPS6286x
THERMAL
METRIC(1)
JEDEC 51-7
TPS62867EVM-121
9 PINS
9 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
90.9
60.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
68.2
n/a(2)
°C/W
°C/W
RθJB
Junction-to-board thermal resistance
25.0
n/a(2)
ΨJT
Junction-to-top characterization parameter
1.9
3.3
°C/W
ΨJB
Junction-to-board characterization parameter
24.7
31.5
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Not applicable to an EVM
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
5
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
7.5 Electrical Characteristics
TJ = –40°C to 125°C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
UNIT
SUPPLY
IQ
Quiescent current
EN = High, no load, device not switching
4
IQ_VOS
Operating quiescent current into VOS pin
EN = High, no load, device not switching,
VVOS = 1.8 V
8
ISD
Shutdown current
EN = Low, TJ = –40℃ to 85℃
VUVLO
Undervoltage lockout threshold
TJSD
µA
µA
0.24
1
µA
VIN rising
2.2
2.3
2.4
V
VIN falling
2.1
2.2
2.3
V
Thermal shutdown threshold
TJ rising
150
°C
Thermal shutdown hysteresis
TJ falling
20
°C
LOGIC INTERFACE
VIH
High-level input threshold voltage at EN
and VSET/MODE
VIL
Low-level input threshold voltage at
EN and VSET/MODE
IEN,LKG
Input leakage current into EN pin
0.84
V
0.4
V
0.01
0.1
µA
STARTUP, POWER GOOD
tDelay
Enable delay time
Time from EN high to device starts switching
249-kΩ resistor connected between VSET/MODE
and GND
420
700
1100
µs
tRamp
Output voltage ramp time
Time from device starts switching to power good
0.8
1
1.5
ms
VPG
Power good lower threshold
VVOS referenced to VOUT nominal
85%
91%
96%
Power good upper threshold
VVOS referenced to VOUT nominal
103%
111%
120%
VPG,OL
Low-level output voltage
Isink = 1 mA, PG pin version
tPG,DLY
Power good deglitch delay
Rising and falling edges
0.36
VOUT
Output voltage accuracy
Fixed voltage operation, FPWM, no load, TJ =
0°C to 85°C
–1%
Fixed voltage operation, FPWM, no load
–2%
VFB
Feedback voltage
Adjustable voltage operation
IFB,LKG
Input leakage into FB pin
IVOS,LKG
Input leakage current into VOS pin
34
V
µs
OUTPUT
RDIS
594
2%
600
606
mV
Adjustable voltage operation, VFB = 0.6 V
0.01
0.4
µA
Output discharge disabled, VVOS = 1.8 V
0.2
2.5
µA
Output discharge resistor at VOS pin
Load regulation
1%
VOUT = 0.9 V, FPWM
3.5
Ω
0.04
%/A
11
mΩ
POWER SWITCH
RDS(on)
High-side FET on-resistance
Low-side FET on-resistance
High-side FET forward current limit
ILIM
fSW
6
Low-side FET forward current limit
10.5
TPS62865
5
TPS62867
7
mΩ
5.5
6
7.7
8.5
TPS62865
4.5
A
A
A
TPS62867
6.5
A
Low-side FET negative current limit
TPS62865, TPS62867
–3
A
PWM switching frequency
IOUT = 1 A, VOUT = 0.9 V
2.4
MHz
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
7.6 Typical Characteristics
27.5
30
On-Resistance (milliohms)
25
22.5
20
17.5
15
12.5
2.5
3.0
3.5
4.0
4.5
Supply Voltage (V)
5.0
5.5
17.5
15
12.5
2.5
3.0
3.5
4.0
4.5
Supply Voltage (V)
5.0
5.5
6.0
Figure 7-2. Low-Side FET On-Resistance
10
1.0
TJ = –40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
8
6
4
2
TJ = –40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
0.8
Shutdown Current (uA)
Quiescent Current – Non-Switching (uA)
20
7.5
2.0
6.0
Figure 7-1. High-Side FET On-Resistance
0
2.0
22.5
10
10
7.5
2.0
TJ = –40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
25
On-Resistance (milliohms)
TJ = –40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
27.5
0.6
0.4
0.2
2.5
3.0
3.5
4.0
4.5
Supply Voltage (V)
5.0
Figure 7-3. Quiescent Current
5.5
6.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
Supply Voltage (V)
5.0
5.5
6.0
Figure 7-4. Shutdown Current
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
7
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
8 Detailed Description
8.1 Overview
The TPS62865 and TPS62867 synchronous step-down converters use the DCS-Control (Direct Control with
Seamless transition into Power Save Mode) topology. This is an advanced regulation topology that combines the
advantages of hysteretic and current-mode control schemes.
The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions
and in Power Save Mode at light load currents. In PWM mode, the converter operates with its 2.4-MHz nominal
switching frequency, having a controlled frequency variation over the input voltage range. Since DCS-Control
supports both operation modes (PWM and PFM) within a single building block, the transition from PWM mode to
Power Save Mode is seamless and does not affect on the output voltage. The devices offer both excellent DC
voltage and superior load transient regulation combined with very low output voltage ripple.
8.2 Functional Block Diagram
PG
91%
VIN
+
–
Control Logic
Reference Selection
UVLO
Thermal Shutdown
Startup Ramp
EN
VSET/MODE
34-µs
Deglitch
VX
+
111%
AGND
–
HS-FET Forward
Current Limit
VSW
VIN
TON
VSW
Direct Control
&
Compensation
–
+
FB
Vref
VX
+
EA
–
SW
Gate
Driver
Modulator
Comparator
LS-FET
Forward Current Limit
Zero Current Detect
Negative Current Limit
VOS
k
HICCUP
k = 1, 0.5, 0.25
PGND
RDIS
PGND
AGND
AGND
AGND
8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the device enters Power Save Mode (PSM) operation. PSM occurs when the
inductor current becomes discontinuous, which is when it reaches 0 A during a switching cycle. Power Save
Mode is based on a fixed on-time architecture, as shown in Equation 1.
t ON =
8
VOUT
× 416 ns
VIN
(1)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized
by increasing the output capacitor or inductor value.
When VIN decreases to typically 15% above VOUT, the TP6286x does enter Power Save Mode, regardless of the
load current. The device maintains output regulation in PWM mode.
8.3.2 Forced PWM Mode
Connecting the VSET/MODE pin to logic high after the start-up, the device switches at 2.4 MHz, even with
a light load. This reduces the output voltage ripple and allows simple filtering of the switching frequency for
noise-sensitive applications. Efficiency at light load is lower in Forced PWM mode (FPWM).
8.3.3 100% Duty Cycle Mode Operation
There is no limitation for small duty cycles since even at very low duty cycles, the switching frequency is reduced
as needed to always ensure a proper regulation.
If the output voltage level comes close to the input voltage, the device enters 100% mode. While the high-side
switch is constantly turned on, the low-side switch is switched off. The difference between VIN and VOUT is
determined by the voltage drop across the high-side MOSFET and the DC resistance of the inductor. The
minimum VIN that is needed to maintain a specific VOUT value is estimated as:
VIN ,MIN = VOUT + (R DS (ON ) + R L )IOUT ,MAX
(2)
where
•
•
•
•
VIN,MIN is the minimum input voltage to maintain an output voltage
IOUT,MAX is the maximum output current
RDS(on) is the high-side FET ON-resistance
RL is the inductor ohmic resistance (DCR)
8.3.4 Soft Start
After enabling the device, there is a 700-µs (typical) enable delay (tdelay) before the device starts switching. After
the enable delay, an internal soft start-up circuitry ramps up the output voltage with a period of 1 ms (tRamp).
This avoids excessive inrush current and creates a smooth output voltage rise-slope. It also prevents excessive
voltage drops of primary cells and rechargeable batteries with high internal impedance. The device is able to
start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the output voltage to its
nominal value.
VIN
EN
VOUT
ttDelayt
ttRampt
ttStartupt
Figure 8-1. Start-up Sequence
8.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, cycle by cycle, the
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
9
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
high-side MOSFET is turned off and the low-side MOSFET is turned on, while the inductor current ramps down
to the low-side MOSFET current limit.
When the high-side MOSFET current limit is triggered 32 times, the device stops switching. The device then
automatically re-starts with an internal soft start-up after a typical delay time of 128 µs has passed. This is
named HICCUP short-circuit protection. The device repeats this mode until the high load condition disappears.
8.3.6 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, undervoltage lockout (UVLO) is implemented when
the input voltage is lower than VUVLO. The device stops switching and the output voltage discharge is active
when the device is in UVLO. When the input voltage recovers, the device automatically returns to operation with
an internal soft start-up.
8.3.7 Thermal Shutdown
When the junction temperature exceeds TJSD, the device goes into thermal shutdown, stops switching, and
activates the output voltage discharge. When the device temperature falls below the threshold by the hysteresis,
the device returns to normal operation automatically with an internal soft start-up. During thermal shutdown, the
internal register values are kept.
8.4 Device Functional Modes
8.4.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic high. In shutdown mode (EN = low), the internal power
switches and the entire control circuitry are turned off. An internal switch smoothly discharges the output through
the VOS pin in shutdown mode. Do not leave the EN pin floating.
8.4.2 Power Good (PG)
The device has an open-drain power-good pin, which is specified to sink up to 1 mA. The power-good output
requires a pullup resistor connecting to any voltage rail less than 5.5 V. The PG has a deglitch delay of 34 µs.
The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.
Leave the PG pin unconnected when not used.
Table 8-1. PG Function Table
DEVICE CONDITIONS
PG PIN
0.9 × VOUT_NOM ≤ VVOS ≤ 1.1 × VOUT_NOM
Hi-Z
VVOS < 0.9 × VOUT_NOM or VVOS > 1.1 × VOUT_NOM
Low
Shutdown
EN = low
Low
Thermal shutdown
TJ > TJSD
Low
UVLO
1.8 V < VIN < VUVLO
Power supply removal
VIN < 1.8 V
Enable
Low
Undefined
8.4.3 Voltage Setting and Mode Selection (VSET/MODE)
During the enable delay (tDelay), the device configuration is set by an external resistor connected to the VSET/
MODE pin through an internal R2D (resistor to digital) converter. Table 8-2 shows the options.
The R2D converter has an internal current source that applies current through the external resistor and an
internal ADC that reads back the resulting voltage level. Depending on the level, the output voltage is set. Once
this R2D conversion is finished, the current source is turned off to avoid current flowing through the external
resistor. Ensure that there is no additional current path or capacitance greater than 30 pF from this pin to GND
during R2D conversion. Otherwise, a false value is set.
10
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
Table 8-2. Voltage Selection Table
RESISTOR (E96 SERIES, ±1% ACCURACY) AT VSET/MODE PIN
FIXED OR ADJUSTABLE OUTPUT VOLTAGE
249 kΩ or logic high
adjustable
205 kΩ
3.30 V
162 kΩ
2.50 V
133 kΩ
1.80 V
105 kΩ
1.50 V
86.6 kΩ
reserved
68.1 kΩ
1.35 V
56.2 kΩ
1.20 V
44.2 kΩ
1.10 V
36.5 kΩ
1.05 V
28.7 kΩ
1.00 V
23.7 kΩ
0.95 V
18.7 kΩ
0.90 V
15.4 kΩ
0.85 V
12.1 kΩ
0.80 V
10 kΩ or logic low
adjustable
When the device is set as a fixed output voltage converter, then FB pin must be connected to the output directly.
Refer to Figure 8-2.
L1
0.22 µH
VIN
2.4 V to 5.5 V
R3
PG
C1, C2
2×10 µF
VIN
SW
EN
VOS
VOUT
1.8 V
C3, C4
2×22 µF
FB
PG
VSET/MODE
PGND
AGND
R4
133 k
Figure 8-2. Fixed Start-up Output Voltage Application Circuit
After the start-up period (tStartup), a different operation mode can be selected. When VSET/MODE is high, the
device operates in forced PWM mode, otherwise the device operates in power save mode.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
11
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Application
L1
0.22 µH
VIN
2.4 V to 5.5 V
R3
C1, C2
2×10 µF
VIN
SW
EN
VOS
VOUT
0.9 V
C3, C4
2×22 µF
R1
PG
PG
FB
VSET/MODE
PGND
R2
AGND
Figure 9-1. Typical Application
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-1 as the input parameters.
Table 9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.4 V to 5.5 V
Output voltage
0.9 V
Maximum output current
6A
Table 9-2 lists the components used for the example.
Table 9-2. List of Components
REFERENCE
(1)
12
DESCRIPTION
MANUFACTURER(1)
C1, C2
10 μF, ceramic capacitor, 10 V, X7R, size 0603,GRM188Z71A106KA73
Murata
C3, C4
22 µF, ceramic capacitor, 6.3 V, X7R, size 0805, GRM21BZ70J226ME44
Murata
L1
0.22 µH, power inductor, XAL4020-221ME (12 A, 5.81 mΩ)
Coilcraft
R1
Depending on the output voltage, chip resistor, 1/16 W, 1%, size 0402
Std
R2
100 kΩ, chip resistor, 1/16 W, 1%, size 0402
Std
R3
100 kΩ, chip resistor, 1/16 W, 1%, size 0402
Std
See the Third-party Products disclaimer.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62865 device with the WEBENCH® Power Designer.
Click here to create a custom design using the TPS62867 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Setting The Output Voltage
The output voltage is set by an external resistor divider according to Equation 3:
(3)
R2 must not be higher than 200 kΩ to achieve high efficiency at light load while providing acceptable noise
sensitivity.
For the fixed output versions, connect the FB pin to the output. R1 and R2 are not needed.
9.2.2.3 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify this process, Table 9-3
outlines possible inductor and capacitor value combinations for most applications. Checked cells represent
combinations that are proven for stability by simulation and lab testing. Further combinations must be checked
for each individual application.
Table 9-3. Matrix of Output Capacitor and Inductor Combinations
NOMINAL L [µH](2)
0.22
(1)
(2)
(3)
NOMINAL COUT [µF](3)
10
2 × 22 or 47
3 × 22
150
+(1)
+
+
This LC combination is the standard value and recommended for most applications.
Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
9.2.2.4 Inductor Selection
The main parameter for the inductor selection is the inductor value, then the saturation current of the inductor. To
calculate the maximum inductor current under static load conditions, Equation 4 is given.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
13
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
(4)
where
•
•
•
•
IOUT,MAX is the maximum output current
ΔIL is the inductor current ripple
fSW is the switching frequency
L is the inductor value
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher
than IL,MAX. In addition, DC resistance and size must also be taken into account when selecting an appropriate
inductor. Table 9-4 lists recommended inductors.
Table 9-4. List of Recommended Inductors
INDUCTANCE
[µH](1)
CURRENT RATING
[A]
DIMENSIONS
[L × W × H mm]
DC RESISTANCE
[mΩ]
PART NUMBER
0.22
18.7
4×4×2
5.81
Coilcraft, XAL4020-221ME
0.24
6.6
2 × 1.6 × 1.2
13
Murata, DFE201612E-R24M
(1)
See the Third-party Products disclaimer.
9.2.2.5 Capacitor Selection
The input capacitor is the low-impedance energy source for the convertersm which helps to provide stable
operation. A low-ESR multilayer ceramic capacitor is recommended for the best filtering and must be placed
between VIN and GND as close as possible to those pins. For most applications, 8 μF of effective 1 capacitance
is sufficient, however, a larger value reduces input current ripple.
The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends
using X7R or X5R dielectrics. The recommended typical output capacitor value is 30 μF of effective 1
capacitance. This capacitance can vary over a wide range as outlined in the output filter selection table.
1
14
The effective capacitance is the capacitance after tolerance, temperature, and DC bias effects have been considered.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
9.2.3 Application Curves
VIN = 5.0 V, VOUT = 0.9 V, TA = 25 °C, BOM = Table 9-2, unless otherwise noted.
100
0.610
90
0.605
+1%
80
Efficiency (%)
60
50
40
VIN = 2.4 V – FPWM
VIN = 2.4 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
30
20
10
0
1m
10m
100m
Output Current (A)
1
Output Voltage (V)
0.600
70
–1%
0.595
0.590
0.585
VIN = 2.5 V – FPWM
VIN = 2.5 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
0.580
0.575
0.570
1m
10
10m
VOUT = 0.6 V
100m
Output Current (A)
1
10
VOUT = 0.6 V
Figure 9-2. Efficiency
Figure 9-3. Load Regulation
100
0.92
90
0.91
+1%
80
Efficiency (%)
60
50
40
VIN = 2.4 V – FPWM
VIN = 2.4 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
30
20
10
0
1m
10m
100m
Output Current (A)
1
Output Voltage (V)
0.90
70
–1%
0.89
0.88
0.87
VIN = 2.5 V – FPWM
VIN = 2.5 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
0.86
0.85
0.84
1m
10
10m
VOUT = 0.9 V
100m
Output Current (A)
1
10
VOUT = 0.9 V
Figure 9-4. Efficiency
Figure 9-5. Load Regulation
100
1.22
90
1.21
+1%
80
Efficiency (%)
60
50
40
VIN = 2.4 V – FPWM
VIN = 2.4 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
30
20
10
0
1m
10m
100m
Output Current (A)
1
10
Output Voltage (V)
1.20
70
–1%
1.19
1.18
1.17
VIN = 2.5 V – FPWM
VIN = 2.5 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
1.16
1.15
1.14
1m
10m
VOUT = 1.2 V
Figure 9-6. Efficiency
100m
Output Current (A)
1
10
VOUT = 1.2 V
Figure 9-7. Load Regulation
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
15
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
100
1.83
90
1.82
80
1.81
70
1.80
60
50
40
VIN = 2.4 V – FPWM
VIN = 2.4 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
30
20
10
0
1m
10m
100m
Output Current (A)
1
Output Voltage (V)
Efficiency (%)
9.2.3 Application Curves (continued)
+1%
1.79
–1%
1.78
1.77
VIN = 2.5 V – FPWM
VIN = 2.5 V – PSM
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
1.76
1.75
1.74
1.73
1m
10
10m
VOUT = 1.8 V
2.54
80
2.52
Efficiency (%)
70
60
50
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 3.7 V – FPWM
VIN = 3.7 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
10
0
1m
10m
100m
Output Current (A)
1
Output Voltage (V)
2.56
90
20
+1%
2.50
–1%
2.48
2.46
VIN = 3.3 V – FPWM
VIN = 3.3 V – PSM
VIN = 3.7 V – FPWM
VIN = 3.7 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
2.44
2.42
2.40
2.38
1m
10
10m
VOUT = 2.5 V
3.36
90
3.34
80
3.32
Output Voltage (V)
Efficiency (%)
70
60
50
40
30
0
1m
VIN = 3.7 V – FPWM
VIN = 3.7 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
10m
10
100m
Output Current (A)
1
10
+1%
3.30
3.28
–1%
3.26
3.24
VIN = 3.7 V – FPWM
VIN = 3.7 V – PSM
VIN = 5.0 V – FPWM
VIN = 5.0 V – PSM
3.22
3.20
3.18
1m
10m
VOUT = 3.3 V
Figure 9-12. Efficiency
16
1
Figure 9-11. Load Regulation
100
10
100m
Output Current (A)
VOUT = 2.5 V
Figure 9-10. Efficiency
20
10
Figure 9-9. Load Regulation
100
30
1
VOUT = 1.8 V
Figure 9-8. Efficiency
40
100m
Output Current (A)
100m
Output Current (A)
1
10
VOUT = 3.3 V
Figure 9-13. Load Regulation
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
3.0
3.0
2.5
2.5
Switching Frequency (MHz)
Switching Frequency (MHz)
9.2.3 Application Curves (continued)
2.0
1.5
VOUT = 0.6 V – FPWM
VOUT = 0.6 V – PSM
VOUT = 1.8 V – FPWM
VOUT = 1.8 V – PSM
VOUT = 3.3 V – FPWM
VOUT = 3.3 V – PSM
1.0
0.5
0.0
0
1
2
3
4
Output Current (A)
5
6
2.0
1.5
1.0
VOUT = 0.6 V
VOUT = 1.2 V
VOUT = 3.3 V
0.5
0.0
2.5
3.0
VIN = 5 V
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
IOUT = 1 A
Figure 9-14. Switching Frequency
Figure 9-15. Switching Frequency
IOUT = 6 A
IOUT = 0.1 A
Figure 9-16. PWM Operation
Figure 9-17. PSM Operation
IOUT = 0.1 A
No Load
Figure 9-18. Forced-PWM Operation
Figure 9-19. Startup with No-Load
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
17
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
9.2.3 Application Curves (continued)
IOUT = 0.6 A to 5.4 A
IOUT = 0.6 A to 5.4 A
Figure 9-20. Load Transient - PWM Operation
Figure 9-21. Load Transient - PSM Operation
IOUT = 1 A
Figure 9-22. HICCUP Short Circuit Protection
18
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
19
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
11 Layout
11.1 Layout Guidelines
A proper layout is critical for the operation of any switched mode power supply, especially at high switching
frequencies. The PCB layout of the TPS62865 and TPS62867 devices requires careful attention to ensure
best performance. A poor layout can lead to issues like bad line and load regulation, instability, increased EMI
radiation, and noise sensitivity. Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter
technical brief for a detailed discussion of general best practices. The following are specific recommendations for
the TPS62865 and TPS62867:
•
•
•
•
•
•
•
The input capacitor or capacitors must be placed as close as possible to the VIN and PGND pins of the
device. This is the most critical component placement. Route the input capacitor or capacitors directly to the
VIN and PGND pins, avoiding vias.
Place the output inductor close to the SW pins. Minimize the copper area at the switch node.
Place the output capacitor or capacitors ground close to the PGND pin and route it directly, avoiding vias.
Minimize the length of the connection from the inductor to the output capacitor. Connect the VOS pin directly
to the output capacitor.
Sensitive traces, such as the connections to the VOS, FB, and VSEL pins, must be connected with short
traces and be routed away from any noise source, such as the SW pin.
Make the connections from the input voltage of the system and the connection to the load as wide as
possible to minimize voltage drops.
Have a solid ground plane between PGND and the input and output capacitor ground connections.
The sensitive signal ground connections for the feedback voltage divider must be connected to a separate
signal ground trace.
C4
C3
11.2 Layout Example
Solution
Size 63mm²
C2
C1
R1
R2
VOUT
VOS
FB
AGND
GND
SW
R4
EN
PG
VSEL
VIN
VIN
L1
GND
Figure 11-1. Layout Example
11.2.1 Thermal Considerations
After the layout recommendations for component placement and routing have been followed, the PCB design
must focus on thermal performance. Thermal design is important and must be considered to remove the heat
generated in the device during operation. The device junction temperature must stay below its maximum rated
temperature of 125°C for correct operation.
Use wide traces and planes, especially to the PGND, VIN, and VOUT pins, and use vias to internal planes to
improve the power dissipation capability of the design. If the application allows it, use airflow in the system to
further improve cooling.
20
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
The Thermal Information table provides the thermal parameters of the device and its package based on the
JEDEC standard 51-7. See the Semiconductor and IC Package Thermal Metrics application report for a detailed
explanation of each parameter. In addition to the JEDEC standard, the thermal information table also contains
the thermal parameters of the EVM. The EVM better reflects a real-world PCB design with thicker traces
connecting to the device.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
21
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62865 device with the WEBENCH® Power Designer.
Click here to create a custom design using the TPS62867 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
application report
Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® are registered trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
22
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
TPS62865, TPS62867
www.ti.com
SLUSDN8 – MARCH 2021
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62865 TPS62867
23
PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62865RQYR
ACTIVE
VQFN-HR
RQY
9
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2EAH
TPS62867RQYR
ACTIVE
VQFN-HR
RQY
9
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2DWH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
