TPS629211-Q1
SLVSGD0A – MARCH 2022 – REVISED MARCH 2023
TPS629211-Q1 1-A, 3-V to 10-V Automotive Low IQ Buck Converter
1 Features
3 Description
•
The automotive-qualified TPS629211-Q1 device is a
highly efficient, small, and highly flexible synchronous
step-down DC-DC converter that is easy to use. A
wide 3-V to 10-V input voltage range supports a wide
variety of systems powered from either 9-V, 5-V, or
3.3-V supply rails, or single-cell or multi-cell Li-Ion
batteries. The TPS629211-Q1 can be configured to
run at either 2.5 MHz or 1 MHz in a forced PWM
mode or a variable frequency (auto PFM) mode. In
auto PFM mode, the device automatically transitions
to power save mode at light loads to maintain high
efficiency. The low 4-µA typical quiescent current also
provides high efficiency down to the smallest loads.
TI's automatic efficiency enhancement (AEE) mode
holds a high conversion efficiency through the whole
operation range without the need of using different
inductors by automatically adjusting the switching
frequency based on input and output voltages. In
addition to selecting the switching frequency behavior,
the MODE/S-CONF input pin can also be used to
select between different combinations of external and
internal feedback dividers and enabling and disabling
the output voltage discharge capability. In the internal
feedback configuration, a resistor between the FB/
VSET pin and GND can be used to select between
18 different output voltage options (see Table 8-2).
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 Applications
•
•
•
•
Advanced driver assistance systems (ADAS)
Automotive infotainment and cluster
Vehicle body electronics and lighting
Hybrid, electric and powertrain systems
VIN
3 V to 10 V
2.2 µH
VIN
Package Information
(1)
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
TPS629211-Q1
DRL (SOT-5X3, 8)
1.60 mm × 2.10 mm
(including pins)
TPS629211-Q1
DYC (SOT-5X3, 8)
1.60 mm × 2.10 mm
(including pins)
For all available packages, see the orderable addendum at
the end of the data sheet.
100
VOUT
0.4 V to 5.5 V
90
80
SW
70
4.7 F
22 F
EN
VOS
FB/
VSET
Efficiency (%)
•
AEC-Q100 qualified for automotive applications:
– –40°C to 150°C operating junction temp range
– Level 2 device HBM ESD classification
– Level C4B CDM ESD classification
Functional Safety-Capable
– Documentation available to aid functional safety
system design
High-efficiency DCS-Control topology
– Internal compensation
– Seamless PWM/PFM transition
4-µA typical low quiescent current
Output current up to 1 A
250-mΩ high side, 85-mΩ low side RDSON
±1% output voltage accuracy
Configurable output voltage options:
– 0.6-V to 5.5-V VFB external divider:
– VSET internal divider:
• 18 options between 0.4 V and 5.5 V
Flexibility through the MODE/S-CONF pin
– 2.5-MHz or 1.0-MHz switching frequency
– Forced PWM or auto (PFM) power save mode
with dynamic mode change option
– Output discharge on, off
No external bootstrap capacitor required
Overcurrent and overtemperature protection
100% duty cycle mode
Precise enable input
Power-good output
Pin-to-pin compatible with the TPS629210-Q1,
TPS629206-Q1, and TPS629203-Q1 devices
0.5-mm pitch, 8-pin SOT-5X3 package
60
50
40
30
20
MODE/
S-CONF
PG
GND
Simplified Schematic
VIN = 6V
VIN = 9V
10
0
1E-5
0.0001
0.001
0.01
Iout (A)
0.1 0.2 0.5 1
Efficiency Versus Output Current
VOUT = 3.3 V at 2.5-MHz Auto PFM/PWM
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS629211-Q1
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SLVSGD0A – MARCH 2022 – REVISED MARCH 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Thermal Information - DYC Package.......................... 6
7.6 Electrical Characteristics.............................................6
7.7 Typical Characteristics................................................ 8
8 Detailed Description...................................................... 11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................16
9 Application and Implementation.................................. 20
9.1 Application Information............................................. 20
9.2 Typical Application.................................................... 20
9.3 System Examples..................................................... 38
9.4 Power Supply Recommendations.............................39
9.5 Layout....................................................................... 39
10 Device and Documentation Support..........................42
10.1 Device Support....................................................... 42
10.2 Documentation Support.......................................... 42
10.3 Receiving Notification of Documentation Updates..42
10.4 Support Resources................................................. 42
10.5 Trademarks............................................................. 42
10.6 Electrostatic Discharge Caution..............................43
10.7 Glossary..................................................................43
11 Mechanical, Packaging, and Orderable
Information.................................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (March 2022) to Revision A (March 2023)
Page
• Added the DYC package.................................................................................................................................... 1
• Added the DYC package.................................................................................................................................... 3
• Added the DYC package.................................................................................................................................... 3
• Added the DYC package.................................................................................................................................. 40
2
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5 Device Comparison Table
Device Number
Output Current
TPS629203-Q1
0 A – 0.3 A
TPS629206-Q1
0 A – 0.6 A
TPS629210-Q1
0A–1A
TPS629211-Q1
0A–1A
Input Voltage
Operating
Temperature
Range
Switching
Frequency
PWM Mode
VO Adjust
3 V – 17 V
–40°C to 150°C
Selectable 1-MHz
or 2.5-MHz options
Selectable auto
PWM/PFM or
forced PWM
Externally
programmable or
18 internal options
Selectable auto
PWM/PFM or
forced PWM
Externally
programmable or
18 internal options
3 V – 10 V
–40°C to 150°C
Selectable 1-MHz
or 2.5-MHz options
Package
Options
DRL
DRL and DYC
DRL and DYC
MO D
E
S - CO /
NF
EN
VIN
GND
8
7
6
5
1
2
3
4
FB/
V S ET
PG
V OS
SW
6 Pin Configuration and Functions
Figure 6-1. TPS629211-Q1 8-Pin DRL SOT-5X3 Pinout (TOP)
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EN
VIN
GND
8
7
6
5
1
2
3
4
PG
VOS
SW
FB/
VSET
MOD
E
S-CO /
NF
SLVSGD0A – MARCH 2022 – REVISED MARCH 2023
Figure 6-2. TPS629211-Q1 8-Pin DYC SOT-5X3 Pinout (TOP)
Table 6-1. Pin Functions
Pin
Name
NO.
I/O
Description
Dependent upon device configuration (see Section 8.3.1)
4
•
FB: Voltage feedback input. Connect a resistive output voltage divider to this pin.
•
VSET: Output voltage setting pin. Connect a resistor to GND to choose the output voltage
according to Table 8-2.
FB/VSET
1
I
PG
2
O
Open-drain power-good output
VOS
3
I
Output voltage sense pin. Connect directly to the positive pin of the output capacitor.
SW
4
Switch pin of the converter. Connected to the internal power switches
GND
5
Ground pin
VIN
6
I
Power supply input. Make sure the input capacitor is connected as close as possible between
the VIN pin and GND.
EN
7
I
Enable/disable pin including a threshold comparator. Connect to logic low to disable the device.
Pull high to enable the device. Do not leave this pin unconnected.
MODE/S-CONF
8
I
Device mode selection (auto PFM/PWM or forced PWM operation) and Smart-CONFIG pin.
Connect a resistor to configure the device according to Table 8-1.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Voltage(2)
VIN, EN, PG, MODE/S-CONF
-0.3
12
V
Voltage(2)
SW(3)
-0.3
VIN + 0.3
V
-3.0
17
V
-0.3
6
V
10
mA
-65
150
°C
Voltage(2)
SW (AC, less than
Voltage(2)
FB/VSET, VOS
Current
PG
Tstg
Storage temperature
(1)
(2)
(3)
10ns)(3)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltage values are with respect to network ground terminal.
While switching.
7.2 ESD Ratings
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
V(ESD)
Electrostatic discharge
Charged device model (CDM), per AEC
Q100-011CDM ESD classification level C4B
(1)
VALUE
UNIT
±2000
V
±750
V
AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
VI
Input voltage range
3.0
VO
Output voltage range
0.4
CI
Effective input capacitance
CO
Effective output capacitance(1)
L
Output inductance(2)
IOUT
Output current
ISINK_PG
Sink current at PG-Pin
TJ
Junction temperature (5)
(1)
(2)
(3)
(4)
(5)
NOM
MAX
10
5.5
3
4.7
UNIT
V
V
µF
10
22
100
µF
1.0(3)
2.2
4.7(4)
µH
0
-40
1
A
1
mA
150
°C
This is for capacitors directly at the output of the device. More capacitance is allowed if there is a series resistance associated to the
capacitor.
Nominal inductance value.
Not recommended for 1 MHz operation
Larger values of inductance may be used to reduce the ripple current, but they may have a negative impact on efficiency and the
overall transient response.
Operating lifetime is derated at junction temperatures greater than 150°C.
7.4 Thermal Information
TPS629211-Q1
THERMAL METRIC(1)
SOT583 8-Pin (DRL)
JEDEC PCB
UNIT
TPS6292xx EVM
RθJA
Junction-to-ambient thermal resistance
120
60
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45
n/a
°C/W
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TPS629211-Q1
THERMAL METRIC(1)
UNIT
SOT583 8-Pin (DRL)
JEDEC PCB
TPS6292xx EVM
RθJB
Junction-to-board thermal resistance
25
n/a
°C/W
ΨJT
Junction-to-top characterization parameter
1
n/a
°C/W
ΨJB
Junction-to-board characterization parameter
20
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information - DYC Package
TPS629211-Q1
THERMAL
METRIC(1)
SOT583 8-Pin (DYC)
JEDEC PCB
UNIT
TPS6292xx DYC EVM
RθJA
Junction-to-ambient thermal resistance
105
55
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45
n/a
°C/W
RθJB
Junction-to-board thermal resistance
22
n/a
°C/W
ΨJT
Junction-to-top characterization parameter
1
n/a
°C/W
ΨJB
Junction-to-board characterization parameter
18
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Electrical Characteristics
VI = 3 V to 10 V, TJ = -40 °C to +150 °C , Typical values at VI = 6 V and TA = 25 °C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Operating Quiescent Current, (Power
Save Mode)
Iout = 0 mA, device not switching
4
µA
IQ;PWM
Operating Quiescent Current (PWM
Mode)
VIN = 6V, VOUT=1.2V; Iout = 0
mA, device switching
5
mA
ISD
Shutdown current into VIN pin
EN = 0 V
0.25
3
µA
Under Voltage Lock-Out
VIN rising
2.85
2.95
3.0
V
Under Voltage Lock-Out
VIN falling
2.65
2.75
2.85
VUVLO
VUVLO
Under Voltage Lock-Out Hysteresis
200
V
mV
CONTROL & INTERFACE
6
ILKG
EN Input leakage current
EN=VIN
3
VIH;MODE
High-Level Input Voltage at MODE/SCONF Pin
VIL;MODE
Low-level input voltage at MODE/
S_CONF Pin
VIH
High-level input voltage at EN-Pin
0.97
VIL
Low-level input voltage at EN-Pin
0.87
VPG
Power good threshold
VFB rising, referenced to VFB nominal
VFB falling, referenced to VFB nominal
VPG_HYS
Power good threshold hysteresis
tPG,DLY
Power good delay time
tPG,DLY
Power good pull down resistance
VPG,OL
Low-level output voltage at PG pin
ISINK = 1 mA
IPG,LKG
Input leakage current into PG pin
VPG = 5 V
300
1.0
hysteresis
V
0.15
V
1.0
1.03
V
0.9
0.93
V
93%
96%
99%
89%
93%
96%
3%
32
µs
10
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0.01
Ω
0.1
V
1
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7.6 Electrical Characteristics (continued)
VI = 3 V to 10 V, TJ = -40 °C to +150 °C , Typical values at VI = 6 V and TA = 25 °C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SWITCHES
RDS;ON
ILIM
ILIM;SINK
High-side FET on resistance
250
Low-side FET on resistance
85
mΩ
High-side FET current limit
1.5
1.8
2.1
A
Low-side FET current limit
1.3
1.6
1.9
A
1
1.2
A
Low-side FET sink current limit
0.8
Thermal Shutdown Threshold
TJ rising
170
Thermal Shutdown Hysteresis
TJ falling
20
fSW
Switching frequency
2.5-MHz selection (FPWM Mode)
2.5
MHz
fSW
Switching frequency
1.0-MHz selection (FPWM Mode)
1.0
MHz
TON(MIN)
Minimum On-time
40
ns
ILKG;SW
Leakage current into SW-Pin
EN = 0V, VSW = VOS = 5.5V
VO
Output Voltage Regulation
VSET Configuration selected, 0°C ≤ TJ
≤ 85°C
VO
Output Voltage Regulation
VO
TSD
0.1
°C
5
µA
OUTPUT
-1%
+1%
VSET Configuration selected, -40°C ≤
TJ ≤ 150°C (DRL Package)
-1.4%
+1.1%
Output Voltage Regulation
VSET Configuration selected, VOUT ≤
3.8V, -40°C ≤ TJ ≤ 150°C
(DYC Package)
-1.4%
+1.1%
VO
Output Voltage Regulation
VSET Configuration selected, VOUT ≥
5.0V, -40°C ≤ TJ ≤ 150°C
(DYC Package)
-1.6%
+1.1%
VFB
Feedback Regulation Voltage
Adjustable Configuration selected
VFB
Feedback Voltage Regulation
FB-Option selected, 0°C ≤ TJ ≤ 85°C
VFB
Feedback Voltage Regulation
FB-Option selected, -40°C ≤ TJ ≤
150°C
IFB
Input leakage current into FB pin
Adjustable configuration, VFB = 0.6 V
1
100
nA
Start-up delay time
IO = 0 mA, time from EN rising
edge until start switching, External FB
Configuration selected
700
1500
µs
Start-up delay time
IO = 0 mA, time from EN rising
edge until start switching, VSET
Configuration selected
1000
1800
µs
TSS
Soft-Start time
IO = 0 mA after Tdelay, from 1st
switching pulse until target VO
600
700
µs
RDISCH
Active Discharge Resistance
Discharge = ON - Option Selected, EN
= LOW,
7.5
20
Ω
Tdelay
0.6
V
-0.75%
+0.75%
-1.2%
+0.75%
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7.7 Typical Characteristics
1
9
0.9
8
0.8
Shutdown Current (A)
10
IVIN (A)
7
6
5
4
3
2
0
-40
-20
0
20
40
60
80 100
Temperature (C)
120
140
0.7
0.6
0.5
0.4
0.3
0.2
Vin = 3V
Vin = 6V
Vin = 9V
1
Vin = 3V
Vin = 6V
Vin = 9V
0.1
0
-40
160
-20
0
20
40
60
80 100
Temperature (C)
120
140
160
Figure 7-2. Typical Shutdown Current vs Temperature
Measured with the device not switching
Figure 7-1. Typical Quiescent Current vs Temperature
0.2
Vin = 3V
Vin = 6V
Vin = 9V
0.15
0.1
VFB Accuracy (%)
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
-40
-20
0
20
40
60
80 100
Temperature (C)
120
140
160
VOUT = 5.0 V
Figure 7-3. Output Voltage Accuracy – External Feedback
Figure 7-4. Output Voltage Accuracy – VSET Selected
1.81
3.315
Vin = 6V
Vin = 9V
3.309
1.806
3.306
1.804
3.303
1.802
3.3
3.297
1.8
1.798
3.294
1.796
3.291
1.794
3.288
1.792
3.285
-40
-20
0
20
40
60
80 100
Temperature (C)
120
140
160
Vin = 3V
Vin = 6V
Vin = 9V
1.808
Vout (V)
Vout (V)
3.312
1.79
-40
-20
VOUT = 3.3 V
20
40
60
80 100
Temperature (C)
120
140
160
VOUT = 1.8 V
Figure 7-5. Output Voltage Accuracy – VSET Selected
8
0
Figure 7-6. Output Voltage Accuracy – VSET Selected
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7.7 Typical Characteristics (continued)
1.206
0.603
Vin = 3V
Vin = 6V
Vin = 9V
1.204
1.202
0.601
1.2
Vout (V)
Vout (V)
Vin = 3V
Vin = 6V
Vin = 9V
0.602
1.198
1.196
0.6
0.599
0.598
1.194
0.597
1.192
1.19
-40
-20
0
20
40
60
80 100
Temperature (C)
120
140
0.596
-40
160
-20
0
20
VOUT = 1.2 V
140
Figure 7-7. Output Voltage Accuracy – VSET Selected
Figure 7-8. Output Voltage Accuracy – VSET Selected
2.8
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1
0.99
0.98
0.97
0.96
0.95
0.94
-40
2.6
Switching Frequency (MHz)
Switching Frequency (MHz)
120
2.5
2.4
2.3
2.2
2.1
2
Vin = 3V
Vin = 6V
Vin = 9V
1.9
1.8
-40
-20
0
20
VOUT = 1.2 V
40
60
80 100
Temperature (C)
160
VOUT = 0.6 V
2.7
120
FSW = 2.5 MHz
FPWM
140
160
Vin = 3V
Vin = 6V
Vin = 9V
-20
0
20
VOUT = 1.2 V
IOUT = 0 A
40
60
80 100
Temperature (C)
120
Fsw = 1.0 MHz
FPWM
140
160
IOUT = 0 A
Figure 7-10. Switching Frequency vs Temperature
Figure 7-9. Switching Frequency vs Temperature
475
160
450
150
425
140
400
375
RDSON_LS (m)
RDSON_HS (m)
40
60
80 100
Temperature (C)
350
325
300
275
250
Vin = 3V
Vin = 6V
Vin = 9V
225
200
175
-40
-20
0
20
40
60
80 100
Temperature (C)
120
140
Figure 7-11. High-Side RDSON vs Temperature
160
130
120
110
100
90
80
Vin = 3V
Vin = 6V
Vin = 9V
70
60
-40
-20
0
20
40
60
80 100
Temperature (C)
120
140
160
Figure 7-12. Low-Side RDSON vs Temperature
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7.7 Typical Characteristics (continued)
1.85
Vin = 3V
Vin = 6V
Vin = 9V
1.84
1.83
1.81
ILIM_LS (A)
ILIM_HS (A)
1.82
1.8
1.79
1.78
1.77
1.76
1.75
-40
-20
0
20
40
60
80 100
Temperature (C)
120
140
160
1.65
1.64
1.63
1.62
1.61
1.6
1.59
1.58
1.57
1.56
1.55
1.54
1.53
1.52
1.51
1.5
-40
Vin = 3V
Vin = 6V
Vin = 9V
-20
0
20
40
60
80 100
Temperature (C)
120
140
160
Figure 7-14. Low-Side ILIM vs Temperature
Figure 7-13. High-Side ILIM vs Temperature
1.03
1.02
1.01
ILIM_NEG (A)
1
0.99
0.98
0.97
0.96
0.95
Vin = 3V
Vin = 6V
Vin = 9V
0.94
0.93
-40
-20
0
20
40
60
80 100
Temperature (C)
120
140
160
Figure 7-16. VIN UVLO Thresholds vs Temperature
1.005
0.9
1.004
0.899
1.003
0.898
VEN Threshold Falling (V)
VEN Threshold Rising (V)
Figure 7-15. Low-Side INEG vs Temperature
1.002
1.001
1
0.999
0.998
0.997
Vin = 3V
Vin = 6V
Vin = 9V
0.996
0.995
-40
-20
0
20
40
60
80 100
Temperature (C)
120
140
160
Figure 7-17. Precision Enable Threshold vs Temperature
10
0.897
0.896
0.895
0.894
0.893
0.892
Vin = 3V
Vin = 6V
Vin = 9V
0.891
0.89
-40
-20
0
20
40
60
80 100
Temperature (C)
120
140
160
Figure 7-18. Precision Enable Threshold vs Temperature
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8 Detailed Description
8.1 Overview
The TPS629211-Q1 synchronous switched mode power converter is based on DCS-Control (Direct Control with
Seamless Transition into power save mode), an advanced regulation topology that combines the advantages
of hysteretic, voltage mode, and current mode control. This control loop takes information about output voltage
changes and feeds it directly to a fast comparator stage. and sets the switching frequency, which is constant for
steady state operating conditions, and provides immediate response to dynamic load changes. To get accurate
DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves
fast and stable operation with small external components and low-ESR capacitors.
8.2 Functional Block Diagram
VIN
PG
Ref
1.0 V
VI
–
HS Limit
+
EN
VO
Internal/External
Divider
FB/VSET
Resistor-toDigital
VFB
Smart-Enable
Ref-System
UVLO
Start-up Handling
Smart-CONFIG
PG-Control
Thermal Shutdown
Power Control
Power Save Mode
Forced PWM
100% Mode
SW
Gate
Driver
Resistor-toDigital
MODE/
S-CONF
LS Limit
MODE Detection
VO
Direct
Control
VFB
TON timer
+
Device
Control
VREF
VI
–
VOS
Device Control
and Logic
VO
DCS-Control
GND
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8.3 Feature Description
8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
The MODE/S-CONF pin is an input with two functions, which can be used to customize the device behavior in
two ways:
• Select the device mode (forced PWM or auto PFM/PWM operation) traditionally with a HIGH or LOW level.
• Select the device configuration (switching frequency, internal and external feedback, output discharge, and
PFM/PWM mode) by connecting a single resistor to this pin.
The device interprets this pin during its start-up sequence after the internal OTP readout and before it starts
switching in soft start. If the device reads a HIGH or LOW level, dynamic mode change is active and PFM/PWM
mode can be changed during operation. If the device reads a resistor value, there is no further interpretation
during operation and the device mode or other configurations cannot be changed afterward.
EN & UVLO
Precise
Enable
detection
OTP
Readout
S-CONF
Readout
VSET
Readout
Resistor-to-Digitial
readout &
interpretation
No interpretation of
MODE/S-CONF or VSET
PG -> High
Switching
Operation
Softstart
MODE-Pin toggling detection
VOUT
Figure 8-1. Interpretation of S-CONF and VSET Flow
Table 8-1. Smart-CONFIG Setting Table
#
M ODE/S-CONF Level Or
Resistor Value [Ω] (1)
FB/VSET
Pin
FSW (MHz)
Output
Discharge
Mode (Auto Or Forced PWM)
Dynamic
Mode
Change
Setting Options by Level
1
GND
external FB
up to 2.5(2)
yes
Auto PFM/PWM with AEE
2
HIGH (> 1.8 V)
external FB
2.5
yes
Forced PWM
Active
Setting Options by Resistor
(1)
(2)
12
3
7.50 k
external FB
up to 2.5(2)
no
Auto PFM/PWM with AEE
4
9.31 k
external FB
2.5
no
Forced PWM
5
11.50 k
external FB
1
yes
Auto PFM/PWM
6
14.30 k
external FB
1
yes
Forced PWM
7
17.80 k
external FB
1
no
Auto PFM/PWM
8
22.10 k
external FB
1
no
Forced PWM
up to
2.5(2)
9
27.40 k
VSET
yes
Auto PFM/PWM with AEE
10
34.00 k
VSET
2.5
yes
Forced PWM
11
42.20 k
VSET
up to 2.5(2)
no
Auto PFM/PWM with AEE
12
52.30 k
VSET
2.5
no
Forced PWM
13
64.90 k
VSET
1
yes
Auto PFM/PWM
14
80.60 k
VSET
1
yes
Forced PWM
15
100.00 k
VSET
1
no
Auto PFM/PWM
16
124.00 k
VSET
1
no
Forced PWM
not active
E96 Resistor Series, 1% accuracy, temperature coefficient better or equal than ±200 ppm/°C
FSW varies based on VIN and VOUT. See Section 8.4.3 for more details.
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8.3.2 Adjustable VO Operation (External Voltage Divider)
If the device is configured to operate in classical adjustable VO operation, the FB/VSET pin is used as the
feedback pin and must sense VO through an external divider network. Figure 8-2 shows the typical schematic for
this configuration.
VIN
3 V to 10 V
2.2 µH
4.7 F
VIN
SW
EN
VOS
VOUT
0.6 V to 5.5 V
22 F
FB/
VSET
MODE/
S-CONF
PG
GND
Figure 8-2. Adjustable VO Operation Schematic
8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)
If the device is configured to VSET operation, the device interprets the VSET pin value following the MODE/
S-CONF readout (see Figure 8-3). There is no further interpretation of the VSET pin during operation and the
output voltage cannot be changed afterward without toggling the EN pin.
Figure 8-3 shows the typical schematic for this configuration, where VO is directly sensed at the VOS pin of the
device. VO is sensed only through the VOS pin by an internal resistor divider. The target VO is programmed by
an external resistor connected between VSET and GND (see Table 8-2).
VIN
3 V to 10 V
2.2 µH
4.7 F
VIN
SW
EN
VOS
VOUT
0.4 V to 5.5 V
22 F
FB/
VSET
MODE/
S-CONF
PG
GND
Figure 8-3. Selectable VO Operation Schematic
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Table 8-2. VSET Selection Table
VSET #
Resistor Value [Ω](1)
Target VO [V]
1
GND
1.2
2
4.87 k
0.4
3
6.04 k
0.6
4
7.50 k
0.8
5
9.31 k
0.85
6
11.50 k
1.0
7
14.30 k
1.1
8
17.80 k
1.25
9
22.10 k
1.3
10
27.40 k
1.35
11
34.00 k
1.8
12
42.20 k
1.9
13
52.30 k
2.5
14
64.90 k
3.8
15
80.60 k
5.0
16
100.00 k
5.1
17
124.00 k
5.5
18
249.00 k or larger/open
3.3
(1)
E96 Resistor Series, 1% accuracy, temperature coefficient
better or equal to ±200 ppm/°C
8.3.4 Smart Enable with Precise Threshold
The voltage applied at the EN pin of the TPS629211-Q1 is compared to a fixed threshold rising voltage. This
allows the user to drive the pin by a slowly changing voltage and enables the use of an external RC network to
achieve a power-up delay.
The precise enable input allows the use of a user-programmable undervoltage lockout by adding a resistor
divider to the input of the EN pin.
The enable input threshold for a falling edge is lower than the rising edge threshold. The TPS629211-Q1 starts
operation when the rising threshold is exceeded. For proper operation, the EN pin must be terminated and must
not be left floating. Pulling the EN pin low forces the device into shutdown. In this mode, the internal high-side
and low-side MOSFETs are turned off and the entire internal control circuitry is switched off.
An internal resistor pulls the EN pin to GND and avoids the pin to be floating. This prevents an uncontrolled
start-up of the device in case the EN pin cannot be driven to a low level safely. With EN low, the device is in
shutdown mode. The device is turned on with EN set to a high level. The pulldown control circuit disconnects the
pulldown resistor on the EN pin after the internal control logic and the reference have been powered up. With EN
set to a low level, the device enters shutdown mode and the pulldown resistor is activated again.
14
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8.3.5 Power Good (PG)
The TPS629211-Q1 has a built-in power-good (PG) feature to indicate whether the output voltage has reached
its target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG
pin is an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage
level. PG is low when the device is turned off due to EN, UVLO (undervoltage lockout), or thermal shutdown. VIN
must remain present for the PG pin to stay low.
If the power-good output is not used, it is recommended to tie to GND or leave open.
Table 8-3. Power-Good Indicator Functional Table
Logic Signals
VI
VVIN > UVLO
EN Pin
HIGH
Thermal Shutdown
No
VO
PG Status
VO on target
High Impedance
VO < target
LOW
Yes
x
LOW
LOW
x
x
LOW
1.8 V < VVIN < UVLO
x
x
x
LOW
VI < 1.8 V
x
x
x
Undefined
8.3.6 Output Discharge Function
The purpose of the discharge function is to make sure there is a defined down-ramp of the output voltage when
the device is being disabled but also to keep the output voltage close to 0 V when the device is off. The output
discharge feature is only active after the TPS629211-Q1 has been enabled at least after since the supply voltage
was applied. The internal discharge resistor is connected to the VOS pin. The discharge function is enabled as
soon as the device is disabled (EN pin = low), in thermal shutdown, or in undervoltage lockout. The minimum
supply voltage required for the discharge function to remain active typically is 2 V.
8.3.7 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both
the power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the
input voltage trips below the threshold for a falling supply voltage.
8.3.8 Current Limit and Short Circuit Protection
The TPS629211-Q1 is protected against overload and short circuit events. If the inductor current exceeds the
current limit, ILIM_HS, the high-side switch is turned off and the low-side switch is turned on to ramp down the
inductor current. The high-side FET turns on again only if the current in the low-side FET has decreased below
the low-side current limit threshold, ILIM_LS.
Due to internal propagation delay, the actual current can exceed the static current limit during that time. The
dynamic current limit is given in Equation 1.
where:
•
•
•
•
V
Ipeak typ = ILIMH + LL × tpd
(1)
ILIMH is the static current limit as specified in the electrical characteristics.
L is the effective inductance at the peak current.
VL is the voltage across the inductor (VIN – VOUT).
tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
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V −V
Ipeak typ = ILIMH + IN L OUT × 50ns
(2)
The TPS629211-Q1 also includes a low-side negative current limit (ILIM:SINK) to protect against excessive
negative currents that can occur in forced PMW mode under heavy to light load transient conditions. If the
negative current in the low-side switch exceeds the ILIM:SINK threshold, the low-side switch is disabled. Both the
low-side and high-side switches remain off until an internal timer re-enables the high-side switch based on the
selected PWM switching frequency.
CAUTION
TI recommends that the inductor be sized such that the inductor ripple current, ΔIL (see Equation 9),
does not exceed 1.6 A to avoid the potential for continuous operation of the negative current limit
with no output load (IO = 0 A).
8.3.9 Thermal Shutdown
The junction temperature of the device, TJ, is monitored by an internal temperature sensor. If TJ rises and
exceeds the thermal shutdown threshold, TSD, the device shuts down. Both the high-side and low-side power
FETs are turned off and PG goes low. When TJ decreases below the hysteresis, the converter resumes normal
operation, beginning with soft start. During a PFM skip pause, the thermal shutdown feature is not active. A
shutdown or restart is only triggered during a switching cycle. See Section 8.4.2.
8.4 Device Functional Modes
8.4.1 Forced Pulse Width Modulation (PWM) Operation
The TPS629211-Q1 has two operating modes: forced PWM mode discussed in this section and auto PFM/PWM
mode as discussed in Section 8.4.2.
With the MODE/S-CONF pin set to forced PWM mode, the device operates with pulse width modulation in
continuous conduction mode (CCM) with a nominal switching frequency of either 1.0 MHz or 2.5 MHz. The
frequency variation in PWM is controlled and depends on VIN, VOUT, and the inductance. The on time in forced
PWM mode is given by Equation 3.
V
TON = VOUT × f 1
IN
SW
(3)
For very small output voltages, an absolute minimum on time of aproximately 40 ns is kept to limit switching
losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high.
16
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8.4.2 Power Save Mode Operation (Auto PFM/PWM)
When the MODE/S-CONF pin is configured for auto PFM/PWM mode, power save mode is allowed. The device
operates in PWM mode as long the output current is higher than half the ripple current of the inductor. To
maintain high efficiency at light loads, the device enters power save mode at the boundary to discontinuous
conduction mode (DCM). This happens if the output current becomes smaller than half the ripple current of the
inductor. Power save mode is entered seamlessly to make sure there is high efficiency in light-load operation.
The device remains in power save mode as long as the inductor current is discontinuous.
In power save mode, the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of power save mode is seamless in both directions.
The TPS629211-Q1 adjusts the on time (TON) in power save mode, depending on the input voltage and the
output voltage to maintain highest efficiency. The on time in steady-state operation can be estimated as:
With the MODE/S-CONF pin set to 1.0-MHz operation:
V
TON µs = VOUT
IN
(4)
With the MODE/S-CONF pin set to 2.5-MHz operation:
V
TON ns = 100 × V −IN
IN VOUT
(5)
Using TON, the typical peak inductor current in power save mode is approximated by:
V −V
ILPSMpeak = IN L OUT × TON
(6)
The output voltage ripple in power save mode is given by Equation 7:
L×V
2
1
1
IN
∆ V = 200 ×
C + VIN − VOUT + VOUT
(7)
Note
When VIN decreases to typically 15% above VOUT, the device does not enter power save mode
regardless of the load current. The device maintains output regulation in PWM mode.
8.4.3 AEE (Automatic Efficiency Enhancement)
When the MODE/S-CONF pin is configured for auto PFM/PWM with AEE mode, the TPS629211-Q1 provides
the highest efficiency over the entire input voltage and output voltage range by automatically adjusting the
switching frequency of the converter (see Equation 8). To keep the efficiency high over the entire duty
cycle range, the switching frequency is adjusted while maintaining the ripple current amplitudes. This feature
compensates for the very small duty cycles of high VIN to low VOUT conversions, which can limit the control
range in other topologies.
V − VOUT
FSW MHz = 10 × VOUT × IN
2
VIN
(8)
Traditionally, the efficiency of a switched mode converter decreases if VOUT decreases, VIN increases, or both.
By decreasing the switching losses at lower VOUT values or higher VIN values, the AEE feature provides an
efficiency enhancement across various duty cycles, especially for the lower VOUT values, where fixed frequency
converters suffer from a significant efficiency drop. Furthermore, when used with the recommended 2.2-μH
inductor, the ripple current amplitudes remains low enough to deliver the full output current without reaching
current limit across the entire range of input and output voltages (see Figure 8-4).
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By using the same TON configuration (see Equation 9) across the entire load range in AEE mode, the inductor
ripple current in AEE mode becomes effectively independent of the output voltage and can be approximated by
Equation 9:
V −V
V V
∆ IL mA = TON × IN L OUT = 0.1 × IN
L μH
(9)
500
Inductor Ripple Current (mA)
450
400
350
300
250
200
150
100
50
0
3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
Input Voltage (V)
L = 2.2 μH
Fsw = 2.5 MHz
Auto PFM/PWM with AEE
Figure 8-4. Typical Inductor Ripple Current Versus Input Voltage in AEE Mode
The TPS629211-Q1 operates in AEE mode as long as the output current is higher than half the ripple current
of the inductor. To maintain high efficiency at light loads, the device enters power save mode at the boundary
to discontinuous mode (DCM), which happens when the output current becomes smaller than half the inductor
ripple current.
8.4.4 100% Duty-Cycle Operation
The duty cycle of the buck converter operated in PWM mode is given in Equation 10.
V
D = VOUT
(10)
IN
The duty cycle increases as the input voltage comes close to the output voltage and the off time of the high-side
switch gets smaller. When the minimum off time of typically 80 ns is reached, the TPS629211-Q1 scales down
its switching frequency while it approaches 100% mode. In 100% mode, the device keeps the high-side switch
on continuously as long as the output voltage is below the internal set point. This allows the conversion of
small input to output voltage differences. For example, getting the longest operation time of battery-powered
applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
VIN MIN = VOUT + IOUT × RDS ON + RL
(11)
where:
• IOUT is the output current.
• RDS(on) is the on-state resistance of the high-side FET.
• RL is the DC resistance of the inductor used.
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8.4.5 Starting into a Prebiased Load
The TPS629211-Q1 is capable of starting into a prebiased output. The device only starts switching when the
internal soft-start ramp is equal or higher than the feedback voltage. If the voltage at the feedback pin is biased
to a higher voltage than the nominal value, the TPS629211-Q1 does not start switching unless the voltage at the
feedback pin drops to the target. Performance is the same for devices configured for VSET operation (internal
feedback), however, the switching is delayed until the soft-start ramp reaches the internal feedback voltage.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers must validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TPS629211-Q1 device is a highly efficient, small, and highly-flexible synchronous step-down DC-DC
converter that is easy to use. A wide input voltage range of 3 V to 10 V supports a wide variety of inputs
like 9-V supply rails, single-cell or dual-cell Li-Ion, and 5-V or 3.3-V rails.
9.2 Typical Application
VIN
3 V to 10 V
2.2 µH
4.7 F
VIN
SW
EN
VOS
VOUT
0.6 V to 5.5 V
22 F
FB/
VSET
MODE/
S-CONF
PG
GND
Figure 9-1. Typical Application Setup
Table 9-1. List of Components
20
Reference
Description
Manufacturer
IC
10-V, 1-A Step-Down Converter
TPS629211-Q1; Texas Instruments
L1
2.2-µH inductor
XGL3530-222; Coilcraft
C1
4.7 µF, 25 V, Ceramic, 1206
CGA5L1X7R1E475K160AC, TDK
C2
22 µF, 6.3 V, Ceramic, 0805
GCM21BD70J226ME36L, MuRata
R1
Depending on VOUT; see Section 9.2.2.2.
Standard 1% metal film
R2
Depending on VOUT; see Section 9.2.2.2.
Standard 1% metal film
R3
Depending on device setting, see Section 8.3.1.
Standard 1% metal film
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9.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS629211-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Programming the Output Voltage
The output voltage of the TPS629211-Q1 is adjustable and can be programmed for output voltages from 0.6 V to
5.5 V, using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value
of the output voltage is set by the selection of the resistor divider from Table 9-2. TI recommends to size R2 to
be less than 300 kΩ to allow for a feedback current of at least 2 μA. Lower resistor values are recommended for
highest accuracy and most robust design.
where
•
R1 = R2 × VOUT
VFB − 1
(12)
VFB is 0.6 V.
Table 9-2. Setting the Output Voltage
Nominal Output Voltage
R1
R2
Exact Output Voltage
0.8 V
51 kΩ
150 kΩ
0.804 V
1.2 V
130 kΩ
130 kΩ
1.200 V
1.5 V
150 kΩ
100 kΩ
1.500 V
1.8 V
475 kΩ
237 kΩ
1.803 V
2.5 V
523 kΩ
165 kΩ
2.502 V
3.3 V
619 kΩ
137 kΩ
3.311 V
5V
619 kΩ
84.5 kΩ
4.995 V
9.2.2.3 External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the control
loop of the device. The TPS629211-Q1 is optimized to work within a range of external components.
9.2.2.3.1 Output Filter and Loop Stability
The TPS629211-Q1 is internally compensated to be stable with a range of LC filter combinations. The LC output
filters inductance and capacitance have to be considered together, creating a double pole, responsible for the
corner frequency of the converter using Equation 13.
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fLC =
1
2π L × C
(13)
Table 9-3 can be used to simplify the output filter component selection. The values in Table 9-3 are nominal
values, and the effective capacitance was considered to be +20% and –50%. Different values can work, but
care has to be taken on the loop stability which is affected. More information on the sizing of the LC filter of a
DCS-Control regulator can be found in the Optimizing the TPS62130/40/50/60 Output Filter Application Note.
Table 9-3. Recommended LC Output Filter Combinations
4.7 µF
1 µH
10 µF
(3) (4)
1.5 µH
2.2 µH
(1)
(2)
(3)
(4)
22 µF
47 µF
100 µF
200 µF
√
√
√
√ (2)
(2)
√
√
√
√
√
√(1)
√
√ (2)
3.3 µH
√
√
√
√
4.7 µH
√
√
√
√(2)
This LC combination is the standard value and recommended for most applications.
Output capacitance must have an ESR of ≥ 10 mΩ for stable operation. See Section 9.3.1.
Not recommended for 1-MHz operation
At full load, ILpeak can exceed ILIM_HS at higher input or output voltages.
Although the TPS629211-Q1 is stable without the pole and zero being in a particular location, an external
feedforward capacitor can also be added to adjust their location based on the specific needs of the application.
This can provide better performance in power save mode, improved transient response, or both.
A more detailed discussion on the optimization for stability versus transient response can be found in
the Optimizing Transient Response of Internally Compensated DC-DC Converters Application Note and
Feedforward Capacitor to Improve Stability and Bandwidth of TPS621/821-Family Application Note.
9.2.2.3.2 Inductor Selection
The TPS629211-Q1 is designed for a nominal 2.2-µH inductor. Larger values can be used to achieve a lower
inductor current ripple but they can have a negative impact on efficiency and transient response. Smaller values
than 2.2 µH cause larger inductor current ripple, which cause larger negative inductor currents in forced PWM
mode and higher peak currents at full load. Therefore, they are not recommended at larger voltages across the
inductor as it is the case for high input voltages and low output voltages. With low output current in forced PWM
mode, this causes a larger negative inductor current peak that can exceed the negative current limit. At low or
no output current and small inductor values, the output voltage can therefore not be regulated any more. More
detailed information on further LC combinations can be found in the Optimizing the TPS62130/40/50/60 Output
Filter Application Note.
The inductor selection is affected by several effects like the following:
•
•
•
•
Inductor ripple current
Output ripple voltage
PWM-to-PFM transition point
Efficiency
In addition, the inductor selected has to be rated for appropriate saturation current and DC resistance (DCR).
Equation 14 calculates the maximum inductor current.
IL MAX = IOUT MAX +
where:
•
22
∆ IL MAX
2
(14)
V
1 − V OUT
IN MAX
∆ IL MAX = VOUT × L
MIN × fSW
(15)
IL(max) is the maximum inductor current.
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•
•
SLVSGD0A – MARCH 2022 – REVISED MARCH 2023
ΔIL is the peak-to-peak inductor ripple current.
L(min) is the minimum effective inductor value.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. It is recommended to add a margin of approximately 20%. A larger inductor
value is also useful to get lower ripple current, but increases the transient response time and size as well. The
following inductors have been used with the TPS629211-Q1 and are recommended for use:
Table 9-4. List of Inductors
Type
Inductance [µH]
DCR [mΩ]
Current [A](1)
Dimensions
[L×W×H] mm
DFE252012PD-2R2M(2)
2.2 µH, ±20%
84
2.8
2.5 × 2.0 × 1.2
muRata
XGL3530-222ME
2.2 μH, ±20%
20
4.0
3.5 × 3.2 × 3
Coilcraft
XGL4020-222ME
2.2 µH, ±20%
19.5
6.2
4 × 4 × 2.1
Coilcraft
XGL3530-332ME
3.3 μH, ±20%
33
3.3
3.5 × 3.2 × 3
Coilcraft
XGL4020-472ME
4.7 µH, ±20%
43
4.1
4 × 4 × 2.1
Coilcraft
(1)
(2)
Manufacturer
ISAT at 30% drop
For smaller size solutions that do not require maximum efficiency at the full output current
The inductor value also determines the load current at which power save mode is entered:
ILoad PSM = 12 × ∆ IL
(16)
9.2.2.3.3 Capacitor Selection
9.2.2.3.3.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TPS629211-Q1 allows the
use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low
output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, TI recommends to use X7R or X5R dielectric. Using a higher value has
advantages like smaller voltage ripple and a tighter DC output accuracy in power save mode (see Optimizing the
TPS62130/40/50/60 Output Filter Application Note for more information).
In power save mode, the output voltage ripple depends on the following:
•
•
•
•
Output capacitance
ESR
ESL
Peak inductor current
Using ceramic capacitors provides small ESR, ESL, and low ripple.
The output capacitor must be as close as possible to the device, and TI recommends to have the VOS signal
and feedback resistors (if used) must be connected to the positive terminal of the output capacitor.
For large output voltages, the DC bias effect of ceramic capacitors is large and the effective capacitance has to
be observed.
9.2.2.3.3.2 Input Capacitor
For most applications, 4.7-µF nominal is sufficient and is recommended, though a larger value reduces input
current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the
converter from the supply. A low-ESR multilayer ceramic capacitor (MLCC) is recommended for best filtering and
must be placed as close as possible to the VIN and GND pins.
Table 9-5. List of Capacitors
Type
Nominal Capacitance [µF]
CGA5L1X7R1E475K160AC
4.7
Voltage Rating [V]
Size
Manufacturer
25
1206(1)
TDK
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Table 9-5. List of Capacitors (continued)
Type
Nominal Capacitance [µF]
Voltage Rating [V]
Size
Manufacturer
CGA5L1X7R1E106K160AC
10
25
1206(1)
TDK
(1)
24
Smaller (0805 or 0603) options may be used and are available from various manufacturers.
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9.2.3 Application Curves
100
100
90
90
80
70
Efficiency (%)
Efficiency (%)
80
70
60
50
60
50
40
30
40
20
30
VIN = 7V
VIN = 9V
20
1E-5
0.0001
0.001
0.01
Iout (A)
VOUT = 5.0 V
L = 2.2 μH
VIN = 7V
VIN = 9V
10
0
0.01
0.1 0.2 0.5 1
Fsw = 2.5 MHz
Auto PFM/PWM
0.02 0.03
0.050.07 0.1
Iout (A)
VOUT = 5.0 V
Figure 9-2. Efficiency vs Output Current
0.2 0.3
L = 2.2 μH
0.5 0.7
1
Fsw = 2.5 MHz
Forced PWM
Figure 9-3. Efficiency vs Output Current
3.5
3
Switching Frequency (MHz)
Switching Frequency (MHz)
2.9
3
2.5
2
1.5
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1
0.5
6
6.5
7
2.7
2.6
2.5
2.4
2.3
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
2.2
2.1
2
7.5
8
8.5
Input Voltage (V)
VOUT = 5.0 V
L = 2.2 μH
9
9.5
10
6
Fsw = 2.5 MHz
Auto PFM/PWM
6.5
7
7.5
8
8.5
Input Voltage (V)
VOUT = 5.0 V
Figure 9-4. Switching Frequency vs Input Voltage
L = 2.2 μH
9
9.5
10
Fsw = 2.5 MHz
Forced PWM
Figure 9-5. Switching Frequency vs Input Voltage
0.21
0.45
VIN = 7V
VIN = 9V
0.4
0.2
0.35
0.19
0.3
Vout Accuracy (%)
Vout Accuracy (%)
2.8
0.25
0.2
0.15
0.1
0.05
0.18
0.17
0.16
0.15
0.14
0
0.13
-0.05
0.12
-0.1
0
0.1
0.2
VOUT = 5.0 V
0.3
0.4
0.5 0.6
Iout (A)
L = 2.2 μH
0.7
0.8
0.9
1
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-6. Output Voltage vs Output Current
VIN = 7V
VIN = 9V
0.11
0
0.1
0.2
VOUT = 5.0 V
0.3
0.4
0.5 0.6
Iout (A)
L = 2.2 μH
0.7
0.8
0.9
1
Fsw = 2.5 MHz
Forced PWM
Figure 9-7. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
100
100
90
90
80
70
Efficiency (%)
Efficiency (%)
80
70
60
50
60
50
40
30
40
20
30
VIN = 7V
VIN = 9V
20
1E-5
0.0001
0.001
0.01
Iout (A)
VOUT = 5.0 V
L = 3.3 μH
VIN = 7V
VIN = 9V
10
0
0.01
0.1 0.2 0.5 1
Fsw = 1.0 MHz
Auto PFM/PWM
L = 3.3 μH
0.5 0.7
1
Fsw = 1.0 MHz
Forced PWM
1.12
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.5
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.11
Switching Frequency (MHz)
1.75
Switching Frequency (MHz)
0.2 0.3
Figure 9-9. Efficiency vs Output Current
2
1.25
1
0.75
0.5
0.25
1.1
1.09
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
0
1
6
6.5
7
7.5
8
8.5
Input Voltage (V)
VOUT = 5.0 V
L = 3.3 μH
9
9.5
10
6
Fsw = 1.0 MHz
Auto PFM/PWM
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.05
6.5
7
7.5
8
8.5
Input Voltage (V)
VOUT = 5.0 V
Figure 9-10. Switching Frequency vs Input Voltage
L = 3.3 μH
9
9.5
10
Fsw = 1.0 MHz
Forced PWM
Figure 9-11. Switching Frequency vs Input Voltage
0.04
VIN = 7V
VIN = 9V
0.035
0.03
0.025
Vout Accuracy (%)
Vout Accuracy (%)
0.050.07 0.1
Iout (A)
VOUT = 5.0 V
Figure 9-8. Efficiency vs Output Current
0.02
0.015
0.01
0.005
0
-0.005
-0.01
VIN = 7V
VIN = 9V
-0.015
-0.02
0
0.1
0.2
VOUT = 5.0 V
0.3
0.4
0.5 0.6
Iout (A)
L = 3.3 μH
0.7
0.8
0.9
1
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-12. Output Voltage vs Output Current
26
0.02 0.03
0
0.1
0.2
VOUT = 5.0 V
0.3
0.4
0.5 0.6
Iout (A)
L = 3.3 μH
0.7
0.8
0.9
1
Fsw = 1.0 MHz
Forced PWM
Figure 9-13. Output Voltage vs Output Current
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
9.2.3 Application Curves (continued)
60
50
40
30
60
50
40
30
20
20
VIN = 6V
VIN = 9V
10
0
1E-5
0.0001
0.001
0.01
Iout (A)
VOUT = 3.3 V
L = 2.2 μH
VIN = 6V
VIN = 9V
10
0
0.01
0.1 0.2 0.5 1
Fsw = 2.5 MHz
Auto PFM/PWM
3
2.75
Switching Frequency (MHz)
Switching Frequency (MHz)
3
2.5
2
1.5
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0
4
5
7
8
Input Voltage (V)
L = 2.2 μH
9
VIN = 6V
VIN = 9V
Vout Accuracy (%)
Vout Accuracy (%)
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0.2
VOUT = 3.3 V
Fsw = 2.5 MHz
Forced PWM
2
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.75
0.3
0.4
0.5 0.6
Iout (A)
L = 2.2 μH
0.7
0.8
0.9
1
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-18. Output Voltage vs Output Current
5
6
7
8
Input Voltage (V)
L = 2.2 μH
9
10
Fsw = 2.5 MHz
Forced PWM
Figure 9-17. Switching Frequency vs Input Voltage
0.4
0.3
1
2.25
VOUT = 3.3 V
Fsw = 2.5 MHz
Auto PFM/PWM
0.35
0.5 0.7
2.5
4
10
Figure 9-16. Switching Frequency vs Input Voltage
0.1
L = 2.2 μH
1.5
6
VOUT = 3.3 V
0
0.2 0.3
Figure 9-15. Efficiency vs Output Current
3.5
0.5
0.050.07 0.1
Iout (A)
VOUT = 3.3 V
Figure 9-14. Efficiency vs Output Current
1
0.02 0.03
0.085
0.08
0.075
0.07
0.065
0.06
0.055
0.05
0.045
0.04
0.035
0.03
0.025
0.02
VIN = 6V
VIN = 9V
0
0.1
0.2
VOUT = 3.3 V
0.3
0.4
0.5 0.6
Iout (A)
L = 2.2 μH
0.7
0.8
0.9
1
Fsw = 2.5 MHz
Forced PWM
Figure 9-19. Output Voltage vs Output Current
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SLVSGD0A – MARCH 2022 – REVISED MARCH 2023
9.2.3 Application Curves (continued)
100
100
90
90
80
70
Efficiency (%)
Efficiency (%)
80
70
60
60
50
40
30
50
20
40
VIN = 6V
VIN = 9V
30
1E-5
0.0001
0.001
0.01
Iout (A)
VOUT = 3.3 V
L = 3.3 μH
VIN = 6V
VIN = 9V
10
0
0.01
0.1 0.2 0.5 1
Fsw = 1.0 MHz
Auto PFM/PWM
0.050.07 0.1
Iout (A)
VOUT = 3.3 V
Figure 9-20. Efficiency vs Output Current
0.2 0.3
L = 3.3 μH
0.5 0.7
1
Fsw = 1.0 MHz
Forced PWM
Figure 9-21. Efficiency vs Output Current
2
1.2
1.5
Switching Frequency (MHz)
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.75
Switching Frequency (MHz)
0.02 0.03
1.25
1
0.75
0.5
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.15
1.1
1.05
1
0.25
0
0.95
4
5
6
VOUT = 3.3 V
7
8
Input Voltage (V)
L = 3.3 μH
9
10
4
Fsw = 1.0 MHz
Auto PFM/PWM
L = 3.3 μH
9
10
Fsw = 1.0 MHz
Forced PWM
0.06
0.055
0.05
Vout Accuracy (%)
Vout Accuracy (%)
7
8
Input Voltage (V)
Figure 9-23. Switching Frequency vs Input Voltage
VIN = 6V
VIN = 9V
0.045
0.04
0.035
0.03
0.025
VIN = 6V
VIN = 9V
0.02
0.015
0
0.1
0.2
VOUT = 3.3 V
0.3
0.4
0.5 0.6
Iout (A)
L = 3.3 μH
0.7
0.8
0.9
1
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-24. Output Voltage vs Output Current
28
6
VOUT = 3.3 V
Figure 9-22. Switching Frequency vs Input Voltage
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.05
5
0
0.1
0.2
VOUT = 3.3 V
0.3
0.4
0.5 0.6
Iout (A)
L = 3.3 μH
0.7
0.8
0.9
1
Fsw = 1.0 MHz
Forced PWM
Figure 9-25. Output Voltage vs Output Current
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
9.2.3 Application Curves (continued)
60
50
40
30
60
50
40
30
20
20
VIN = 3V
VIN = 6V
VIN = 9V
10
0
1E-5
0.0001
0.001
0.01
Iout (A)
VOUT = 1.8 V
0
0.01
0.1 0.2 0.5 1
L = 2.2 μH
VIN = 3V
VIN = 6V
VIN = 9V
10
Fsw = 2.5 MHz
Auto PFM/PWM
0.2 0.3
L = 2.2 μH
0.5 0.7
1
Fsw = 2.5 MHz
Forced PWM
Figure 9-27. Efficiency vs Output Current
4
3.1
3
Switching Frequency (MHz)
3.5
Switching Frequency (MHz)
0.050.07 0.1
Iout (A)
VOUT = 1.8 V
Figure 9-26. Efficiency vs Output Current
3
2.5
2
1.5
1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.5
0
3
4
2.9
2.8
2.7
2.6
2.5
2.4
2.3
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
2.2
2.1
2
5
6
7
Input Voltage (V)
VOUT = 1.8 V
L = 2.2 μH
8
9
10
3
Fsw = 2.5 MHz
Auto PFM/PWM
4
5
VOUT = 1.8 V
Figure 9-28. Switching Frequency vs Input Voltage
6
7
Input Voltage (V)
L = 2.2 μH
8
9
10
Fsw = 2.5 MHz
Forced PWM
Figure 9-29. Switching Frequency vs Input Voltage
0.16
0.5
VIN = 3V
VIN = 6V
VIN = 9V
0.45
0.4
0.15
0.14
0.35
Vout Accuracy (%)
Vout Accuracy (%)
0.02 0.03
0.3
0.25
0.2
0.15
0.1
0.13
0.12
0.11
0.1
0.09
0.08
0.05
0.07
0
0.06
-0.05
0
0.1
0.2
VOUT = 1.8 V
0.3
0.4
0.5 0.6
Iout (A)
L = 2.2 μH
0.7
0.8
0.9
1
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-30. Output Voltage vs Output Current
VIN = 3V
VIN = 6V
VIN = 9V
0.05
0
0.1
0.2
VOUT = 1.8 V
0.3
0.4
0.5 0.6
Iout (A)
L = 2.2 μH
0.7
0.8
0.9
1
Fsw = 2.5 MHz
Forced PWM
Figure 9-31. Output Voltage vs Output Current
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
9.2.3 Application Curves (continued)
60
50
40
30
60
50
40
30
20
20
VIN = 3V
VIN = 6V
VIN = 9V
10
0
1E-5
0.0001
0.001
0.01
Iout (A)
VOUT = 1.8 V
L = 3.3 μH
VIN = 3V
VIN = 6V
VIN = 9V
10
0
0.01
0.1 0.2 0.5 1
Fsw = 1.0 MHz
Auto PFM/PWM
L = 3.3 μH
0.5 0.7
1
Fsw = 1.0 MHz
Forced PWM
1.25
1.25
Switching Frequency (MHz)
Switching Frequency (MHz)
0.2 0.3
Figure 9-33. Efficiency vs Output Current
1.5
1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.75
0.5
0.25
0
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.2
1.15
1.1
1.05
1
0.95
3
4
5
VOUT = 1.8 V
6
7
Input Voltage (V)
L = 3.3 μH
8
9
10
3
Fsw = 1.0 MHz
Auto PFM/PWM
4
5
6
7
Input Voltage (V)
VOUT = 1.8 V
Figure 9-34. Switching Frequency vs Input Voltage
L = 3.3 μH
8
9
10
Fsw = 1.0 MHz
Forced PWM
Figure 9-35. Switching Frequency vs Input Voltage
0.5
0.025
VIN = 3V
VIN = 6V
VIN = 9V
0.45
0.4
0.02
0.015
0.01
Vout Accuracy (%)
0.35
Vout Accuracy (%)
0.050.07 0.1
Iout (A)
VOUT = 1.8 V
Figure 9-32. Efficiency vs Output Current
0.3
0.25
0.2
0.15
0.1
0.005
0
-0.005
-0.01
-0.015
0.05
-0.02
0
-0.025
-0.05
-0.03
VIN = 3V
VIN = 6V
VIN = 9V
-0.035
-0.1
0
0.1
0.2
VOUT = 1.8 V
0.3
0.4
0.5 0.6
Iout (A)
L = 3.3 μH
0.7
0.8
0.9
1
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-36. Output Voltage vs Output Current
30
0.02 0.03
0
0.1
0.2
VOUT = 1.8 V
0.3
0.4
0.5 0.6
Iout (A)
L = 3.3 μH
0.7
0.8
0.9
1
Fsw = 1.0 MHz
Forced PWM
Figure 9-37. Output Voltage vs Output Current
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
9.2.3 Application Curves (continued)
60
50
40
30
60
50
40
30
20
20
VIN = 3V
VIN = 6V
VIN = 9V
10
0
1E-5
0.0001
0.001
0.01
Iout (A)
VOUT = 1.2 V
0
0.01
0.1 0.2 0.5 1
L = 2.2 μH
VIN = 3V
VIN = 6V
VIN = 9V
10
Fsw = 2.5 MHz
Auto PFM/PWM
0.02 0.03
0.050.07 0.1
Iout (A)
VOUT = 1.2 V
Figure 9-38. Efficiency vs Output Current
0.2 0.3
L = 2.2 μH
0.5 0.7
1
Fsw = 2.5 MHz
Forced PWM
Figure 9-39. Efficiency vs Output Current
4
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
Switching Frequency (MHz)
3.5
3
2.5
2
1.5
1
0.5
0
3
4
5
VOUT = 1.2 V
6
7
Input Voltage (V)
L = 2.2 μH
8
9
10
Fsw = 2.5 MHz
Auto PFM/PWM
VOUT = 1.2 V
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
Fsw = 2.5 MHz
Forced PWM
Figure 9-41. Switching Frequency vs Input Voltage
0.16
VIN = 3V
VIN = 6V
VIN = 9V
0.14
0.12
Vout Accuracy (%)
Vout Accuracy (%)
Figure 9-40. Switching Frequency vs Input Voltage
L = 2.2 μH
0.1
0.08
0.06
0.04
VIN = 3V
VIN = 6V
VIN = 9V
0.02
0
0
0.1
0.2
VOUT = 1.2 V
0.3
0.4
0.5 0.6
Iout (A)
L = 2.2 μH
0.7
0.8
0.9
1
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-42. Output Voltage vs Output Current
0
0.1
0.2
VOUT = 1.2 V
0.3
0.4
0.5 0.6
Iout (A)
L = 2.2 μH
0.7
0.8
0.9
1
Fsw = 2.5 MHz
Forced PWM
Figure 9-43. Output Voltage vs Output Current
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100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
9.2.3 Application Curves (continued)
60
50
40
30
60
50
40
30
20
20
VIN = 3V
VIN = 6V
VIN = 9V
10
0
1E-5
0.0001
0.001
0.01
Iout (A)
VOUT = 1.2 V
0
0.01
0.1 0.2 0.5 1
L = 3.3 μH
VIN = 3V
VIN = 6V
VIN = 9V
10
Fsw = 1.0 MHz
Auto PFM/PWM
L = 3.3 μH
0.5 0.7
1
Fsw = 1.0 MHz
Forced PWM
1.3
1.2
Switching Frequency (MHz)
Switching Frequency (MHz)
0.2 0.3
Figure 9-45. Efficiency vs Output Current
1.4
1
0.8
0.6
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
0.4
0.2
3
3.8
4.6
5.4
6.2
7
7.8
Input Voltage (V)
VOUT = 1.2 V
L = 3.3 μH
8.6
9.4
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.25
1.2
1.15
1.1
1.05
1
3
10
4
5
6
7
Input Voltage (V)
VOUT = 1.2 V
Fsw = 1.0 MHz
Auto PFM/PWM
L = 3.3 μH
8
9
10
Fsw = 1.0 MHz
Forced PWM
Figure 9-47. Switching Frequency vs Input Voltage
Figure 9-46. Switching Frequency vs Input Voltage
0.3
0.06
VIN = 3V
VIN = 6V
VIN = 9V
0.25
0.04
Vout Accuracy (%)
0.2
Vout Accuracy (%)
0.050.07 0.1
Iout (A)
VOUT = 1.2 V
Figure 9-44. Efficiency vs Output Current
0.15
0.1
0.05
0
0.02
0
-0.02
-0.04
VIN = 3V
VIN = 6V
VIN = 9V
-0.06
-0.05
-0.1
-0.08
0
0.1
0.2
VOUT = 1.2 V
0.3
0.4
0.5 0.6
Iout (A)
L = 3.3 μH
0.7
0.8
0.9
1
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-48. Output Voltage vs Output Current
32
0.02 0.03
0
0.1
0.2
VOUT = 1.2 V
0.3
0.4
0.5 0.6
Iout (A)
L = 3.3 μH
0.7
0.8
0.9
1
Fsw = 1.0 MHz
Forced PWM
Figure 9-49. Output Voltage vs Output Current
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100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
9.2.3 Application Curves (continued)
60
50
40
30
60
50
40
30
20
20
VIN = 3V
VIN = 6V
VIN = 9V
10
0
1E-5
0.0001
0.001
0.01
Iout (A)
VOUT = 0.6 V
0
0.01
0.1 0.2 0.5 1
L = 2.2 μH
VIN = 3V
VIN = 6V
VIN = 9V
10
Fsw = 2.5 MHz
Auto PFM/PWM
0.2 0.3
L = 2.2 μH
0.5 0.7
1
Fsw = 2.5 MHz
Forced PWM
Figure 9-51. Efficiency vs Output Current
3
3.5
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
3.3
Switching Frequency (MHz)
2.5
2
1.5
1
0.5
3.1
2.9
2.7
2.5
2.3
2.1
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.9
1.7
0
1.5
3
4
5
6
7
Input Voltage (V)
VOUT = 0.6 V
L = 2.2 μH
8
9
10
3
Fsw = 2.5 MHz
Auto PFM/PWM
4
5
6
7
Input Voltage (V)
VOUT = 0.6 V
Figure 9-52. Switching Frequency vs Input Voltage
L = 2.2 μH
8
9
10
Fsw = 2.5 MHz
Forced PWM
Figure 9-53. Switching Frequency vs Input Voltage
1.25
0.125
VIN = 3V
VIN = 6V
VIN = 9V
1
0.1
0.075
0.75
Vout Accuracy (%)
Vout Accuracy (%)
0.050.07 0.1
Iout (A)
VOUT = 0.6 V
Figure 9-50. Efficiency vs Output Current
Switching Frequency (MHz)
0.02 0.03
0.5
0.25
0
0.05
0.025
0
-0.025
-0.05
-0.075
-0.1
-0.25
VIN = 3V
VIN = 6V
VIN = 9V
-0.125
-0.15
-0.5
0
0.1
0.2
VOUT = 0.6 V
0.3
0.4
0.5 0.6
Iout (A)
L = 2.2 μH
0.7
0.8
0.9
1
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-54. Output Voltage vs Output Current
0
0.1
0.2
VOUT = 0.6 V
0.3
0.4
0.5 0.6
Iout (A)
L = 2.2 μH
0.7
0.8
0.9
1
Fsw = 2.5 MHz
Forced PWM
Figure 9-55. Output Voltage vs Output Current
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100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
9.2.3 Application Curves (continued)
60
50
40
30
60
50
40
30
20
20
VIN = 3V
VIN = 6V
VIN = 9V
10
0
1E-5
0.0001
0.001
0.01
Iout (A)
VOUT = 0.6 V
0
0.01
0.1 0.2 0.5 1
L = 3.3 μH
VIN = 3V
VIN = 6V
VIN = 9V
10
Fsw = 1.0 MHz
Auto PFM/PWM
L = 3.3 μH
0.5 0.7
1
Fsw = 1.0 MHz
Forced PWM
1.5
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.5
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.6A
IOUT = 1.0A
1.45
Switching Frequency (MHz)
1.6
Switching Frequency (MHz)
0.2 0.3
Figure 9-57. Efficiency vs Output Current
1.7
1.4
1.3
1.2
1.1
1
1.4
1.35
1.3
1.25
1.2
1.15
1.1
1.05
1
0.95
0.9
0.9
3
4
5
6
7
Input Voltage (V)
VOUT = 0.6 V
L = 3.3 μH
8
9
3
10
VIN = 3V
VIN = 6V
VIN = 9V
0.3
Vout Accuracy (%)
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
0.1
0.2
VOUT = 0.6 V
0.3
0.4
0.5 0.6
Iout (A)
L = 3.3 μH
0.7
0.8
0.9
1
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-60. Output Voltage vs Output Current
5
6
7
Input Voltage (V)
L = 3.3 μH
8
9
10
Fsw = 1.0 MHz
Forced PWM
Figure 9-59. Switching Frequency vs Input Voltage
0.4
0.35
4
VOUT = 0.6 V
Fsw = 1.0 MHz
Auto PFM/PWM
Figure 9-58. Switching Frequency vs Input Voltage
Vout Accuracy (%)
0.050.07 0.1
Iout (A)
VOUT = 0.6 V
Figure 9-56. Efficiency vs Output Current
34
0.02 0.03
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
VIN = 3V
VIN = 6V
VIN = 9V
0
0.1
0.2
VOUT = 0.6 V
0.3
0.4
0.5 0.6
Iout (A)
L = 3.3 μH
0.7
0.8
0.9
1
Fsw = 1.0 MHz
Forced PWM
Figure 9-61. Output Voltage vs Output Current
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9.2.3 Application Curves (continued)
VIN = 6 V
VOUT = 3.3 V
L = 2.2 μH
IO = 0 A
Fsw = 2.5 MHz
Auto PFM/PWM
VIN = 6 V
VOUT = 3.3 V
Figure 9-62. Start-Up Timing
VIN = 6 V
VOUT = 3.3 V
L = 2.2 μH
IO = 0 A
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
Forced PWM
Figure 9-63. Start-Up Timing
Fsw = 2.5 MHz
Forced PWM
Figure 9-64. Start-Up into Prebiased Output
VIN = 6 V
VOUT = 3.3 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
Forced PWM
Figure 9-66. Shutdown Timing with Output Discharge Disabled
VIN = 6 V
VOUT = 3.3 V
L = 2.2 μH
IO = 0 A
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-65. Shutdown Timing with Output Discharge Enabled
VIN = 6 V
VOUT = 3.3 V
L = 2.2 μH
IO = 0 A to 0.5 A
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-67. Load Transient Response
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9.2.3 Application Curves (continued)
VIN = 6 V
VOUT = 3.3 V
L = 2.2 μH
IO = 0.5 A to 1 A
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-68. Load Transient Response
VIN = 6 V
VOUT = 3.3 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-70. Output Voltage Ripple
VIN = 6 V
VOUT = 3.3 V
L = 3.3 μH
IO = 1 A
Fsw = 2.5 MHz
Forced PWM
Figure 9-72. Output Voltage Ripple
36
VIN = 6 V
VOUT = 3.3 V
L = 2.2 μH
IO = 0 A
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-69. Output Voltage Ripple
VIN = 6 V
VOUT = 3.3 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
Forced PWM
Figure 9-71. Output Voltage Ripple
VIN = 6 V
VOUT = 3.3 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
Auto PFM/PWM
Figure 9-73. Input Voltage Ripple
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VIN = 6 V
VOUT = 3.3 V
L = 2.2 μH
IO = 1 A
Fsw = 2.5 MHz
Forced PWM
Figure 9-74. Input Voltage Ripple
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
Gain
-25
Phase
-30
1000 2000
5000 10000
VIN = 6 V
VOUT = 0.6 V
100000
Frequency (Hz)
L = 2.2 μH
IO = 1 A
240
210
180
150
120
90
60
30
0
-30
-60
-90
-120
-150
-180
1000000
Phase (Deg)
Gain (db)
9.2.3 Application Curves (continued)
Fsw = 2.5 MHz
Forced PWM
Figure 9-75. Bode Plot
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9.3 System Examples
9.3.1 Powering Multiple Loads
In applications where the TPS629211-Q1 is used to power multiple load circuits, it is possible that the total
capacitance on the output is very large. To properly regulate the output voltage, there must be an appropriate
AC signal level on the VOS pin. Tantalum capacitors have a large enough ESR to keep output voltage ripple
sufficiently high on the VOS pin. With low-ESR ceramic capacitors, the output voltage ripple can get very low,
so it is not recommended to use a large capacitance directly on the output of the device. If there are several
load circuits with their associated input capacitor on a PCB, these loads are typically distributed across the
board. This adds enough trace resistance (Rtrace) to keep a large enough AC signal on the VOS pin for proper
regulation.
The minimum total trace resistance on the distributed load is 10 mΩ. The total capacitance n × CIN in Figure
9-76 was 32 × 47 μF of ceramic X7R capacitors.
Load1
Rtrace
VIN
3 V to 10 V
TPS629211-Q1
VIN
SW
C2
22 F
VOS
EN
C1
4.7 F
CIN
VOUT
0.4 V to 5.5 V
L1
Load2
Rtrace
CIN
FB/
VSET
MODE/
S-CONF
R1
PG
R2
GND
Loadn
Rtrace
CIN
Figure 9-76. Multiple Loads Example
9.3.2 Inverting Buck-Boost (IBB)
The must generate negative voltage rails for electronic designs is a common challenge. The wide 3-V to 10-V
input voltage range of the TPS629211-Q1 makes it ideal for an inverting buck-boost (IBB) circuit, where the
output voltage is inverted or negative with respect to ground.
The circuit operation in the IBB topology differs from that in the traditional buck topology. Though the
components are connected the same as with a traditional buck converter, the output voltage terminals are
reversed. See Figure 9-77 and Figure 9-78.
The maximum input voltage that can be applied to an IBB converter is less than the maximum voltage that can
be applied to the TPS629211-Q1 in a typical buck configuration. This is because the ground pin of the IC is
connected to the (negative) output voltage. Therefore, the input voltage across the device is VIN to VOUT, and not
VIN to ground. Thus, the input voltage range of the TPS629211-Q1 in an IBB configuration becomes 3 V to 10 V
+ VOUT, where VOUT is a negative value.
The output voltage range is the same as when configured as a buck converter, but only negative. Thus, the
output voltage for a TPS629211-Q1 in an IBB configuration can be set between –0.4 V and –5.5 V.
The maximum output current for the TPS629211-Q1 in an IBB topology is normally lower than a traditional buck
configuration due to the average inductor current being higher in an IBB configuration. Traditionally, lower input
or (more negative) output voltages results in a lower maximum output current. However, using a larger inductor
value or the higher 2.5-MHz frequency setting can be used to recover some or all of this lost maximum current
capability.
38
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When implementing an IBB design, it is important to understand that the IC ground is tied to the negative voltage
rail, and in turn, the electrical characteristics of the TPS629211-Q1 device are referenced to this rail. During
power up, as there is no charge in the output capacitor, the IC GND pin (and VOUT) are effectively 0 V, thus
parameters such as the VIN UVLO and EN thresholds are the same as in a typical buck configuration. However,
after the output voltage is in regulation, due to the negative voltage on the IC GND pin, the device traditionally
continues to operate below what can appear to be the normal UVLO/EN falling thresholds relative to the system
ground. Thus, special care must be taken if the user is using the dynamic mode change feature on the MODE
pin of the TPS629211-Q1 or driving the EN pin from an upstream microcontroller as the high and low thresholds
are relative to the negative rail and not the system ground.
More information on using a DCS regulator in an IBB configuration can be found in the Description
Compensating the Current Mode Boost Control Loop Application Note and Using the TPS6215x in an Inverting
Buck-Boost Topology Application Note.
TPS6292xx
2.2 µH
VIN
VIN
SW
EN
VOS
22 F
10 F
FB/
VSET
MODE/
S-CONF
PG
VOUT
-0.6 V to -5.5 V
GND
Figure 9-77. IBB Example with Adjustable Feedback
TPS6292xx
2.2 µH
VIN
VIN
SW
EN
VOS
22 F
10 F
FB/
VSET
MODE/
S-CONF
PG
GND
VOUT
-0.4 V to -5.5 V
Figure 9-78. IBB Example with Internal Feedback
9.4 Power Supply Recommendations
The power supply to the TPS629211-Q1 must have a current rating according to the supply voltage, output
voltage, and output current of the TPS629211-Q1.
9.5 Layout
9.5.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more so at high switching
frequencies. Therefore, the PCB layout of the TPS629211-Q1 demands careful attention to make sure proper
operation and to get the performance specified. A poor layout can lead to issues like the following:
•
•
Poor regulation (both line and load)
Stability and accuracy weaknesses
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•
•
Increased EMI radiation
Noise sensitivity
See Figure 9-79 for the recommended layout of the TPS629211-Q1, which is designed for common external
ground connections. The input capacitor must be placed as close as possible between the VIN and GND pin of
the TPS629211-Q1.
Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load
current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops that conduct an
alternating current must outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS must be connected with short wires and not nearby high dv/dt signals (for
example, SW). As they carry information about the output voltage, they also must be connected as close as
possible to the actual output voltage (at the output capacitor). The FB resistors, R1 and R2, must be kept close
to the IC and connect directly to those pins and the system ground plane. The same applies for the S-CONFIG/
MODE and VSET programming resistors.
The package uses the pins for power dissipation. Thermal vias on the VIN, GND, and SW pins help to spread
the heat through the PCB.
In case any of the digital inputs (EN or S-CONF/MODE pins) must be tied to the input supply voltage at VIN, the
connection must be made directly at the input capacitor as indicated in the schematics.
The recommended layout is implemented on the EVM and shown in the TPS629211-Q1EVM User's Guide.
9.5.2 Layout Example
GND
VOUT
GND
SW
VIN
VOS
EN
PG
S-CONFIG
FB
VIN
Figure 9-79. TPS629211-Q1 Layout
9.5.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
The following are basic approaches for enhancing thermal performance:
•
•
40
Improving the power dissipation capability of the PCB design (for example, increasing copper thickness,
thermal vias, number of layers)
Introducing airflow in the system
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For more details on how to use the thermal parameters, see the Thermal Characteristics of Linear and Logic
Packages Using JEDEC PCB Designs Application Note and Semiconductor and IC Package Thermal Metrics
Application Note.
The TPS629211-Q1 is designed for a maximum operating junction temperature (TJ) of 150°C. Therefore, the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. If the thermal resistance of the package is given,
the size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal
resistance. To get an improved thermal behavior, TI recommends to use top layer metal to connect the device
with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved
thermal performance. Additionally, the DYC package option (see Figure 6-2) with extended leads can also be
used to further reduce the thermal resistance of a design.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.1.2 Development Support
10.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS629211-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
•
Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
Application Note
Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Note
Texas Instruments, TPS629211-Q1EVM User's Guide
Texas Instruments, Description Compensating the Current Mode Boost Control Loop Application Note
Texas Instruments, Using the TPS6215x in an Inverting Buck-Boost Topology Application Note
Texas Instruments, Optimizing the TPS62130/40/50/60 Output Filter Application Note
Texas Instruments, Optimizing Transient Response of Internally Compensated DC-DC Converters Application
Note
Texas Instruments, Description Compensating the Current Mode Boost Control Loop Application Note
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
42
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All trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS629211QDRLRQ1
ACTIVE
SOT-5X3
DRL
8
4000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 150
T211
Samples
TPS629211QDYCRQ1
ACTIVE
SOT-5X3
DYC
8
4000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 150
T11Q
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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