TPS62A02DRLR

TPS62A01, TPS62A01A, TPS62A02, TPS62A02A SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 TPS62A0x and TPS62A0xA, 1-A, 2-A High-Efficiency Synchronous Buck Converters in a SOT563 and a SOT23 Package 1 Features 3 Description • • • The TPS62A0x family of devices are synchronous step-down buck DC/DC converters optimized for high efficiency and compact design size. The devices integrate switches capable of delivering an output current up to 2 A. At medium to heavy loads, the devices operate in pulse width modulation (PWM) mode with 2.4-MHz switching frequency. At light load, the devices automatically enter power save mode (PSM) to maintain high efficiency over the entire load current range. In shutdown, the current consumption is minimal as well. The TPS62A0xA variants of this device family operate in forced PWM across the whole load current range. • • • • • • • • • • • • • 2.5-V to 5.5-V input voltage range 0.6-V to VIN adjustable output voltage range 180-mΩ and 120-mΩ low RDSON switches (1-A DRL) 100-mΩ and 67-mΩ low RDSON switches (1-A DDC, 2-A) < 23-µA quiescent current 1% feedback accuracy (0°C to 125°C) 100% mode operation 2.4-MHz switching frequency Power save mode or PWM option available Power-good output pin Short-circuit protection (HICCUP) Internal soft start-up Active output discharge Thermal shutdown protection Pin-to-pin compatible with the TLV62585 (DRL) Pin-to-pin compatible with the TLV62569 (DDC) 2 Applications • • • • • Set top box, TV applications IP network camera, Multi-function printer Wireless router, solid state drive Battery-powered applications General purpose point-of-load supply The TPS62A0x devices provide an adjustable output voltage through an external resistor divider. An internal soft-start circuit limits the inrush current during start-up. Other features like overcurrent protection, thermal shutdown protection, and power good are built-in. The devices are available in a SOT563 and SOT23-6 package. Package Information PACKAGE(1) PART NUMBER TPS62A01x TPS62A0x L1 1.0 µH VIN 2.5 V to 5.5 V VIN SW GND FB VOUT 0.6 V to VIN R1 200 k C1 4.7
F EN PG C2 22 F R2 100 k VPG (1) (2) 1.60 mm × 1.60 mm 2.90 mm × 2.80 mm(3) DRL (SOT-563, 6) 1.60 mm × 1.60 mm DDC (SOT-23, 6) 2.90 mm × 2.80 mm (3) C3: optional For more information, see Section 11. The package size (length × width) is a nominal value and includes pins, where applicable. Preview information (not Production Data). Device Information Typical Application PART 100 95 NUMBER(1) OPERATION MODE OUTPUT CURRENT TPS62A01 PSM, PWM 1A TPS62A01A FPWM 1A 80 TPS62A02 PSM, PWM 2A 75 TPS62A02A FPWM 2A 90 85 Efficiency [%] DRL (SOT-563, 6) DDC (SOT-23, 6)(3) C3* VIN R4 499 k TPS62A02x PACKAGE SIZE(2) 70 (1) 65 60 VOUT = 3.3 V VOUT = 1.8 V VOUT = 1.2 V 55 50 1m See the Device Comparison Table. 10m 100m IOUT [A] 1 2 Efficiency vs Output Current at 5 VIN (TPS62A02x) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Device Comparison Table...............................................3 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics.............................................5 6.6 Typical Characteristics................................................ 7 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Feature Description.....................................................8 2 Submit Document Feedback 7.4 Device Functional Modes............................................9 8 Application and Implementation.................................. 11 8.1 Application Information..............................................11 8.2 Typical Application.................................................... 11 8.3 Power Supply Recommendations.............................16 8.4 Layout....................................................................... 16 9 Device and Documentation Support............................18 9.1 Device Support......................................................... 18 9.2 Receiving Notification of Documentation Updates....18 9.3 Support Resources................................................... 18 9.4 Trademarks............................................................... 18 9.5 Electrostatic Discharge Caution................................18 9.6 Glossary....................................................................18 10 Revision History.......................................................... 19 11 Mechanical, Packaging, and Orderable Information.................................................................... 19 Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 4 Device Comparison Table (1) Device Number Output Current Package Operation Mode TPS62A01DRLR 1A SOT-563, 6 PSM, PWM TPS62A01ADRLR 1A SOT-563, 6 FPWM TPS62A02DRLR 2A SOT-563, 6 PSM, PWM TPS62A02ADRLR 2A SOT-563, 6 FPWM TPS62A01PDDCR(1) 1A SOT-23, 6 PSM, PWM TPS62A01APDDCR(1) 1A SOT-23, 6 FPWM TPS62A02PDDCR 2A SOT-23, 6 PSM, PWM TPS62A02APDDCR 2A SOT-23, 6 FPWM Preview information (not Production Data). 5 Pin Configuration and Functions SOT23-6 DDC package (Top View) SOT563-6 DRL package (Top View) GND 1 6 PG SW 2 5 FB VIN 3 4 EN Not to scale EN 1 6 FB GND 2 5 PG SW 3 4 VIN Not to scale Figure 5-1. 6-Pin DRL SOT-563 Package (Top View), 6-Pin DDC SOT-23 package (Top View) Table 5-1. Pin Functions Pin Number Name SOT563-6 EN 4 FB 5 GND 1 PG 6 SW 2 VIN 3 (1) SOT23-6 Type(1) 1 Description I Device enable logic input. Logic high enables the device. Logic low disables the device and turns the device into shutdown. Do not leave the pin floating. I Feedback pin for the internal control loop. Connect this pin to an external feedback divider. 2 G Ground pin. 5 O Power-good open-drain output pin. The pullup resistor cannot be connected to any voltage higher than 5.5 V. If unused, leave the pin open or connect to GND. O Switch pin connected to the internal FET switches and inductor terminal. Connect the inductor of the output filter to this pin. I Input voltage pin. Connect the input capacitor as close as possible between VIN and GND. 6 3 4 I = Input, O = Output, G = Ground Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A Submit Document Feedback 3 TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VIN, EN, PG –0.3 6 V SW, DC –0.3 VIN + 0.3 V SW, transient < 10 ns –3.0 10 V FB –0.3 3 V TJ Operating junction temperature –40 150 °C Tstg Storage temperature –55 150 °C Pin voltage(2) (1) (2) UNIT Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are with respect to the network ground terminal. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input supply voltage range 2.5 5.5 V VOUT Output voltage range 0.6 VIN V IOUT Output current range TPS62A01 0 1 A IOUT Output current range (1) TPS62A02 0 2 A L Effective inductance 1.0 µH COUT Output capacitance VOUT < 1.2 V 44 µF COUT Output capacitance 1.2 V ≤ VOUT < 1.8 V 22 µF COUT Output capacitance VOUT ≥ 1.8 V 10 IPG Power Good input current capability TJ Operating junction temperature (1) µF 0 1 mA –40 125 °C Operating continuously at 2 A with input voltages < 3.3 V or at ambient temperatures > 85°C can result in thermal shutdown, per EVM measurements. 6.4 Thermal Information TPS62A0x THERMAL 4 METRIC(1) TPS62A0x DRL DDC 6 PINS 6 PINS UNIT RθJA Junction-to-ambient thermal resistance 157.3 132.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 92.2 74.9 °C/W RθJB Junction-to-board thermal resistance 45.6 45.5 °C/W ψJT Junction-to-top characterization parameter 4.0 25.5 °C/W Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 TPS62A0x TPS62A0x DRL DDC 6 PINS 6 PINS 45.0 45.1 THERMAL METRIC(1) ψJB (1) Junction-to-board characterization parameter UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics TJ = –40°C to +125°C, VIN = 2.5 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ(VIN) VIN quiescent current Non-switching; VEN = High; VFB = 610 mV; TPS62A01xDRL 20 µA IQ(VIN) VIN quiescent current Non-switching; VEN = High; VFB = 610 mV; TPS62A02xDRL; TPS62A01xDDC; TPS62A02xDDC 23 µA ISD(VIN) VIN shutdown supply current VEN = Low VUVLO(R) VIN UVLO rising threshold VIN rising VUVLO(F) VIN UVLO falling threshold VIN falling VEN(R) EN voltage rising threshold EN rising; enable switching 1.2 VEN(F) EN voltage falling threshold EN falling, disable switching 0.4 V VEN(LKG) EN Input leakage current VEN = 5 V 100 nA 0.01 2 µA 2.3 2.4 2.5 V 2.2 2.3 2.4 V UVLO ENABLE V REFERENCE VOLTAGE VFB FB voltage TJ = 0°C to 125°C, PWM mode 594 600 606 mV VFB FB voltage PWM mode 591 600 609 mV IFB(LKG) FB input leakage current VFB = 0.6 V 100 nA SWITCHING FREQUENCY fSW(FCCM) Switching frequency, FPWM operation VIN = 5 V; VOUT = 1.8 V 2400 kHz Internal fixed soft-start time From EN = High to VFB = 0.56 V RDSON(HS) High-side MOSFET on-resistance TPS62A01xDRL; VIN = 5 V 180 mΩ RDSON(LS) Low-side MOSFET on-resistance TPS62A01xDRL; VIN = 5 V 120 mΩ RDSON(HS) High-side MOSFET on-resistance VIN = 5 V; TPS62A02xDRL; TPS62A01xDDC; TPS62A02xDDC 100 mΩ RDSON(LS) Low-side MOSFET on-resistance VIN = 5 V; TPS62A02xDRL; TPS62A01xDDC; TPS62A02xDDC 67 mΩ 1.8 A 1.8 A 3.4 A STARTUP 1 ms POWER STAGE OVERCURRENT PROTECTION IHS(OC) High-side peak current limit TPS62A01 ILS(OC) Low-side valley current limit TPS62A01 1.3 IHS(OC) High-side peak current limit TPS62A02 ILS(OC) Low-side valley current limit TPS62A02xDRL 4.2 A ILS(OC) Low-side valley current limit TPS62A02xDDC 3.15 A VPGTH Power Good threshold PG low, FB falling 93.5 % VPGTH Power Good threshold PG high, FB rising 96 % PG delay falling 35 µs PG delay rising 10 µs 2.7 POWER GOOD IPG(LKG) PG pin Leakage current when open drain output is high VPG = 5 V Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A 100 Submit Document Feedback nA 5 TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 6.5 Electrical Characteristics (continued) TJ = –40°C to +125°C, VIN = 2.5 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V (unless otherwise noted) PARAMETER PG pin output low-level voltage TEST CONDITIONS MIN TYP IPG = 1 mA MAX UNIT 400 mV OUTPUT DISCHARGE Output discharge current on SW pin VIN = 3 V, VOUT = 2.0 V; TPS62A01xDRL 60 mA Output discharge current on SW pin VIN = 3 V, VOUT = 2.0 V; TPS62A01xDDC; TPS62A02xDDC; 76 mA 170 °C 20 °C THERMAL SHUTDOWN 6 TJ(SD) Thermal shutdown threshold TJ(HYS) Thermal shutdown hysteresis Submit Document Feedback Temperature rising Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 28 28 26 26 24 24 22 20 18 16 TJ TJ TJ TJ 14 12 2.5 3 3.5 4 4.5 Input Voltage [V] = = = = −40°C 30°C 85°C 125°C 5 5.5 Figure 6-1. Quiescent Current vs Input Voltage (TPS62A01) Quiescent Current [µA] Quiescent Current [µA] 6.6 Typical Characteristics 22 20 18 16 TJ TJ TJ TJ 14 12 2.5 3 3.5 4 4.5 Input Voltage [V] = = = = −40C 30C 85C 125C 5 5.5 Figure 6-2. Quiescent Current vs Input Voltage (TPS62A02) 0.25 0.225 Shutdown Current [µA] 0.2 VIN = 2.5 V VIN = 3.6 V VIN = 5.5 V 0.175 0.15 0.125 0.1 0.075 0.05 0.025 0 −40 −20 0 20 40 60 80 Junction Temperature [°C] 100 125 Figure 6-3. Shutdown Current vs Junction Temperature Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A Submit Document Feedback 7 TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 7 Detailed Description 7.1 Overview The TPS62A0x is a high-efficiency synchronous step-down converter. The device operates with an adaptive off time with a peak current control scheme. The device operates typically at 2.4-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the required off time for the low-side MOSFET, making the switching frequency relatively constant regardless of the variation of the input voltage, output voltage, and load current. 7.2 Functional Block Diagram VIN VI Device Control and Logic EN HS Limit Peak Current Detect UVLO Soft Start HICCUP protection Thermal Shutdown Modulator and Power Control SW Power Save Mode & PWM Operation VFB VFB Gate Driver 100% Mode – + VREF LS Limit Zero Current Detect Active Discharge EN PG VI TOFF timer + VPG – VFB VO GND 7.3 Feature Description 7.3.1 Power Save Mode The device automatically enters power save mode to improve efficiency at light load when the inductor current becomes discontinuous. In power save mode, the converter reduces the switching frequency and minimizes current consumption. In power save mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized by increasing the output capacitor or adding a feedforward capacitor. 8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 7.3.2 100% Duty Cycle Low Dropout Operation The device offers low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input voltage to maintain output regulation, depending on the load current and output voltage, is calculated as: VIN(MIN) = VOUT + IOUT × (RDS(ON) + RL) (1) where • • RDS(ON) = High-side FET on-resistance RL = Inductor ohmic resistance (DCR) 7.3.3 Soft Start After enabling the device, internal soft-start circuitry ramps up the output voltage, which reaches the nominal output voltage during start-up time, avoiding excessive inrush current and creating a smooth voltage rise slope. Internal soft-start circuitry also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal impedance. The TPS62A0x is able to start into a prebiased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to the nominal value. 7.3.4 Switch Current Limit and Short-Circuit Protection (HICCUP) The switch current limit prevents the device from high inductor current and drawing excessive current from the battery or input rail. Due to internal propagation delay, the AC peak current can exceed the static current limit during that time. Excessive current can occur with a shorted or saturated inductor, an overload or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET is turned off and the low-side MOSFET is turned on to ramp down the inductor current with an adaptive off time. When this switch current limit is triggered 32 times, the device stops switching to protect the output. The device then automatically starts a new start-up after a typical delay time of 100 µs has passed. This is named HICCUP short-circuit protection. The device repeats this mode until the high load condition disappears. HICCUP protection is also enabled during the start-up. 7.3.5 Undervoltage Lockout To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) is implemented, which shuts down the device at voltages lower than VUVLO. 7.3.6 Thermal Shutdown The device goes into thermal shutdown and stops switching when the junction temperature exceeds TJSD. When the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically. 7.4 Device Functional Modes 7.4.1 Enable and Disable The device is enabled by setting the EN input to a logic High. Accordingly, a logic Low disables the device. If the device is enabled, the internal power stage starts switching and regulates the output voltage to the set point voltage. The EN input must be terminated and not be left floating. 7.4.2 Power Good The TPS62A0x has a built-in power-good (PG) feature to indicate whether the output voltage has reached the target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage level. PG is low when the device is turned off due to EN, UVLO (undervoltage lockout), or thermal shutdown. VIN must remain present for the PG pin to stay low. If not used, the power-good can be tie to GND or left open. The PG indicator has a de-glitch to avoid the signal indicating glitches or transient responses from the loop. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A Submit Document Feedback 9 TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 Table 7-1. Power-Good indicator Functional Table Logic Signals VI EN Pin HIGH VI > UVLO NO VO PG Status VO on target High Impedance VO < target LOW YES LOW LOW YES x UVLO < VI < 1.8 V x x LOW x x x Undefined VI < 1.8 V 10 Thermal Shutdown Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The following section discusses the design of the external components to complete the power supply design for several input and output voltage options by using typical applications as a reference. 8.2 Typical Application TPS62A01 L1 1.0 µH VIN 2.5 V to 5.5 V VIN VOUT 1.8 V / 1 A SW R1 200 k GND C1 4.7
F C3* FB C2 22 F VIN R4 499 k EN PG R2 100 k VPG Figure 8-1. TPS62A01 Typical Application Circuit TPS62A02 L1 1.0 µH VIN 2.5 V to 5.5 V VIN VOUT 1.8 V / 2 A SW R1 200 k GND C1 4.7
F C3* FB C2 22 F VIN R4 499 k EN PG R2 100 k VPG Figure 8-2. TPS62A02 Typical Application Circuit *C3 is optional 8.2.1 Design Requirements For this design example, use the parameters listed in Table 8-1 as the input parameters Table 8-1. Design Parameters Design Parameter Example Value Input voltage 2.5 V to 5.5 V Output voltage 1.8 V Maximum output current 1.0 A, 2.0 A Table 8-2 lists the components used for the example. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A Submit Document Feedback 11 TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 Table 8-2. List of Components (1) Manufacturer (1) Reference Description C1 4.7 µF, Ceramic Capacitor, 10 V, X7R, size 0805, GRM21BR71A475KA73L Murata C2 22 µF, Ceramic Capacitor, 10 V, X7R, size 0805, GRM21BZ71A226KE15L Murata L1 1 µH, Power Inductor, DFE252012F-1R0M (1-A) / XGL3520-102MEC (2-A) Murata / Coilcraft R1, R2 Chip resistor, 1%, size 0603 Std. C3 Optional, 120 pF if needed Std. See the Third-Party Products Disclaimer. 8.2.2 Detailed Design Procedure 8.2.2.1 Setting the Output Voltage The output voltage is set by an external resistor divider according to Equation 2. R1 = R2 × VOUT VOUT VFB − 1 = R2 × 0.6 V − 1 (2) R2 must not be higher than 100 kΩ to provide acceptable noise sensitivity. 8.2.2.2 Output Filter Design The inductor and output capacitor together provide a low-pass filter. To simplify this process, Table 8-3 outlines possible inductor and capacitor value combinations. Checked cells represent combinations that are proven for stability by simulation and lab test. Check further combinations for each individual application. Table 8-3. Matrix of Output Capacitor and Inductor Combinations for TPS62A01 and TPS62A02 VOUT [V] L [µH](1) 0.6 ≤ VOUT < 1.2 1 1.2 ≤ VOUT < 1.8 1 1.8 ≤ VOUT (1) (2) (3) (4) 1 COUT [µF](2) 10 +(4) 22 2 × 22 + ++(3) ++(3) + ++(3) + Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and –30%. Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by +20% and –50%. This LC combination is the standard value and recommended for most applications. The minimum COUT of 10 µF does not support an additional feedforward capacitor. A 0.47-uH inductor can also be used with the same recommended output capacitors for the TPS62A02x. In case a lower output ripple is desired, higher output capacitance can help reduce the ripple. 8.2.2.3 Input and Output Capacitor Selection The architecture of the TPS62A0x allows use of tiny ceramic-type output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are thus recommended. To keep resistance up to high frequencies and to achieve narrow capacitance variation with temperature, TI recommends to use X7R or X5R dielectric. The input capacitor is the low impedance energy source for the converter that helps provide stable operation. TI recommends a low-ESR multilayer ceramic capacitor for best filtering. For most applications, a 4.7-μF input capacitor is sufficient; a larger value reduces input voltage ripple. The TPS62A0x is designed to operate with an output capacitor of 10 μF to 47 μF, depending on the selected output voltage, as outlined in Table 8-3. A feedforward capacitor reduces the output ripple in PSM and improves the load transient response. A 120-pF capacitor is good for the 1.8-V output typical application. 12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 100 100 95 95 90 90 85 85 Efficiency [%] Efficiency [%] 8.2.3 Application Curves 80 75 70 65 80 75 70 65 60 50 1m 60 VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 55 10m 100m Output Current [A] TPS62A01 (PSM/PWM) 500m 50 1m 1 SOT-563 (DRL) 500m 1 SOT-563 (DRL) Figure 8-4. 1.2-V Output Efficiency 100 100 95 95 90 90 85 Efficiency [%] 85 Efficiency [%] 10m 100m Output Current [A] TPS62A01 (PSM/PWM) Figure 8-3. 0.6-V Output Efficiency 80 75 70 65 80 75 70 65 60 55 60 VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 55 50 1m 10m 100m Output Current [A] TPS62A01 (PSM/PWM) 500m VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 50 45 40 1 0 SOT-563 (DRL) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Output Current [A] TPS62A01A (FPWM) Figure 8-5. 1.8-V Output Efficiency 0.8 0.9 1 SOT-563 (DRL) Figure 8-6. 1.8-V Output Efficiency 100 100 95 95 90 90 85 85 Efficiency [%] Efficiency [%] VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 55 80 75 70 80 75 70 65 65 60 50 1m 60 VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 55 10m 100m Output Current [A] TPS62A02 (PSM/PWM) 500m 1 SOT-563 (DRL) Figure 8-7. 0.6-V Output Efficiency VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 55 2 50 1m 10m 100m Output Current [A] TPS62A02 (PSM/PWM) 500m 1 2 SOT-563 (DRL) Figure 8-8. 1.2-V Output Efficiency Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A Submit Document Feedback 13 TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 100 100 95 95 90 90 85 Efficiency [%] Efficiency [%] 85 80 75 70 65 80 75 70 65 60 55 60 VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 55 50 1m 10m 100m Output Current [A] TPS62A02 (PSM/PWM) 500m 1 45 40 2 0 SOT-563 (DRL) 100 100 95 95 90 90 85 85 80 80 Efficiency [%] Efficiency [%] 0.4 0.6 0.8 1 1.2 1.4 Output Current [A] 1.6 1.8 2 SOT-563 (DRL) Figure 8-10. 1.8-V Output Efficiency 75 70 65 60 55 75 70 65 60 55 VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 50 45 40 1m 10m 100m Output Current [A] TPS62A01 (PSM/PWM) 500m VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 50 45 40 1m 1 SOT-23 (DDC) 10m 100m Output Current [A] TPS62A01 (PSM/PWM) Figure 8-11. 0.6-V Output Efficiency 500m 1 SOT-23 (DDC) Figure 8-12. 1.2-V Output Efficiency 100 100 95 95 90 90 85 85 80 80 Efficiency [%] Efficiency [%] 0.2 TPS62A02A (FPWM) Figure 8-9. 1.8-V Output Efficiency 75 70 65 60 55 75 70 65 60 55 VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 50 45 40 1m 10m 100m Output Current [A] TPS62A01 (PSM/PWM) 500m SOT-23 (DDC) Figure 8-13. 1.8-V Output Efficiency 14 VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 50 Submit Document Feedback 1 VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 50 45 2 40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Output Current [A] TPS62A01A (FPWM) 0.8 0.9 1 SOT-23 (DDC) Figure 8-14. 1.8-V Output Efficiency Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A TPS62A01, TPS62A01A, TPS62A02, TPS62A02A SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 100 100 95 95 90 90 85 85 80 80 Efficiency [%] Efficiency [%] www.ti.com 75 70 65 60 55 75 70 65 60 55 VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 50 45 40 1m 10m 100m Output Current [A] TPS62A02 (PSM/PWM) 500m 1 45 40 1m 2 SOT-23 (DDC) 10m 100m Output Current [A] TPS62A02 (PSM/PWM) Figure 8-15. 0.6-V Output Efficiency 500m 1 2 SOT-23 (DDC) Figure 8-16. 1.2-V Output Efficiency 100 100 95 95 90 90 85 85 80 80 Efficiency [%] Efficiency [%] VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 50 75 70 65 60 75 70 65 60 55 55 VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 50 45 40 1m 10m 100m Output Current [A] TPS62A02 (PSM/PWM) 500m SOT-23 (DDC) Figure 8-17. 1.8-V Output Efficiency 1 VIN = 2.5 V VIN = 3.3 V VIN = 5.0 V 50 45 40 2 0 0.5 1 Output Current [A] TPS62A02A (FPWM) 1.5 2 SOT-23 (DDC) Figure 8-18. 1.8-V Output Efficiency CH1: 1.8V DC-offset CH1: 1.8V DC-offset IOUT = 500 mA Figure 8-19. PWM Operation IOUT = 100 mA Figure 8-20. Power Save Mode Operation Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A Submit Document Feedback 15 TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 CH1: 1.8V DC-offset IOUT = 1 A Figure 8-21. Start-Up with Load Load step: 0.3 A to 1 A Figure 8-22. Load Transient 8.3 Power Supply Recommendations The device is designed to operate from an input voltage supply range from 2.5 V to 5.5 V. Make sure that the input power supply has a sufficient current rating for the application. 8.4 Layout 8.4.1 Layout Guidelines The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the TPS62A01x and TPS62A02x devices. • Place the input and output capacitors and the inductor as close as possible to the IC. This action keeps the power traces short. Routing these power traces direct and wide results in low trace resistance and low parasitic inductance. • Connect the low side of the input and output capacitors properly to the GND pin to avoid a ground potential shift. • The sense traces connected to FB is a signal trace. Take special care to avoid noise being induced. Keep these traces away from SW nodes. • Use a common ground. GND layers can be used for shielding. See Figure 8-23 and Figure 8-24 for the recommended PCB layout. 8.4.2 Layout Example Figure 8-23. TPS62A0x (SOT563) PCB Layout Recommendation 16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 GND L1 C1 VIN VIN SW PG GND FB 1 EN VOUT C2 R2 R1 C3 GND Figure 8-24. TPS62A0x (SOT23-6) PCB Layout Recommendation Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A Submit Document Feedback 17 TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 9 Device and Documentation Support 9.1 Device Support 9.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 9.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 9.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 9.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 9.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 9.6 Glossary TI Glossary 18 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A TPS62A01, TPS62A01A, TPS62A02, TPS62A02A www.ti.com SLUSEG9C – DECEMBER 2021 – REVISED DECEMBER 2023 10 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (July 2022) to Revision C (December 2023) Page • Added DDC package option throughout the data sheet..................................................................................... 3 • Changed ESD Ratings CDM row from showing testing was per JESD22-C101 to show that testing was per JS-002................................................................................................................................................................ 4 • Changed block diagram PG circuit by swapping VPG and VFB ..........................................................................8 • Changed block diagram high-side MOSFET from PMOS to NMOS.................................................................. 8 Changes from Revision A (March 2022) to Revision B (July 2022) Page • Added TPS62A02 and TPS62A02A................................................................................................................... 3 Changes from Revision * (December 2021) to Revision A (March 2022) Page • Changed document status from Advance Information to Production Data.........................................................1 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS62A01 TPS62A01A TPS62A02 TPS62A02A Submit Document Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS62A01ADRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 1J8 Samples TPS62A01DRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 1J7 Samples TPS62A02ADRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 1JM Samples TPS62A02DRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 1JL Samples TPS62A02PDDCR ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 A02P Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of