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TPS65000-Q1
SLVSC45C – AUGUST 2013 – REVISED JUNE 2017
TPS65000-Q1 2.25-MHz Step-Down Converter With Dual LDOs
1 Features
3 Description
•
•
The TPS65000-Q1 device is a single-chip powermanagement IC for automotive applications. This
device combines a single step-down converter with
two low-dropout regulators. The step-down converter
enters a low-power mode at light load for maximum
efficiency across the widest possible range of load
currents. For low-noise applications, the device can
be forced into fixed-frequency PWM using the MODE
pin. The step-down converter allows the use of a
small inductor and capacitors to achieve a small
solution size. A power-good status output can be
used for sequencing. The LDOs can supply 300 mA,
and can operate with an input voltage range from 1.6
V tp 6 V, thus allowing them to be supplied from the
step-down converter. The step-down converter and
the LDOs have separate voltage inputs and enables,
thus allowing for design and sequencing flexibility.
1
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 2:
–40°C to +105°C Ambient Operating
Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Step-Down Converters:
– VIN Range From 2.3 V to 6 V
– Spread-Spectrum Clock (SSC) Generation for
Reduced EMI
– 2.25-MHz Fixed-Frequency Operation
– 600-mA Output Current
LDOs:
– VIN Range From 1.6 V to 6 V
– Adjustable Output Voltage
– Up to 300-mA Output Current
– Separate Power Inputs and Enables
3-mm × 3-mm 16-Pin WQFN
The TPS65000-Q1 is available in a 16-pin leadless
package (3-mm × 3-mm WQFN).
Device Information(1)
PART NUMBER
TPS65000-Q1
Automotive
Automotive
Automotive
Automotive
BODY SIZE (NOM)
WQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
PACKAGE
Camera Module
Infotainment
Cluster
Sensor Fusion
Typical Application Schematic
TPS65000-Q1
Oscillator
SSCG
EN_DCDC
VINDCDC
VIN
10mF
P
A
2.2mH
SW
Step-Down
600mA
680W
FB_DCDC
10mF
VIN
P
MODE
150kW
A
PG
22pF
VDCDC
3.3V
470kW
PG
VLDO1
470kW
FB_LDO1
EN_LDO1
VINLDO1
LDO1
300mA
180kW
A
VLDO2
EN_LDO2
VINLDO2
VDCDC
A
PGND
AGND
180kW
P
VLDO1
1.8V
P
820kW
FB_LDO2
LDO2
300mA
10mF
10mF
VLDO2
2.8V
P
A
Bandgap Reference
TPS65000-Q1 Function/Pin
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65000-Q1
SLVSC45C – AUGUST 2013 – REVISED JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application .................................................. 16
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Examples................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2015) to Revision C
Page
•
Deleted SVS from the document title .................................................................................................................................... 1
•
Changed the list of applications ............................................................................................................................................ 1
•
Changed the CDM values in the ESD Ratings table.............................................................................................................. 4
•
Changed the temperature range in the Overview section from –40°C to +85°C to –40°C to +105°C................................. 10
•
Changed the PWM description of the MODE pin in the Device Functional Modes section................................................. 15
•
Deleted extra devices from the Design Parameters table .................................................................................................... 16
•
Deleted the tables with recommended inductors and capacitors ......................................................................................... 17
•
Added the Receiving Notification of Documentation Updates section ................................................................................. 21
•
Changed the Electrostatic Discharge Caution statement..................................................................................................... 21
Changes from Revision A (October 2013) to Revision B
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Original (August 2012) to Revision A
Page
•
Changed description for MODE pin in Pin Functions table .................................................................................................... 3
•
Deleted power dissipationrow of Absolute Maximum Ratings table....................................................................................... 4
•
Changed DCDC to VDCDC in CO row of Recommended Operating Conditions ................................................................... 4
•
Changed DCDC to VDCDC in STEP-DOWN CONVERTER OUTPUT VOLTAGE sectiion of Electrical Characteristics ..... 6
•
Deleted SUPPLY VOLTAGE SUPERVISOR section of Electrical Characteristics table ....................................................... 6
2
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5 Pin Configuration and Functions
EN_LDO1
1
EN_LDO2
2
VINLDO2
VLDO2
FB_LDO2
VINLDO1
RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
16
15
14
13
12
VLDO1
11
FB_LDO1
Exposed Thermal Pad
AGND
PGND
4
9
FB_DCDC
SW
5
6
7
8
EN_DCDC
10
MODE
3
VINDCDC
PG
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
10
—
EN_DCDC
8
I
Enable DC-DC converter
EN_LDO1
1
I
Enable LDO1
EN_LDO2
2
I
Enable LDO2
FB_DCDC
9
I
Voltage to DC-DC error amplifier
FB_LDO1
11
I
Voltage to LDO1 error amplifier
FB_LDO2
14
I
Voltage to LDO2 error amplifier
MODE
7
I
Selects forced-PWM or PWM-to-PFM automatic-transition mode
PG
3
O
Open-drain active-low power-good output
PGND
4
—
Power ground – connected to the thermal pad
SW
5
O
Switch pin – connect inductor here
VINDCDC
6
I
Input voltage to DC-DC converter and all other control blocks
VINLDO1
13
I
Input voltage to LDO1
VINLDO2
16
I
Input voltage to LDO2
VLDO1
12
O
LDO1 output voltage
VLDO2
15
O
LDO2 output voltage
—
Exposed thermal pad
EP
Analog ground – Star back to PGND as close to the IC as possible
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
Output voltage
Current
MIN
MAX
On all pins except AGND, PGND, EN_DCDC, VLDO1, VLDO2,
FB_LDO1, FB_LDO2, FB_DCDC pins with respect to AGND
–0.3
7
On EN_DCDC with respect to AGND
–0.3
VIN + 0.3, ≤ 7
On VLDO1, VLDO2, FB_LDO1, FB_LDO2, FB_DCDC
–0.3
3.6
V
VINDCDC, SW, PGND,
1800
mA
VINLDO1, VINLDO2, VLDO1, VLDO1, AGND
800
mA
1
mA
105
°C
150
°C
150
°C
At all other pins
Operating free-air temperature, TA
–40
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
–65
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic
discharge
Charged device model (CDM), per AEC
Q100-011
UNIT
±2500
Corner pins (1, 4, 5, 8, 9, 12, 13, and 16)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
L1
CI
CO
IO
TA
4
MIN
NOM
MAX
SW pin inductor
1.5
2.2
3.3
Input capacitor at VINDCDC
10
Input capacitor at VINLDO1, VINLDO2
2.2
Output capacitor for VDCDC
10
Output capacitor for LDO1, LDO2
2.2
UNIT
μH
μF
μF
22
μF
μF
DC-DC converter output current
600
mA
LDO1 output current
300
mA
LDO2 output current
300
mA
105
°C
Operating ambient temperature
–40
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6.4 Thermal Information
TPS65000-Q1
THERMAL METRIC (1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
46.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.1
°C/W
RθJB
Junction-to-board thermal resistance
19.2
°C/W
ψJT
Junction-to-top characterization parameter
1.1
°C/W
ψJB
Junction-to-board characterization parameter
19.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over full operating ambient temperature range, typical values are at TA = 25° C. Unless otherwise noted, specifications apply
for condition VIN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, COUT = 10 μF, CIN = 4.7 μF.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING VOLTAGE
Input voltage for VINDCDC of DCDC converter
VIN
Input voltage for LDO1 (VINLDO1)
See
(1)
Input voltage for LDO2 (VINLDO2)
See
(1)
Internal undervoltage (UVLO)
lockout threshold
VCC falling
2.3
6
V
1.6
6
V
1.6
6
V
1.82
V
1.72
Internal undervoltage (UVLO)
lockout hysteresis
1.77
160
mV
SUPPLY CURRENT
IQ
Operating quiescent current
ISD
Shutdown Current
MODE low, EN_DCDC high,
EN_LDO1, EN_LDO2 low,
IOUT = 0 mA and no switching
23
MODE low, EN_DCDC low,
EN_LDO1, EN_LDO2 high, IOUT = 0 mA
IOUT = 0 mA and no switching
50
EN_DCDC high, MODE high,
EN_LDO1, EN_LDO2 low, IOUT = 0 mA
4
32
μA
EN_DCDC low EN_LDO1 and EN_LDO2 low
0.16
57
mA
2.2
μA
DIGITAL PINS (EN_DCDC, EN_LDO1, EN_LDO2, MODE, PG
VIH
High-level input voltage
VIL
Low-level input voltage
1.2
VOL
Low-level output voltage
PG pins only, IO = –100 μA
Ilkg
Input leakage current
MODE, EN_DCDC, EN_LDO1, EN_LDO2 tied to
GND or VINDCDC
V
0.4
V
0.4
V
0.01
0.1
μA
1.722
2.25
2.847
2.01
2.25
2.41
OSCILLATOR
fSW
Oscillator frequency
SSCG enabled, SSC modulation ratio = 16%
SSCG disabled, SSC modulation ratio disabled
MHz
STEP-DOWN CONVERTER POWER SWITCH
rDS(on)
IO
(1)
High-side MOSFET ON-resistance
VINDCDC = VGS = 3.6 V
240
480
mΩ
Low-side MOSFET ON-resistance
VINDCDC = VGS = 3.6 V
185
380
mΩ
DC output current
2.3 V ≤ VINDCDC ≤ 2.5 V
300
2.5 V ≤ VINDCDC ≤ 6 V
600
mA
The design principle allows only VINDCDC to be the highest supply in the system. If separate input voltage supplies are used for the
DC-DC converter and LDOs, then choose VINDCDC ≥ VINLDO1 and VINDCDC ≥ VINLDO2.
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Electrical Characteristics (continued)
Over full operating ambient temperature range, typical values are at TA = 25° C. Unless otherwise noted, specifications apply
for condition VIN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, COUT = 10 μF, CIN = 4.7 μF.
PARAMETER
TEST CONDITIONS
Forward current limit, PMOS and
NMOS
ILIMF
2.3 V ≤ VINDCDC ≤ 6 V
MIN
TYP
MAX
UNIT
800
1000
1400
mA
STEP-DOWN CONVERTER POWER SWITCH (continued)
TSD
Thermal shutdown
Increasing junction temperature
150
°C
Thermal shutdown hysteresis
Decreasing junction temperature
30
°C
STEP-DOWN CONVERTER OUTPUT VOLTAGE
VDCDC
Adjustable output voltage range,
VDCDC
0.6
FB_DCDC pin current
Vref
Internal reference voltage
VDCDC
RDIS
VIND
CDC
V
0.1
μA
0.594
0.6
0.606
V
–1.5%
0%
1.5%
Output-voltage accuracy (PWM
mode) (2)
MODE = high,
2.3 ≤ VINDCDC ≤ 6 V
Output-voltage accuracy (PFM
mode) (3)
MODE low
+1% voltage positioning active
1%
Load regulation (PWM mode)
MODE high
0.5
%/A
Internal discharge resistance at
SW
EN_DCDC low
450
Ω
LOW-DROPOUT REGULATORS
VI
Input voltage for LDOx (VINLDOx)
VO
Adjustable output voltage, LDOx
(VLDOx) (4)
IO
Continuous-pass FET current
ISC
Short-circuit current limit
1.6
6
V
0.73
VINLD
Ox –
VDO
V
300
2.3 V ≤ VINLDOx
340
700
VINLDOx < 2.3 V
210
700
FB_LDOx pin current
FB_LDOx voltage
VDO
Dropout voltage
μA
VINLDOx ≥ 2.3 V, IOUT = 250 mA
370
mV
VINLDOx < 2.3 V, IOUT = 175 mA
370
mV
0.5
V
IO = 1 mA to 300 mA, VINLDOx = 2.3 V–6 V,
VLDOx = 1.2 V
–3.5%
3.5%
IO = 1 mA to 175 mA, VINLDOx = 1.6 V–6 V,
VLDOx = 1.2 V
–3.5%
3.5%
Load regulation
IO = 1 mA to 300 mA, VINLDOx = 3.6 V
VLDOx = 1.2 V
–1.5%
1.5%
Line regulation
VINLDOx = 1.6 V–6 V, VLDOx = 1.2 V at
IO = 1 mA
–0.5%
0.5%
PSRR
Power-supply rejection ratio
fNOISE ≤ 10 kHz, COUT ≥ 2.2 μF, VIN = 2.3 V,
VOUT = 1.3 V, IOUT = 10 mA
RDIS
Internal discharge resistance at
VLDOx
TSD
Output voltage accuracy
(2)
(3)
(4)
(5)
(6)
6
(6)
mA
0.1
Adjustable VOUT mode only
(5)
mA
40
dB
EN_LDOx low
450
Ω
Thermal shutdown
Increasing temperature
150
°C
Thermal shutdown hysteresis
Decreasing temperature
30
°C
For VINDCDC = VDCDC + 1 V
In PFM mode, the internal reference voltage is typically 1.01 × VREF.
Maximum output voltage VLDOx = 3.6 V.
VDO = VINLDOx – VLDOx, where VINLDOx = VLDOx(nom) – 100 mV
Output voltage specification does not include tolerance of external programming resistors.
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STEP-DOWN CONVERTER OUTPUT VOLTAGE
tStart
Start-up time
EN_DCDC to start of switching
(10%)
250
µs
tRamp
VDCDC ramp-up time
VDCDC ramp from 10% to 90%
250
µs
VLDOx ramp from 10% to 90%
200
µs
LOW-DROPOUT REGULATORS
tRAMP
VLDOx ramp time
6.7 Typical Characteristics
100
90
100
VOUT = 1.2V
o
TA = 25 C
90
VOUT = 1.2V
o
TA = 25 C
4.2V
80
80
3.6V
3.3V
70
6V
2.8V
Efficiency - %
Efficiency - %
70
5.5V
60
5V
2.3V
50
4.5V
4.2V
40
3.3V
60
6V
2.8V
50
5.5V
2.3V
40
3.6V
30
30
20
20
10
10
0
0.00001
0.0001
0.001
0.01
0.1
1
4.5V
0
0.00001
IO - Output Current - A
0.0001
0.001
0.01
0.1
1
IO - Output Current - A
Figure 2. Efficiency (DC-DC 600-mA PWM Mode)
vs Output Current
VINDCDC = 3.6 V
o
TA = 25 C
VDCDC = 1.2 V
Load Current = 60mA
EN_DCDC = high
EN_LDO1 = low
EN_LDO2 = low
Ch4: Load Current
DCDC
20mAdiv
Ch2: SW
2V/div
Ch2: SW
2V/div
Ch1: VDCDC
10mV/div
Ch1: VDCDC
10mV/div
Figure 1. Efficiency (DC-DC 600-mA PFM Mode)
vs Output Current
Ch3: Load Current
DCDC
20mAdiv
5V
VINDCDC = 3.6 V
o
TA = 25 C
VDCDC = 1.2 V
Load DCDC = 400mA
EN_DCDC = high
EN_LDO1 = low
EN_LDO2 = low
t - Time - 2ms/div
t - Time - 200ns/div
Figure 3. Output Voltage Ripple (DC-DC PFM Mode)
Figure 4. Output Voltage Ripple (DC-DC PWM Mode)
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Ch1: VINLDOx
1V/div
Ch1: EN_LDOx
500mV/div
VINDCDC = 3.6 V
VINLDOx = 2.3V
TA = 25oC
VLDOx = 1.2 V
VINDCDC = 3.6 V
o
TA = 25 C
VDCDC = 1.2 V
Ch3: VLDOx
500mV/div
Ch3: SW
20V/div
Ch2: VDCDC Ch1: EN_DCDC
500mV/div
2V/div
Typical Characteristics (continued)
Load DCDC = 100mA
EN_DCDC = 0V to 3.6V
EN_LDO1 = low
EN_LDO2 = low
Load LDOx = 100mA
EN_LDOx = 0V to 2.3V
EN_DCDC = low
t - Time - 100ns/div
t - Time - 100ns/div
VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = GND
VINDCDC = 3.6 V to 4.2V to 3.6V
o
TA = 25 C
Ch2: VDCDC
20mV/div
VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = VINDCDC
t - Time - 100ms/div
Figure 8. Line Transient Response (DC-DC PWM Mode)
VINDCDC = 3.6V
o
TA = 25 C
VDCDC = 1.8V
Ch1: VDCDC
50mV/div
VINDCDC = 6V
VINLDOx = 1.6 V to 2.3V to 1.6V
o
TA = 25 C
Ch2: DCDC Load Current
200mA/div
Ch1: VINLDOx
500mV/div
t - Time - 100ms/div
Figure 7. Line Transient Response (DC-DC PFM Mode)
Ch2: VLDOx
20mV/div
8
Figure 6. Start-Up Timing (LDOx)
Ch1: VINDCDC
500mV/div
VINDCDC = 3.6 V to 4.2V to 3.6V
TA = 25oC
Ch2: VDCDC
20mV/div
Ch1: VINDCDC
500mV/div
Figure 5. Start-Up Timing (DC-DC)
VLDOx = 1.007V
LDOx Load Current = 1mA
EN_DCDC = GND
DCDC Load Current = 60mA to 540 mA
Mode = GND
t - Time - 100ms/div
t - Time - 100ms/div
Figure 9. Line Transient Response (LDOx)
Figure 10. Load Transient Response (DC-DC PFM Mode)
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Ch1: LDOx Load Current
50mA/div
VINDCDC = 3.6V
o
TA = 25 C
VDCDC = 1.8V
DCDC Load Current = 60mA to 540 mA
Mode = VINDCDC
Ch2: VLDOx
20mV/div
Ch2: DCDC Load Current
200mA/div
Ch1: VDCDC
50mV/div
Typical Characteristics (continued)
VINDCDC = 3.6V
VINLDOx = 3.6V
o
TA = 25 C
LDOx Load Current = 15mA to 100mA
VLDOx = 1.2V
EN_DCDC = GND
t - Time - 200ms/div
Figure 12. Load Transient Response (LDOx)
Ch1: Mode
2V/div
VINDCDC = 3.6V
o
TA = 25 C
DCDC Load Current = 30mA
VDCDC = 1.8V
Ch2: VDCDC
20mV/div
VINDCDC = 3.6V
o
TA = 25 C
DCDC Load Current = 30mA
VDCDC = 1.8V
Ch3: SW
2V/div
Ch3: SW
2V/div
Ch2: VDCDC
20mV/div
Ch1: Mode
2V/div
t - Time - 100ms/div
Figure 11. Load Transient Response (DC-DC PWM Mode)
t - Time - 4ms/div
t - Time - 4ms/div
Figure 13. PFM to PWM Transition (DC-DC)
Figure 14. PWM to PFM Transition (DC-DC)
100
VIN = 2.3V
VLDOx = 1.3V
CI = 2.2mF
CO = 10mF
90
Rejection Ratio - dB
80
70
60
50
IO = 10mA
40
30
20
10
0
10
100
1k
10k
100k
1M
10M
f - Frequency - MHz
Figure 15. Power-Supply Rejection Ratio (LDOx) vs Frequency
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7 Detailed Description
7.1 Overview
The TPS65000-Q1 device provides one step-down converter, two low dropout regulators and spread spectrum
clock generation. The device has an input voltage range of
2.3 V to 6 V. This device is intended for (but not limited to) powering automotive camera modules.
The output voltage of the step-down converter can be selected through resistor networks on the output. To
maximize efficiency, there are two modes of operation based on load conditions: PWM or PFM. By pulling the
MODE pin high, forced PWM can be achieved. Pulling this pin low results in an automatic adjustment between
PFM and PWM modes.
The two general-purpose low-dropout regulators each have their own separate enables and voltage inputs. The
inputs can be tied to the output of the step-down converter or to a separate voltage source. Resistor networks
are required on the output of the regulator to set the output voltage.
The switching frequency of the step-down converter is handled by the oscillator, with a typical frequency of
2.25 MHz. The spread spectrum clock (SSC) modulates this frequency when the device is in PWM mode. This
additional circuit in the oscillator block reduces power that may cause EMI.
The TPS65000-Q1 device also provides a power good signal to monitor the condition of the DC-DC and both
LDOs. The DC-DC and LDOs are only monitored if their enable signal is high. If all enabled resources are in
regulation, the pin is pulled low. If one or more of the enabled resources are out of regulation, the pin is placed in
Hi-Z .
7.2 Functional Block Diagram
3-mm × 3-mm QFN
TPS65000-Q1
Oscillator
SSCG
VINDCDC
EN_DCDC
MODE
VINLDO1
EN_LDO1
VINLDO2
EN_LDO2
Buck Converter
600 mA
SW
FB_DCDC
PG
LDO1
300 mA
VLDO1
FB_LDO1
LDO2
300 mA
PGND
VLDO2
FB_LDO2
AGND
Band-Gap Reference
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7.3 Feature Description
7.3.1 Step-Down Converter
The step-down converter is intended to allow maximum flexibility in the end equipment. The output voltage is
user-selectable with a resistor network on the output. Figure 16 shows the necessary connections.
L
VINDCDC
SW
EN_DCDC
MODE
P
Switch Control
DISCHG
CF
RDC1
FB_DCDC
θJA Diode
+
Oscillator
CO
RDC2
-
ZLOAD
P
A
P
VREF(DCDC)
AGND
PGND
A
P
Figure 16. DC-DC Converter Block Diagram and Output Voltage Setting
The output voltage of the DC-DC converter is set by Equation 1:
+ RDC2 )
(R
VDCDC = VFB_DCDC x DC1
RDC2
VDCDC = 0.6V x
(RDC1 + RDC2 )
RDC2
(1)
The combined resistance of RDC1 and RDC2 should be less than 1 MΩ.
Fixed output voltages and additional current-limit options are also possible. Contact TI for further information.
The step-down converter has two modes of operation to maximize efficiency at different load conditions. At
moderate to heavy load currents, the device operates in a fixed-frequency pulse-width modulation (PWM) mode
that results in small output ripple and high efficiency. Pulling the MODE pin to a DC-high level results in PWM
mode over the entire load range.
At light load currents, the device operates in a pulsed frequency-modulation (PFM) mode to improve efficiency.
The transition to this mode occurs when the inductor current through the low-side FET becomes zero, indicating
discontinuous conduction. PFM mode also results in the output voltage increasing by 1% from its nominally set
value. This voltage positioning is intended to minimize both the voltage undershoot of a load step from light to
heavy loads, as when a processor moves from sleep to active modes, and the voltage overshoot at load
removal. Figure 17 shows the voltage positioning behavior for a light-to-heavy load step.
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Feature Description (continued)
Output voltage
VOUT(nom) + 1%
Light load
PFM Mode
VOUT(nom)
moderate to heavy load
PWM Mode
Time
Figure 17. PFM Voltage Positioning
Pulling the MODE pin to DC ground results in an automatic transition between PFM and PWM modes to
maximize efficiency.
The DC-DC converter output automatically discharges to ground through an internal 450-Ω load when EN_DCDC
goes low or when the UVLO condition is met.
7.3.2 Soft Start
The step-down converter has an internal soft-start circuit that limits the inrush current during start-up. During soft
start, the output voltage ramp-up is controlled as shown in Figure 18.
EN
90%
10%
VOUT
tStart
tRAMP
Figure 18. Soft Start
7.3.3 Linear Regulators
The two linear dropout regulators (LDOs) in the TPS65000-Q1 are designed to provide flexibility in system
design. Each LDO has a separate voltage input and enable signal. The input can be tied to the output of the
step-down converter or the output of another voltage source. Each LDO output discharges to ground
automatically when EN_LDOx goes low.
A resistor network is needed to set the output voltage of the LDOs. Fixed-voltage output versions are also
available; contact a TI sales representative for more information.
The LDOs are general-purpose devices that can handle inputs from 6 V down to 1.6 V. Figure 19 shows the
necessary connections for LDO1. The same architecture applies to LDO2.
12
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Feature Description (continued)
VLDO1
VINLDO1
RLDO1_1
θJA Diode
DISCHG
+
EN_LDO1
CO(LD01)
FB_LDO1
ZLOAD
VREF(LD01)
RLOD1_2
AGND
PGND
A
P
P
A
Figure 19. LDO Block Diagram and Output Voltage Setting
The output voltages of the LDOs are set by Equation 2:
VLDO1 = VFB_LDO1 x
VLDO1 = 0.5V x
(RLDO1_1 + RLDO1_2 )
RLDO1_2
(RLDO1_1 + RLDO1_2 )
RLDO1_2
(2)
The combined resistance of RLDO1_1 and RLDO1_2 should be less than 1 MΩ.
7.3.4 Oscillator and Spread-Spectrum Clock Generation
The TPS65000-Q1 contains an internal oscillator running at a typical frequency of 2.25 MHz. This frequency is
the fundamental switching frequency of the step-down converter when it is running in PWM mode. An additional
circuit in the oscillator block implements spread-spectrum clocking, which modulates the main switching
frequency when the device is in PWM mode. This spread-spectrum oscillation reduces the power that may cause
EMI. When viewed in the frequency domain, the SSC spreads out the frequency that may introduce interference
while simultaneously reducing the power. Because the frequency is continually shifting, the amount of time the
switcher spends at any single frequency is reduced. This reduction in time means that the receiver that may see
the interference has less time to integrate the interference.
Different spin versions of SSC settings are also possible; contact a TI sales representative for more information.
Figure 20 and Figure 21 show the advantage of SSC with the frequency spectrum centering on the nominal
frequency 2.25 MHz. The blue spectrum is the result of the spread change. As shown in the figures, the
harmonic spectrum is attenuated to 10 dB, compared to the same device without SSC.
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Feature Description (continued)
70
70
RBW = 10 kHz
RBW = 10 kHz
60
60
50
50
40
40
30
30
dBmV
dBmV
SSC
ON
20
20
10
10
0
0
-10
-10
-20
-20
-30
Start 1.5 MHz
Stop 150 MHz
Figure 20. SSC On and Off Comparison from 1.5 MHz to
150 MHz
SSC
OFF
-30
Start 1.5 MHz
Stop 3.5 MHz
Figure 21. Zoom In of SSC On and Off Comparison from
1.5 MHz to 3.5 MHz
7.3.5 Power Good
The open-drain PG output is used to indicate the condition of the step-down converter and each LDO. This is a
combined output, with the outputs being compared when the appropriate enable signal is high. The pin is pulled
low when all enabled outputs are greater than 90% of the target voltage, and it is pulled into Hi-Z when an
enabled output is less than 90% of its intended value or when all the enable signals are pulled low.
EN_DCDC
EN_LDO1
EN_LDO2
VDCDC
VDCDC
VDCDC
Target
PG
+
A
VLDO1
VLDO1
Target
VLDO2
VLDO2
Target
+
-
+
-
Figure 22. Power-Good Functionality
14
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7.4 Device Functional Modes
The step-down converter has two modes of operation to maximize efficiency:
1. PFM
– For light loads
– For automatic transition to between this mode and PWM mode automatically when MODE pin is pulled
low over all load ranges
– To increase in output voltage setting by 1%
– For better accuracy
2. PWM
– For moderate to heavy loads
– For a small output ripple
– For maintaining the specified switching frequency variation by pulling the MODE pin high which places
the device in a forced PWM mode over the entire load range.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS65000-Q1 can be used in an automotive-camera sensor module to generate the AVDD, DVDD, and
IOVDD voltage rails. For noise immunity, one of the LDOs should be used to generate the AVDD voltage rail. To
minimize power dissipation, the DC-DC converter should be used to power the DVDD rail because the DVDD rail
normally has a lower operating voltage and higher current consumption.
8.2 Typical Application
TPS65000-Q1
VIN
10mF
A
P
EN_DCDC
VINDCDC
MODE
2.2mH
SW
VDCDC
3.3V
680kW
10mF
P
FB_DCDC
150kW
A
22pF
470kW
VIN
PG
VLDO1
FB_LDO1
470kW
10mF
180kW
EN_LDO1
VDCDC
P
A
EN_LDO2
VINLDO1
VLDO2
FB_LDO2
PGND
AGND
VLDO2
2.8V
820kW
10mF
P
VINLDO2
A
VLDO1
1.8V
P
180kW
A
Figure 23. Typical TPS65000-Q1 Application Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 1.
Table 1. Design Parameters
16
RESOURCES
VOLTAGE
SW
3.3 V
VLDO1
1.8 V
VLDO2
2.8 V
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Filter Design (Inductor and Output Capacitor)
8.2.2.1.1 Inductor Selection
The typical value for the converter inductor is 2.2-μH output inductor. Larger or smaller inductor values in the
range of 1.5 μH to 3.3 μH can optimize the performance of the device for specific operation conditions. The
selected inductor must be rated for its DC resistance and saturation current. The DC resistance of the inductance
influences the efficiency of the converter directly. An inductor with lowest DC resistance must be selected for
highest efficiency. For more information on inductor selection, refer to Choosing Inductors and Capacitors for
DC/DC Converters.
Equation 3 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 4. TI
recommends this because during heavy load transient, the inductor current rises above the calculated value.
V
1 - OUT
VIN
DIL = VOUT x
Lxf
where
•
•
•
f = Switching Frequency (2.25-MHz typical)
L = Inductor Value
ΔIL = Peak-to-peak Inductor Ripple Current
ILmax = IOUTmax
(3)
DI
+ L
2
where
•
ILmax = Maximum Inductor Current
(4)
The highest inductor current occurs at maximum VIN.
Open-core inductors have a soft saturation characteristic and can usually handle higher inductor currents versus
a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Consider that the core material from inductor to inductor differs and impacts the
efficiency especially at high-switching frequencies.
The step down converter has internal loop compensation. TI designed the internal loop compensation to work
with a certain output filter corner frequency calculated as in Equation 5:
1
fC =
with L = 2.2mH, COUT = 10mF
2p L x COUT
(5)
The selection of external L-C filter must be coped with Equation 5. The product of L × COUT must be constant
while selecting smaller inductor or increasing output capacitor value.
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8.2.2.1.2 Output Capacitor Selection
The advanced fast response voltage mode control scheme of the converter allows the use of small ceramic
capacitors with a typical value of 22 μF, without having large output voltage under and overshoots during heavy
load transients. TI recommends ceramic capacitors with low ESR values because they result in lowest output
voltage ripple. See for the TI-recommended components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. The RMS ripple current is calculated as in Equation 6:
V
1 - OUT
VIN
1
IRMSCout = VOUT x
x
Lxf
2x 3
(6)
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the
output capacitor as calculated in Equation 7:
V
1 - OUT
æ
ö
VIN
1
DVOUT = VOUT x
x ççç
+ ESR÷÷÷
Lx f
èç 8 x COUT x f
ø÷
(7)
Where the highest output voltage ripple occurs at the highest input voltage VIN.
At light load currents, the converter operates in power save mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
The adjustable output voltage of the DC-DC converter is calculated by Equation 1 in the Step-Down Converter.
To keep the external resistor divider network robust against noise, an external feed forward capacitor is required
for optimum load transient response. The value of feed forward capacitor must be in the range between 22 pF
and 33 pF provided the equivalent resistance of RDC1 || RDC2 in Equation 1 is approximately 300 kΩ. Scale
change on RDC1||RDC2 would apply a scale change to the feed forward capacitor to keep the RC product a
constant.
8.2.2.1.3 Input Capacitor Selection
Due to the DC-DC converter having a pulsating input current, a low-ESR input capacitor is required for best input
voltage filtering, and minimizing the interference with other circuits caused by high-input voltage spikes . Place
the input capacitor as close as possible to the VINDCDC pin with the clean GND connection. Do the same for
the output capacitor and the inductor. The converters require a ceramic input capacitor of 10 μF. The input
capacitor can increase without any limit for better input voltage filtering.
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VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = GND
VINDCDC = 3.6 V to 4.2V to 3.6V
o
TA = 25 C
VDCDC = 1.8V
DCDC Load Current = 50mA
Mode = VINDCDC
Ch2: VDCDC
20mV/div
Ch1: VINDCDC
500mV/div
VINDCDC = 3.6 V to 4.2V to 3.6V
TA = 25oC
Ch2: VDCDC
20mV/div
Ch1: VINDCDC
500mV/div
8.2.3 Application Curves
t - Time - 100ms/div
Figure 24. Line Transient Response (DC-DC PFM Mode)
Figure 25. Line Transient Response (DC-DC PWM Mode)
Ch2: DCDC Load Current
200mA/div
Ch1: VDCDC
50mV/div
VINDCDC = 6V
VINLDOx = 1.6 V to 2.3V to 1.6V
o
TA = 25 C
VLDOx = 1.007V
LDOx Load Current = 1mA
EN_DCDC = GND
VINDCDC = 3.6V
o
TA = 25 C
VDCDC = 1.8V
DCDC Load Current = 60mA to 540 mA
Mode = GND
t - Time - 100ms/div
Figure 27. Load Transient Response (DC-DC PFM Mode)
Ch1: LDOx Load Current
50mA/div
t - Time - 100ms/div
Figure 26. Line Transient Response (LDOx)
VINDCDC = 3.6V
o
TA = 25 C
VDCDC = 1.8V
DCDC Load Current = 60mA to 540 mA
Mode = VINDCDC
Ch2: VLDOx
20mV/div
Ch2: DCDC Load Current
200mA/div
Ch1: VDCDC
50mV/div
Ch2: VLDOx
20mV/div
Ch1: VINLDOx
500mV/div
t - Time - 100ms/div
VINDCDC = 3.6V
VINLDOx = 3.6V
o
TA = 25 C
LDOx Load Current = 15mA to 100mA
VLDOx = 1.2V
EN_DCDC = GND
t - Time - 100ms/div
t - Time - 200ms/div
Figure 28. Load Transient Response (DC-DC PWM Mode)
Figure 29. Load Transient Response (LDOx)
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9 Power Supply Recommendations
The device is designed to operate with an input voltage supply range from 1.6 V to 6 V. This input supply can be
from a DC supply, or other externally regulated supply. If the input supply is located more than a few inches from
the TPS65000-Q1, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 10 µF is a typical choice.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
The VINDCDC and VINLDOx pins must be bypassed to ground with a low-ESR ceramic bypass capacitor. TI
recommends the typical bypass capacitance is 10 μF and 2.2 μF with a X5R dielectric.
The optimum placement is closest to the VINDCDCx and VINLDOx pins of the device. Minimize the loop area
formed by the bypass capacitor connection, the VINDCDC and VINLDO pins, and the thermal pad of the
device.
The thermal pad must be tied to the PCB ground plane with multiple vias.
The traces of the VLDOx and VDCDCx pins (feedback pins) must be routed away from any potential noise
source to avoid coupling.
VODC output capacitance must be placed immediately at the VODC pin. Excessive distance between the
capacitance and DCDCx pin may cause poor converter performance.
AGND star back to PGND as close to the device as possible.
DGND connect to the thermal pad
10.2 Layout Examples
Thermal pad
Vias to GND
plane
Figure 30. Layout Recommendation
Bypass capacitors to GND for VIN pins
Vias to
GND
Figure 31. Bypass Capacitor and Via Placement Recommendation
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
Choosing Inductors and Capacitors for DC/DC Converters
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65000TRTERQ1
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
SJO
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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