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TPS65023QRHARQ1

TPS65023QRHARQ1

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VQFN-40_6X6MM-EP

  • 描述:

    IC BAT PWR MGMT LI-ION 1C 40VQFN

  • 数据手册
  • 价格&库存
TPS65023QRHARQ1 数据手册
Order Now Product Folder Support & Community Tools & Software Technical Documents TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 TPS65023-Q1 Power Management IC (PMIC) With 3 DC/DCs, 3 LDOs, I2C Interface and DVS 1 Features 2 Applications • • • • • • 1 • • • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C4A (RHA Package) or C5 (RSB Package) 1.5 A, 90% Efficient Step-Down Converter for Processor Core (VDCDC1) 1.2 A, Up to 95% Efficient Step-Down Converter for System Voltage (VDCDC2) 1 A, 92% Efficient Step-Down Converter for Memory Voltage (VDCDC3) 30 mA LDO/Switch for Real Time Clock (VRTC) 2 × 200 mA General-Purpose Low Dropout (LDO) Dynamic Voltage Management for Processor Core Preselectable LDO Voltage Using Two Digital Input Pins Externally Adjustable Reset Delay Time Battery Backup Functionality Separate Enable Pins for Inductive Converters I2C-Compatible Serial Interface 85-μA Quiescent Current Low-Ripple Pulse-Frequency Modulation (PFM) Mode Thermal Shutdown Protection Automotive Clusters Automotive Infotainment Systems Digital Radios Supply DaVinci™ Digital Signal Processor (DSP) Family Solutions 3 Description The TPS65023-Q1 device is an integrated powermanagement integrated circuit (IC) for applications powered by one Li-Ion or Li-Polymer cell, which require multiple power rails. The TPS65023-Q1 device provides three highly efficient, step-down converters targeted at providing the core voltage, peripheral, input and output (I/O), and memory rails in a processor-based system. The core converter allows for on-the-fly voltage changes through a serial interface, allowing the system to implement dynamic power savings. All three step-down converters enter a low-power mode at light load for maximum efficiency across the widest possible range of load currents. Device Information(1) PART NUMBER TPS65023-Q1 PACKAGE BODY SIZE (NOM) VQFN (40) 6.00 mm × 6.00 mm WQFN (40) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic TPS65023-Q1 Example SoC 2.2 µH Monitored Voltage1 R1 DCDC1 R2 PWRFAIL + ± R4 LOWBATT + ± Monitored Voltage2 R3 CORE 22 µF 2.2 µH 1.8-V IO Domain DCDC2 22 µF 3.3-V IO Domain LDO1 2.2 µF BACKUP RTC AND RESPWRON VBACKUP 2.2 µF System Reset Memory 2.2 µH DCDC3 DCDC1_EN DCDC2_EN DCDC3_EN LDO_EN DEFDCDC1 DEFDCDC2 DEFDCDC3 22 µF Memory Enables and Vout Select LDO1 Peripherals 2.2 µF System Platform 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 1 1 1 2 3 3 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Timing Requirements .............................................. 10 Typical Characteristics ............................................ 11 Detailed Description ............................................ 16 8.1 8.2 8.3 8.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 16 16 17 18 8.5 Programming........................................................... 22 8.6 Register Maps ......................................................... 24 9 Application and Implementation ........................ 31 9.1 Application Information............................................ 31 9.2 Typical Application .................................................. 33 10 Power Supply Recommendations ..................... 37 11 Layout................................................................... 38 11.1 Layout Guidelines ................................................. 38 11.2 Layout Example .................................................... 38 12 Device and Documentation Support ................. 39 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support...................................................... Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 39 39 39 39 39 39 39 13 Mechanical, Packaging, and Orderable Information ........................................................... 39 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (March 2016) to Revision F Page • Changed the title of the data sheet ........................................................................................................................................ 1 • Changed all references of PowerPAD to thermal pad............................................................................................................ 4 • Changed the units of the current and peak current parameters from V to mA in the Absolute Maximum Ratings table ...... 5 • Added the Receiving Notification of Documentation Updates section ................................................................................. 39 Changes from Revision D (September 2011) to Revision E • 2 Page Added Device Information table, Table of Contents, Revision History section, Pin Configuration and Functions section, Specifications section, ESD Ratings table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 5 Description (continued) The TPS65023-Q1 device also integrates two general-purpose 200-mA LDO voltage regulators, which are enabled with an external input pin. Each LDO operates with an input voltage range between 1.5 V and 6.5 V, allowing them to be supplied from one of the step-down converters or directly from the battery. The default output voltage of the LDOs can be digitally set to four different voltage combinations using the DEFLDO1 and DEFLDO2 pins. The serial interface can be used for dynamic voltage scaling, masking interrupts, or for disabling, enabling, and setting the LDO output voltages. The interface is compatible with the fast- or standard-mode I2C specifications, allowing transfers at up to 400 kHz. The TPS65023-Q1 device operates over a free-air temperature of –40°C to 125°C. 6 Pin Configuration and Functions AGND1 LOWBAT_SNS PWRFAIL_SNS VCC VINDCDC2 L2 PGND2 VDCDC2 DEFDCDC2 PWRFAIL 40 39 38 37 36 35 34 33 32 31 RHA and RSB Packages 40-Pin VQFN and WQFN Top View DEFDCDC3 1 30 SCLK VDCDC3 2 29 SDAT PGND3 3 28 INT L3 4 27 RESPWRON VINDCDC3 5 26 TRESPWRON VINDCDC1 6 25 DCDC1_EN L1 7 24 DCDC2_EN PGND1 8 23 DCDC3_EN VDCDC1 9 22 LDO_EN 10 21 LOW_BAT 11 12 13 14 15 16 17 18 19 20 DEFLD01 DEFLD02 VSYSIN VBACKUP VRTC AGND2 VLDO2 VINLDO VLDO1 Pad HOT_RESET DEFDCDC1 Thermal Not to scale Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 3 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com Pin Functions PIN NAME NO. I/O DESCRIPTION SWITCHING REGULATOR AGND1 40 — Analog ground. All analog ground pins are connected internally on the chip AGND2 17 — Analog ground. All analog ground pins are connected internally on the chip DCDC1_EN 25 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator DCDC2_EN 24 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator DCDC3_EN 23 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator DEFDCDC1 10 I Input for signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V. DEFDCDC1 can also be connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V. DEFDCDC2 32 I Input for signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V. DEFDCDC2 can also be connected to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V. DEFDCDC3 1 I Input for signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V. DEFDCDC3 can also be connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V. L1 7 — Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here. L2 35 — Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here L3 4 — Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here PGND1 8 — Power ground for VDCDC1 converter PGND2 34 — Power ground for VDCDC2 converter PGND3 3 — Power ground for VDCDC3 converter VCC 37 I Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters. VCC must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. VCC also supplies serial interface block. VDCDC1 9 I VDCDC1 feedback voltage sense input. Connect directly to VDCDC1 VDCDC2 33 I VDCDC2 feedback voltage sense input. Connect directly to VDCDC2 VDCDC3 2 I VDCDC3 feedback voltage sense input. Connect directly to VDCDC3 VINDCDC1 6 I Input for VDCDC1 step-down converter. VINDCDC1 must be connected to the same voltage supply as VINDCDC2, VINDCDC3, and VCC VINDCDC2 36 I Input for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage supply as VINDCDC1, VINDCDC3, and VCC VINDCDC3 5 I Input for VDCDC3 step-down converter. VINDCDC3 must be connected to the same voltage supply as VINDCDC1, VINDCDC2, and VCC Thermal pad — — DEFLD01 12 I Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2 DEFLD02 13 I Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2 LDO_EN 22 I Enable input for LDO1 and LDO2. A logic high enables the LDOs, a logic low disables the LDOs VBACKUP 15 I Connect the backup battery to this input pin VINLDO 19 I Input for LDO1 and LDO2 VLDO1 20 O Output of LDO1 VLDO2 18 O Output of LDO2 VRTC 16 O Output of the LDO/switch for the real time clock VSYSIN 14 I Input of system voltage for VRTC switch Connect the thermal pad to analog ground LDO REGULATOR 2 CONTROL AND I C HOT_RESET 11 I Push-button input that reboots or wakes up the processor through RESPWRON output pin INT 28 O Open drain output LOW_BAT 21 O Open-drain output of LOW_BAT comparator LOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT output PWRFAIL 31 O Open-drain output. Active low when PWRFAIL comparator indicates low VBAT condition 4 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 Pin Functions (continued) PIN NAME I/O NO. DESCRIPTION PWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL output RESPWRON 27 O Open-drain system reset output SCLK 30 I Serial interface clock line SDAT 29 I/O TRESPWRON 26 I Serial interface data/address Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF → 100 ms. 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX –0.3 7 V L1, L2, L3, PGND1, PGND2, PGND3, VINDCDC1, VINDCDC2, VINDCDC3 2000 mA All pins except L1, L2, L3, PGND1, PGND2, PGND3, VINDCDC1, VINDCDC2, VINDCDC3 1000 mA 125 °C 150 °C 150 °C Input voltage (2) All pins except AGND and PGND Current Peak current Operating free-air temperature –40 Maximum junction temperature, TJ(MAX) Storage temperature, Tstg (1) (2) –65 UNIT Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltages are in respect to AGND. 7.2 ESD Ratings VALUE UNIT TPS65023-Q1 IN RHA PACKAGE V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±2000 Charged-device model (CDM), per AEC Q100-011 ±750 Machine model (MM) ±50 V TPS65023-Q1 IN RSB PACKAGE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±2000 Charged-device model (CDM), per AEC Q100-011 ±1000 Machine model (MM) ±100 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 5 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC Input voltage range step-down converters MAX UNIT 2.5 6 Output voltage range for VDCDC1 step-down converter (1) 0.6 VCC Output voltage range for VDCDC2 step-down converter (1) 0.6 VCC Output voltage range for VDCDC3 step-down converter (1) 0.6 VCC VINLDO Input voltage range for LDOs VINLDO1, VINLDO2 1.5 6.5 VO Output voltage range for LDOs VLDO1, VLDO2 1 VCC V IO(DCDC1) Output current L1 1500 mA VO VCC, VINDCDC1, VINDCDC2, VINDCDC3 NOM Inductor at L1 (2) 1.5 CI(DCDC1) Input capacitor at VINDCDC1 (2) 10 CO(DCDC1) Output capacitor at VDCDC1 (2) 10 22 IO(DCDC2) Output current at L2 Inductor at L2 (2) 1.5 2.2 CI(DCDC2) Input capacitor at VINDCDC2 (2) 10 CO(DCDC2) Output capacitor at VDCDC2 (2) 10 22 IO(DCDC3) Output current at L3 Inductor at L3 (2) 1.5 2.2 Input capacitor at VINDCDC3 (2) 10 CI(DCDC3) 2.2 V V μH μF μF 1200 mA μH μF μF 1000 (2) V mA μH μF CO(DCDC3) Output capacitor at VDCDC3 CI(VCC) Input capacitor at VCC (2) 10 1 μF CI(VINLDO) Input capacitor at VINLDO (2) 1 μF (2) CO(VLDO1-2) Output capacitor at VLDO1, VLDO2 IO(VLDO1-2) Output current at VLDO1, VLDO2 CO(VRTC) Output capacitor at VRTC (2) 4.7 TA Operating ambient temperature –40 TJ Operating junction temperature –40 22 2.2 μF 200 mA μF Resistor from VINDCDC3, VINDCDC2, and VINDCDC1 to VCC used for filtering (3) (1) (2) (3) μF 1 125 °C 125 °C 10 Ω When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1 See Detailed Design Procedure for more information. Up to 3 mA can flow into VCC when all three converters are running in PWM. This resistor causes the UVLO threshold to be shifted accordingly. 7.4 Thermal Information TPS65023-Q1 THERMAL METRIC (1) RHA (VQFN) RSB (WQFN) UNIT 40 PINS 40 PINS RθJA Junction-to-ambient thermal resistance 31.6 34.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 18.2 14.7 °C/W RθJB Junction-to-board thermal resistance 6.6 6.6 °C/W ψJT Junction-to-top characterization parameter 0.2 0.2 °C/W ψJB Junction-to-board characterization parameter 6.5 6.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 1.3 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 7.5 Electrical Characteristics VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CONTROL SIGNALS: SCLK, SDAT (INPUT), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2 VIH High-level input voltage Resistor pullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 1.3 VCC V VIH High-level input voltage, SDAT Resistor pullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 1.45 VCC V VIL Low-level input voltage Resistor pullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 0 0.4 V IH Input bias current 0.1 μA V 0.01 CONTROL SIGNALS: HOT_RESET VIH High-level input voltage 1.3 VCC VIL Low-level input voltage 0 0.4 V IIB Input bias current 0.01 0.1 μA tglitch Deglitch time at HOT_RESET 30 35 ms 6 V 25 CONTROL SIGNALS: LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (OUTPUT) VOH High-level output voltage VOL Low-level output voltage IIL = 5 mA Duration of low pulse at RESPWRON External capacitor 1 nF Reset power-on threshold 0 0.3 100 V ms VRTC falling –3% 2.4 3% VRTC rising –3% 2.52 3% V SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3 I(q) II I(q) All three DC-DC converters enabled, zero load, no switching, and LDOs enabled VCC = 3.6 V, VBACKUP = 3 V, VSYSIN = 0 V 85 100 All three DC-DC converters enabled, zero load, no switching, and LDOs off VCC = 3.6 V, VBACKUP = 3 V, VSYSIN = 0 V 78 90 DCDC1 and DCDC2 converters enabled, zero load, no switching, and LDOs off VCC = 3.6 V, VBACKUP = 3 V, VSYSIN = 0 V 57 70 DCDC1 converter enabled, zero load, no switching, and LDOs off VCC = 3.6 V, VBACKUP = 3 V, VSYSIN = 0 V 43 55 All three DC-DC converters enabled and running in PWM, LDOs off VCC = 3.6 V, VBACKUP = 3 V, VSYSIN = 0 V 2 3 DCDC1 and DCDC2 converters enabled and running in PWM, LDOs off VCC = 3.6 V, VBACKUP = 3 V, VSYSIN = 0 V 1.5 2.5 DCDC1 converter enabled and running in PWM, LDOs off VCC = 3.6 V, VBACKUP = 3 V, VSYSIN = 0 V 0.85 2 VCC = 3.6 V, VBACKUP = 3 V, VSYSIN = 0 V 23 33 VCC = 2.6 V, VBACKUP = 3 V, VSYSIN = 0 V 3.5 5 Operating quiescent current, PFM Current into VCC, PWM Quiescent current All converters disabled, LDOs off μA VCC = 3.6 V, VBACKUP = 0 V, VSYSIN = 0 V mA μA 43 SUPPLY PINS: VBACKUP, VSYSIN, VRTC I(q) Operating quiescent current VBACKUP = 3 V, VSYSIN = 0 V, VCC = 2.6 V, current into VBACKUP I(SD) Operating quiescent current VRTC LDO output voltage Output current for VRTC IO VO 20 33 μA VBACKUP < V_VBACKUP, current into VBACKUP 2 3 μA VSYSIN = VBACKUP = 0 V, IO = 0 mA 3 VSYSIN < 2.57 V and VBACKUP < 2.57 V 30 mA VRTC short-circuit current limit VRTC = GND, VSYSIN = VBACKUP = 0 V 100 mA Maximum output current at VRTC for RESPWRON = 1 VRTC > 2.6 V, VCC = 3 V, VSYSIN = VBACKUP = 0 V Output voltage accuracy for VRTC VSYSIN = VBACKUP = 0 V, IO = 0 mA V 30 –1% mA 1% Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 7 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com Electrical Characteristics (continued) VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER Ilkg TEST CONDITIONS MIN Line regulation for VRTC VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA –1% Load regulation VRTC IO = 1 mA to 30 mA, VSYSIN = VBACKUP = 0 V –3% Regulation time for VRTC Load change from 10% to 90% Input leakage current at VSYSIN VSYSIN < V_VSYSIN TYP MAX UNIT 1% 1% 10 μs 2 μA rDS(on) of VSYSIN switch 12.5 Ω rDS(on) of VBACKUP switch 12.5 Ω Input voltage range at VBACKUP (1) 2.73 3.75 V Input voltage range at VSYSIN (1) 2.73 3.75 V VSYSIN threshold VSYSIN falling –3% 2.55 3% V VSYSIN threshold VSYSIN rising –3% 2.65 3% V VBACKUP threshold VBACKUP falling –3% 2.55 3% V VBACKUP threshold VBACKUP falling –3% 2.65 3% V SUPPLY PIN: VINLDO I(q) Operating quiescent current Current per LDO into VINLDO 16 30 μA I(SD) Shutdown current Total current for both LDOs into VINLDO, VINLDO = 0 V 0.1 1 μA VDCDC1 STEP-DOWN CONVERTER IO Maximum output current I(SD) Shutdown supply current in VINDCDC1 DCDC1_EN = GND 0.1 1 μA rDS(on) P-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 125 261 mΩ Ilkg P-channel leakage current VCC = 6 V 2 μA rDS(on) N-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 130 260 mΩ Ilkg N-channel leakage current V(DS) = 6 V μA Forward current limit (P-channel and N-channel) 2.5 V < VI(MAIN) < 6 V fS 1500 Oscillator frequency Fixed output voltage FPWMDCDC1 = 0 mA 7 10 1.9 2.19 2.6 A 1.95 2.25 2.55 MHz VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.5 A –2% 2% VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.5 A –1% 1% Adjustable output voltage with resistor divider at DEFDCDC1, FPWMDCDC1 = 0 VCC = VDCDC1 + 0.3 V (minimum 2.5 V) to 6 V, 0 mA ≤ IO ≤ 1.2 A –2% 2% Adjustable output voltage with resistor divider at DEFDCDC1, FPWMDCDC1 = 1 VCC = VDCDC1 + 0.3 V (minimum 2.5 V) to 6 V, 0 mA ≤ IO ≤ 1.2 A –1% 1% Line regulation VCC = VDCDC1 + 0.3 V (minimum. 2.5 V) to 6 V, IO = 10 mA 0 %/V Load regulation IO = 10 mA to 1200 mA 0.25 %/A Soft-start ramp time VDCDC1 ramping from 5% to 95% of target value 750 μs 1 MΩ Fixed output voltage FPWMDCDC1 = 1 All VDCDC1 Internal resistance from L1 to GND VDCDC1 discharge resistance DCDC1 discharge = 1 Ω 300 VDCDC2 STEP-DOWN CONVERTER DEFDCDC2 = GND 1200 VCC = 3.6 V, 3.3 V – 1% ≤ VDCDC2 ≤ 3.3 V + 1% 1000 IO Maximum output current I(SD) Shutdown supply current in VINDCDC2 DCDC2_EN = GND 0.1 1 μA rDS(on) P-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 140 300 mΩ Ilkg P-channel leakage current VCC = 6 V 2 μA rDS(on) N-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 150 297 mΩ Ilkg N-channel leakage current V(DS) = 6 V μA ILIMF Forward current limit (P-channel and N-channel) 2.5 V < VCC < 6 V fS Oscillator frequency Fixed output voltage FPWMDCDC2=0 (1) 8 mA 7 10 1.7 1.94 2.2 A 1.95 2.25 2.55 MHz VDCDC2 = 1.8 V VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.2 A –2% 2% VDCDC2 = 3.3 V VCC = 3.7 V to 6 V, 0 mA ≤ IO ≤ 1.2 A –1% 1% Based on the requirements for the Intel PXA270 processor. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 Electrical Characteristics (continued) VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER Fixed output voltage FPWMDCDC2=1 TEST CONDITIONS MIN TYP MAX VDCDC2 = 1.8 V VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.2 A –2% 2% VDCDC2 = 3.3 V UNIT VCC = 3.7 V to 6 V, 0 mA ≤ IO ≤ 1.2 A –1% 1% Adjustable output voltage with resistor divider at DEFDCDC2 FPWMDCDC2 = 0 VCC = VDCDC2 + 0.3 V (minimum 2.5 V) to 6 V, 0 mA ≤ IO ≤ 1 A –2% 2% Adjustable output voltage with resistor divider at DEFDCDC2, FPWMDCDC2 = 1 VCC = VDCDC2 + 0.3 V (minimum 2.5 V) to 6 V, 0 mA ≤ IO ≤ 1 A –1% 1% Line regulation VCC = VDCDC2 + 0.3 V (minimum. 2.5 V) to 6 V, IO = 10 mA 0 %/V Load regulation IO = 10 mA to 1000 mA 0.25 %/A Soft-start ramp time VDCDC2 ramping from 5% to 95% of target value 750 μs 1 MΩ Internal resistance from L2 to GND VDCDC2 discharge resistance DCDC2 discharge = 1 Ω 300 VDCDC3 STEP-DOWN CONVERTER DEFDCDC3 = GND 1000 IO Maximum output current I(SD) Shutdown supply current in VINDCDC3 DCDC3_EN = GND 0.1 1 μA rDS(on) P-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 310 698 mΩ Ilkg P-channel leakage current VCC = 6 V 0.1 2 μA rDS(on) N-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 220 503 mΩ Ilkg N-channel leakage current V(DS) = 6 V μA Forward current limit (P-channel and N-channel) 2.5 V < VCC < 6 V fS VCC = 3.6 V, 3.3 V – 1% ≤ VDCDC3 ≤ 3.3 V + 1% Oscillator frequency mA 525 7 10 1.28 1.49 1.69 A 1.95 2.25 2.55 MHz Fixed output voltage FPWMDCDC3=0 VDCDC3 = 1.8 V VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1 A –2% 2% VDCDC3 = 3.3 V VCC = 3.6 V to 6 V, 0 mA ≤ IO ≤ 1 A –1% 1% Fixed output voltage FPWMDCDC3=1 VDCDC3 = 1.8 V VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1 A –2% 2% VDCDC3 = 3.3 V VCC = 3.6 V to 6 V, 0 mA ≤ IO ≤ 1 A –1% 1% Adjustable output voltage with resistor divider at DEFDCDC3 FPWMDCDC3 = 0 VCC = VDCDC3 + 0.5 V (minimum 2.5 V) to 6 V, 0 mA ≤ IO ≤ 800 mA –2% 2% Adjustable output voltage with resistor divider at DEFDCDC3, FPWMDCDC3 = 1 VCC = VDCDC3 + 0.5 V (minimum 2.5 V) to 6 V, 0 mA ≤ IO ≤ 800 mA –1% 1% Line regulation VCC = VDCDC3 + 0.3 V (minimum. 2.5 V) to 6 V, IO = 10 mA 0 %/V Load regulation IO = 10 mA to 1000 mA 0.25 %/A Soft-start ramp time VDCDC3 ramping from 5% to 95% of target value 750 μs 1 MΩ Internal resistance from L3 to GND VDCDC3 discharge resistance DCDC3 discharge = 1 Ω 300 VLDO1 AND VLDO2 LOW DROPOUT REGULATORS VI Input voltage range for LDO1, 2 VO(LD01) LDO1 output voltage range VO(LDO2) LDO2 output voltage range IO Maximum output current for LDO1, LDO2 I(SC) LDO1 and LDO2 short circuit current limit Minimum voltage drop at LDO1, LDO2 VCC = 1.8 V, VO = 1.3 V 1.5 6.5 V 1 3.15 V 1 3.3 V 200 VCC = 1.5 V, VO = 1.3 V mA 120 V(LDO1) = GND, V(LDO2) = GND 400 IO = 50 mA, VINLDO = 1.8 V 120 IO = 50 mA, VINLDO = 1.5 V 65 IO = 200 mA, VINLDO = 1.8 V 150 IO = 10 mA –2% 1% Line regulation for LDO1, LDO2 VINLDO = VLDO1,2 + 0.5 V (minimum 2.5 V) to 6.5 V, IO = 10 mA –1% 1% Load regulation for LDO1, LDO2 IO = 0 mA to 50 mA –1% Regulation time for LDO1, LDO2 Load change from 10% to 90% 1% 10 Submit Documentation Feedback Product Folder Links: TPS65023-Q1 mV 300 Output voltage accuracy for LDO1, LDO2 Copyright © 2009–2018, Texas Instruments Incorporated mA μs 9 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com Electrical Characteristics (continued) VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.3 VCC V 0 0.1 V 0.05 μA ANALOG SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3 VIH High-level input voltage (2) VIL Low-level input voltage Input bias current 0.001 THERMAL SHUTDOWN T(SD) Thermal shutdown Increasing junction temperature 160 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C INTERNAL UNDERVOLTAGE LOCK OUT UVLO Internal UVLO VUVLO_HYST Internal UVLO comparator hysteresis VCC falling –2% 2.35 2% V 120 mV VOLTAGE DETECTOR COMPARATORS Comparator threshold (PWRFAIL_SNS, LOWBAT_SNS) Falling threshold Hysteresis Propagation delay –2% 1 2% V 40 50 60 mV 10 μs 25-mV overdrive POWER GOOD VPGOODF VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, decreasing –12% –10% –8% VPGOODR VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, increasing –7% –5% –3% (2) The input voltage can go as high as 6 V. If the input voltage exceeds VCC, an input current of (V(PB_IN) - 0.7 V - VCC) / 10 kΩ flows. 7.6 Timing Requirements MIN MAX UNIT 400 kHz fMAX Clock frequency twH(HIGH) Clock high time 600 twL(LOW) Clock low time 1300 tr DATA and CLK rise time 300 ns tf DATA and CLK fall time 300 ns th(STA) Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns th(DATA) Setup time for repeated START condition 600 ns th(DATA) Data input hold time 300 ns tsu(DATA) Data input setup time 300 ns tsu(STO) STOP condition setup time 600 ns t(BUF) Bus free time 1300 ns ns ns DATA t(BUF) th(STA) t(LOW) tf tr CLK th(STA) t(HIGH) tsu(STA) th(DATA) STO STA tsu(STO) tsu(DATA) STA STO Figure 1. Serial Interface Timing Diagram 10 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 7.7 Typical Characteristics Table 1. EVM Parameters for Typical Characteristics Measurement (1) CONVERTER INDUCTOR OUTPUT CAPACITOR OUTPUT CAPACITOR VALUE VDCDC1 VLCF4020-2R2 C2012X5R0J106M 2 × 10 μF VDCDC2 VLCF4020-2R2 C2012X5R0J106M 2 × 10 μF VDCDC3 VLF4012AT-2R2M1R5 C2012X5R0J106M 2 × 10 μF (1) Graphs were taken using the evaluation module (EVM), TPS65023EVM-205, with the inductor and output capacitor combinations in Table 1. See TPS65023EVM, User's Guide for more information. Table 2. Table Of Graphs FIGURE Efficiency vs Output current Output voltage vs Output current at 85°C Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7 Figure 8, Figure 9 Line transient response Figure 10, Figure 11, Figure 12 Load transient response Figure 13, Figure 14, Figure 15 VDCDC2 PFM operation Figure 16 VDCDC2 low ripple PFM operation Figure 17 VDCDC2 PWM operation Figure 18 Startup VDCDC1, VDCDC2 and VDCDC3 Figure 19 Startup LDO1 and LDO2 Figure 20 Line transient response Figure 21, Figure 22, Figure 23 Load transient response Figure 24, Figure 25, Figure 26 100 100 VI = 2.5 V 90 80 90 VI = 3.6 V 80 VI = 4.2 V 60 VI = 5 V 40 VI = 3.6 V 60 50 40 VI = 4.2 V 30 30 TA = 25°C VO = 1.2 V PWM/PFM Mode 20 10 0 0.01 VI = 2.5 V 70 Efficiency - % Efficiency - % 70 50 TA = 25°C VO = 1.2 V PWM Mode 0.1 1 10 100 IO - Output Current - mA 1k 20 VI = 5 V 10 10 k Figure 2. DCDC1: Efficiency vs Output Current 0 0.01 0.1 1 10 100 IO - Output Current - mA 1k 10 k Figure 3. DCDC1: Efficiency vs Output Current Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 11 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 100 90 www.ti.com 100 VI = 2.5 V VI = 3.6 V 80 80 60 VI = 5 V 40 30 TA = 25°C VO = 1.8 V PWM/PFM Mode 10 0.1 100 1 10 100 IO - Output Current - mA 1k 0 0.01 10 k VI = 2.5 V Efficiency - % Efficiency - % VI = 5 V 40 30 0.1 1 10 100 IO - Output Current - mA 1k 10 k VI = 2.5 V 60 50 VI = 4.2 V 40 VI = 5 V 20 TA = 25°C VO = 1.8 V PWM/PFM Mode 10 1k VI = 3.6 V 30 20 10 0 0.01 10 k Figure 6. DCDC3: Efficiency vs Output Current 0.1 1 10 100 IO - Output Current - mA 1k 10 k Figure 7. DCDC3: Efficiency vs Output Current TA = 85°C DEFDCDC2 = VINDCDC2 3.354 TA = 85°C DEFDCDC3 = VINDCDC3 3.334 3.314 VO - Output Voltage - V 3.334 VI = 3.8 V 3.294 VI = 3.7 V 3.274 3.234 0.1 TA = 25°C VO = 1.8 V PWM Mode 70 VI = 4.2 V 60 3.254 1 10 100 IO - Output Current - mA Figure 5. DCDC2: Efficiency vs Output Current 80 3.354 0.1 100 80 0 0.01 VI = 5 V 10 90 50 VI = 4.2 V 40 90 VI = 3.6 V 70 VO - Output Voltage - V 50 20 Figure 4. DCDC2: Efficiency vs Output Current VI = 3.5 V VI = 3.6 V 1 IO - Output Current - A 3.314 VI = 4 V 3.294 3.274 3.254 10 Figure 8. DCDC2: Output Voltage vs Output Current At 85°C 12 60 30 20 0 0.01 VI = 2.5 V VI = 3.6 V 70 VI = 4.2 V Efficiency - % Efficiency - % 70 50 TA = 25°C VO = 1.8 V PWM Mode 90 3.234 0.1 VI = 3.5 V VI = 3.6 V VI = 3.9 V VI = 3.8 V VI = 3.7 V 1 IO - Output Current - A 10 Figure 9. DCDC3: Output Voltage vs Output Current At 85°C Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 VINDCDC1 VDCDC1 IO = 100 mA VINDCDC1 = 3.7 V - 4.7 V DEFDCDC1 = VINDCDC1 PWW Mode VINDCDC2 C1 High 4.71 V C1 High 4.01 V C1 Low 3.68 V C1 Low 3.02 V C2 Pk-Pk 28.5 mV C2 Mean 1.18925 V Figure 10. VDCDC1 Line Transient Response C2 Pk-Pk 48.9 mV VDCDC2 C2 Mean 1.81053 V IO = 100 mA VINDCDC2 = 3 V - 4 V DEFDCDC2 = GND PWW Mode Figure 11. VDCDC2 Line Transient Response VINDCDC3 C1 High 4.20 V C1 Low 3.59 V VDCDC3 IO = 100 mA VINDCDC3 = 3.6 V - 4.2 V DEFDCDC3 = VINDCDC3 PWW Mode C2 Pk-Pk 60.4 mV C2 Mean 3.28264 V Figure 12. VDCDC3 Line Transient Response Figure 13. VDCDC1 Load Transient Response VDCDC3 = 3.3 V @ 50 mV/Div (AC Coupled) ILOAD @ 500 mA/Div 800 mA 100 mA VIN = 3.8 V Figure 14. VDCDC2 Load Transient Response TIMESCALE = 50 ms/Div Figure 15. VDCDC3 Load Transient Response Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 13 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com Figure 16. VDCDC2 Output Voltage Ripple Figure 17. VDCDC2 Output Voltage Ripple Figure 18. VDCDC2 Output Voltage Ripple Figure 19. Startup VDCDC1, VDCDC2, and VDCDC3 ENABLE Ch1 = VI Ch2 = VO IO = 25 mA VO = 1.1 V o TA = 25 C C1 High 3.83 V C1 Low 3.29 V LDO1 C2 PK-PK 6.2 mV C2 Mean 1.09702 V LDO2 Figure 20. Startup LDO1 and LDO2 14 Figure 21. LDO1 Line Transient Response Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 Ch1 = VI Ch2 = VO IO = 25 mA VO = 3.3 V TA = 25oC C1 High 4.51 V IO = 10 mA VO = 3 V o TA = 25 C Ch1 = VI Ch2 = VO C1 Low 3.99 V C1 Low 3.28 V C2 PK-PK 6.1 mV C2 PK-PK 22.8 mV C2 Mean 3.29828 V C2 Mean 2.98454 V Figure 22. LDO2 Line Transient Response Figure 23. VRTC Line Transient Response C4 High 47.8 mA C4 High 48.9 mA C4 Low -2.9 mA C4 Low 2.1 mA C2 PK-PK 40.4 mV C2 PK-PK 42.5 mV C2 Mean 3.29821 V C2 Mean 1.09664 V Ch2 = VO Ch4 = IO C1 High 3.82 V VI = 3.3 V VO = 1.1 V o TA = 25 C Ch2 = VO Ch4 = IO VI = 4 V VO = 3.3 V o TA = 25 C Figure 25. LDO2 Load Transient Response Figure 24. LDO1 Load Transient Response C4 High 21.4 mA C4 Low -1.4 mA C2 PK-PK 76 mV C2 Mean 2.9762 V Ch2 = VO Ch4 = IO VI = 3.8 V VO = 3 V o TA = 25 C Figure 26. VRTC Load Transient Response Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 15 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com 8 Detailed Description 8.1 Overview The TPS65023-Q1 device has 5 regulator channels, 3 DCDCs, and 2 LDOs. DCDC3 has dynamic voltage scaling feature (DVS) that allows for power reduction to CORE supplies during idle operation or overvoltage during heavy-duty operation. With DVS and 2 more DCDCs plus 2 LDOs, the TPS65023-Q1 is ideal for CORE, Memory, IO, and peripheral power for the entire system of a wide range of suitable applications. The device incorporates enables for the DCDCs and LDOs, I2C for device control, push button, and a reset interface that complete the system and allow the TPS65023-Q1 to be adapted for different kinds of processors or FPGAs. For noise-sensitive circuits, the DCDCs can be synchronized out of phase from one another, reducing the peak noise at the switching frequency. Each converter can be forced to operate in PWM mode to ensure constant switching frequency across the entire load range. However, for low load efficiency performance the DCDCs automatically enter PSM mode which reduces the switching frequency when the load current is low, saving power at idle operation. 8.2 Functional Block Diagram TPS65023-Q1 VCC VSYSIN BBAT SWITCH VBACKUP Thermal Shutdown VRTC VINDCDC1 L1 DCDC1 Buck Converter 1500 mA SCLK SDAT VDCDC1 DEFDCDC1 PGND1 Serial Interface VINDCDC2 DCDC1_EN L2 DCDC2_EN DCDC2 Buck Converter 1200 mA DCDC3_EN LDO_EN CONTROL VDCDC2 DEFDCDC2 PGND2 HOT_RESET Dynamic Voltage Management RESPWRON INT VINDCDC3 L3 LOWBAT_SNS PWRFAIL_SNS LOW_BATT PWRFAIL DCDC3 Buck Converter 1000 mA UVLO VREF OSC VDCDC3 DEFDCDC3 PGND3 TRESPWRON LDO1 200 mA DEFLDO1 DEFLDO2 VLDO1 VINLDO LDO2 200 mA VLDO2 AGND1 AGND2 16 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 8.3 Feature Description 8.3.1 Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3 The TPS65023-Q1 incorporates three synchronous step-down converters operating typically at 2.25 MHz fixedfrequency pulse-width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter the power-save mode (PSM), and operate with pulse-frequency modulation (PFM). The VDCDC1 converter is capable of delivering 1.5-A output current, the VDCDC2 converter is capable of delivering 1.2 A, and the VDCDC3 converter is capable of delivering up to 1 A. The converter output voltages can be programmed through the DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins. The pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND. The VDCDC1 converter defaults to 1.2 V or 1.6 V, depending on the DEFDCDC1 configuration pin. If DEFDCDC1 is tied to ground, the default is 1.2 V. If it is tied to VCC, the default is 1.6 V. When the DEFDCDC1 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VCC. See Application and Implementation for more details. The core voltage can be reprogrammed through the serial interface in the range of 0.8 V to 1.6 V with a programmable slew rate. The converter is forced into PWM operation while any programmed voltage change is underway, whether the voltage is being increased or decreased. The DEFCORE and DEFSLEW registers are used to program the output voltage and slew rate during voltage transitions. The VDCDC2 converter defaults to 1.8 V or 3.3 V, depending on the DEFDCDC2 configuration pin. If DEFDCDC2 is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC2 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VCC. The VDCDC3 converter defaults to 1.8 V or 3.3 V, depending on the DEFDCDC3 configuration pin. If DEFDCDC3 is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC3 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VCC. The step-down converter outputs (when enabled) are monitored by power good (PG) comparators, the outputs of which are available through the serial interface. The outputs of the DC-DC converters can be optionally discharged through on-chip 300-Ω resistors when the DC-DC converters are disabled. During PWM operation, the converters use a unique fast-response voltage-mode controller scheme with inputvoltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The current-limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the adaptive dead time used to prevent shoot-through current, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel rectifier and turning on the P-channel switch. The three DC-DC converters operate synchronized to each other with the VDCDC1 converter as the master. A 180° phase shift between the VDCDC1 switch turnon and the VDCDC2 and a further 90° shift to the VDCDC3 switch turnon decreases the input rms current, and smaller input capacitors can be used. This is optimized for a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 1.2 V, the VDCDC2 converter from 3.7 V to 1.8 V, and the VDCDC3 converter from 3.7 V to 3.3 V. The phase of the three converters can be changed using the CON_CTRL register. 8.3.2 Soft Start Each of the three converters has an internal soft-start circuit that limits the inrush current during start-up. The soft start is realized by using a low initial current to charge the internal compensation capacitor. The soft-start time is typically 750 μs if the output voltage ramps from 5% to 95% of the final target value. If the output is already precharged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a short delay of typically 170 μs between the converter being enabled and switching activity actually starting. This allows the converter to bias itself properly, to recognize if the output is precharged, and if so to prevent discharging of the output while the internal soft-start ramp catches up with the output voltage. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 17 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com Feature Description (continued) 8.3.3 Active Discharge When Disabled When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDC_EN or OVERTEMP condition, it is possible to pull down the outputs actively. This feature is disabled per default and is individually enabled through the CON_CTRL2 register in the serial interface. When this feature is enabled, the VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300-Ω (typical) load which is active as long as the converters are disabled. 8.3.4 Power-Good Monitoring All three step-down converters and both the LDO1 and LDO2 linear regulators have power-good comparators. Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5% hysteresis. The outputs of these comparators are available in the PGOODZ register through the serial interface. An interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are disabled and the relevant PGOODZ register bits indicate that power is good. 8.3.5 Low-Dropout Voltage Regulators The low-dropout voltage regulators are designed to operate well with low-value ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 300 mV at rated output current. Each LDO supports a current-limit feature. Both LDOs are enabled by the LDO_EN pin, and both LDOs can be disabled or programmed through the serial interface using the REG_CTRL and LDO_CTRL registers. The LDOs also have reverse-conduction prevention. This allows the possibility to connect external regulators in parallel in systems with a backup battery. The TPS65023-Q1 step-down and LDO voltage regulators automatically power down when the VCC voltage drops below the UVLO threshold or when the junction temperature rises above 160°C. 8.3.6 Undervoltage Lockout The undervoltage-lockout circuit for the five regulators on the TPS65023-Q1 prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis. Note that when any of the DC-DC converters are running, there is an input current at the VCC pin, which is up to 3 mA when all three converters are running in PWM mode. This current must be considered if an external RC filter is used at the VCC pin to remove switching noise from the TPS65023-Q1 internal analog circuitry supply. 8.4 Device Functional Modes 8.4.1 VRTC Output and Operation With or Without Backup Battery The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail (that is, for a real-time clock). The TPS65023-Q1 asserts the RESPWRON signal if VRTC drops below 2.4 V. VRTC is selected from a priority scheme based on the VSYSIN and VBACKUP inputs. When the voltage at the VSYSIN pin exceeds 2.65 V, VRTC connects to the VSYSIN input through a PMOS switch and all other paths to VRTC are disabled. The PMOS switch drops a maximum of 375 mV at 30 mA, which should be considered when using VRTC. VSYSIN can be connected to any voltage source with the appropriate input voltage, including VCC or, if set to 3.3-V output, DCDC2 or DCDC3. When VSYSIN falls below 2.65 V or shorts to ground, the PMOS switch connecting VRTC and VSYSIN opens and VRTC then connects to either VBACKUP or the output of a dedicated 3-V, 30-mA LDO. TI recommends connecting VSYSIN to VCC or ground—VCC if a non-replaceable primary cell is connected to VBACKUP and ground if the VRTC output floats. If the PMOS switch between VSYSIN and VRTC is open and VBACKUP exceeds 2.65 V, VRTC connects to VBACKUP through a PMOS switch. The PMOS switch drops a maximum of 375 mV at 30 mA, which should be considered if using VRTC. A typical application may connect VBACKUP to a primary Li button cell, but any battery that provides a voltage between 2.65 V and 6 V (that is, a single Li-Ion cell or a single boosted NiMH battery) is acceptable, to supply the VRTC output. In systems with no backup battery, the VBACKUP pin should be connected to GND. If the switches between VRTC and VSYSIN or VBACKUP are open, the dedicated 3-V, 30-mA LDO, driven from VCC, connects to VRTC. This LDO is disabled if the voltage at the VSYSIN input exceeds 2.65 V. 18 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 Device Functional Modes (continued) Inside TPS65023-Q1 there is a switch (VMAX switch) which selects the higher voltage between VCC and VBACKUP. This is used as the supply voltage for some basic functions. The functions powered from the output of the VMAX switch are: • INT output • RESPWRON output • HOT_RESET input • LOW_BAT output • PWRFAIL output • Enable pins for DC-DC converters, LDO1 and LDO2 • Undervoltage lockout comparator (UVLO) • Reference system with low-frequency timing oscillators • LOW_BAT and PWRFAIL comparators The main 2.25-MHz oscillator, and the I2C interface are only powered from VCC. VSYSIN Vref V_VSYSIN VCC VBACKUP Vref V_VBACKUP V_VSYSIN EN V_VBACKUP priority #1 priority #2 VRTC LDO priority #3 VRTC Vref A. V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3% B. RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3% RESPWRON Figure 27. Power Switches Block Diagram Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 19 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com Device Functional Modes (continued) 8.4.2 Power-Save Mode Operation (PSM) As the load current decreases, the converters enter the power-save mode of operation. During PSM, the converters operate in a burst mode (PFM mode) with a frequency between 750 kHz and 2.25 MHz, nominal, for one burst cycle. However, the frequency between different burst cycles depends on the actual load current and is typically far less than the switching frequency, with a minimum quiescent current to maintain high efficiency. To optimize the converter efficiency at light load, the average current is monitored, and if in PWM mode the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM is calculated as follows: VINDCDC1 IPFMDCDC1enter = 24 W IPFMDCDC2 enter = VINDCDC2 26 W IPFMDCDC3 enter = VINDCDC3 39 W (1) During PSM, the output voltage is monitored with a comparator, and by maximum skip burst duration. As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on, and the converter effectively delivers a constant current defined as follows. VINDCDC1 IPFMDCDC1leave = 18 W IPFMDCDC2 leave = VINDCDC2 20 W IPFMDCDC3 leave = VINDCDC3 29 W (2) If the load is below the delivered current, then the output voltage rises until the same threshold is crossed in the other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage has again dropped below the threshold. The power-save mode is exited, and the converter returns to PWM mode if either of the following conditions is met: • the output voltage drops 2% below the nominal VO due to increasing load current • the PFM burst time exceeds 16 × 1 / fS (7.11 μs typical). These control methods reduce the quiescent current to typically 14 μA per converter, and the switching activity to a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal output voltage at light load current results in a low output-voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The PSM is disabled through the I2C interface to force the individual converters to stay in fixed-frequency PWM mode. 8.4.3 Low-Ripple Mode Setting bit 3 in register CON-CTRL to 1 enables the low-ripple mode for all of the DC-DC converters if operated in PFM mode. For an output current less than approximately 10 mA, the output-voltage ripple in PFM mode is reduced, depending on the actual load current. The lower the actual output current on the converter, the lower the output ripple voltage. For an output current above 10 mA, there is only a minor difference in output-voltage ripple between PFM mode and low-ripple PFM mode. As this feature also increases switching frequency, it is used to keep the switching frequency above the audible range in PFM mode down to a low output current. 20 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 Device Functional Modes (continued) 8.4.4 100% Duty-Cycle Low-Dropout Operation The TPS65023-Q1 converters offer a low input-to-output voltage difference while still maintaining operation with the use of the 100% duty-cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage required to maintain DC regulation depends on the load current and output voltage. Use Equation 3 to calculate the minimum input voltage. ( VIN(min) = VOUT(min) + IOUT(max) ´ rDS(ON) max + R L ) where • • • • IOUT(max) = maximum load current (Note: ripple current in the inductor is zero under these conditions) rDS(on)max = maximum P-channel switch rDS(on) RL = DC resistance of the inductor VOUT(min) = nominal output voltage minus 2% tolerance limit (3) 8.4.5 System Reset and Control Signals The RESPWRON signal can be used as a global reset for the application. It is an open-drain output. The RESPWRON signal is generated according to the power-good comparator of VRTC, and remains low for tnrespwron seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms. The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and LOWBAT_SNS input signals. Each input signal is compared to a 1-V threshold (falling edge) with 5% (50 mV) hysteresis. The DCDC1 converter is reset to its default output voltage defined by the DEFDCDC1 input, when HOT_RESET is asserted. Other I2C registers are not affected. Generally, the DCDC1 converter is set to its default voltage with one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout (UVLO) condition, or RESPWRON active. 8.4.5.1 DEFLDO1 and DEFLDO2 These two pins are used to set the default output voltage of the two 200-mA LDOs. The digital value applied to the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of both LDOs can be changed during operation with the I2C interface as described in the interface description. Table 3. VLDO1 and VLDO2 Voltage Options DEFLDO2 DEFLDO1 VLDO1 VLDO2 0 0 1.3 V 3.3 V 0 1 2.8 V 3.3 V 1 0 1.3 V 1.8 V 1 1 1.8 V 3.3 V 8.4.5.2 Interrupt Management and the INT Pin The INT pin combines the outputs of the PGOOD comparators from each DC-DC converter and the LDOs. The INT pin is used as a POWER_OK pin to indicate when all enabled supplies are in regulation. The INT pin remains active (low state) during power up as long as all enabled power rails are below their regulation limit. Once the last enabled power rail is within regulation, the INT pin transitions to a high state. During operation, if one of the enabled supplies goes out of regulation, INT transitions to a low state, and the corresponding bit in the PGOODZ register goes high. If the supply goes back to its regulation limits, INT transitions back to a high state. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 21 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com While INT is in an active low state, reading the PGOODZ register through the I2C bus forces INT into a high-Z state. Because this pin requires an external pullup resistor, the INT pin transitions to a logic-high state even though the supply in question is still out of regulation. The corresponding bit in the PGOODZ register still indicates that the power rail is out of regulation. Interrupts can be masked using the MASK register. The default operation is not to mask any DCDC or LDO interrupts, because these provide the POWER_OK function. 8.5 Programming 8.5.1 Power-Up Sequencing The TPS65023-Q1 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved by providing separate enable pins for each switch-mode converter and a common enable signal for the LDOs. The relevant control pins are described in Table 4. Table 4. Control Pins and Status Outputs For DC-DC Converters PIN NAME I/O FUNCTION DEFDCDC3 I Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to 1.8 V, DEFDCDC3 = VCC defaults VDCDC3 to 3.3 V. DEFDCDC2 I Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 3.3 V. DEFDCDC1 I Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 1.2 V, DEFDCDC1 = VCC defaults VDCDC1 to 1.6 V. DCDC3_EN I Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter DCDC2_EN I Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter DCDC1_EN I Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter HOT_RESET I The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any TPS65023-Q1 settings except the output voltage of VDCDC1. Activating HOT_RESET sets the voltage of VDCDC1 to its default value defined with the DEFDCDC1 pin. HOT_RESET is internally de-bounced by the TPS65023-Q1. RESPWRON O RESPWRON is held low when power is initially applied to the TPS65023-Q1. The VRTC voltage is monitored: RESWPRON is low when VRTC < 2.4 V and remains low for a time defined by the external capacitor at the TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin. TRESPWRON I Connect a capacitor here to define the RESET time at the RESPWRON pin (1 nF typically gives 100 ms). 8.5.2 Serial Interface The serial interface is compatible with the standard- and fast-mode I2C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power-supply solution, enabling most functions to be programmed to new values, depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as VCC remains above 2 V. The TPS65023-Q1 has a 7-bit address: 1001000; other addresses are available on contact with the factory. Attempting to read data from the register addresses not listed in this section results in FFh being read out. For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65023-Q1 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65023-Q1 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65023-Q1 device must leave the data line high to enable the master to generate the stop condition. 22 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 DATA CLK Data Line Stable; Data Valid Change of Data Allowed Figure 28. Bit Transfer on the Serial Interface CE DATA CLK S P START Condition STOP Condition Figure 29. Start and Stop Conditions SCLK SDAT A6 A5 A0 A4 R/W ACK R5 R0 ACK 0 0 Start R6 R7 D7 D6 D5 D0 ACK 0 0 Register Address Slave Address Stop Data Note: SLAVE = TPS65020 Figure 30. Serial Interface Write to TPS65023-Q1 Device SCLK SDAT A6 Start A0 R/W ACK 0 0 R7 Slave Address R0 ACK A6 A0 0 Register Address R/W ACK 1 0 Slave Address D7 D0 Slave Drives the Data ACK Stop Master Drives ACK and Stop Repeated Start Note: SLAVE = TPS65020 Figure 31. Serial Interface Read from TPS65023-Q1: Protocol A Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 23 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com SCLK SDA A6 A0 R/W 0 Start ACK R7 R0 0 A6 ACK 0 R/W 1 Stop Start Register Address Slave Address A0 Slave Address ACK D0 D7 ACK 0 Slave Drives the Data Stop Master Drives ACK and Stop Note: SLAVE = TPS65020 Figure 32. Serial Interface Read from TPS65023-Q1: Protocol B 8.6 Register Maps 8.6.1 VERSION Register (address: 00h) Read-Only Figure 33. VERSION Register Fields 7 6 5 4 3 2 1 0 R-0 R-0 R-1 R-1 VERSION R-0 R-0 R-1 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset 24 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 8.6.2 PGOODZ Register (address: 01h) Read-Only Figure 34. PGOODZ Register Fields 7 6 PWRFAILZ LOWBATTZ R R 5 PGOODZ VDCDC1 R 4 PGOODZ VDCDC2 R 3 PGOODZ VDCDC3 R 2 PGOODZ LDO2 R 1 PGOODZ LDO1 R 0 R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5. PGOODZ Register Field Descriptions Bit Field Type Reset PWRFAILZ R 0 Description Set by signal: PWRFAIL 7 0 = indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold. 1 = indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold. Set by signal: LOWBATT 6 LOWBATTZ R 0 0 = indicates that the LOWBATT_SNS input voltage is above the 1-V threshold. 1 = indicates that the LOWBATT_SNS input voltage is below the 1-V threshold. Set by signal: PGOODZ_VDCDC1 5 PGOODZ VDCDC1 R 0 0 = indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if the VDCDC1 converter is disabled. 1 = indicates that the VDCDC1 converter output voltage is below its target regulation voltage. Set by signal: PGOODZ_VDCDC2 4 PGOODZ VDCDC2 R 0 0 = indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if the VDCDC2 converter is disabled. 1 = indicates that the VDCDC2 converter output voltage is below its target regulation voltage. Set by signal: PGOODZ_VDCDC3 3 PGOODZ VDCDC3 R 0 0 = indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if the VDCDC3 converter is disabled and during a DVMcontrolled output-voltage transition. 1 = indicates that the VDCDC3 converter output voltage is below its target regulation voltage. Set by signal: PGOODZ_LDO2 2 PGOODZ LDO2 R 0 0 = indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is disabled. 1 = indicates that LDO2 output voltage is below its target regulation voltage. Set by signal: PGOODZ_LDO1 1 PGOODZ LDO1 R 0 0 = indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is disabled. 1 = indicates that the LDO1 output voltage is below its target regulation voltage. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 25 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com 8.6.3 MASK Register (address: 02h) Figure 35. MASK Register Fields 7 MASK PWRFAILZ R/W-1 6 MASK LOWBATTZ R/W-1 5 MASK VDCDC1 R/W-0 4 MASK VDCDC2 R/W-0 3 MASK VDCDC3 R/W-0 2 1 MASK LDO2 MASK LDO1 R/W-0 R/W-0 0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK = 1 masks PGOODZ. 8.6.4 REG_CTRL Register (address: 03h) The REG_CTRL register is used to disable or enable the power supplies through the serial interface. The contents of the register are logically ANDed with the enable pins to determine the state of the supplies. A UVLO condition resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The REG_CTRL bits are automatically reset to default when the corresponding enable pin is low. Figure 36. REG_CTRL Register Fields 7 6 R-1 R-1 5 VDCDC1 ENABLE R/W-1 4 VDCDC2 ENABLE R/W-1 3 VDCDC3 ENABLE R/W-1 2 1 LDO2 ENABLE LDO1 ENABLE R/W-1 R/W-1 0 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6. REG_CTRL Register Field Descriptions Bit Field Type Reset Description Set by signal: DCDC1_ENZ 5 VDCDC1 ENABLE R/W 1 DCDC1 enable. This bit is logically ANDed with the state of the DCDC1_EN pin to turn on the DCDC1 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the DCDC1_EN pin is pulled to GND, allowing DCDC1 to turn on when DCDC1_EN returns high. Set by signal: DCDC2_ENZ 4 VDCDC2 ENABLE R/W 1 DCDC2 enable. This bit is logically ANDed with the state of the DCDC2_EN pin to turn on the DCDC2 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the DCDC2_EN pin is pulled to GND, allowing DCDC2 to turn on when DCDC2_EN returns high. Set by signal: DCDC3_ENZ 3 VDCDC3 ENABLE R/W 1 DCDC3 enable. This bit is logically ANDed with the state of the DCDC3_EN pin to turn on the DCDC3 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the DCDC3_EN pin is pulled to GND, allowing DCDC3 to turn on when DCDC3_EN returns high. Set by signal: LDO_ENZ 2 LDO2 ENABLE R/W 1 LDO2 enable. This bit is logically ANDed with the state of the LDO2_EN pin to turn on LDO2. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the LDO_EN pin is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high. Set by signal: LDO_ENZ 1 26 LDO1 ENABLE R/W 1 LDO1 enable. This bit is logically ANDed with the state of the LDO1_EN pin to turn on LDO1. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the LDO_EN pin is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 8.6.5 CON_CTRL Register (address: 04h) Figure 37. CON_CTRL Register Fields 7 DCDC2 PHASE1 R/W-1 6 DCDC2 PHASE0 R/W-0 5 DCDC3 PHASE1 R/W-1 4 DCDC3 PHASE0 R/W-1 3 2 1 0 LOW RIPPLE FPWM DCDC2 FPW DCDC1 FPWM DCDC3 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset The CON_CTRL register is used to force any or all of the converters into forced PWM operation when low output-voltage ripple is vital. It is also used to control the phase shift between the three converters to minimize the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is taken as the reference and consequently has a fixed-zero phase shift. Table 7. CON_CTRL Register Field Descriptions Bit Field Type Reset Description DCDC2 Converter delay is set by these bits. 7–6 DCDC2 PHASE1, PHASE0 00 = Zero R/W 10 01 = 1/4 cycle 10 = 1/2 cycle 11 = 3/4 cycle DCDC3 Converter delay is set by these bits. 5–4 DCDC3 PHASE1, PHASE0 00 = Zero R/W 11 01 = 1/4 cycle 10 = 1/2 cycle 11 = 3/4 cycle 3 LOW RIPPLE: R/W 0 0 = PFM mode operation optimized for high efficiency for all converters 1 = PFM mode operation optimized for low output-voltage ripple for all converters 2 FPWM DCDC2: R/W 0 0 = DCDC2 converter operates in PWM or PFM mode 1 = DCDC2 converter is forced into fixed-frequency PWM mode. 1 FPWM DCDC1: R/W 0 0 = DCDC1 converter operates in PWM or PFM mode 1 = DCDC1 converter is forced into fixed-frequency PWM mode. 0 FPWM DCDC3: R/W 0 0 = DCDC3 converter operates in PWM or PFM mode 1 = DCDC3 converter is forced into fixed-frequency PWM mode. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 27 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com 8.6.6 CON_CTRL2 Register (address: 05h) Figure 38. CON_CTRL2 Register Fields 7 6 Core adj allowed R/W-1 GO R/W-0 5 4 3 R/W-0 R/W-0 R/W-0 2 DCDC2 discharge R/W-0 1 DCDC1 discharge R/W-0 0 DCDC3 discharge R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset The CON_CTRL2 register can be used to take control the inductive converters. RESET(1): CON_CTRL2[6] is reset to its default value by one of these events: • Undervoltage lockout (UVLO) • HOT_RESET pulled low • RESPWRON active • VRTC below threshold Table 8. CON_CTRL2 Register Field Descriptions Bit Field Type Reset Description 0 = no change in the output voltage for the DCDC1 converter 7 GO R/W 0 1 = the output voltage of the DCDC1 converter is changed to the value defined in DEFCORE with the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is complete. The transition is considered complete in this case when the desired output voltage code has been reached, not when the VDCDC3 output voltage is actually in regulation at the desired voltage. 0 = the output voltage is set with the I2C register 6 2–0 28 CORE ADJ allowed DCDC2, DCDC1, DCDC3 discharge R/W 1 1 = DEFDCDC1 is either connected to GND or VCC or an external voltage divider. When connected to GND or VCC, VDCDC1 defaults to 1.2 V or 1.6 V, respectively, at start-up. 0 = the output capacitor of the associated converter is not actively discharged when the converter is disabled. R/W 000 1 = the output capacitor of the associated converter is actively discharged when the converter is disabled. This decreases the fall time of the output voltage at light load. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 8.6.7 DEFCORE Register (address: 06h) Figure 39. DEFCORE Register Fields 7 6 5 4 CORE4 R/W-0 R/W-0 R/W-0 R/W-1 3 CORE3 R/WDEFDCDC1 2 CORE2 R/WDEFDCDC1 1 CORE1 R/WDEFDCDC1 0 CORE0 R/WDEFDCDC1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset RESET(1): DEFCORE is reset to its default value by one of these events: • Undervoltage lockout (UVLO) • HOT_RESET pulled low • RESPWRON active • VRTC below threshold Table 9. DEFCORE Register Field Descriptions Bit Field Type Reset Description These bits set VDCDC1. 4–0 CORE4, CORE3, CORE2, CORE1,CORE0 R/W 10100 00000 = 0.8 V 10000 = 1.2 V 00001 = 0.825 V 10001 = 1.225 V 00010 = 0.85 V 10010 = 1.25 V 00011 = 0.875 V 10011 = 1.275 V 00100 = 0.9 V 10100 = 1.3 V 00101 = 0.925 V 10101 = 1.325 V 00110 = 0.95 V 10110 = 1.35 V 00111 = 0.975 V 10111 = 1.375 V 01000 = 1 V 11000 = 1.4 V 01001 = 1.025 V 11001 = 1.425 V 01010 = 1.05 V 11010 = 1.45 V 01011 = 1.075 V 11011 = 1.475 V 01100 = 1.1 V 11100 = 1.5 V 01101 = 1.125 V 11101 = 1.525 V 01110 = 1.15 V 11110 = 1.55 V 01111 = 1.175 V 11111 = 1.6 V Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 29 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com 8.6.8 DEFSLEW Register (address: 07h) Figure 40. DEFSLEW Register Fields 7 6 5 4 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 2 SLEW2 R/W-1 1 SLEW1 R/W-1 0 SLEW0 R/W-0 1 LDO1_1 R/W-DEFLDOx 0 LDO1_0 R/W-DEFLDOx LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 10. DEFSLEW Register Field Descriptions Bit Field Type Reset Description These bits set the VDCDC1 SLEW RATE 000 = 0.225 mV/μs 001 = 0.45 mV/μs 2–0 SLEW2, SLEW1, SLEW0 010 = 0.9 mV/μs R/W 110 011 = 1.8 mV/μs 100 = 3.6 mV/μs 101 = 7.2 mV/μs 110 = 14.4 mV/μs 111 = Immediate 8.6.9 LDO_CTRL Register (address: 08h) Figure 41. LDO_CTRL Register Fields 7 Reserved R/W-0 6 LDO2_2 R/W-DEFLDOx 5 LDO2_1 R/W-DEFLDOx 4 LDO2_0 R/W-DEFLDOx 3 Reserved R/W-0 2 LDO1_2 R/W-DEFLDOx The default value for this register is set with DEFLDO1 and DEFLDO2. LEGEND: R/W = Read/Write; R = Read only; -n = value after reset The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2. LDO_CTRL[7] and LDO_CTRL[3] are reserved and should always be written to 0. The default voltage is set with DEFLDO1 and DEFLDO2 pins as described in Table 11. Table 11. LDO_CTRL Register Field Descriptions Bit Field Type Reset Description 000 = 1.05 V 001 = 1.2 V 010 = 1.3 V 6–4 LDO2_2, LDO2_1, LDO2_0 R/W See (1) 011 = 1.8 V 100 = 2.5 V 101 = 2.8 V 110 = 3 V 111 =3.3 V 000 = 1 V 001 = 1.1 V 010 = 1.3 V 2–0 LDO1_2, LDO1_1, LDO1_0 R/W See (1) 011 = 1.8 V 100 = 2.2 V 101 = 2.6 V 110 = 2.8 V 111 = 3.15 V (1) 30 Table 3 describes the default voltage options based on DEFLDO1 and DEFLDO2 pins. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Reset Condition of DCDC1 If DEFDCDC1 is connected to ground and DCDC1_EN is pulled high after VINDCDC1 is applied, the output voltage of DCDC1 defaults to 1.225 V instead of 1.2 V (high by 2%). Figure 42 illustrates the problem. VCC/VINDCDC1 DCDC1_EN 1.225 V 1.225 V 1.225 V VDCDC1 Figure 42. Default DCDC1 Workaround 1: Tie DCDC1_EN to VINDCDC1 (Figure 43) VCC/VINDCDC1 DCDC1_EN 1.20 V 1.20 V 1.20 V VDCDC1 Figure 43. Workaround 1 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 31 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com Application Information (continued) Workaround 2: Write the correct voltage to the DEF_CORE register through I2C. This can be done before or after the converter is enabled. If written before the enable, the only bit changed is DEF_CORE[0]. The voltage is 1.2 V, however, when the enable is pulled high (Figure 44). VCC/VINDCDC1 DCDC1_EN I2C Bus DEF_CORE ?? 0x1F 0x11 1.225 V VDCDC1 0x10 ?? 0x1F 0x1E 1.20 V 1.20 V Pull DCDC1_EN High Write DEF_CORE to 0x10 Write CON_CTRL [7] to 1 0x10 Write DEF_CORE to 0x10 Pull DCDC1_EN High Figure 44. Workaround 2 Workaround 3: Generate a HOT_RESET after enabling DCDC1 (Figure 45) VCC/VINDCDC1 DCDC1_EN HOT_RESET 1.225 V 1.20 V VDCDC1 1.225 V 1.20 V Figure 45. Workaround 3 32 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 9.2 Typical Application -Q1 Figure 46. Typical Configuration for the Texas Instruments TMS320DM644x DaVinci Processors 9.2.1 Design Requirements The TPS65023-Q1 devices have only a few design requirements. Use the following parameters for the design examples: • 1-μF bypass capacitor on VCC, located as close as possible to the VCC pin to ground. • VCC and VINDCDCx must be connected to the same voltage supply with minimal voltage difference. • Input capacitors must be present on the VINDCDCx and VIN_LDO supplies if used. • Output inductor and capacitors must be used on the outputs of the DC-DC converters if used. • Output capacitors must be used on the outputs of the LDOs if used. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 33 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com Typical Application (continued) 9.2.2 Detailed Design Procedure 9.2.2.1 Inductor Selection for the DC-DC Converters Each of the converters in the TPS65023-Q1 typically uses a 2.2-μH output inductor. Larger or smaller inductor values are used to optimize the performance of the device for specific operation conditions. The selected inductor must be rated for its DC resistance and saturation current. The DC resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest DC resistance should be selected for highest efficiency. For a fast transient response, TI recommends a 2.2-μH inductor in combination with a 22-μF output capacitor. Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is needed because during a heavy load transient the inductor current rises above the value calculated under Equation 4. DIL = VOUT ´ 1- VOUT VIN L´ƒ IL(max) = IOUT(max) (4) DI + L 2 where • • • • • f = Switching frequency (2.25 MHz typical) L = Inductor value ΔIL = Peak-to-peak inductor ripple current ILMAX = Maximum inductor current (5) The highest inductor current occurs at maximum VIN. Open-core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents versus a comparable shielded inductor. A more-conservative approach is to select the inductor current rating just for the maximum switch current of the TPS65023-Q1 (2 A for the VDCDC1 and VDCDC2 converters, and 1.5 A for the VDCDC3 converter). The core material from inductor to inductor differs and has an impact on the efficiency, especially at high switching frequencies. See Table 12 and the typical applications for possible inductors. Table 12. Tested Inductors DEVICE All converters INDUCTOR VALUE TYPE COMPONENT SUPPLIER 2.2 μH LPS4012-222LMB Coilcraft 2.2 μH VLCF4020T-2R2N1R7 TDK 9.2.2.2 Output Capacitor Selection The advanced fast-response voltage-mode control scheme of the inductive converters implemented in the TPS65023-Q1 allow the use of small ceramic capacitors with a typical value of 10 μF for each converter without having large output-voltage under- and overshoots during heavy load transients. Ceramic capacitors having low ESR values have the lowest output-voltage ripple and are recommended. See Table 13 for recommended components. If ceramic output capacitors are used, the capacitor rms ripple-current rating always meets the application requirements. Just for completeness, the rms ripple current is calculated as: IRMSCOUT = VOUT ´ 34 1- VOUT VIN L´ƒ ´ 1 2´ 3 (6) Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 At nominal load current, the inductive converters operate in PWM mode. The overall output-voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: DVOUT = VOUT ´ 1- VOUT VIN L´ƒ æ ö 1 ´ç + ESR ÷ 8 C ƒ ´ ´ OUT è ø where • the highest output-voltage ripple occurs at the highest input-voltage VIN (7) At light load currents, the converters operate in PSM and the output-voltage ripple is dependent on the outputcapacitor value. The output-voltage ripple is set by the internal comparator delay and the external capacitor. The typical output-voltage ripple is less than 1% of the nominal output voltage. 9.2.2.3 Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low-ESR input capacitor is required for best input-voltage filtering and minimizing the interference with other circuits caused by high inputvoltage spikes. Each DC-DC converter requires a 10-μF ceramic input capacitor on its input pin VINDCDCx. The input capacitor is increased without any limit for better input-voltage filtering. The VCC pin is separated from the input for the DC-DC converters. A filter resistor of up to 10R and a 1-μF capacitor are used for decoupling the VCC pin from switching noise. Note that the filter resistor may affect the UVLO threshold, because up to 3 mA can flow through this resistor into the VCC pin when all converters are running in PWM mode. Table 13. Possible Capacitors CAPACITOR VALUE CASE SIZE 22 μF 1206 TDK C3216X5R0J226M Ceramic 22 μF 1206 Taiyo Yuden JMK316BJ226ML Ceramic 22 μF 0805 TDK C2012X5R0J226MT Ceramic 22μF 0805 Taiyo Yuden JMK212BJ226MG Ceramic 10 μF 0805 Taiyo Yuden JMK212BJ106M Ceramic 10 μF 0805 TDK C2012X5R0J106M Ceramic COMPONENT SUPPLIER COMMENTS 9.2.2.4 Output Voltage Selection The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down converter. See Table 14 for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 47. The output voltage of VDCDC1 is set with the I2C interface. If the voltage is changed from the default, using the DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC1 does not change the voltage set with the register. Table 14. DCDC1, DCDC2, and DCDC3 Default Voltage Levels PIN DEFDCDC1 DEFDCDC2 DEFDCDC3 LEVEL DEFAULT OUTPUT VOLTAGE VCC 1.6 V GND 1.2 V VCC 3.3 V GND 1.8 V VCC 3.3 V GND 1.8 V Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 35 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com Using an external resistor divider at DEFDCDCx: 10 R V(bat) VCC 1 mF VDCDC3 L3 VINDCDC3 CI CO DCDC3_EN VO L R1 DEFDCDC3 R2 AGND PGND Figure 47. External Resistor Divider When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input voltage V(bat). The total resistance (R1 + R2) of the voltage divider should be kept in the 1-MR range to maintain a high efficiency at light load. V(DEFDCDCx) = 0.6 V VOUT = VDEFDCDCx ´ R1 + R2 R2 æ VOUT R1 = R2 ´ ç è VDEFDCDCx ö ÷ - R2 ø (8) 9.2.2.5 VRTC Output TI recommends adding a 4.7-μF (minimum) capacitor to the VRTC pin. 9.2.2.6 LDO1 and LDO2 The LDOs in the TPS65023-Q1 are general-purpose LDOs which are stable using ceramic capacitors. The minimum output capacitor required is 2.2 μF. The LDO output voltages can be changed to different values between 1 V and 3.3 V using the I2C interface. Therefore, they can also be used as general-purpose LDOs in applications powering processors different from DaVinci processors. The supply voltage for the LDOs must be connected to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and providing the highest efficiency. 9.2.2.7 TRESPWRON This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V. The timing is generated by charging and discharging the capacitor with a current of 2 μA between a threshold of 0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms. æ (1 V - 0.25 V )´ C (reset) ö t (reset) = 2 ´ 128 ´ ç ÷÷ ç 2 µA è ø where • • 36 t(reset) is the reset delay time C(reset) is the capacitor connected to the TRESPWRON pin Submit Documentation Feedback (9) Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 9.2.2.8 VCC Filter An RC filter connected at the VCC input is used to keep noise from the internal supply for the band-gap and other analog circuitry. A typical value of 1 Ω and 1 μF is used to filter the switching spikes generated by the DCDC converters. A larger resistor than 10 Ω should not be used, because the current into VCC of up to 3 mA causes a voltage drop at the resistor causing the undervoltage lockout circuitry connected at VCC internally to switch off too early. 9.2.3 Application Curves Graphs were taken using the EVM with the inductor and output capacitor combinations found in Table 1. 100 100 VI = 2.5 V 90 80 90 VI = 3.6 V 80 70 Efficiency - % Efficiency - % 70 VI = 4.2 V 60 50 VI = 5 V 40 VI = 4.2 V 60 VI = 5 V 50 40 30 30 TA = 25°C VO = 1.2 V PWM/PFM Mode 20 10 0 0.01 VI = 2.5 V VI = 3.6 V 0.1 1 10 100 IO - Output Current - mA 1k TA = 25°C VO = 1.8 V PWM/PFM Mode 20 10 0 0.01 10 k 0.1 1 10 100 IO - Output Current - mA 1k 10 k Figure 49. DCDC2 Efficiency Figure 48. DCDC1 Efficiency 100 VI = 2.5 V 90 VI = 3.6 V 80 Efficiency - % 70 VI = 4.2 V 60 VI = 5 V 50 40 30 20 TA = 25°C VO = 1.8 V PWM/PFM Mode 10 0 0.01 0.1 1 10 100 IO - Output Current - mA 1k 10 k Figure 50. DCDC3 Efficiency 10 Power Supply Recommendations For a supply voltage on pins VCC, VINDCDC1, VINDCDC2, and VINDCDC3 below 3 V, TI recommends enabling the DCDC1, DCDC2, and DCDC3 converters in sequence. If all 3 step-down converters are enabled at the same time while the supply voltage is close to the internal reset detection threshold, a reset may be generated during power up. Therefore TI recommends enabling the DC-DC converters in sequence. This can be done by driving one or two of the enable pins with a RC delay or by driving the enable pin by the output voltage of one of the other step-down converters. If a voltage above 3 V is applied on pin VBACKUP while VCC and VINDCDCx is below 3 V, there is no restriction in the power-up sequencing as VBACKUP is used to power the internal circuitry. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 37 TPS65023-Q1 SLVS927F – MARCH 2009 – REVISED JULY 2018 www.ti.com 11 Layout 11.1 Layout Guidelines As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Take care in board layout to get the specified performance. If the layout is not carefully done, the regulators may show poor line, load regulation, or both, along with stability issues and EMI problems. It is critical to provide a low impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitors must be placed as close as possible to the IC pins as well as the inductor and output capacitor. For the TPS65023-Q1 device, connect the PGND pins of the device to the thermal pad land of the PCB and connect the analog ground connections (AGND) to the PGND at the thermal pad. It is essential to provide a good thermal and electrical connection of all GND pins using multiple vias to the GND-plane. Keep the common path to the AGND pins, which returns the small signal components, and the high current of the output capacitors as short as possible to avoid ground noise. The VDCDCx line must be connected right to the output capacitor and routed away from noisy components and traces (for example, the L1, L2, and L3 traces). 11.2 Layout Example VIN Cout L3 Cout CIN VDCDC3 PGND3 Figure 51. Layout Example of a DC-DC Converter 38 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 TPS65023-Q1 www.ti.com SLVS927F – MARCH 2009 – REVISED JULY 2018 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: • Texas Instruments, Choosing an Appropriate Pull-up/Pull-down Resistor for Open Drain Outputs application report • Texas Instruments, Power Supply Design for NXP i.MX 7 Using the TPS65023 application report • Texas Instruments, Power Supply Design for NXP i.MX 6 Using the TPS65023 application report • Texas Instruments, TPS65023EVM User's Guide 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks DaVinci, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS65023-Q1 39 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS65023QRHARQ1 ACTIVE VQFN RHA 40 3000 RoHS & Green NIPDAU Level-3-260C-168 HR TPS65023QRSBRQ1 ACTIVE WQFN RSB 40 3000 RoHS & Green NIPDAU Level-3-260C-168 HR 65023Q RHA -40 to 125 TPS 65023Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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