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TPS650240, TPS650241, TPS650242
TPS650243, TPS650244, TPS650245
SLVS774C – JUNE 2007 – REVISED JANUARY 2016
TPS65024x Power Management ICs for Li-Ion Powered Systems
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
•
•
•
1.6-A, 1.0-A, or 0.8-A, 97% Efficient Step-Down
Converter for System Voltage (VDCDC1)
– 3.3 V or 2.80 V or Adjustable
1.6-A, 1.0-A, or 0.8-A, up to 95% Efficient StepDown Converter for Memory Voltage (VDCDC2)
– 1.8 V or 2.5 V or Adjustable
0.8-A, 90% Efficient Step-Down Converter for
Processor Core (VDCDC3)
Two Selectable Voltages for VDCDC3
– TPS650240:
– DEFDCDC3 = LOW: VO = 1.0 V
– DEFDCDC3 = HIGH: VO = 1.3 V
– TPS650241:
– DEFDCDC3 = LOW: VO = 0.9 V
– DEFDCDC3 = HIGH: VO= 1.375 V
– TPS650242:
– DEFDCDC3 = LOW: VO = 1.0 V
– DEFDCDC3 = HIGH: VO = 1.5 V
– TPS650243:
– DEFDCDC3 = LOW: VO = 1.0 V
– DEFDCDC3 = HIGH: VO = 1.2 V
– TPS650244:
– DEFDCDC3 = LOW: VO = 1.55 V
– DEFDCDC3 = HIGH: VO = 1.6 V
– TPS650245:
– DEFDCDC3 = LOW: VO = 0.9 V
– DEFDCDC3 = HIGH: VO = 1.1 V
30-mA LDO for Vdd_alive
2 × 200-mA General-Purpose LDOs (LDO1 and
LDO2)
Dynamic Voltage Management for Processor Core
LDO1 and LDO2 Voltage Externally Adjustable
Separate Enable Pins for Inductive Converters
2.25-MHz Switching Frequency
85-μA Quiescent Current
Thermal Shutdown Protection
•
•
•
•
Split-Supply DSP and μP Solutions, ARM-Based
Processors, and so on
Cellular and Smart Phones
GPS
Digital Cameras
PDA
3 Description
The TPS65024x devices are integrated power
management ICs for applications powered by one LiIon or Li-Polymer cell, which require multiple power
rails. The TPS65024x provide three highly efficient,
step-down converters targeted at providing the core
voltage, peripheral, I/O, and memory rails in a
processor-based system. All three step-down
converters enter a low power mode at light load for
maximum efficiency across the widest possible range
of load currents. The converters can be forced into
fixed-frequency PWM mode by pulling the MODE pin
high.
Device Information(1)
PART NUMBER
TPS65024x
PACKAGE
BODY SIZE (NOM)
VQFN (32)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
TPS650240
1R
VCC
Vbat
1mF
L1
VINDCDC 1
Vbat
10mF
DCDC1 (I/O)
ENABLE
STEP-DOWN
CONVERTER
1000 mA
EN_DCDC 1
VINDCDC 2
Vbat
DCDC 2
(memory)
10mF
STEP-DOWN
CONVERTER
800 mA
EN_DCDC 2
ENABLE
VINDCDC 3
Vbat
3.3V or 2.8V
2.2 mH
R1
22 mF
DEFDCDC 1
PGND 1
R2
2.5V or 1.8V
L2
VDCDC2
2.2 mH
STEP-DOWN
CONVERTER
800 mA
DEFDCDC 3
EN_DCDC 3
R3
22 mF
DEFDCDC 2
PGND 2
R4
1.0V or 1.3V
L3
DCDC 3 (core)
10mF
1.0V / 1.3V
ENABLE
VDCDC1
VDCDC 3
2.2uH
22 mF
PGND 3
MODE
PWM / PFM
VIN_LDO
VIN
VLDO 1
VLDO1
R5
200 mA LDO
EN_LDO
ENABLE
2.2 mF
R6
VLDO 2
VLDO2
R7
200 mA LDO
EN_Vdd_aliv
e
ENABLE
VCC
Vbat
2.2 mF
R8
VLDO 3
30 mA LDO
Vdd_alive
1.2 V
2.2 mF
R9
I/O voltage
PWRFAIL _SNS
R10
-
PWRFAIL
R19
+
Vref = 1 V
AGND 1
AGND2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS650240, TPS650241, TPS650242
TPS650243, TPS650244, TPS650245
SLVS774C – JUNE 2007 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Voltage Options .....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
1
1
1
2
3
3
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics: Control Signals and Supply
Pins ............................................................................ 7
Electrical Characteristics: VDCDC1 Step-Down
Converter ................................................................... 8
Electrical Characteristics: VDCDC2 Step-Down
Converter ................................................................... 9
Electrical Characteristics: VDCDC3 Step-Down
Converter ................................................................. 10
Electrical Characteristics: General .......................... 11
8.10 Typical Characteristics .......................................... 12
9
Detailed Description ............................................ 16
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
17
18
19
10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
10.2 Typical Applications .............................................. 23
11 Power Supply Recommendations ..................... 27
12 Layout................................................................... 28
12.1 Layout Guidelines ................................................. 28
12.2 Layout Example .................................................... 28
13 Device and Documentation Support ................. 29
13.1
13.2
13.3
13.4
13.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
14 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2009) to Revision C
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision A (December 2007) to Revision B
Page
•
Changed LDO1 output voltage range max value from VinLDO to 3.3V............................................................................... 11
•
Changed LDO2 output voltage range max value from VinLDO to 3.3V............................................................................... 11
2
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Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245
TPS650240, TPS650241, TPS650242
TPS650243, TPS650244, TPS650245
www.ti.com
SLVS774C – JUNE 2007 – REVISED JANUARY 2016
5 Description (continued)
The TPS65024x also integrates two general-purpose 200-mA LDO voltage regulators, which are enabled with an
external input pin. Each LDO operates with an input voltage range between 1.5 V and 6.5 V, allowing them to be
supplied from one of the step-down converters or directly from the battery. The output voltage of the LDOs can
be set with an external resistor divider for maximum flexibility. Additionally there is a 30-mA LDO typically used to
provide power in a processor-based system to a voltage rail that is always on. TPS65024x provide voltage
scaling on DCDC3 using the DEFDCDC3 pin. This pin either needs to be connected to a logic HIGH or logic
LOW level to set the output voltage of DCDC3. The TPS65024x comes in a small 5-mm × 5-mm, 32-pin VQFN
package (RHB).
6 Voltage Options
PACKAGE (1)
32-Pin VQFN
(RHB)
(1)
(2)
VOLTAGE AT
DCDC3
OUTPUT CURRENT ON
DCDC1 / DCDC2 / DCDC3
VOLTAGE AT
VDD_ALIVE
TPS650240RHB
1.0 V / 1.3 V
1.0 A / 0.8 A / 0.8 A
1.2 V
TPS650241RHB
0.9 V / 1.375 V
1.6 A / 1.0 A / 0.8 A
1.2 V
TPS650242RHB
1.0 V / 1.5 V
1.0 A / 0.8 A / 0.8 A
1.2 V
TPS650243RHB
1.0 V / 1.2 V
1.6 A / 1.0 A / 0.8 A
1.2 V
TPS650244RHB
1.55 V / 1.6 V
0.8 A / 1.6 A / 0.8 A
1.2 V
TPS650245RHB
0.9 V / 1.1 V
1.0 A / 0.8 A / 0.8 A
1.1 V
PART NUMBER (2)
TA
–40°C to
85°C
For the most current package and ordering information, see Mechanical, Packaging, and Orderable Information or at www.ti.com.
The RHB package is available in tape and reel. Add R suffix (TPS650240RHBR) to order quantities of 3000 parts per reel. Add T suffix
(TPS650240RHBT) to order quantities of 250 parts per reel.
Copyright © 2007–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245
3
TPS650240, TPS650241, TPS650242
TPS650243, TPS650244, TPS650245
SLVS774C – JUNE 2007 – REVISED JANUARY 2016
www.ti.com
7 Pin Configuration and Functions
DEFDCDC3
AGND1
PWRFAIL_SNS
Vcc
VINDCDC2
L2
PGND2
VDCDC2
RHB Package
32-Pin VQFN
Top View
32 31 30 29 28 27 26 25
VDCDC3
PGND3
L3
VINDCDC3
VINDCDC1
L1
PGND1
VDCDC1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
TPS65024
EN_Vdd_alive
MODE
DEFDCDC2
PWRFAIL
EN_DCDC1
EN_DCDC2
EN_DCDC3
EN_LDO
DEFDCDC1
FB_LDO2
FB_LDO1
Vdd_alive
AGND2
VLDO2
VINLDO
VLDO1
9 10 11 12 13 14 15 16
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
SWITCHING REGULATOR SECTION
AGND1
31
–
Analog ground connection. All analog ground pins are connected internally on the chip.
AGND2
13
–
Analog ground connection. All analog ground pins are connected internally on the chip.
DEFDCDC1
9
I
DEFDCDC2
22
I
Input signal indicating default VDCDC1 voltage, 0 = 2.80 V, 1 = 3.3 V
This pin can also be connected to a resistor divider between VDCDC1 and GND. In this case the output
voltage of the DCDC1 converter can be set in a range from 0.6V to VINDCDC1
Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V
This pin can also be connected to a resistor divider between VDCDC2 and GND. In this case the output
voltage of the DCDC2 converter can be set in a range from 0.6V to VINDCDC2.
DEFDCDC3
32
I
Input signal indicating VDCDC3 voltage.
TPS650240: 0 = 1.0 V, 1 = 1.3 V
TPS650241: 0 = 0.9 V, 1 = 1.375 V
TPS650242: 0 = 1.0 V, 1 = 1.5 V
TPS650243: 0 = 1.0 V, 1 = 1.2 V
TPS650244: 0 = 1.55 V, 1 = 1.6 V
TPS650245: 0 = 0.9 V, 1 = 1.1 V
EN_DCDC1
20
I
VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
EN_DCDC2
19
I
VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
EN_DCDC3
18
I
VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
L1
6
–
Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
L2
27
–
Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
L3
3
–
Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
PGND1
7
–
Power ground for VDCDC1 converter
PGND2
26
–
Power ground for VDCDC2 converter
PGND3
2
–
Power ground for VDCDC3 converter
PowerPad
–
–
Connect the power pad to analog ground
4
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Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245
TPS650240, TPS650241, TPS650242
TPS650243, TPS650244, TPS650245
www.ti.com
SLVS774C – JUNE 2007 – REVISED JANUARY 2016
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
VCC
29
I
Power supply for digital and analog circuitry of DCDC1, DCDC2, and DCDC3 DC-DC converters. This must
be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2.
VDCDC1
8
I
VDCDC1 feedback voltage sense input, connect directly to VDCDC1
VDCDC2
25
I
VDCDC2 feedback voltage sense input, connect directly to VDCDC2
VDCDC3
1
I
VDCDC3 feedback voltage sense input, connect directly to VDCDC3
VINDCDC1
5
I
Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply as
VINDCDC2, VINDCDC3, and VCC.
VINDCDC2
28
I
Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply as
VINDCDC1, VINDCDC3, and VCC.
VINDCDC3
4
I
Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply as
VINDCDC1, VINDCDC2, and VCC.
LDO REGULATOR SECTION
EN_LDO
17
I
Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs.
EN_Vdd_alive
24
I
Enable input for Vdd_alive LDO. Logic high enables the LDO, logic low disables the LDO.
FB_LDO1
11
I
Feedback pin for LDO1
FB_LDO2
10
I
Feedback pin for LDO2
Vdd_alive
12
O
Output voltage for Vdd_alive
VINLDO
15
I
Input voltage for LDO1 and LDO2
VLDO1
16
O
Output voltage of LDO1
VLDO2
14
O
Output voltage of LDO2
2
CONTROL AND I C SECTION
MODE
23
I
Select between power safe mode and forced PWM mode for DCDC1, DCDC2, and DCDC3. In power safe
mode PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM mode is
selected. If the pin has low level, then the device operates in power safe mode.
PWRFAIL
21
O
Open-drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
PWRFAIL_SNS
30
I
Input for the comparator driving the PWRFAIL output
Copyright © 2007–2016, Texas Instruments Incorporated
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5
TPS650240, TPS650241, TPS650242
TPS650243, TPS650244, TPS650245
SLVS774C – JUNE 2007 – REVISED JANUARY 2016
www.ti.com
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Input voltage range on all pins except A/PGND, VLDO1, and VLDO2 pins,
with respect to AGND
–0.3
7
V
Voltage range on pins VLDO1 and VLDO2 with respect to AGND
–0.3
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3
Peak current at all other pins
TA
Operating free-air temperature
TJ
Maximum junction temperature
–40
Lead temperature 1.6 mm (1/16-inch) from case for 10 seconds
Tstg
(1)
Storage temperature
–65
3.6
V
2000
mA
1000
mA
85
°C
125
°C
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VINDCDC1,
VINDCDC2,
VINDCDC3, VCC
Input voltage range step-down converters
2.5
6
V
VDCDC1
Output voltage range for VDCDC1 step-down converter (1)
0.6
VINDCDC1
V
VDCDC2
Output voltage range for mem step-down converter (1)
0.6
VINDCDC2
V
VDCDC3
Output voltage range for core step-down converter
0.9
1.5
V
VINLDO1, VINLDO2
Input voltage range for LDOs
1.5
6.5
V
VLDO1-2
Output voltage range for LDOs
1
3.3
IOUTDCDC1
Output current at L1
L1
Inductor at L1 (2)
1600
1.5
CINDCDC1
Input capacitor at VINDCDC1
COUTDCDC1
Output capacitor at VDCDC1
(2)
IOUTDCDC2
Output current at L2
L2
Inductor at L2 (2)
CINDCDC2
Input capacitor at VINDCDC2
(2)
10
COUTDCDC2
Output capacitor at VDCDC2
(2)
10
22
IOUTDCDC3
Output current at L3
L3
Inductor at L3 (2)
1.5
2.2
CINDCDC3
Input capacitor at VINDCDC3
(2)
10
COUTDCDC3
Output capacitor at VDCDC3
(2)
10
1.5
μF
μF
22
(2)
Input capacitor at VCC
Input capacitor at VINLDO (2)
COUT1-2
Output capacitor at VLDO1, VLDO2 (2)
mA
μH
2.2
μF
μF
800
Cin1-2
6
10
1600
CVcc
(1)
(2)
10
μH
2.2
(2)
V
mA
mA
μH
μF
22
μF
1
μF
1
μF
2.2
μF
When using an external resistor divider at DEFDCDC2, DEFDCDC1.
See Inductor Selection for the DC-DC Converters for more information, for Vout > 2.85 V choose 3.3-μH inductor.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245
TPS650240, TPS650241, TPS650242
TPS650243, TPS650244, TPS650245
www.ti.com
SLVS774C – JUNE 2007 – REVISED JANUARY 2016
Recommended Operating Conditions (continued)
MIN
NOM
MAX
UNIT
200
mA
ILDO1,2
Output current at VLDO1, VLDO2
CVRTC
Output capacitor at Vdd_alive (2)
IVdd_alive
Output current at Vdd_alive
30
mA
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
RCC
Resistor from VINDCDC3,VINDCDC2, VINDCDC1 to VCC used for filtering (3)
10
Ω
(3)
μF
2.2
1
Up to 2.5-mA can flow into VCC when all 3 converters are running in PWM, this resistor causes the UVLO threshold to be shifted
accordingly.
8.4 Thermal Information
TPS650240
THERMAL METRIC (1)
RHB (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
32.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.0
°C/W
RθJB
Junction-to-board thermal resistance
6.2
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
6.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
8.5 Electrical Characteristics: Control Signals and Supply Pins
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TA = –40°C to +85°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER
MIN TYP ( MAX
TEST CONDITIONS
1)
UNIT
CONTROL SIGNALS: EN_DCDC1, EN_DCDC2, EN_DCDC3, EN_LDO, MODE, EN_VDD_ALIVE
VIH
High level input voltage
1.45
VCC
V
VIL
Low level input voltage
0
0.4
V
IH
Input bias current
0.01
0.1
μA
PFM all 3 DCDC converters enabled, zero load
and no switching, LDOs enabled
135
170
PFM all 3 DCDC converters enabled, zero load
and no switching, LDO1, LDO2 = OFF,
Vdd_alive = ON
75
100
PFM DCDC1 and DCDC2 converters enabled,
zero load and no switching,
LDO1, LDO2 = OFF, Vdd_alive = ON
55
80
PFM DCDC1 converter enabled, zero load
and no switching, LDO1, LDO2 = OFF,
Vdd_alive = ON
40
60
SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3
I(qPFM)
Operating quiescent current
VCC = 3.6 V
uA
All 3 DCDC converters enabled
and running in PWM, LDOs off
IVcc(PWM)
Current into VCC; PWM
VCC = 3.6 V
PWM DCDC1 and DCDC2 converters enabled
and running in PWM, LDOs off
PWM DCDC1 converter enabled
and running in PWM, LDOs off
(1)
2
1.5
2.5
0.85
2
mA
Typical values are at TA = 25°C
Copyright © 2007–2016, Texas Instruments Incorporated
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Product Folder Links: TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245
7
TPS650240, TPS650241, TPS650242
TPS650243, TPS650244, TPS650245
SLVS774C – JUNE 2007 – REVISED JANUARY 2016
www.ti.com
Electrical Characteristics: Control Signals and Supply Pins (continued)
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TA = –40°C to +85°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER
Iq
Quiescent current
MIN TYP ( MAX
TEST CONDITIONS
VCC = 3.6 V
1)
All converters disabled, LDO1, LDO2 = OFF,
Vdd_alive = OFF
16
All converters disabled, LDO1, LDO2 = OFF,
Vdd_alive = ON
26
UNIT
μA
8.6 Electrical Characteristics: VDCDC1 Step-Down Converter
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, TA = –40°C to +85°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
IO
Maximum output current for TPS650240,
TPS650242, and TPS650245
VO = 3.3 V
1000
mA
IO
Maximum output current for TPS650241 and
TPS650243
VO = 3.3 V
1600
mA
IO
Maximum output current for TPS650244
VO = 3.3 V
800
mA
ISD
Shutdown supply current in VINDCDC1
EN_DCDC1 = GND
0.1
1
μA
RDS(ON)
P-channel MOSFET ON-resistance
VINDCDC1 = VGS = 3.6 V
125
261
mΩ
ILP
P-channel leakage current
VINDCDC1 = 6 V
2
μA
RDS(ON)
N-channel MOSFET ON-resistance
VINDCDC1 = VGS = 3.6 V
130
260
mΩ
ILN
N-channel leakage current
VDS = 6.0 V
7
10
μA
Forward current limit (P- and N-channel) for
TPS650244
2.5 V < VINMAIN < 6.0 V
0.98
1.1
1.21
A
Forward current limit (P- and N-channel) for
TPS650240, TPS650242, and TPS650245
2.5 V < VINMAIN < 6.0 V
1.15
1.3
1.39
A
Forward current limit (P- and N-channel) for
TPS650241 and TPS650243
2.5 V < VINMAIN < 6.0 V
1.75
1.97
2.15
A
1.95
2.25
2.55
MHz
fS
Oscillator frequency
6
UNIT
Input voltage range
ILIMF
2.5
MAX
VVINDCDC1
Fixed output voltage MODE = 0 (PWM/PFM)
VINDCDC1 = 3.3 V to 6 V;
0 mA ≤ IO ≤ 1.6 A
2.80 V
3.3 V
–2%
2%
Fixed output voltage MODE = 1 (PWM)
VINDCDC1 = 3.7 V to 6 V;
0 mA ≤ IO ≤ 1.6 A
2.80 V
–1%
1%
3.3 V
–1%
1%
Adjustable output voltage with resistor divider
at DEFDCDC1; MODE = 0 (PWM/PFM)
VINDCDC1 = VDCDC1 +0.4 V (min 2.5
V) to 6 V; 0 mA ≤ IO ≤ 1.6 A
–2%
2%
Adjustable output voltage with resistor divider
at DEFDCDC1; MODE = 1 (PWM)
VINDCDC1 = VDCDC1 +0.4 V (min 2.5
V) to 6 V; 0 mA ≤ IO ≤ 1.6 A
–1%
1%
Line regulation
VINDCDC1 = VDCDC1 + 0.3 V (min 2.5
V) to 6 V; IO = 10 mA
Load regulation
IO = 10 mA to 1.6 A
TSS
Soft-start ramp time
VDCDC1 ramping from 5% to 95% of
target value
R(L1)
Internal resistance from L1 to GND
VDCDC1
(1)
8
–2%
2%
V
0%
V
0.25%
A
750
μs
1
MΩ
Typical values are at TA = 25°C
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SLVS774C – JUNE 2007 – REVISED JANUARY 2016
8.7 Electrical Characteristics: VDCDC2 Step-Down Converter
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TA = –40°C to +85°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER
MIN TYP (1) MAX
TEST CONDITIONS
Input voltage range
2.5
IO
Maximum output current for TPS650240,
VO = 2.5 V
TPS650242, and TPS650245
800
mA
IO
Maximum output current for TPS650241
and TPS650243
VO = 2.5 V
1000
mA
IO
Maximum output current for TPS650244
VO = 2.5 V
1600
ISD
Shutdown supply current in VINDCDC2
EN_DCDC2 = GND
0.1
1
μA
RDS(ON)
P-channel MOSFET ON-resistance
VINDCDC2 = VGS = 3.6 V
140
300
mΩ
ILP
P-channel leakage current
VINDCDC2 = 6 V
2
μA
RDS(ON)
N-channel MOSFET ON-resistance
VINDCDC2 = VGS = 3.6 V
150
297
mΩ
ILN
N-channel leakage current
VDS = 6 V
7
10
μA
ILIMF
Forward current limit (P- and N-channel)
for TPS650240, TPS650242, and
TPS650245
2.5 V < VINDCDC2 < 6 V
1.05
1.16
1.29
A
ILIMF
Forward current limit (P- and N-channel)
for TPS650241 and TPS650243
2.5 V < VINDCDC2 < 6 V
1.22
1.35
1.5
A
ILIMF
Forward current limit (P- and N-channel)
for TPS650244
2.5 V < VINDCDC2 < 6 V
1.75
1.97
2.15
A
fS
Oscillator frequency
1.95
2.25
2.55
MHz
Fixed output voltage MODE = 0
(PWM/PFM)
Fixed output voltage MODE = 1 (PWM)
VDCDC2
1.8 V
–2%
2%
VINDCDC2 = 3.0 V to 6 V;
0 mA ≤ IO ≤ 1.6 A
2.5 V
–2%
2%
VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.6 A
1.8 V
–2%
2%
VINDCDC2 = 3.0 V to 6 V;
0 mA ≤ IO ≤ 1.6 A
2.5 V
–1%
1%
Adjustable output voltage with resistor
divider at DEFDCDC2; MODE = 0
(PWM)
VINDCDC2 = VDCDC2 + 0.5 V (min 2.5 V) to 6 V;
0 mA ≤ IO ≤ 1.6 A
–2%
2%
Adjustable output voltage with resistor
divider at DEFDCDC2; MODE = 1
(PWM)
VINDCDC2 = VDCDC2 + 0.5 V (min 2.5 V) to 6 V;
0 mA ≤ IO ≤ 1.6 A
–1%
1%
Line regulation
VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) to 6 V;
IO = 10 mA
Load regulation
IO = 10 mA to 1.6 A
Soft-start ramp time
VDCDC2 ramping from 5% to 95% of target value
R(L2)
Internal resistance from L2 to GND
V
mA
VINDCDC2 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 1.6 A
TSS
(1)
6
UNIT
VVINDCDC2
0%
V
0.25%
A
750
μs
1
MΩ
Typical values are at TA = 25°C
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8.8 Electrical Characteristics: VDCDC3 Step-Down Converter
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TA = –40°C to +85°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
IO
Maximum output current
VO = 1.6 V
ISD
Shutdown supply current in
VINDCDC3
EN_DCDC3 = GND
0.1
1
μA
RDS(ON)
P-channel MOSFET ON-resistance
VINDCDC3 = VGS = 3.6 V
310
698
mΩ
ILP
P-channel leakage current
VINDCDC3 = 6.0 V
0.1
2
μA
RDS(ON)
N-channel MOSFET ON-resistance
VINDCDC3 = VGS = 3.6 V
220
503
mΩ
ILN
N-channel leakage current
VDS = 6 V
7
10
μA
ILIMF
Forward current limit (P- and Nchannel)
2.5 V < VINDCDC3 < 6 V
1
1.2
1.4
A
fS
Oscillator frequency
1.95
2.25
2.55
MHz
VDCDC3
Fixed output voltage MODE = 1
(PWM)
800
VINDCDC3 = 2.5 V to 6 V;
0 mA ≤ IO ≤ 800 mA, VO = 0.9 V to 1.6 V
Line regulation
VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V) to 6 V;
IO = 10 mA
Load regulation
IO = 10 mA to 600 mA
TSS
Soft-start ramp time
VDCDC3 ramping from 5% to 95% of target value
R(L3)
Internal resistance from L3 to GND
(1)
10
6
UNIT
Input voltage range
Fixed output voltage MODE = 0
(PWM/PFM)
2.5
MAX
VVINDCDC3
V
mA
–2%
2%
–1%
1%
0%
V
0.25%
A
750
μs
1
MΩ
Typical values are at TA = 25°C
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SLVS774C – JUNE 2007 – REVISED JANUARY 2016
8.9 Electrical Characteristics: General
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TA = –40°C to +85°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
VLDO1 AND VLDO2 LOW DROPOUT REGULATORS
I(q)
Operating quiescent current
Current per LDO into VINLDO
16
30
μA
I(SD)
Shutdown current
Total current into VINLDO, VLDO = 0 V
0.6
2
μA
VINLDO
Input voltage range for LDO1, LDO2
1.5
6.5
V
VLDO1
LDO1 output voltage range
1
3.3
V
VLDO2
LDO2 output voltage range
1
3.3
V
VFB
LDO1 and LDO2 feedback voltage
See
IO
Maximum output current for LDO1, LDO2
Vin = 1.8 V, Vo = 1.3 V
IO
Maximum output current for LDO1, LDO2
Vin = 1.5 V; Vo = 1.3 V
ISC
LDO1 & LDO2 short circuit current limit
VLDO1 = GND, VLDO2 = GND
400
mA
Minimum voltage drop at LDO1, LDO2
IO = 50 mA, VINLDO = 1.8 V
120
mV
Minimum voltage drop at LDO1, LDO2
IO = 50 mA, VINLDO = 1.5 V
150
mV
Minimum voltage drop at LDO1, LDO2
IO = 200 mA, VINLDO = 1.8 V
300
mV
Output voltage ccuracy for LDO1, LDO2
IO = 10 mA
–2%
1%
Line regulation for LDO1, LDO2
VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5
V, IO = 10 mA
–1%
1%
Load regulation for LDO1, LDO2
IO = 0 mA to 200 mA
–1%
Regulation time for LDO1, LDO2
Load change from 10% to 90%
10
Vdd_alive LDO output voltage,
TPS650240 to TPS650244
IO = 0 mA
1.2
Vdd_alive LDO output voltage,
TPS650245
IO = 0 mA
1.1
(2)
1
V
200
mA
120
65
mA
1%
μs
Vdd_alive LOW DROPOUT REGULATOR
Vdd_alive
V
IO
Output current for Vdd_alive
ISC
Vdd_alive short circuit current limit
Vdd_alive = GND
Output voltage accuracy for Vdd_alive
IO = 0 mA
–1%
Line regulation for Vdd_alive
VCC = Vdd_alive + 0.5 V to 6.5 V, IO = 0 mA
–1%
Regulation time for Vdd_alive
Load change from 10% to 90%
30
mA
100
mA
1%
1%
μs
10
ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH
High level input voltage
1.3
VCC
VIL
Low level input voltage
0
0.1
V
IH
Input bias current
0.05
μA
0.001
V
THERMAL SHUTDOWN
TSD
Thermal shutdown
Increasing junction temperature
160
°C
Thermal shudown hysteresis
Decreasing junction temperature
20
°C
INTERNAL UNDER VOLTAGE LOCK OUT
UVLO
Internal UVLO
VUVLO_HYST
Internal UVLO comparator hysteresis
VCC falling
–3%
2.35
3%
120
V
mV
VOLTAGE DETECTOR COMPARATOR
PWRFAIL_SNS
Comparator threshold
Falling threshold
Hysteresis
VOL
(1)
(2)
–2%
1
2%
V
40
50
60
mV
Propagation delay
25 mV overdrive
10
μs
Power fail output low voltage
IOL = 5 mA
0.3
V
Typical values are at TA = 25°C
If the feedback voltage is forced higher than above 1.2 V, a leakage current into the feedback pin may occur.
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8.10 Typical Characteristics
Table 1. Table of Graphs
FIGURE
η
Efficiency VDCDC1
vs Load current PWM/PFM; VO = 3.3 V
Figure 1
η
Efficiency VDCDC1
vs Load current PWM; VO = 3.3 V
Figure 2
η
Efficiency VDCDC2
vs Load current PWM/PFM; VO = 1.8 V
Figure 3
η
Efficiency VDCDC2
vs Load current PWM; VO = 1.8 V
Figure 4
η
Efficiency VDCDC3
vs Load current PWM/PFM; VO = 1.3 V
Figure 5
η
Efficiency VDCDC3
vs Load current PWM; VO = 1.3 V
Figure 6
Line transient response VDCDC1
Figure 7
Line transient response VDCDC2
Figure 8
Line transient response VDCDC3
Figure 9
Load transient response VDCDC1
Figure 10
Load transient response VDCDC2
Figure 11
Load transient response VDCDC3
Figure 12
Output voltage ripple DCDC2; PFM mode
Figure 13
Output voltage ripple DCDC2; PWM mode
Figure 14
Load regulation for Vdd_alive
Figure 15
Start-up VDCDC1 to VDCDC3
Figure 16
Start-up LDO1 and LDO2
Figure 17
100
100
90
90
VI = 3.8 V
80
80
70
VI = 5 V
Efficiency - %
Efficiency - %
70
VI = 4.2 V
60
50
40
VI = 3.8 V
50
VI = 4.2 V
40
VI = 5 V
TA = 25°C,
VO = 3.3 V,
PFM/PWM Mode
20
10
1
10
100
1k
IO - Output Current - mA
20
10
10k
Figure 1. DCDC1: Efficiency vs Output Current
12
60
30
30
0
0.1
TA = 25°C,
VO = 3.3 V,
PWM Mode
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0
0.1
1
10
100
1k
IO - Output Current - mA
10k
Figure 2. DCDC1: Efficiency vs Output Current
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SLVS774C – JUNE 2007 – REVISED JANUARY 2016
VI = 2.5 V
VI = 3.8 V
Efficiency - %
Efficiency - %
VI = 3.8 V
VI = 4.2 V
VI = 4.2 V
VI = 2.5 V
VI = 5 V
VI = 5 V
TA = 25oC
VO = 1.8 V
PWM Mode
o
TA = 25 C
VO = 1.8 V
PWM / PFM Mode
0.01
0.1
10
1
100
1k
10 k
0.01
0.1
80
VI = 2.5 V
70
VI = 2.5 V
Efficiency - %
Efficiency - %
TA = 25°C,
VO = 1.5 V,
PWM Mode
90
70
60
VI = 3 V
50
VI = 3.8 V
VI = 4.2 V
VI = 3 V
VI = 3.8 V
60
50
VI = 4.2 V
40
VI = 5 V
30
20
0
0.01
10 k
100
TA = 25°C,
90 VO = 1.5 V,
PWM/PFM Mode
80
10
1k
Figure 4. DCDC2: Efficiency vs Output Current
100
30
100
IO - Output Current - mA
Figure 3. DCDC2: Efficiency vs Output Current
40
10
1
IO - Output Current - mA
20
VI = 5 V
10
0.1
1
10
100
IO - Output Current - mA
1k
Figure 5. DCDC3: Efficiency vs Output Current
Ch1 = VI
0
0.01
0.1
1
10
100
IO - Output Current - mA
1k
Figure 6. DCDC3: Efficiency vs Output Current
Ch1 = VI
Ch2 = VO
Ch2 = VO
IO = 100 mA
VI = 3.8 V to 4.5 V
VO = 3.3 V
Figure 7. VDCDC1 Line Transient Response
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IO = 100 mA
VI = 3 V to 4 V
VO = 1.8 V
PWM Mode
Figure 8. VDCDC2 Line Transient Response
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Ch4 = IO
Ch1 = VI
Ch2 = VO
Ch2 = VO
IO = 160 mA to 1400 mA
VO = 3.3 V
IO = 100 mA
VI = 3 V to 4 V
VO = 1.375 V
Figure 9. VDCDC3 Line Transient Response
Ch4 = IO
Ch4 = IO
Ch2 = VO
Ch2 = VO
IO = 80 mA to 720 mA
VO = 1.375 V
IO = 100 mA to 900 mA
VO = 1.8 V
Figure 11. VDCDC2 Load Transient Response
VI = 3.8 V
VO = 1.8 V
IO = 1 mA
o
TA = 25 C
PFM Mode
Figure 13. VDCDC2 Output Voltage Ripple, PFM Mode
14
Figure 10. VDCDC1 Load Transient Response
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Figure 12. VDCDC3 Load Transient Response
VI = 3.8 V
VO = 1.8 V
IO = 1 mA
TA = 25oC
PWM Mode
Figure 14. VDCDC2 Output Voltage Ripple, PWM Mode
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SLVS774C – JUNE 2007 – REVISED JANUARY 2016
1.26
ENABLE
VCC = 3.6 V
VO - Output Voltage - V
1.24
VDCDC1
1.22
1.2
VDCDC2
1.18
1.16
VDCDC3
1.14
0
5
10
15
20
25
30 35
IO - Output Current - mA
40
45
Figure 15. VDD_ALIVE Output Voltage vs Output Current
Figure 16. Startup VDCDC1, VDCDC2, VDCDC3
ENABLE
LDO1
LDO2
Figure 17. Start-Up LDO1 AND LDO2
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9 Detailed Description
9.1 Overview
The TPS65024x are integrated power management ICs that contain three highly efficient step-down DC–DC
converters, two 200-mA LDOs, and one 30-mA LDO. Capable of using one Li-Ion or Li-Polymer cell as the input
voltage source, the TPS65024x family can support various battery-powered applications for a variety of voltages.
Each TPS65024x device uses predefined output voltages, differentiated by the default output voltages defined for
DCDC3. The output voltages of the 200-mA LDOs and two of the step-down converters are the same for all
devices, and may be adjusted through external feedback resistors to operate outside of their predefined default
values. The third step-down converter, DCDC3, uses DEFDCDC3 slightly differently than the other two
converters, and as such requires an alternative method for adjusting the output voltages.
16
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SLVS774C – JUNE 2007 – REVISED JANUARY 2016
9.2 Functional Block Diagram
TPS650240
1R
VCC
Vbat
1mF
L1
VINDCDC 1
Vbat
10mF
DCDC1 (I/O)
ENABLE
STEP-DOWN
CONVERTER
1000 mA
EN_DCDC 1
VINDCDC 2
Vbat
DCDC 2
(memory)
10mF
STEP-DOWN
CONVERTER
800 mA
EN_DCDC 2
ENABLE
VINDCDC 3
Vbat
VDCDC1
R1
22 mF
DEFDCDC 1
PGND 1
R2
2.5V or 1.8V
L2
VDCDC2
2.2 mH
STEP-DOWN
CONVERTER
800 mA
DEFDCDC 3
EN_DCDC 3
R3
22 mF
DEFDCDC 2
PGND 2
R4
1.0V or 1.3V
L3
DCDC 3 (core)
10mF
1.0V / 1.3V
ENABLE
3.3V or 2.8V
2.2 mH
VDCDC 3
2.2uH
22 mF
PGND 3
MODE
PWM / PFM
VIN_LDO
VIN
VLDO 1
VLDO1
R5
200 mA LDO
EN_LDO
ENABLE
2.2 mF
R6
VLDO 2
VLDO2
R7
200 mA LDO
R8
EN_Vdd_aliv
e
ENABLE
VCC
Vbat
2.2 mF
VLDO 3
30 mA LDO
Vdd_alive
1.2 V
2.2 mF
R9
I/O voltage
PWRFAIL _SNS
R10
-
PWRFAIL
R19
+
Vref = 1 V
AGND 1
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AGND2
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9.3 Feature Description
9.3.1 Step-Down Converters, VDCDC1, VDCDC2 and VDCDC3
The TPS65024x devices incorporate three synchronous step-down converters operating typically at 2.25-MHz
fixed-frequency pulse width modulation (PWM) for moderate to heavy-load currents. At light-load currents the
converters automatically enter power save mode and operate with pulse frequency modulation (PFM). The
maximum supported load currents for VDCDC1 and VDCDC2 are device specific, unlike VDCDC3 which does
not have the capability to exceed an 800-mA output.
The converter output voltages can be programmed through the DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins.
The pins can often be connected to GND, VCC, or to a resistor divider between the output voltage and GND.
The VDCDC1 converter defaults to 2.80 V or 3.3 V depending on the DEFDCDC1 configuration pin, if
DEFDCDC1 is tied to ground the default is 2.80 V, if it is tied to VCC the default is 3.3 V. When the DEFDCDC1
pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V.
Reference the Output Voltage Selection section for details on setting the output voltage range.
The VDCDC2 converter defaults to 1.8 V or 2.5 V depending on the DEFDCDC2 configuration pin, if DEFDCDC2
is tied to ground the default is 1.8 V, if it is tied to VCC the default is 2.5 V. When the DEFDCDC2 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.
The VDCDC3 converter defaults to 1.0 V or 1.3 V for the TPS650240 depending on the DEFDCDC3
configuration pin, if DEFDCDC3 is tied to ground the default is 1.0 V, if it is tied to VCC the default is 1.3 V. The
DEFDCDC3 pin cannot be connected to a resistor divider. In opposition to DEFDCDC1 and DEFDCDC2, the
DEFDCDC3 pin can be used to change the core voltage during operation by changing its logic level from HIGH
to LOW or vice versa. TPS650241 to TPS650245 allow different voltages for the VDCDC3 converter. Reference
the Voltage Options section for the TPS650240, TPS650241, TPS650242, TPS650243, TPS650244, and
TPS650245 default voltage options.
During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feedforward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
The current limit comparator also turns off the switch in case the current limit of the P-channel switch is
exceeded. After the adaptive dead-time used to prevent shoot through current, the N-channel MOSFET rectifier
is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off
the N-channel rectifier and turning on the P-channel switch.
The three DC–DC converters operate synchronized to each other, with the VDCDC1 converter as the master. A
180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3
switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a
typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V, the
VDCDC2 converter from 3.7 V to 2.5 V and the VDCDC3 converter from 3.7 V to 1.5 V.
18
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9.4 Device Functional Modes
9.4.1 Power Save Mode Operation
As the load current decreases, the converters enter power save mode operation. During power save mode the
converters operate in a burst mode (PFM mode) with a frequency between 1.125 MHz and 2.25 MHz for one
burst cycle. However, the frequency between different burst cycles depends on the actual load current and is
typically far less than the switching frequency, with a minimum quiescent current to maintain high efficiency.
To optimize the converter efficiency at light load, the average current is monitored, and if in PWM mode, the
inductor current remains below a certain threshold before the device enters power save mode. The typical
threshold to enter power save mode can be calculated in Equation 1, Equation 2, and Equation 3:
I PFMDCDC1enter = VINDCDC 1
(1)
24Ω
VINDCDC
2
I PFMDCDC2enter =
26Ω
(2)
I PFMDCDC3leave = VINDCDC 3
39Ω
(3)
During power save mode the output voltage is monitored with a comparator and by maximum skip burst width.
As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the
converter effectively delivers a constant current as defined in Equation 4, Equation 5, and Equation 6.
I PFMDCDC1leave = VINDCDC 1
18Ω
(4)
I PFMDCDC2leave = VINDCDC 2
20Ω
(5)
VINDCDC
3
I PFMDCDC3enter =
29Ω
(6)
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the
other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage
has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode
if either of the following conditions are met:
1. The output voltage drops 2% below the nominal VO due to increased load current
2. The PFM burst time exceeds 16 × 1 / fs (7.1 μs typical)
These control methods reduce the quiescent current to typically 14 μA per converter and the switching activity to
a minimum thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal
output voltage at light-load current results in a very low output voltage ripple. The ripple depends on the
comparator delay and the size of the output capacitor; increasing capacitor values makes the output ripple tend
to zero. Power save mode can be disabled by pulling the MODE pin high. This forces all DC–DC converters into
fixed-frequency PWM mode.
9.4.2 Soft-Start
Each of the three converters has an internal soft-start circuit that limits the inrush current during start-up. The
soft-start is realized by using a very low current to initially charge the internal compensation capacitor. The softstart time is typically 750 μs if the output voltage ramps from 5% to 95% of the final target value. If the output is
already precharged to some voltage when the converter is enabled, then this time is reduced proportionally.
There is a short delay of typically 170 μs between the converter being enabled and switching activity actually
starting. This is to allow the converter to bias itself properly, to recognize if the output is precharged, and if so, to
prevent discharging of the output while the internal soft-start ramp catches up with the output voltage.
9.4.3 100% Duty Cycle Low-Dropout Operation
The TPS65024x converters offer a low input-to-output voltage difference while still maintaining operation with the
use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage required to maintain DC regulation depends on the load
current and output voltage and can be calculated in Equation 7.
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Device Functional Modes (continued)
Vin min + Vout min ) Iout max
ǒRDSonmax ) R LǓ
where
•
•
•
•
Ioutmax = Maximum load current (note: ripple current in the inductor is zero under these conditions)
RDSonmax = Maximum P-channel switch RDSon
RL = DC resistance of the inductor
Voutmin = Nominal output voltage minus 2% tolerance limit
(7)
9.4.4 Low-Dropout Voltage Regulators
The low-dropout voltage regulators are designed to operate well with low-value ceramic input and output
capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 300
mV at the rated output current. Each LDO sports a current limit feature. Both LDOs are enabled by the EN_LDO
pin. The LDOs also have reverse conduction prevention. This allows the possibility to connect external regulators
in parallel in systems with a backup battery. The TPS65024x step-down and LDO voltage regulators
automatically power down when the VCC voltage drops below the UVLO threshold or when the junction
temperature rises above 160°C.
9.4.5 Undervoltage Lockout
The undervoltage lockout circuit for the five regulators on the TPS65024x prevents the device from
malfunctioning at low input voltages and from excessive discharge of the battery. It disables the converters and
LDOs. The UVLO circuit monitors the VCC pin; the threshold is set internally to 2.35 V with 5% (120 mV)
hysteresis.
NOTE
When any of the DC–DC converters are running there is an input current at the VCC pin,
which can be up to 3 mA when all three converters are running in PWM mode. Take this
current into consideration if an external RC filter is used at the VCC pin to remove
switching noise from the TPS65024x internal analog circuitry supply.
See VCC Filter for details on the external RC filter.
9.4.6 Power-Up Sequencing
The TPS65024x power-up sequencing is designed to be entirely flexible and customer driven; this is achieved
simply by providing separate enable pins for each switch-mode converter and a common enable signal for LDO1
and LDO2. The relevant control pins are described in Table 2.
Table 2. Control Pins for DCDC Converters
PIN NAME
INPUT/
OUTPUT
DEFDCDC3
I
Defines the default voltage of the VDCDC3 switching converter. See Table 3 for details.
DEFDCDC2
I
Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8 V,
DEFDCDC2 = VCC defaults VDCDC2 to 2.5 V.
DEFDCDC1
I
Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 2.80 V,
DEFDCDC1 = VCC defaults VDCDC1 to 3.3 V.
EN_DCDC3
I
Set EN_DCDC3 = 0 to disable or EN_DCDC3 = 1 to enable the VDCDC3 converter
EN_DCDC2
I
Set EN_DCDC2 = 0 to disable or EN_DCDC2 = 1 to enable the VDCDC2 converter
EN_DCDC1
I
Set EN_DCDC1 = 0 to disable or EN_DCDC1 = 1 to enable the VDCDC1 converter
9.4.7
FUNCTION
PWRFAIL
The PWRFAIL signal is generated by a voltage detector at the PWRFAIL_SNS input. The input signal is
compared to a 1-V threshold (falling edge) with 5% (50 mV) hysteresis. PWRFAIL is an open-drain output which
is actively low when the input voltage at PWRFAIL_SNS is below the threshold.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Output Voltage Selection
The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down
converter. See Table 3 for the default voltages if the pins are pulled to GND or to VCC.
Table 3. Voltage Options
PIN
LEVEL
DEFDCDC1
All versions
DEFDCDC2
All versions
TPS650240
TPS650241
TPS650242
DEFDCDC3
TPS650243
TPS650244
TPS650245
DEFAULT OUTPUT VOLTAGE
VCC
3.3 V
GND
2.80 V
VCC
2.5 V
GND
1.8 V
VCC
1.3 V
GND
1.0 V
VCC
1.375 V
GND
0.9 V
VCC
1.5 V
GND
1.0 V
VCC
1.2 V
GND
1.0 V
VCC
1.6 V
GND
1.55 V
VCC
1.1 V
GND
0.9 V
If a different voltage is needed, an external resistor divider can be added to the DEFDCDC1 or DEFDCDC2 pin
as shown in Figure 18.
10 R
Vbat
VCC
1 mF
VDCDC1
L1
VINDCDC1
CIN
COUT
EN_DCDC1
VOUT
L
R1
DEFDCDC1
R2
AGND
PGND
Figure 18. External Resistor Divider Diagram
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When a resistor divider is connected to DEFDCDC1 or DEFDCDC2, the output voltage can be set from 0.6 V up
to the input voltage Vbat. The total resistance (R1 + R2) of the voltage divider must be kept in the 1-MΩ range to
maintain a high efficiency at light load. Detailed calculations for selecting these resistance values are presented
in Equation 8 and Equation 9, where VDEFDCDCx = 0.6 V.
V OUT = V DEFDCDCx x R1 + R2
(8)
R2
V OUT
R1 = R2
- R2
VDEFDCDCx
(9)
(
)
10.1.2 Voltage Change on VDCDC3
The output voltage of VDCDC3 can be changed during operation from, for example, 1.0 V to 1.3 V (TPS650240),
and back. While the output voltage at VDCDC1 and VDCDC2 is fixed after the device exits undervoltage lockout
(UVLO), the status of the DEFDCDC3 pin is sensed during operation and the voltage is changed as soon as the
logic level on this pin changes from low to high or vice versa. Therefore it is not possible to connect a resistor
divider to DEFDCDC3 and set a voltage different from the predefined voltages.
10.1.3 Vdd_alive Output
The Vdd_alive LDO is typically connected to a logic input of an external device or application processor, and is
capable of providing an output voltage of 1.2 V at 30 mA. For the TPS650245, the output voltage for vdd_alive is
set to 1.1 V. TI recommends adding a capacitor of 2.2 μF minimum to the Vdd_alive pin. The LDO can be
disabled by pulling the EN_Vdd_alive pin to GND.
10.1.4 LDO1 and LDO2
The LDOs in the TPS65024x are general-purpose LDOs which are stable using ceramics capacitors. The
minimum output capacitance required is 2.2 μF. The LDOs output voltage can be changed to different voltages
between 1.0 V and Vin using an external resistor divider. Therefore they can also be used as general-purpose
LDOs in the application. The supply voltage for the LDOs needs to be connected to the VINLDO pin, giving the
flexibility to connect the lowest voltage available in the system and therefore providing the highest efficiency.
The total resistance (R5 + R6) of the voltage divider must be kept in the 1-MΩ range to maintain high efficiency
at light load. Detailed calculations for selecting these resistance values are presented in Equation 10 and
Equation 11, where VFBLDOx= 1.0 V.
V OUT = V FBLDOx x R5 + R6
R6
(10)
V OUT
R5 = R6 x
- R6
VFBLDOx
(
)
(11)
10.1.5 VCC Filter
An RC filter connected at the VCC input is recommended to prevent noise from entering the internal supply used
for the bandgap and other analog circuitry. A typical value of 1 Ω and 1 μF is used to filter the switching spikes,
generated by the DC–DC converters. A larger resistor than 10 Ω must not be used because the current into VCC
of up to 2.5 mA causes a voltage drop at the resistor causing the undervoltage lockout circuitry connected at VCC
internally to switch off too early.
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10.2 Typical Applications
10.2.1 Typical Configuration for the Samsung Processor S3C6400-533MHz
The typical configuration for the Samsung processor S3C6400-533-MHz is shown in Figure 19. This application
uses only the default output values for the step-down converters, specifying regulation targets with high and low
logic on the DEFDCDCx pins.
S3C6400533MHz
Vcc
VIN
TPS650245
1m F
VIN
VDDMMC (3.3V)
VINDCDC1
DCDC1
1000mA
10mF
VIN VINDCDC2
10mF
VIN
VDDEXT (3.3V)
3.3mH
L1
VDDHI (3.3V)
10mF
L2
DCDC2
800mA
VINDCDC3
VDDLCD (3.3V)
VDDPCM (3.3V)
VDCDC1
VDDSYS (3.3V)
2.2mH
VDCDC2
VDD_MEM0 (1.8V)
VDD_MEM1 (1.8V)
10mF
10mF
DCDC3
800mA
DEFDCDC1
VIN
L3
10mF
LDO2
300kW
LDO2
200mA
FB_LDO2
DEFDCDC3
VDDADC (3.3V)
VDDDAC (3.3V)
2.2mF
VDDOTG (3.3V)
VDDUH (3.3V)
130kW
LDO1
EN_DCDC1
LDO1
200mA
EN_DCDC2
EN_DCDC3
VDDOTGI (1.1V)
33kW
FB_LDO1
2.2mF
330kW
VINLDO1/2
VIN
VDDARM (0.9V/1.1V)
VDCDC3
DEFDCDC2
0.9V/1.1V
2.2mH
1 mF
Vdd_alive 1.1V
VDDALIVE
EN_LDO1/2
1mF
VIO
VIN
EN_VDDalive
VIN
1MW
R2
PWRFAIL
PWRFAIL_SNS
-
R3
1V
+
GND
APLL (1.0V)
2.2mH
EPLL (1.0V)
MPLL (1.0V)
VIN
VIN
10mF
AGND , PowerPAD
VDDINT (1.0V)
SW
EN
EN
TPS62260
MODE
FB 22pF
GND
100kW
10mF
150kW
Figure 19. Samsung Processor Configuration
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Typical Applications (continued)
10.2.1.1 Design Requirements
Each step-down converter requires an input decoupling capacitor, an output inductor, and an output filter
capacitor. Desired output voltages must be configured through appropriate DEFDCDCx voltages, and all
components must be selected to handle the maximum output currents, as well as any transient or ripple
specifications that may be required for the expected loads.
The LDOs must have a decoupling capacitor on the input voltage pin, and a dedicated filter capacitor on each
LDO output.
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Inductor Selection for the DC-DC Converters
The three converters operate with 2.2-µH output inductors. Larger or smaller inductor values can be used to
optimize performance of the device for specific conditions. The selected inductor has to be rated for its DC
resistance and saturation current. The DC resistance of the inductor influences directly the efficiency of the
converter. Therefore, an inductor with the lowest DC resistance must be selected for the highest efficiency.
For a fast transient response, a 2.2-μH inductor in combination with a 22-μF output capacitor is recommended.
For an output voltage above 2.8 V, an inductor value of 3.3 μH minimum is required. Lower values result in an
increased output voltage ripple in PFM mode. The minimum inductor value is 1.5 μH, but an output capacitor of
22 μF minimum is needed in this case.
Equation 12 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor must be rated higher than the maximum inductor current as calculated with Equation 12. This is
recommended because during heavy-load transient, the inductor current rises above the calculated value.
1 * Vout
DI
Vin
DI L + Vout
I Lmax + I outmax ) L
2
L ƒ
where
•
•
•
•
f = Switching frequency (2.25 MHz typical)
L = Inductor value
ΔIL = Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
(12)
The highest inductor current occurs at maximum Vin.
Open-core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Consideration must be given to the difference in the core material from inductor to
inductor which has an impact on efficiency especially at high switching frequencies.
10.2.1.2.2 Output Capacitor Selection
The advanced fast response voltage mode control scheme of the inductive converters implemented in the
TPS65024x allows the use of small ceramic capacitors with a typical value of 10 µF for each converter, without
having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low
ESR values have the lowest output voltage ripple and are recommended.
If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application
requirements. For completeness, the RMS ripple current is calculated as Equation 13:
1 * Vout
1
Vin
I RMSCout + Vout
L ƒ
2 Ǹ3
(13)
At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
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Typical Applications (continued)
DVout + Vout
1 * Vout
Vin
L ƒ
ǒ8
1
Cout
ƒ
Ǔ
) ESR
where
•
the highest output voltage ripple occurs at the highest input voltage, Vin
(14)
At light-load currents the converters operate in power save mode and output voltage ripple is dependent on the
output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. Typical output voltage ripple is less than 1% of the nominal output voltage.
10.2.1.2.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing interference with other circuits caused by high input
voltage spikes. Each DC–DC converter requires a 10-μF ceramic input capacitor on its input pin VINDCDCx. The
input capacitor can be increased without any limit for better input voltage filtering. The VCC pin must be separated
from the input for the DC–DC converters. A filter resistor of up to 10 Ω and a 1-μF capacitor must be used for
decoupling the VCC pin from switching noise.
NOTE
The filter resistor may affect the UVLO threshold since up to 3 mA can flow through this
resistor into the VCC pin when all converters are running in PWM mode.
10.2.1.3 Application Curves
100
VI = 2.5 V
90
VI = 3.8 V
80
VI = 5 V
VI = 3.8 V
Efficiency - %
Efficiency - %
70
VI = 4.2 V
60
50
VI = 4.2 V
VI = 5 V
40
30
o
TA = 25°C,
VO = 3.3 V,
PFM/PWM Mode
20
10
0
0.1
TA = 25 C
VO = 1.8 V
PWM / PFM Mode
1
10
100
1k
IO - Output Current - mA
10k
Figure 20. DCDC1: Efficiency vs Output Current
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0.01
0.1
1
10
100
1k
10 k
IO - Output Current - mA
Figure 21. DCDC2: Efficiency vs Output Current
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Typical Applications (continued)
10.2.2 Typical Configuration for the Titan 2 Processor
The typical configuration for the Titan processor is shown in Figure 22. This application highlights the ability to
increase the voltage on DCDC3 by using a single external resistor.
Vcc
VIN
Titan
TPS650244
1mF
VINDCDC1
VIN
10mF
3.3mH LPS3015
L1
VINDCDC2
VIN
DCDC1
800mA
10mF
VINDCDC3
VIN
VDDIO (3.3V)
10mF
VDCDC1
2.2mH LPS3015
L3
VDD _ MEM (1.8V)
10mF
DCDC3
800mA
DEFDCDC1
VIN
DEFDCDC3
(set to1.8V)
VIN
DCDC2
1600mA
VDCDC2
220kW
62kW
22mF
VDCDC3
L2
2.2mH VLCF4020
core (1.2V)
VDCDC2
22mF
DEFDCDC2
LDO2
RTC I /O (3.3V)
220kW
LDO2
200mA
EN_DCDC1
2.2mF
130kW
EN_DCDC2
LDO1
EN_DCDC3
VIN
300kW
FB_LDO2
LDO1
200mA
100kW
FB_LDO1
RTC core (1.2V)
2.2mF
510kW
VINLDO1/2
1mF
Vdd_alive 1.2V
(not used)
open
EN_LDO1/2
VIO
1MW
EN_VDDalive
PWRFAIL_SNS
Input Voltage
TBD
POWERFAIL
+
Figure 22. Titan Processor Configuration
10.2.2.1 Design Requirements
Each step-down converter requires an input decoupling capacitor, an output inductor, and an output filter
capacitor. Desired output voltages must be configured through appropriate DEFDCDCx voltages, and all
components must be selected to handle the maximum output currents, as well as any transient or ripple
specifications that may be required for the expected loads.
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Typical Applications (continued)
The LDOs must have a decoupling capacitor on the input voltage pin, and a dedicated filter capacitor on each
LDO output.
10.2.2.2 Detailed Design Procedure
Refer to the Samsung Processor Detailed Design Procedure for full design procedure details.
As only DCDC2 on the TPS650244 is capable of supporting a sufficient core current up to 1.6 A, a resistive
divider is first implemented on DEFDCDC2 to produce this required 1.2-V rail. DCDC3 is then modified to support
the memory voltage of 1.8 V. As DCDC3 cannot support 1.8 V from a default configuration, the output voltage is
first programmed to a lower value, in this case 1.6 V, by setting DEFDCDC3 = HIGH. Even though DCDC3 does
not support an external resistor divider on DEFDCDC3, it can still be tricked into regulating a higher output
voltage of 1.8 V by presenting the VDCDC3 feedback pin with 200 mV less than the original target of 1.6 V. The
internal resistance at VDCDC3 when programmed to 1.6 V is 480 kΩ, so the external resistance needed to drop
200 mV within the feedback path and increase the output voltage from 1.6 V to 1.8 V is 60 kΩ (62 kΩ).
11 Power Supply Recommendations
To avoid damaging the device, ensure all applied voltages to the pins do not exceed the absolute maximums
listed in Absolute Maximum Ratings. Input voltage to the LDOs must be at least 300 mV higher than the largest
LDO output voltage to accommodate for the maximum dropout voltage. As power supply requirements varies
across applications, consider the expected output voltages and the maximum load currents of each regulator
when determining a minimum required current rating for an acceptable power supply.
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12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
•
•
The input capacitors for the DC-DC converters must be placed as close as possible to the VINDCDCx and
VCC pins.
The inductor of the output filter must be placed as close as possible to the device to provide the shortest
switch node possible, reducing the noise emitted into the system and increasing the efficiency.
Sense the feedback voltage of the output at the output capacitors to ensure the best DC accuracy. Feedback
must be routed away from noisy sources such as the inductor. If possible route on the opposite side from the
switch node and inductor and place a GND plane between the feedback and the noisy sources or a keep-out
underneath them entirely.
Place the output capacitors as close as possible to the inductor to reduce the feedback loop. This ensures the
best regulation at the feedback point.
Place the device as close as possible to the most demanding or sensitive load. The output capacitors must
be placed close to the input of the load. This ensures the best AC performance possible.
The input and output capacitors for the LDOs must be placed close to the device for best regulation
performance.
Use vias to connect thermal pad to ground plane.
A common ground plane is recommended for the layout of this device. The AGND can be separated from the
PGND, but a large low-parasitic PGND is required to connect the PGNDx pins to the CIN and external PGND
connections. If the AGND and PGND planes are separated, have one connection point to reference the
grounds together. Place this connection point close to the IC.
12.2 Layout Example
Figure 23. Layout Diagram
28
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Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245
TPS650240, TPS650241, TPS650242
TPS650243, TPS650244, TPS650245
www.ti.com
SLVS774C – JUNE 2007 – REVISED JANUARY 2016
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS650240
Click here
Click here
Click here
Click here
Click here
TPS650241
Click here
Click here
Click here
Click here
Click here
TPS650242
Click here
Click here
Click here
Click here
Click here
TPS650243
Click here
Click here
Click here
Click here
Click here
TPS650244
Click here
Click here
Click here
Click here
Click here
TPS650245
Click here
Click here
Click here
Click here
Click here
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2007–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245
29
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS650240RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
650240
Samples
TPS650240RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
650240
Samples
TPS650241RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
650241
Samples
TPS650241RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
650241
Samples
TPS650242RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
650242
Samples
TPS650243RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
650243
Samples
TPS650243RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
650243
Samples
TPS650244RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
650244
Samples
TPS650244RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
650244
Samples
TPS650245RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
650245
Samples
TPS650245RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
650245
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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