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TPS65053-Q1
SLVSAW1A – JUNE 2011 – REVISED JANUARY 2017
TPS65053-Q1 5-Channel Power Management IC With Two Step-Down Converters
and Three Low-Input Voltage LDOs
1 Features
3 Description
•
•
The TPS65053-Q1 device is integrated power
management IC (PMIC) for applications powered by
one Li-Ion or Li-Polymer cell, which require multiple
power rails. The TPS65053-Q1 device provides two
highly efficient, 2.25-MHz step-down converters
targeted at providing the core voltage and I/O voltage
in a processor-based system. Both step-down
converters enter a low power mode at light loads for
maximum efficiency across the widest possible range
of load currents. For low-noise applications, the
devices can be forced into fixed-frequency PWM
mode by pulling the MODE pin high. Both converters
allow the use of small inductors and capacitors to
achieve a small solution size.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 3: –40°C to +85°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Up To 95% Efficiency
Output Current for DC-DC Converters:
– DCDC1 = 1 A; DCDC2 = 0.6 A
DC-DC Converters Externally Adjustable
VIN Range for DC-DC Converters
From 2.5 V to 6 V
2.25-MHz Fixed Frequency Operation
Power Save Mode at Light-Load Current
180° Out-of-Phase Operation
Output Voltage Accuracy in PWM Mode ±1%
Total Typical 32-μA Quiescent Current for Both
DC-DC Converters
100% Duty Cycle for Lowest Dropout
One General-Purpose 400-mA LDO
Two General-Purpose 200-mA LDOs
VIN Range for LDOs from 1.5 V to 6.5 V
Output Voltage for LDO3:
– VLDO3 = 1.3 V
Available in a 4-mm × 4-mm 24-Pin VQFN
Package
2 Applications
•
Automotive Li-Ion Battery-Powered Devices
– GPS, Emergency Cell Phone
– Digital Cameras
– Satellite Radio Modules
– OMAP™ and Low-Power DSP
The TPS65053-Q1 device provides an output current
of up to 1 A on the DCDC1 converter and up to 0.6 A
on the DCDC2 converter. The device also integrates
one 400-mA LDO and two 200-mA LDO voltage
regulators, which can be turned on and off using
separate enable pins on each LDO. Each LDO
operates with an input voltage range from 1.5 V to
6.5 V, allowing them to be supplied from one of the
step-down converters or directly from the main
battery. LDO1 and LDO2 are externally adjustable,
while LDO3 has a fixed output voltage of 1.3 V.
The TPS65053-Q1 device is available in a small 24pin leadless package (4-mm × 4-mm VQFN) with a
0,5-mm pitch.
Device Information(1)
PART NUMBER
PACKAGE
TPS65053-Q1
VQFN (24)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency of DCDC1
100
90
80
5V
Efficiency − %
70
4.2 V
60
50
3.8 V
3.4 V
40
30
20
10
0
0.0001
0.1
0.001
0.01
IO − Output Current − A
1
10
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65053-Q1
SLVSAW1A – JUNE 2011 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Function ...........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ....................................... 10
Feature Description................................................. 11
Device Functional Modes........................................ 12
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2011) to Revision A
Page
•
Added the Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
•
Deleted all references to TPS650531-Q1 and TPS650532-Q1 devices ............................................................................... 1
•
Changed values in the Thermal Information table to align with JEDEC standards................................................................ 5
2
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SLVSAW1A – JUNE 2011 – REVISED JANUARY 2017
5 Pin Configuration and Function
PGND1
L1
VINDCDC1/2
L2
PGND2
FB_DCDC2
18
17
16
15
14
13
RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
FB_DCDC1
19
12
EN_LDO3
EN_DCDC1
20
11
EN_LDO2
EN_DCDC2
21
10
RESET
EN_LDO1
22
9
VLDO3
MODE
23
8
VINLDO2/3
AGND
24
7
VLDO2
Thermal
1
2
3
4
5
6
VCC
VINLDO1
VLDO1
FB_LDO1
THRESHOLD
FB_LDO2
Pad
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
24
I
Analog GND, connect to PGND and thermal pad
EN_DCDC1
20
I
Enable Input for converter 1, active high
EN_DCDC2
21
I
Enable Input for converter 2, active high
EN_LDO1
22
I
Enable input for LDO1. Logic high enables the LDO, logic low disables the LDO.
EN_LDO2
11
I
Enable input for LDO2. Logic high enables the LDO, logic low disables the LDO.
EN_LDO3
12
I
Enable input for LDO3. Logic high enables the LDO, logic low disables the LDO.
FB_DCDC1
19
I
Input to adjust output voltage of converter 1 between 0.6 V and VI. Connect external resistor divider between VOUT1, this
pin and GND.
FB_DCDC2
13
I
Input to adjust output voltage of converter 2 between 0.6 V and VIN. Connect external resistor divider between VOUT2, this
pin and GND.
FB_LDO1
4
I
Feedback input for the external voltage divider.
FB_LDO2
6
I
Feedback input for the external voltage divider.
L1
17
O
Switch pin of converter 1. Connected to Inductor
L2
15
O
Switch Pin of converter 2. Connected to Inductor.
MODE
23
I
Select between Power Save Mode and forced PWM Mode for DCDC1 and DCDC2. In Power Save Mode, PFM is used at
light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low level, then the
device operates in Power Save Mode.
PGND1
18
I
GND for converter 1
PGND2
14
I
GND for converter 2
RESET
10
O
Open drain active low reset output, 100-ms reset delay time.
THRESHOLD
5
I
Reset input
VCC
1
I
Power supply for digital and analog circuitry of DCDC1, DCDC2 and LDOs. This pin must be connected to the same voltage
supply as VINDCDC1/2.
VINDCDC1/2
16
I
Input voltage for VDCDC1 and VDCDC2 step-down converter. This must be connected to the same voltage supply as VCC.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
VINLDO1
2
I
Input voltage for LDO1
VINLDO2/3
8
I
Input voltage for LDO2 and LDO3
VLDO1
3
O
Output voltage of LDO1
VLDO2
7
O
Output voltage of LDO2
VLDO3
9
O
Output voltage of LDO3
—
Connect to GND
Thermal Pad
6 Specifications
6.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VI
Input voltage
VO
MIN
MAX
All pins except AGND, PGND, and EN_LDO1 pins with respect to
AGND
–0.3
7
EN_LDO1 pin with respect to AGND
–0.3
VCC + 0.5
Output voltage for LDO1, LDO2 and LDO3
–0.3
UNIT
V
4
V
VINDCDC1/2, L1, PGND1, L2, PGND2
1800
All other pins
1000
II
Current
TA
Operating free-air temperature
–40
85
°C
Tstg
Storage temperature
–65
150
°C
(1)
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
Electrostatic
discharge
V(ESD)
(1)
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 6, 7, 12, 13,
18, 19, and 24)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VINDCDC1/2
Input voltage for step-down converters
2.5
6
V
VINLDO1,
VINLDO2/3
Input voltage range for LDOs
1.5
6.5
V
VDCDC1
Output voltage range for externally adjustable VDCDC1 step-down converter
0.6
VINDCDC1
V
VDCDC2
Output voltage range for externally adjustable VDCDC2 step-down converter
0.6
VINDCDC2
V
VLDO1-2
Output voltage range for externally adjustable LDO1 and LDO2
1
3.6
V
VLDO3
Output voltage for LDO3
IOUTDCDC1
Output current at L1
1000
mA
IOUTDCDC2
Output current at L2
600
mA
ILDO1
Output current at VLDO1
400
mA
ILDO2,3
Output current at VLDO2 and VLDO3
200
mA
CINDCDC1/2 Input capacitor at VINDCDC1/2
1.3
(1)
(1)
CVCC
Input capacitor at VCC
Cin1-2
Input capacitor at VINLDO1, VINLDO2/3
(1)
4
(1)
V
22
μF
1
μF
2.2
μF
See the Application and Implementation section of this data sheet for more details.
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Recommended Operating Conditions (continued)
MIN
NOM
COUTDCDC1 Output capacitor at VDCDC1 (1)
10
22
μF
COUTDCDC2 Output capacitor at VDCDC2 (1)
10
22
μF
(1)
COUT1
Output capacitor at VLDO1
COUT2-3
Output capacitor at VLDO2-3
L1
Inductor at L1 (1)
L2
Inductor at L2 (1)
MAX
UNIT
4.7
(1)
μF
2.2
μF
1.5
2.2
μH
1.5
2.2
μH
(2)
RCC
Resistor from battery voltage to VCC used for filtering
10
Ω
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(2)
1
Up to 2 mA can flow into VCC when both converters are running in PWM, this resistor causes the UVLO threshold to be shifted
accordingly.
6.4 Thermal Information
TPS65053-Q1
THERMAL METRIC
(1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
31.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
23.7
°C/W
RθJB
Junction-to-board thermal resistance
8.0
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
8.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.2
°C/W
(1)
6.5
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Electrical Characteristics
VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, COUT = 22 μF, TA = –40°C to +85°C (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VCC
Input voltage range
2.5
6
One converter, IOUT = 0 mA. PFM mode enabled (Mode = GND)
device not switching, EN_DCDC1 = VIN OR EN_DCDC2 = VIN;
EN_LDO1= EN_LDO2 = EN_LDO3 = GND
One converter, IOUT = 0 mA. PFM mode enabled (Mode = GND)
device not switching, EN_DCDC1 = VIN OR EN_DCDC2 = VIN;
EN_LDO1= EN_LDO2 = EN_LDO3 = GND, TA = 25°C
IQ
Operating quiescent current
Total current into VCC,
VINDCDC1/2, VINLDO1,
VINLDO2/3
30
20
Two converters, IOUT = 0 mA, PFM mode enabled (Mode = 0) device
not switching, EN_DCDC1 = VIN AND EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3 = GND
Two converters, IOUT = 0 mA, PFM mode enabled (Mode = 0) device
not switching, EN_DCDC1 = VIN AND EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3 = GND, TA = 25°C
40
μA
32
One converter, IOUT = 0 mA, PFM mode enabled (Mode = GND)
device not switching, EN_DCDC1 = VIN OR EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3 = VIN
IQ
Operating quiescent current into
VCC
V
210
One converter, IOUT = 0 mA, PFM mode enabled (Mode = GND)
device not switching, EN_DCDC1 = VIN OR EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3 = VIN, TA = 25°C
145
One converter, IOUT = 0 mA, Switching with no load (Mode = VIN),
PWM operation, EN_DCDC1 = VIN OR EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3 = GND, TA = 25°C
0.85
mA
Two converters, IOUT = 0 mA, Switching with no load (Mode = VIN),
PWM operation, EN_DCDC1 = VIN AND EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3 = GND, TA = 25°C
1.25
mA
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Electrical Characteristics (continued)
VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, COUT = 22 μF, TA = –40°C to +85°C (unless otherwise
noted).
PARAMETER
I(SD)
Shutdown current
Undervoltage lockout threshold
for DC-DC converters and LDOs
UVLO
TEST CONDITIONS
MIN
TYP
EN_DCDC1 = EN_DCDC2 = GND, EN_LDO1 = EN_LDO2 =
EN_LDO3 = GND
MAX
UNIT
12
μA
EN_DCDC1 = EN_DCDC2 = GND, EN_LDO1 = EN_LDO2 =
EN_LDO3 = GND, TA = 25°C
9
Voltage at VCC
2
Voltage at VCC, TA = 25°C
1.8
V
EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, MODE
VIH
High-level input voltage
MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3
1.2
VCC
V
VIL
Low-level input voltage
MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3
0
0.4
V
Input bias current
MODE, EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3,
MODE = GND or VIN, TA = 25°C
1
μA
IIN
0.01
POWER SWITCH
VINDCDC1/2 = 3.6 V
P-channel MOSFET on
resistance, DCDC1, DCDC2
rDS(on)
ILD_PMOS
P-channel leakage current
rDS(on)
N-channel MOSFET on
resistance, DCDC1, DCDC2
630
VINDCDC1/2 = 3.6 V, TA = 25°C
280
VINDCDC1/2 = 2.5 V, TA = 25°C
400
V(DS) = 6 V
1
VINDCDC1/2 = 3.6 V
μA
450
VINDCDC1/2 = 3.6 V, TA = 25°C
220
VINDCDC1/2 = 2.5 V, TA = 25°C
320
V(DS) = 6 V
mΩ
10
ILK_NMOS
N-channel leakage current
I(LIMF)
Forward current limit PMOS (high DCDC1, 2.5 V ≤ VIN ≤ 6 V, TA = 25°C
side) and NMOS (low side)
DCDC2, 2.5 V ≤ VIN ≤ 6 V
TSD,DCDC
Thermal shutdown
Increasing junction temperature, TA = 25°C
Thermal shutdown hysteresis
Decreasing junction temperature below TSD,DCDC for resuming normal
operation, TA = 25°C
V(DS) = 6 V, TA = 25°C
7
DCDC1, 2.5 V ≤ VIN ≤ 6 V
1.1
μA
1.8
1.4
0.85
DCDC2, 2.5 V ≤ VIN ≤ 6 V, TA = 25°C
TSDhys,DCDC
mΩ
1.15
A
1
150
°C
20
°C
OSCILLATOR
fSW
Oscillator frequency
2.025
TA = 25°C
2.475
2.25
MHz
OUTPUT
VOUT
Output voltage range
Vref
Reference voltage
VOUT
DC output voltage accuracy
0.6
TA = 25°C
-2%
0
2%
VIN = 2.5 V to 6 V, Mode = VIN, PWM operation,
0 mA < IOUT < IOUTmax
–1%
0
1%
Power save mode ripple
voltage (1)
IOUT = 1 mA, Mode = GND, VO = 1.3 V, Bandwidth = 20 MHz,
TA = 25°C
tStart
Start-up time
tRamp
VOUT ramp up time
VOL
Vth
(1)
6
25
mVPP
Time from active EN to start switching, TA = 25°C
170
μs
Time to ramp from 5% to 95% of VOUT, TA = 25°C
750
Input voltage at threshold pin rising
80
Input voltage at threshold pin rising, TA = 25°C
RESET output low voltage
IOL = 1 mA, Vth < 1 V
RESET sink current
TA = 25°C
RESET output leakage current
Vth > 1 V, TA = 25°C
Threshold voltage
V
mV
VIN = 2.5 V to 6 V, Mode = GND, PFM operation,
0 mA < IOUT < IOUTmax
ΔVOUT
RESET delay time
VIN
600
Falling voltage
Falling voltage, TA = 25°C
μs
120
100
0.2
1
nA
1.02
1
V
mA
10
0.98
ms
V
In Power Save Mode, operation is typically entered at IPSM = VIN / 32 Ω.
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Electrical Characteristics (continued)
VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, COUT = 22 μF, TA = –40°C to +85°C (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO1, VLDO2, VLDO3 LOW DROPOUT REGULATORS
VINLDO
Input voltage range for LDO1,
LDO2, LDO3
VLDO1
VLDO2
VLDO3
LDO3 output voltage
TA = 25°C
1.3
V
V(FB)
Feedback voltage for FB_LDO1,
FB_LDO2
TA = 25°C
1
V
IO
1.5
6.5
V
LDO1 output voltage range
1
3.6
V
LDO2 output voltage range
1
3.6
V
Maximum output current for
LDO1
400
mA
Maximum output current for
LDO2, LDO3
200
mA
LDO1 short-circuit current limit
VLDO1 = GND
850
mA
LDO2 and LDO3 short-circuit
current limit
VLDO2 = GND, VLDO3 = GND
420
mA
Dropout voltage at LDO1
IO = 400 mA, VINLDO1 = 1.8 V
280
mV
Dropout voltage at LDO2, LDO3
IO = 200 mA, VINLDO2/3 = 1.8 V
280
mV
Output voltage accuracy for
LDO1, LDO2, LDO3 (2)
IO = 10 mA
–2%
1%
Line regulation for LDO1, LDO2,
LDO3
VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5 V, IO = 10 mA
–1%
1%
Load regulation for LDO1, LDO2,
LDO3
IO = 0 mA to 400 mA for LDO1, IO = 0 mA to 200 mA for LDO2,
LDO3
–1%
1%
Regulation time for LDO1, LDO2,
LDO3
Load change from 10% to 90%, TA = 25°C
R(DIS)
Internal discharge resistor at
VLDO1, VLDO2, VLDO3
TSD,LDO
I(SC)
TSDhys,LDO
(2)
25
μs
Active when LDO is disabled, TA = 25°C
350
Ω
Thermal shutdown
Increasing junction temperature
140
°C
Thermal shutdown hysteresis
Decreasing junction temperature below TSD,LDO for resuming normal
operation
20
°C
Output voltage specification does not include tolerance of external voltage programming resistors.
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6.6 Typical Characteristics
100
100
90
90
80
70
5V
60
4.2 V
3.8 V
70
Efficiency − %
Efficiency − %
80
3.4 V
50
40
3.4 V
20
20
10
10
VDCDC1 = 2.85 V
1
0
0.0001
10
VINDCDC1/2 = 3.4, 3.8, 4.2, and 5 V
0.1
0.001
0.01
IO − Output Current − A
VDCDC1 = 2.85 V
Figure 1. Efficiency (η) of DCDC1 in PWM/PFM Mode
1
10
VINDCDC1/2 = 3.4, 3.8, 4.2, and 5 V
Figure 2. Efficiency (η) of DCDC1 in PWM Mode
100
100
90
4.2 V
40
30
0.1
0.001
0.01
IO − Output Current − A
5V
50
30
0
0.0001
3.3 V
90
3.8 V
70
Efficiency - %
4.2 V
70
60
5V
50
40
5V
60
4.2 V
40
30
20
20
10
10
VDCDC2 = 1.8 V
0.001
0.01
0.1
IO - Output Current - A
3.8 V
50
30
0
0.0001
3.3 V
80
80
Efficiency - %
3.8 V
60
0
0.0001
1
VINDCDC1/2 = 3.4, 3.8, 4.2, and 5
0.001
0.01
0.1
IO - Output Current - A
VDCDC2 = 1.8 V
Figure 3. Efficiency (η) of DCDC2 in PWM/PFM Mode
1
VINDCDC1/2 = 3.4, 3.8, 4.2, and 5 V
Figure 4. Efficiency (η) of DCDC2 in PWM Mode
100
90
Rejection Ratio - dB
80
70
60
50
40
30
20
10
0
10
100
1k
10 k
100 k
f - Frequency - Hz
1M
10 M
Figure 5. LDO1 Power-Supply Rejection Ratio
8
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7 Detailed Description
7.1 Overview
The TPS65053-Q1 device includes two synchronous step-down converters. The converters operate with 2.25MHz fixed frequency pulse-width modulation (PWM) at moderate to heavy load currents. At light load currents
the converters automatically enter Power Save Mode and operate with PFM (pulse frequency modulation).
During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
The current limit comparator will also turn off the switch in case the current limit of the P-channel switch is
exceeded. After the adaptive dead time prevents shoot-through current, the N-channel MOSFET rectifier is
turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off
the N-channel rectifier and turning on the P-channel switch.
The two DC-DC converters operate synchronized to each other, with converter 1 as the master. A 180° phase
shift between Converter 1 and Converter 2 decreases the input RMS current. Therefore smaller input capacitors
can be used.
The converters output voltage is set by an external resistor divider connected to FB_DCDC1 or FB_DCDC2,
respectively. See the Application and Implementation section for more details.
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7.2 Functional Block Diagram
TPS65053
VINDCDC1/2
1Ω
VCC
VIN
22 µF
1 µF
2.2 µH
DCDC1 (I/O)
ENABLE
EN_DCDC1
STEP-DOWN
CONVERTER
L1
FB_DCDC1
R1
PGND1
R2
Cff
10 µF
Cff
10 µF
1000 mA
MODE
2.2 µH
L2
DCDC2 (core)
FB_DCDC2
EN_DCDC2
ENABLE
R3
STEP-DOWN
CONVERTER
R4
PGND2
600 mA
VLDO1
VIN_LDO1
VLDO1
VIN
R5
2.2 µF
ENABLE
EN_LDO1
400 mA LDO
4.7 µF
FB1
R6
VIN
VIN_LDO2/3
VLDO2
2.2 µF
ENABLE
EN_LDO2
200 mA LDO
VLDO2
FB2
R7
2.2 µF
R8
ENABLE
EN_LDO3
VLDO3
VLDO3
2.2 µF
200 mA LDO
I/O voltage
THRESHOLD
Reset
R19
RESET
AGND
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7.3 Feature Description
7.3.1 Mode Selection
The MODE pin allows mode selection between forced PWM Mode and Power Save Mode for both converters.
Connecting this pin to GND enables the automatic PWM and Power Save Mode operation. The converters
operate in fixed-frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,
maintaining high efficiency over a wide load current range.
Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load
currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the
switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the Power
Save Mode during light loads. For additional flexibility, switch from Power Save Mode to forced PWM mode
during operation ehich allows efficient power management by adjusting the operation of the converter to the
specific system requirements.
7.3.2 Enable
The device has a separate enable pin for each of the DC-DC converters and for each of the LDO to start up
independently. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3 are set to high, the corresponding
converter starts up with soft start as previously described.
Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the
Electrical Characteristics table. In this mode, the P and N-Channel MOSFETs are turned-off, the and the entire
internal control circuitry is switched-off. If disabled, the outputs of the LDOs are pulled low by internal 350-Ω
resistors, actively discharging the output capacitor. For proper operation the enable pins must be terminated and
must not be left unconnected.
7.3.3 Reset
The TPS65053-Q1 device contains circuitry that can generate a reset pulse for a processor with a 100-ms delay
time. The input voltage at a comparator is sensed at an input called THRESHOLD. When the voltage exceeds
the 1-V threshold, the output goes high after a 100-ms delay time. This circuitry is functional as soon as the
supply voltage at VCC exceeds the undervoltage lockout threshold. The RESET circuitry is active even if all DCDC converters and LDOs are disabled.
Vbat
threshold
Reset
+
-
100 ms
delay
Vref =1 V
Vbat
Threshold
Comparator
Output (Internal)
Reset
TNRESPWRON
Figure 6. RESET Pulse Circuit
7.3.4 Short-Circuit Protection
All outputs are short circuit protected with a maximum output current as defined in the Electrical Characteristics
table.
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Feature Description (continued)
7.3.5 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 150°C (typical) for the DC-DC converters, the device goes into
thermal shutdown. In this mode, the P and N-Channel MOSFETs are turned-off. The device continues operation
when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for one of
the DC-DC converters will disable both converters simultaneously.
The thermal shutdown temperature for the LDOs are set to typically 140°C. Therefore an LDO that can be used
to power an external voltage will never heat up the chip high enough to turn off the DC-DC converters. If one
LDO exceeds the thermal shutdown temperature, all LDOs will turn off simultaneously.
7.3.5.1 Low Dropout Voltage Regulators
The low dropout (LDO) voltage regulators are designed to be stable with low value ceramic input and output
capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 280
mV at rated output current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1,
EN_LDO2, and EN_LDO3 pin. The output voltage of LDO1 and LDO2 is set using an external resistor divider
whereas LDO3 has a fixed output voltage of 1.3 V.
7.4 Device Functional Modes
7.4.1 Power Save Mode
The Power Save Mode is enabled with the MODE pin set to low. If the load current decreases, the converters
enter Power Save Mode operation automatically. During Power Save Mode the converters operate with reduced
switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The
converter positions the output voltage typically 1% above the nominal output voltage. This voltage positioning
feature minimizes voltage drops caused by a sudden load step.
To optimize the converter efficiency at light load the average current is monitored and if in PWM mode the
inductor current remains below a certain threshold, then Power Save Mode is entered. The typical threshold can
be calculated according to Equation 1 and Equation 2.
V
I PFM_enter = INDCDC1/2
32 Ω
where
•
IPFM_enter is the average output current threshold to enter PFM mode.
IPFM _ leave
(1)
V
= INDCDC1/2
24 W
where
•
IPFM_leave is the average output current threshold to leave PFM mode.
(2)
During the Power Save Mode the output voltage is monitored with a comparator. As the output voltage falls
below the skip comparator threshold (skip comp) of VOUTnominal +1%, the P-channel switch will turn on and the
converter effectively delivers a constant current as defined above. If the load is below the delivered current then
the output voltage will rise until the same threshold is crossed again, whereupon all switching activity ceases,
hence reducing the quiescent current to a minimum until the output voltage has dropped below the threshold
again. If the load current is greater than the delivered current then the output voltage will fall until it crosses the
skip comparator low (Skip Comp Low) threshold set to 1% below nominal VOUT, whereupon Power Save Mode is
exited and the converter returns to PWM mode.
These control methods reduce the quiescent current typically to 12 μA per converter and the switching frequency
to a minimum thereby achieving the highest converter efficiency. The PFM mode operates with very low output
voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing
capacitor values will make the output ripple tend to zero.
The Power Save Mode can be disabled by driving the MODE pin high. Both converters will operate in fixed PWM
mode. Power Save Mode Enable/Disable applies to both converters.
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Device Functional Modes (continued)
7.4.1.1 Dynamic Voltage Positioning
This feature reduces the voltage undershoot and overshoot at load steps from light to heavy load and vice versa.
It is activated in Power Save Mode operation when the converter runs in PFM Mode. It provides more headroom
for both the voltage drop at a load step increase and the voltage increase at a load throw-off which improves
load transient behavior.
At light loads, in which the converters operate in PFM Mode, the output voltage is regulated typically 1% higher
than the nominal value. In case of a load transient from light load to heavy load, the output voltage will drop until
it reaches the skip comparator low threshold set to –1% below the nominal value and enters PWM mode. During
a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation
turning on the N-channel switch.
Smooth
increased load
+1%
PFM Mode
light load
Fast load transient
PFM Mode
light load
VOUT_NOM
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
-1%
COMP_LOW threshold
Figure 7. Dynamic Voltage Positioning
7.4.1.2 Soft Start
The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft
start, the output voltage ramp up is controlled as shown in Figure 8.
EN
95%
5%
VOUT
tStart
tRAMP
Figure 8. Soft Start
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Device Functional Modes (continued)
7.4.1.3 100% Duty-Cycle Low Dropout Operation
The converters offer a low input to output voltage difference while still maintaining operation with the use of the
100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in
battery-powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range; essentially the minimum input voltage to maintain regulation depends on the load current and
output voltage and can be calculated as shown in Equation 3.
VINmin = VOUT max + IOUT max ´ (RDSonmax + RL )
where
•
•
•
•
IOUTmax = maximum output current plus inductor ripple current
RDSonmax = maximum P-channel switch rDS(on)
RL = DC resistance of the inductor
VOUTmax = nominal output voltage plus maximum output voltage tolerance
(3)
With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically the switching losses are
minimized and the device runs with a minimum quiescent current maintaining high efficiency.
In Power Save Mode the converter only operates when the output voltage trips below its nominal output voltage.
It ramps up the output voltage with several pulses and goes again into Power Save Mode when the output
voltage exceeds the nominal output voltage.
7.4.1.4 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunctioning by disabling the converter at low input
voltages and from excessive discharge of the battery. The undervoltage lockout threshold is 1.8 V (typical) and
2 V (maximum).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS65053-Q1 PMIC integrates two step-down converters and three LDOs which can be used to power the
voltage rails needed by a processor or another application. The PMIC can be controlled via the ENABLE and
MODE pins or sequenced from the VIN using RC delay circuits. There is a logic output, RESET, to provide the
application processor or load a logic signal indicating power good or reset.
8.2 Typical Application
TPS65053
1Ω
Vbat
VINDCDC1/2
Vbat
VCC
2.2 µH
1 µF
Vbat
22 µF
L1
2.8 V
DCDC1(I/O)
EN_DCDC1
STEP- DOWN
CONVERTER
1A
MODE
FB_DCDC1 R 1
PGND1
Cff
10 µF
R2
2.2 µH
L2
DCDC2(core)
EN_DCDC2
VDCDC1
Vbat
STEP- DOWN
CONVERTER
600 mA
VIN_LDO1
VLDO1
EN_LDO1
400 mA LDO
FB_DCDC2 R 3
10 µF
R4
PGND2
VLDO1
FB1
1.8 V
Cff
1.6 V
R5
4.7 µF
R6
VIN_LDO2/3
VLDO2
EN_LDO2
200 mA LDO
VLDO2
FB2
3.3 V
R7
2.2 µF
R8
EN_LDO3
VLDO3
VLDO3
200 mA LDO
VDCDC1
R9
THRESHOLD
1.3 V
2.2 µF
I/O voltage
Reset
RESET
R19
R10
AGND
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Figure 9. Typical Application Circuit
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Typical Application (continued)
8.2.1 Design Requirements
Table 1 lists the design parameters for this application example.
Table 1. Power Design Requirements
PARAMETER
VALUE
Buck 1 and 2 Input voltage, VINDCDC1/2
2.9 to 6 V (labeled Vbat in Figure 9)
Buck 1 Output voltage, VDCDC1
2.85 V (see Table 2 for FB_DCDC1 resistor divider
selection)
Buck 1 Output current, IOUTDCDC1
1A
Buck 2 Output voltage, VDCDC2
1.8 V (see Table 2 for FB_DCDC2 resistor divider
selection)
Buck 2 Output current, IOUTDCDC2
600 mA
Linear Regulator 1 Input voltage, VINLDO1
2.85 V (from VDCDC1, as shown in Figure 9)
Linear Regulator 1 Output voltage, VLDO1
1.6 V (see Table 5 for FB_LDO1 resistor divider
selection)
Linear Regulator 1 Output current, ILDO1
400 mA
Linear Regulator 2 and 3 Input voltage, VINLDO2/3
2.9 to 6 V (labeled Vbat in Figure 9)
Linear Regulator 2 Output voltage, VLDO2
3.3 V (see Table 5 for FB_LDO2 resistor divider
selection)
Linear Regulator 2 Output current, ILDO2
200 mA
Linear Regulator 3 Output voltage, VLDO3
1.3 V (fixed)
Linear Regulator 3 Output current, ILDO3
200 mA
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Setting
Use Equation 4 to calculate the output voltage of the DC-DC converters, with an internal reference voltage Vref,
0.6 V (typical). This voltage can be set by an external resistor network.
R1 ö
æ
VOUT = Vref ´ ç 1 +
÷
è R2 ø
(4)
TI recommends setting the total resistance of R1 + R2 to less than 1 MΩ. The resistor network connects to the
input of the feedback amplifier; therefore, requiring some small feed-forward capacitor in parallel to R1. A typical
value of 47 pF is sufficient.
æ
ö
VOUT
R1 = R2 ´ ç
÷ - R2
ç V(FB _ DCDC1) ÷
è
ø
(5)
Table 2. Typical DC-DC Feedback Resistor Values
16
OUTPUT VOLTAGE
R1
R2
NOMINAL VOLTAGE
TYPICAL Cff
3.3 V
680 kΩ
150 kΩ
3.32 V
47 pF
3V
510 kΩ
130 kΩ
2.95 V
47 pF
2.85 V
560 kΩ
150 kΩ
2.84 V
47 pF
2.5 V
510 kΩ
160 kΩ
2.51 V
47 pF
1.8 V
300 kΩ
150 kΩ
1.8 V
47 pF
1.6 V
200 kΩ
120 kΩ
1.6 V
47 pF
1.5 V
300 kΩ
200 kΩ
1.5 V
47 pF
1.2 V
330 kΩ
330 kΩ
1.2 V
47 pF
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8.2.2.2 Output Filter Design (Inductor and Output Capacitor)
8.2.2.2.1 Inductor Selection
The two converters operate typically with a 2.2-μH output inductor. Larger or smaller inductor values can be used
to optimize the performance of the device for specific operation conditions. For output voltages higher than 2.8 V,
an inductor value of 3.3 μH minimum should be selected, otherwise the inductor current will ramp down too fast
causing imprecise internal current measurement and therefore increased output voltage ripple under some
operating conditions in PFM mode.
The selected inductor must be rated for its DC resistance and saturation current. The DC resistance of the
inductance will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance
should be selected for highest efficiency.
Use Equation 6 to calculate the maximum inductor current under static load conditions. The saturation current of
the inductor should be rated higher than the maximum inductor current as calculated with Equation 6. This is
recommended because during heavy load transient the inductor current will rise above the calculated value.
V
1 - OUT
VIN
DI
IL max = IOUT max + L
DIL = VOUT ´
L´f
2
where
•
•
•
•
f = Switching Frequency (2.25-MHz typical)
L = Inductor Value
Δ IL = Peak-to-peak inductor ripple current
ILmax = Maximum Inductor current
(6)
The highest inductor current occurs at the maximum VIN. Open core inductors have a soft saturation
characteristic, and they can normally handle higher inductor currents versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. The fact that the core material from inductor to inductor differs and will have an impact
on the efficiency especially at high switching frequencies must be considered. Refer to Table 3 and the typical
applications for possible inductors.
Table 3. Tested Inductors
INDUCTOR TYPE
INDUCTOR VALUE
SUPPLIER
LPS3010
2.2 μH
Coilcraft
LPS3015
3.3 μH
Coilcraft
LPS4012
2.2 μH
Coilcraft
VLF4012
2.2 μH
TDK
8.2.2.2.2 Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the two converters allow the use of small ceramic
capacitors with a typical value of 10 μF, without having large output voltage under and overshoots during heavy
load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple and are
therefore recommended. See the recommended components in Table 5.
If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application
requirements. Use Equation 7 to calculate the rms ripple current.
V
1 - OUT
VIN
1
IRMSCout = VOUT ´
´
L´f
2´ 3
(7)
At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor as shown in Equation 8.
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VOUT
æ
ö
VIN
1
´ç
+ ESR ÷
L´f
è 8 ´ COUT ´ f
ø
1DVOUT = VOUT ´
(8)
Where the highest output voltage ripple occurs at the highest input voltage, VIN.
At light load currents, the converters operate in Power Save Mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
8.2.2.2.3 Input Capacitor Selection
Because of the nature of the buck converter, having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. The converters need a ceramic input capacitor of 10 μF. The input capacitor can be increased
without any limit for better input voltage filtering.
Table 4. Possible Capacitors for DC-DC Converters and LDOs
CAPACITOR VALUE
SIZE
SUPPLIER
TYPE
2.2 μF
0805
TDK C2012X5R0J226MT
Ceramic
2.2 μF
0805
Taiyo Yuden JMK212BJ226MG
Ceramic
10 μF
0805
Taiyo Yuden JMK212BJ106M
Ceramic
10 μF
0805
TDK C2012X5R0J106M
Ceramic
8.2.2.3 Low Dropout Voltage Regulators (LDOs)
The output voltage of LDO1 and LDO2 can be set by an external resistor network and can be calculated as
shown in Equation 9 with an internal reference voltage, Vref, typical 1 V.
æ R5 ö
VOUT = Vref ´ ç 1 +
÷
è R6 ø
(9)
TI recommends setting the total resistance of R5 + R6 to less than 1 MΩ. Typically, no feedforward capacitor is
required at the voltage dividers for the LDOs.
VOUT = V(FB ) ´
æV
ö
R5 = R6 ´ ç OUT ÷ - R6
ç V(FB ) ÷
è
ø
R5 + R6
R6
(10)
Table 5. Typical LDO Feedback Resistor Values
OUTPUT VOLTAGE
R5
R6
NOMINAL VOLTAGE
3.3 V
300 kΩ
130 kΩ
3.31 V
3V
300 kΩ
150 kΩ
3V
2.85 V
240 kΩ
130 kΩ
2.85 V
2.8 V
360 kΩ
200 kΩ
2.8 V
2.5 V
300 kΩ
200 kΩ
2.5 V
1.8 V
240 kΩ
300 kΩ
1.8 V
1.5 V
150 kΩ
300 kΩ
1.5 V
1.3 V
36 kΩ
120 kΩ
1.3 V
1.2 V
100 kΩ
510 kΩ
1.19 V
1.1 V
33 kΩ
330 kΩ
1.1 V
8.2.2.3.1 Input Capacitor and Output Capacitor Selection for the LDOs
The minimum input capacitor on VIN_LDO1 and on VIN_LDO2/3 is 2.2 μF minimum. LDO1 is designed to be
stable with an output capacitor of 4.7 μF minimum; whereas, LDO2 and LDO3 are stable with a minimum
capacitor value of 2.2 μF.
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CH1 (VDCDC2 = 1.5 V)
20 mV/div
CH4 (IL DCDC1 = 600 mA)
100 mA/div
CH1 (VDCDC1 = 3.3 V)
200 mA/div
100 mA/div
CH2 (VDCDC2 = 1.5 V)
20 mV/div
CH1 (VDCDC1 = 3.3 V)
20 mV/div
CH3 (IL DCDC2 = 600 mA)
CH4 (IL DCDC1 = 80 mA)
200 mA/div
CH3 (IL DCDC2 = 80 mA)
t − Time = 2 ms/div
t − Time = 500 ns/div
PWM/PFM Mode = Low
PWM Mode = High
Figure 10. Output Voltage Ripple of DCDC1/2 in PFM Mode
CH4 (ENLDO1,2,3)
5 V/div
CH1: EN_DCDC1/2, ENLDO1, Load = 600 mA
Figure 11. Output Voltage Ripple of DCDC1/2 in
PWM Mode
CH1 (VLDO1)
CH4: VLDO1
CH2 (VLDO2)
1 V/div
20 mV/div
8.2.3 Application Curves
1 V/div
CH3: VDCD2
CH3 (VLDO3)
1 V/div
CH2: VDCDC1
t − Time = 40 ms/div
Figure 13. LDO1 to LDO3 Startup Timing
50 mV/div
50 mV/div
Figure 12. DCDC1, DCDC2, LDO1 Startup Timing
CH1 (VDCDC1)
CH1 (VDCDC1)
CH2
I(DCDC1)
200 mA/div
200 mA/div
CH2
I(DCDC1)
t − Time = 100 ms/div
t − Time = 100 ms/div
Figure 14. DCDC1 Load Transient Response in PWM Mode
Figure 15. DCDC1 Load Transient Response in PFM Mode
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50 mV/div
50 mV/div
SLVSAW1A – JUNE 2011 – REVISED JANUARY 2017
CH1 (VDCDC2)
CH1 (VDCDC2)
CH2
I(DCDC2)
200 mA/div
200 mA/div
CH2
I(DCDC2)
t − Time = 100 ms/div
t − Time = 100 ms/div
Figure 16. DCDC2 Load Transient Response in PWM Mode
Figure 17. DCDC2 Load Transient Response in PFM Mode
500 mV/div
CH1
VIN (VDCDC2)
20 mV/div
20 mV/div
500 mV/div
CH1
VIN (VDCDC1)
CH2 (VDCDC1)
CH2 (VDCDC2)
CH1 (VLDO1)
CH2
I(LDO1)
CH1 (VLDO3)
200 mA/div
200 mA/div
50 mV/div
t − Time = 100 ms/div
Figure 19. DCDC2 Line Transient Response in PWM Mode
50 mV/div
t − Time = 100 ms/div
Figure 18. DCDC1 Line Transient Response in PWM Mode
CH2
I(LDO3)
t − Time = 200 ms/div
t − Time = 100 ms/div
Figure 20. LDO1 Load Transient Response
20
Figure 21. LDO3 Load Transient Response
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20 mV/div
500 mV/div
CH1
VIN (LDO1)
CH2 (VLDO1)
t − Time = 100 ms/div
Figure 22. LDO1 Line Transient Response
9 Power Supply Recommendations
The TPS65053-Q1 has only a few power supply recommendations in addition to adhering to the minimum and
maximum values in the Recommended Operating Conditions. The following check list provides power supply
recommendations that should be used in conjunction with complying to the Recommended Operating Conditions
of the device.
• 1-µF Bypass cap on VCC, located as close as possible to the VCC pin to ground.
• VCC and VINDCDC1/2 must be connected to the same voltage supply with minimal voltage difference.
• Input capacitors must be present on the VINDCDC1/2, VIN_LDO1, and VIN_LDO2/3 supplies if used.
• Output filters must be used on the outputs of the DCDC converters if used.
• Output capacitors must be used on the outputs of the LDOs if used.
10 Layout
10.1 Layout Guidelines
The following check list provides layout guidelines that have been followed in the Layout Example shown in
Figure 23.
• The input capacitors for the DC-DC converters should be placed as close as possible to the VINDCDC1/2 pin
and the PGND1 and PGND2 pins.
• The inductor of the output filter should be placed as close as possible to the device to provide the shortest
switch node possible, reducing the noise emitted into the system and increasing the efficiency.
• Sense the feedback voltage from the output at the output capacitors to ensure the best DC accuracy.
Feedback should be routed away from noisy sources such as the inductor. If possible route on the opposing
side as the switch node and inductor and place a GND plane between the feedback and the noisy sources or
keep-out underneath them entirely.
• Place the output capacitors as close as possible to the inductor to reduce the feedback loop as much as
possible. This will ensure best regulation at the feedback point.
• Place the device as close as possible to the most demanding or sensitive load. The output capacitors should
be placed close to the input of the load. This will ensure the best AC performance possible.
• The input and output capacitors for the LDOs should be placed close to the device for best regulation
performance.
• The use a one common ground plane is recommended for the device layout. The AGND can be separated
from the PGND, but a large low parasitic PGND is required to connect the PGND1/2 pins to the CIN and
external PGND connections.
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TPS65053-Q1
SLVSAW1A – JUNE 2011 – REVISED JANUARY 2017
www.ti.com
10.2 Layout Example
Figure 23. Layout Example for TPS65053-Q1
22
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Choosing an Appropriate Pull-up/Pull-down Resistor for Open Drain Outputs
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65053IRGERQ1
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS
65053Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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