TPS65058
www.ti.com................................................................................................................................................... SLVS851A – MAY 2008 – REVISED SEPTEMBER 2008
2.25 MHz Dual STEP DOWN CONVERTER
WITH 3 LOW-INPUT VOLTAGE LDOs
FEATURES
APPLICATIONS
• Up To 95% Efficiency
• Output Current for DC/DC Converters:
– DCDC1 = 0.6A; DCDC2 = 1A
• VIN Range for DC/DC Converters From
2.5V to 6V
• Dynamic Voltage Switching for Processor
Core Supply Supported
• 2.25MHz Fixed Frequency Operation
• Power Save Mode at Light Load Current
• 180° Out-of-Phase Operation
• Output Voltage Accuracy in PWM mode ±1%
• Total Typical 32µA Quiescent Current for Both
DC/DC Converters
• 100% Duty Cycle for Lowest Dropout
• One General-Purpose 400mA LDO
• Two General-Purpose 200mA LDOs
• VIN Range for LDOs from 1.5V to 6.5V
• Reset Generator and Power Monitor
• Available in a 4 mm x 4 mm 24-Pin QFN
Package
•
1
2
Satellite Radio Modules
TPS 65058
10 W
VIN
VINDCDC1/2
VCC
ENABLE
2.2 mH
EN_DCDC1
DCDC1(I/O)
STEP-DOWN
CONVERTER
MODE
L1
DCDC2(core)
EN_DCDC2
DEF_DCDC2
STEP-DOWN
CONVERTER
3.3 V
FB_DCDC
10uF
PGND1
PGOOD1
ENABLE
Voltage
Switching (1/0)
VIN
22 mF
1 mF
2.2 mH
1.8 V / 1.2 V
L2
FB_DCDC2
10 mF
PGND2
PGOOD2
VIN
2.2 mF
ENABLE
Voltage
Switching (1/0)
VIN_LDO1
EN_LDO1
VLDO1
VLDO1
4.7 mF
400 mA LDO
DEF_LDO
VIN_LDO2/
VIN
VLDO2
2.2 mF
ENABLE
3.3 V / 3.3 V
EN_LDO2
VLDO2
1.8 V / 1.2 V
2.2 mF
200 mA LDO
EN_LDO3
VLDO3
ENABLE
VLDO3
1.8 V / 1.3 V
2.2 mF
200 mA LDO
RESET
I/O Voltage
R19
RESET
AGND
NOTE: Other voltage options available upon
request.
Contact
your
Texas
Instruments representative.
DESCRIPTION
The TPS65058 is an integrated Power Management IC for applications powered by one Li-Ion or Li-Polymer cell,
which require multiple power rails. The TPS65058 provides two highly efficient, 2.25MHz step down converters
targeted at providing the core voltage and I/O voltage in a processor based system. Both step-down converters
enter a low power mode at light load for maximum efficiency across the widest possible range of load currents.
For low noise applications, the devices can be forced into fixed frequency PWM mode by pulling the MODE pin
high. Both converters allow the use of small inductors and capacitors to achieve a small solution size. TPS65058
provides an output current of up to 0.6A on the DCDC1 converter, and up to 1A on the DCDC2 converter. The
TPS65058 also integrates one 400mA LDO and two 200mA LDO voltage regulators, which can be turned on/off
using separate enable pins on each LDO. Each LDO operates with an input voltage range between 1.5V and
6.5V allowing them to be supplied from one of the step down converters or directly from the main battery.
The TPS65058 comes in a small 24-pin leadless package (4mm × 4mm QFN) with a 0,5mm pitch.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS65058
SLVS851A – MAY 2008 – REVISED SEPTEMBER 2008................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
(1)
(2)
TA
PART
NUMBER
QFN (2)
PACKAGE
PACKAGE MARKING
–40°C to 85°C
TPS65058
RGE
65058
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
The RGE package is available in tape and reel. Add R suffix (TPS65058RGER) to order quantities of
3000 parts per reel. Add T suffix (TPS65058RGET) to order quantities of 250 parts per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNITS
VI
II
Input voltage range on all pins except AGND, PGND, and EN_LDO1 pins with respect to AGND
–0.3 V to 7 V
Input voltage range on EN_LDO1 pin with respect to AGND
–0.3 V to VCC + 0.5 V
Current at VINDCDC1/2, L1, PGND1, L2, PGND2
1800 mA
Current at all other pins
1000 mA
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature
–40°C to 85°C
TJ
Maximum junction temperature
125°C
Tstg
Storage temperature range
(1)
–65°C to 150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
2
PACKAGE
RθJA
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
RGE
35 K/W
2.8 W
28 mW/K
1.57 W
1.14 W
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RECOMMENDED OPERATING CONDITIONS
MIN
NOM
2.5
MAX
6
UNIT
VINDCDC1/2
Input voltage range for step-down converters
VDCDC1
Output voltage range for VDCDC1 step-down converter
VDCDC2
Output voltage range for VDCDC2 step-down converter (DEF_DCDC2 = 1/0)
VINLDO1,
VINLDO2/3
Input voltage range for LDOs
VLDO1
Output voltage range for LDO1 (DEF_LDO = 1/0)
3.3/3.3
V
VLDO2
Output voltage range for LDO2 (DEF_LDO = 1/0)
1.8/1.2
V
VLDO3
Output voltage for LDO3 (DEF_LDO = 1/0)
1.8/1.3
IOUTDCDC1
Output current at L1
L1
Inductor at L1 (1)
V
1.8/1.2
V
1.5
6.5
1.5
V
V
600
(1)
V
3.3
mA
µH
2.2
µF
CINDCDC1/2
Input capacitor at VINDCDC1/2
COUTDCDC1
Output capacitor at VDCDC1 (1)
22
IOUTDCDC2
Output current at L2
L2
Inductor at L2 (1)
1.5
2.2
µH
COUTDCDC2
Output capacitor at VDCDC2 (1)
10
22
µF
CVCC
Input capacitor at VCC (1)
10
µF
22
1000
(1)
mA
1
µF
2.2
µF
Cin1-2
Input capacitor at VINLDO1, VINLDO2/3
COUT1-2
Output capacitor at VLDO1-3
ILDO1
Output current at LDO1
400
mA
ILDO2
Output current at LDO2
230
mA
ILDO3
Output current at LDO3
200
mA
TA
Operating ambient temperature range
–40
85
°C
TJ
Operating junction temperature range
–40
125
°C
10
Ω
RCC
(1)
(2)
(1)
µF
2.2
Resistor from battery voltage to VCC used for filtering
(2)
1
See the Application Information section of this data sheet for more details.
Up to 2 mA can flow into VCC when both converters are running in PWM, this resistor causes the UVLO threshold to be shifted
accordingly.
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TPS65058
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ELECTRICAL CHARACTERISTICS
Vcc = VINDCDC1/2 = 3.6V, EN = Vcc, MODE = GND, L = 2.2µH, COUT = 22µF, TA = –40°C to 85°C typical values
are at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
Vcc
IQ
IQ
Input voltage range
2.5
Operating quiescent current
Total current into VCC, VINDCDC1/2,
VINLDO1, VINLDO2/3
Operating quiescent current into VCC
6.
V
20
30
µA
32
40
µA
One converter, IOUT = 0 mA, PFM mode enabled (Mode = GND)
device not switching,
EN_DCDC1 = Vin OR EN_DCDC2 = Vin;
EN_LDO1 = EN_LDO2 = EN_LDO3 = Vin
145
210
µA
One converter, IOUT = 0 mA,
Switching with no load (Mode = Vin),
PWM operation EN_DCDC1 = Vin OR EN_DCDC2 = Vin;
EN_LDO1 = EN_LDO2 = EN_LDO3 = GND
0.85
mA
Two converters, IOUT = 0 mA,
Switching with no load (Mode = Vin),
PWM operation EN_DCDC1 = Vin AND EN_DCDC2 = Vin;
EN_LDO1 = EN_LDO2 = EN_LDO3 = GND
1.25
mA
One converter, IOUT = 0 mA.PFM mode enabled (Mode = GND)
device not switching,
EN_DCDC1 = Vin OR EN_DCDC2 = Vin;
EN_LDO1= EN_LDO2 = EN_LDO3 = GND
Two converters, IOUT = 0 mA, PFM mode enabled (Mode = 0)
device not switching,
EN_DCDC1 = Vin AND EN_DCDC2 = Vin;
EN_LDO1 = EN_LDO2 = EN_LDO3 = GND
I(SD)
Shutdown current
EN_DCDC1 = EN_DCDC2 = GND
EN_LDO1 = EN_LDO2 = EN_LDO3 = GND
V(UVLO)
Undervoltage lockout threshold for
DCDC converters and LDOs
Voltage at VCC
9
12
µA
1.8
2
V
EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, MODE
VIH
High-level input voltage
MODE, EN_DCDC1, EN_DCDC2,
EN_LDO1, EN_LDO2, EN_LDO3,
DEF,DEF_LDO,DEF_DCDC2
1.2
VCC
V
VIL
Low-level input voltage
MODE, EN_DCDC1, EN_DCDC2,
EN_LDO1, EN_LDO2, EN_LDO3,
DEF_LDO, DEF_DCDC2
0
0.4
V
IIN
Input bias current
MODE, EN_DCDC1, EN_DCDC2,
EN_LDO1, EN_LDO2, EN_LDO3,
DEF_LDO, DEF_DCDC2
µA
MODE = GND or VIN
0.01
1
VINDCDC1/2 = 3.6V
250
350
VINDCDC1/2 = 2.5V
380
500
250
POWER SWITCH
rDS(on)
P-channel MOSFET on
resistance
DCDC1,
DCDC2
ILD_PMOS
P-channel leakage current
V(DS) = 6V
rDS(on)
N-channel MOSFET on
resistance
VINDCDC1/2 = 3.6V
180
VINDCDC1/2 = 2.5V
250
ILK_NMOS
N-channel leakage current
I(LIMF)
Forward Current Limit
PMOS (High-Side) and
NMOS (Low side)
TSD
Thermal shutdown
Increasing junction temperature
150
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
DCDC1,
DCDC2
1
V(DS) = 6V
DCDC1
DCDC2
2.5V ≤ VIN ≤ 6V
7
10
1.19
1.4
1.65
0.85
1.0
1.15
mΩ
µA
mΩ
µA
A
OSCILLATOR
fSW
4
Oscillator frequency
2.025
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2.25
2.475
MHz
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www.ti.com................................................................................................................................................... SLVS851A – MAY 2008 – REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS (continued)
Vcc = VINDCDC1/2 = 3.6V, EN = Vcc, MODE = GND, L = 2.2µH, COUT = 22µF, TA = –40°C to 85°C typical values
are at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN = 2.5V to 6V, Mode = GND,
PFM operation, 0 mA < IOUT < IOUTMAX
-2%
0
2%
VIN = 2.5V to 6V, Mode = VIN,
PWM operation, 0 mA < IOUT < IOUTMAX
–1%
0
1%
UNIT
OUTPUT
VOUT
DC output voltage
accuracy
DCDC1,
DCDC2
ΔVOUT
Power save mode ripple voltage
IOUT = 1mA, Mode = GND, VO = 1.3V,
Bandwidth = 20MHz
25
mVPP
tStart
Start-up time
Time from active EN to Start switching
170
µs
tRamp
VOUT Ramp up Time
Time to ramp from 5% to 95% of VOUT
750
RESET delay time
Input voltage at threshold pin rising
RESET output low voltage
IOL = 1mA
VOL
80
100
µs
120
0.2
RESET sink current
RESET output leakage current
ms
V
1
mA
10
nA
VLDO1, VLDO2, VLDO3 LOW DROPOUT REGULATORS
VINLDO
Input voltage range for LDO1, LDO2,
LDO3
VLDO1
LDO1 output voltage range
(DEF_LDO = 1/0)
3.3/3.3
V
VLDO2
LDO2 output voltage
range(DEF_LDO = 1/0)
1.8/1.2
V
VLDO3
LDO3 output voltage
(DEF_LDO = 1/0)
1.8/1.3
V
V(FB)
Feedback voltage for FB_LDO1,
FB_LDO2
1
V
IO
1.5
6.5
V
Maximum output current for LDO1
400
mA
Maximum output current for LDO2
230
mA
Maximum output current for LDO3
200
mA
LDO1 short-circuit current limit
VLDO1 = GND
850
mA
LDO2 and LDO3 short-circuit current
limit
VLDO2 = GND, VLDO3 = GND
420
mA
Dropout voltage at LDO1
IO = 400mA, VINLDO1 = 1.8V
280
mV
Dropout voltage at LDO2, LDO3
IO = 200mA, VINLDO = 1.8V
280
mV
Output voltage accuracy for LDO1,
LDO2, LDO3
IO = 10mA
–2%
1%
Line regulation for LDO1, LDO2,
LDO3
VINLDO1,2 = VLDO1,2 + 0.5V (min. 2.5V) to 6.5V,
IO = 10 mA
–1%
1%
Load regulation for LDO1, LDO2,
LDO3
IO = 0mA to 400mA for LDO1
IO = 0mA to 230mA for LDO2
IO = 0mA to 200mA for LDO3
–1%
1%
Regulation time for LDO1, LDO2,
LDO3
Load change from 10% to 90%
10
µs
PSRR
Power supply rejection ratio
f = 10kHz; IO = 50mA; VI = VO + 1 V
70
dB
R(DIS)
Internal discharge resistor at VLDO1,
VLDO2, VLDO3
Active when LDO is disabled
300
Ω
TSD
Thermal shutdown
Increasing junction temperature
140
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
I(SC)
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TPS65058
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PIN ASSIGNMENTS
FB_DCDC2
PGND1
L1
VINDCDC1/2
L2
PGND2
RGE PACKAGE
(TOP VIEW)
18 17 16 15 14 13
FB_DCDC1
EN_DCDC1
EN_DCDC2
EN_LDO1
MODE
AGND
12
11
10
9
8
7
19
20
21
22
23
24
EN_LDO3
EN_LDO2
RESET
VLDO3
VINLDO2/3
VINLDO2
VCC
VIN_LDO1
VLDO1
DEF_LDO
DEF_DCDC2
VCC
1 2 3 4 5 6
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
VCC
1, 6
I
Power supply for digital and analog circuitry of DCDC1, DCDC2 and LDOs. This pin must be connected to the same
voltage supply as VINDCDC1/2.
FB_DCDC1
19
I
Feedback input for DCDC1
MODE
23
I
Select between Power Safe Mode and forced PWM Mode for DCDC1 and DCDC2. In Power Safe Mode PFM is used
at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low level,
then Device operates in Power Safe Mode.
VINDCDC1/2
16
I
Input voltage for VDCDC1 and VDCDC2 step-down converter. This must be connected to the same voltage supply as
VCC.
FB_DCDC2
13
I
Feedback input for DCDC1
L1
17
O
Switch pin of converter 1. Connected to Inductor
PGND1
18
I
GND for converter 1
PGND2
14
I
GND for converter 2
AGND
24
I
Analog GND, connect to PGND and PowerPAD™
L2
15
O
Switch Pin of converter 2. Connected to Inductor.
EN_DCDC1
20
I
Enable Input for converter 1, active high
EN_DCDC2
21
I
Enable Input for converter 2, active high
VINLDO1
2
I
Input voltage for LDO1
VINLDO2/3
8
I
Input voltage for LDO2 and LDO3
VLDO1
3
O
Output voltage of LDO1
VLDO2
7
O
Output voltage of LDO2
VLDO3
9
O
Output voltage of LDO3
DEF_DCDC2
5
I
Switches output voltages at DCDC2, logic high = 1.8V, logic low = 1.2V
DEF_LDO
4
I
Switches output voltages at LDO1, logic high = 3.3V, logic low = 3.3V
Switches output voltages at LDO2, logic high = 1.8V, logic low = 1.2V
Switches output voltages at LDO3, logic high = 1.8V, logic low = 1.3V
EN_LDO1
22
I
Enable input for LDO1. Logic high enables the LDO, logic low disables the LDO.
EN_LDO2
11
I
Enable input for LDO2. Logic high enables the LDO, logic low disables the LDO.
EN_LDO3
12
I
Enable input for LDO3. Logic high enables the LDO, logic low disables the LDO.
6
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
RESET
10
PowerPAD™
–
I/O
DESCRIPTION
O
Open drain active low reset output, 100ms reset delay time after both DCDC1 and DCDC2 are within 95% of nominal
output voltage (see Reset Generation and Output Monitoring section)
Connect to GND
FUNCTIONAL BLOCK DIAGRAM
10 W
VINDCDC1/2
VCC
VIN
22 mF
1 mF
ENABLE
VIN
2.2 mH
EN_DCDC1
DCDC1 (I/O)
STEP-DOWN
CONVERTER
600 mA
MODE
L1
3.3 V
FB_DCDC1
10 mF
PGND1
PGOOD1
2.2 mF
DCDC2 (core)
ENABLE
Voltage
Switching (1/0)
EN_DCDC2
DEF_DCDC2
1.8V / 1.2V
L2
FB_DCDC2
STEP-DOWN
CONVERTER
1A
10 mF
PGND2
PGOOD2
VIN
2.2 mF
ENABLE
Voltage
Switching (1/0)
VIN
2.2 mF
ENABLE
ENABLE
VLDO1
VIN_LDO1
3.3 V / 3.3 V
VLDO1
4.7 mF
EN_LDO1
400 mA LDO
DEF_LDO
VIN_LDO2/3
VLDO2
EN_LDO2
VLDO2
1.8 V / 1.2 V
2.2 mF
200 mA LDO
EN_LDO3
VLDO3
VLDO3
1.8 V / 1.3 V
2.2 mF
200 mA LDO
I/O Voltage
RESET
R19
RESET
AGND
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Efficiency converter 1
vs Load current PWM/PFM mode
Figure 1
Efficiency converter 1
vs Load current PWM mode
Figure 2
Efficiency converter 2
vs Load current PWM/PFM mode
Figure 3
Efficiency converter 2
vs Load current PWM mode
Figure 4
Output voltage ripple in PFM mode
vs Input voltage
Figure 5
Output voltage ripple in PWM mode
Scope plot
Figure 6
Startup converter 1 and 2
Scope plot
Figure 7
Startup LDO1 to 3
Scope plot
Figure 8
Load transient response converter 2 in PWM mode
Scope plot
Figure 9
Load transient response converter 2 in PFM mode
Scope plot
Figure 10
Line transient response converter 1
Scope plot
Figure 11
Line transient response converter 2
Scope plot
Figure 12
Load transient response LDO 1
Scope plot
Figure 13
Load transient response LDO 2 and LDO 3
Scope plot
Figure 14
Line transient response LDO 1
Scope plot
Figure 15
Power supply rejection ratio LDO 1
vs Frequency
Figure 16
EFFICIENCY CONVERTER 1
vs
LOAD CURRENT PWM/PFM MODE
EFFICIENCY CONVERTER 1
vs
LOAD CURRENT PWM MODE
100
100
3.8 V
VO = 3.3 V,
90 T = 25°C,
A
PFM Mode
80
90
80
60
5V
3.4 V
3.8 V
70
Efficiency - %
Efficiency - %
70
4.2 V
50
40
30
60
3.4 V
50
40
5V
30
4.2 V
20
10
0
0.0001
20
VO = 3.3 V,
TA = 25°C,
PFM Mode
0.001
0.01
0.1
IO - Output Current - A
10
1
0
0.0001
Figure 1.
8
0.001
0.01
0.1
IO - Output Current - A
1
Figure 2.
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EFFICIENCY CONVERTER 2
vs
LOAD CURRENT PWM/PFM MODE
EFFICIENCY CONVERTER 2
vs
LOAD CURRENT PWM MODE
100
100
90
90
3.4 V
80
80
VO = 1.2 V,
TA = 25°C,
PWM Mode
3.4 V
5V
70
4.2 V
Efficiency - %
Efficiency - %
70
60
3.8 V
50
40
30
4.2 V
50
40
5V
30
20
20
VO = 1.2 V,
TA = 25°C,
PFM/PWM Mode
10
0
0.0001
0.001
0.01
0.1
IO - Output Current - A
1
10
0
0.0001
10
0.001
0.01
0.1
IO - Output Current - A
1
Figure 3.
Figure 4.
OUTPUT VOLTAGE RIPPLE
PFM MODE
OUTPUT VOLTAGE RIPPLE
PWM MODE
10
CH1 (VDCDC1 = 3.3 V)
20 mV/div
20 mV/div
3.8 V
60
Mode = Low,
VI = 4.2 V,
CH1 (VDCDC1 = 3.3 V)
Mode = High,
VI = 4.2 V,
TA = 25oC
CH2 (VDCDC2 = 1.2 V)
20 mV/div
CH4 (IL DCDC1 = 80 mA)
CH3 (IL DCDC1 = 600 mA)
100 mA/div
100 mA/div
200 mA/div
200 mA/div
CH3 (IL DCDC2 = 80 mA)
CH2 (VDCDC2 = 1.2 V)
20 mV/div
o
TA = 25 C
CH4 (IL DCDC2 = 600 mA)
t − Time = 400 ns/div
t − Time = 2 ms/div
Figure 5.
Figure 6.
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Mode = Low,
VI = 3.6 V,
TA = 25oC
1 V/div
CH1 (EN_DCDC1 / 2 EN_LDO1)
5 V/div
STARTUP LDO1 TO LDO3
1 V/div
CH1 (EN_LDO1 / 2 / 3)
DEF_LDO1 = 1,
VI = 3.6 V,
TA = 25oC
CH2 (VLDO1)
VDCDC1 = 3.3 V,
VDCDC2 = 1.2 V,
DCDC1 IO = 600 mA
DCDC2 IO = 600 mA
1 V/div
CH3 (VDCDC2)
1 V/div
1 V/div
CH2 (VDCDC)
CH3 (VLDO2)
LDO1 IO = 100 mA,
LDO2 IO = 600 mA,
1 V/div
5 V/div
STARTUP CONVERTER 1 AND 2
LDO3 IO = 600 mA
CH4 (VLDO1)
CH4 (VLDO3)
t − Time = 200 ms/div
LOAD TRANSIENT RESPONSE
CONVERTER 2 IN PWM MODE
LOAD TRANSIENT RESPONSE
CONVERTER 2 IN PFM MODE
50 mV/div
CH2 (IO DCDC2)
Mode = High
VI = 3.6 V,
VO DCDC2 = 1.2 V,
DCDC2 IO = 60 mA to 540 mA
TA = 25oC
200 mA/div
50 mV/div
Figure 8.
CH1 (VO DCDC2)
200 mA/div
t − Time = 40 ms/div
Figure 7.
CH1 (VO DCDC2)
Mode = Low
VI = 3.6 V,
CH2 (IO DCDC2)
o
TA = 25 C
t − Time = 100 ms/div
t − Time = 100 ms/div
Figure 9.
10
VO DCDC2 = 1.2 V,
DCDC2 IO = 600 mA to 540 mA
Figure 10.
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500 mV/div
LINE TRANSIENT RESPONSE
CONVERTER 2
CH1 (VI DCDC1)
CH1 (VI)
Mode = High
VI = 3.6 V to 4.5 V to 3.6 V,
Mode = High
VI = 3.6 V to 4.5 V to 3.6 V,
CDC1 IO = 600 mA,
CDC1 IO = 600 mA,
o
TA = 25 C
20 mA/div
20 mA/div
500 mV/div
LINE TRANSIENT RESPONSE
CONVERTER 1
CH2 (VO DCDC1)
TA = 25oC
CH2 (VO)
t − Time = 100 ms/div
t − Time = 100 ms/div
Figure 11.
Figure 12.
LOAD TRANSIENT RESPONSE
LDO1
LOAD TRANSIENT RESPONSE
LDO2 AND LDO3
VI = 3.6 V
VI = 3.6 V
VO LDO3 = 3.3 V,
VO LDO3 = 1.83 V,
LDO3 IO = 20 mA to 180 mA,
TA = 25oC
LDO1 IO = 40 mA to 360 mA,
50 mV/div
TA = 25 C
CH1 (VO LDO1)
200 mA/div
200 mA/div
50 mV/div
o
CH2 (IO LDO1)
CH1 (VO DCDC2)
CH2 (IO DCDC2)
t − Time = 100 ms/div
t − Time = 100 ms/div
Figure 13.
Figure 14.
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POWER SUPPLY REJECTION RATIO, LDO1
vs
FREQUENCY
LINE TRANSIENT RESPONSE
LDO1
100
VI = 3.6 V to 4.2 V to 3.6 V
LDO IO = 100 mA,
80
Rejection Ratio - dB
20 mA/div
500 mV/div
TA = 25oC
CH1 (VI LDO1)
VIN = 3.8 V,
VOUT = 3.3 V,
IOUT = 10 mA,
TA = 25°C,
90
CIN = 2.2 mF,
70
COUT = 4.7 mF
60
50
40
30
20
CH2 (VO LDO1)
10
t − Time = 100 ms/div
0
10
Figure 15.
12
100
1k
10 k
100 k
f - Frequency - Hz
1M
10 M
Figure 16.
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DETAILED DESCRIPTION
OPERATION
The TPS65058 includes two synchronous step-down converters. The converters operate with 2.25MHz fixed
frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the
converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation).
During PWM operation, the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
The current limit comparator will also turn off the switch in case the current limit of the P-channel switch is
exceeded. After the adaptive dead time prevents shoot through current, the N-channel MOSFET rectifier is
turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off
the N-channel rectifier and turning on the P-channel switch.
The two DC-DC converters operate synchronized to each other, with converter 1 as the master. A 180° phase
shift between Converter 1 and Converter 2 decreases the input RMS current. Therefore smaller input capacitors
can be used.
The converters output voltage is set by an external resistor divider connected to FB_DCDC1 or FB_DCDC2,
respectively. See application section for more details.
POWER SAVE MODE
The Power Save Mode is enabled with Mode Pin set to low. If the load current decreases, the converters will
enter Power Save Mode operation automatically. During Power Save Mode the converters operate with reduced
switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The
converter will position the output voltage typically 1% above the nominal output voltage. This voltage positioning
feature minimizes voltage drops caused by a sudden load step.
In order to optimize the converter efficiency at light load the average current is monitored and if in PWM mode
the inductor current remains below a certain threshold, then Power Save Mode is entered. The typical threshold
can be calculated according to:
Equation 1: Average output current threshold to enter PFM mode.
VINDCDC
I PFM_enter +
32 W
(1)
Equation 2: Average output current threshold to leave PFM mode.
VINDCDC
I PFM_leave +
24 W
(2)
During the Power Save Mode the output voltage is monitored with a comparator. As the output voltage falls
below the skip comparator threshold (skip comp) of VOUTnominal +1%, the P-channel switch will turn on and the
converter effectively delivers a constant current as defined above. If the load is below the delivered current then
the output voltage will rise until the same threshold is crossed again, whereupon all switching activity ceases,
hence reducing the quiescent current to a minimum until the output voltage has dropped below the threshold
again. If the load current is greater than the delivered current then the output voltage will fall until it crosses the
skip comparator low (Skip Comp Low) threshold set to 1% below nominal Vout, whereupon Power Save Mode is
exited and the converter returns to PWM mode.
These control methods reduce the quiescent current typically to 12µA per converter and the switching frequency
to a minimum thereby achieving the highest converter efficiency. The PFM mode operates with very low output
voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing
capacitor values will make the output ripple tend to zero.
The Power Save Mode can be disabled by driving the MODE pin high. Both converters will operate in fixed PWM
mode. Power Save Mode Enable/Disable applies to both converters.
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Dynamic Voltage Positioning
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is
activated in Power Save Mode operation when the converter runs in PFM Mode. It provides more headroom for
both the voltage drop at a load step increase and the voltage increase at a load throw-off. This improves load
transient behavior.
At light loads, in which the converters operate in PFM Mode, the output voltage is regulated typically 1% higher
than the nominal value. In case of a load transient from light load to heavy load, the output voltage will drop until
it reaches the skip comparator low threshold set to –1% below the nominal value and enters PWM mode. During
a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation
turning on the N-channel switch.
Smooth
increased load
+1%
PFM Mode
light load
Fast load transient
PFM Mode
light load
VOUT_NOM
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
-1%
COMP_LOW threshold
Figure 17. Dynamic Voltage Positioning
Soft Start
The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft
start, the output voltage ramp up is controlled as shown in Figure 18.
EN
95%
5%
VOUT
tStart
tRAMP
Figure 18. Soft Start
14
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100% Duty Cycle Low Dropout Operation
The converters offer a low input to output voltage difference while still maintaining operation with the use of the
100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in
battery-powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range, i.e. The minimum input voltage to maintain regulation depends on the load current and output
voltage and can be calculated as:
VImin = VOUTmax + IOUTmax × (RDS(on)max + RL)
with:
IOUTmax = maximum output current plus inductor ripple current
RDS(on)max = maximum P-channel switch rDS(on)
RL = DC resistance of the inductor
VOUTmax = nominal output voltage plus maximum output voltage tolerance
With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically the switching losses are
minimized and the device runs with a minimum quiescent current maintaining high efficiency.
In power save mode, the converter only operates when the output voltage trips below its nominal output voltage.
It ramps up the output voltage with several pulses and goes again into power save mode once the output voltage
exceeds the nominal output voltage.
Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunctioning by disabling the converter at low input
voltages and from excessive discharge of the battery. The undervoltage lockout threshold is typically 1.8 V, max
2 V.
MODE SELECTION
The MODE pin allows mode selection between forced PWM Mode and power Save Mode for both converters.
Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters
operate in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,
maintaining high efficiency over a wide load current range.
Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load
currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the
switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power
save mode during light loads. For additional flexibility it is possible to switch from power save mode to forced
PWM mode during operation. This allows efficient power management by adjusting the operation of the converter
to the specific system requirements.
ENABLE
The device has a separate enable pin for each dcdc converter and for each LDO to start up each converter
independently. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3 are set to high, the corresponding
converter starts up with soft start as previously described.
Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the
electrical characteristics. In this mode, the P and N-Channel MOSFETs are turned-off, the and the entire internal
control circuitry is switched-off. If disabled, the outputs of the LDOs are pulled low by internal 300Ω resistors,
actively discharging the output capacitor. For proper operation, the enable pins must be terminated and must not
be left unconnected.
OUTPUT VOLTAGE SELECTION
The output voltage of the DCDC Converter 2 can be selected by a logic level on pin DEF_DCDC2. The output
voltage can be changed dynamically during operation. The slew rate of the change of output voltage is controlled
on DCDC2 to be 9.6mV/µs.
The output voltages on the LDOs can also be changed dynamically between two voltages by changing the logic
level on pin DEF_LDO.
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The output voltage options are:
Table 1. Output Voltage Selection
DEF_LDO
1
0
LDO1
3.3 V
3.3 V
LDO2
1.8 V
1.2 V
LDO3
1.8 V
1.3 V
DEF_DCDC2
1
0
DCDC2
1.8 V
1.2 V
RESET GENERATION AND OUTPUT MONITORING
The TPS65058 contains a monitor circuitry that monitors the outputs of the DCDC converters and applies a reset
pulse to the RESET pin. As soon as the supply voltage on the VCC pin is above the undervoltage lockout
threshold, the RESET pin is pulled low. After the enabling of both DCDC converters, the output voltages are
monitored. When both outputs are within 95% of the desired output voltage, the reset timer is started and after a
delay of 100ms the Reset output is switched to high impedance. If one of the output voltages is outside of the
regulation band (90% of the desired value) the RESET pin remains to be pulled to ground. After both outputs are
back in regulation, the 100ms timer is started, and after 100ms the RESET output is again switched to high
impedance.
Undervoltage lockout
Vcc
Enable
DCDC 1
Enable
DCDC 2
90 %
Vout
DCDC 1
95 %
95 %
Vout
DCDC 2
100 ms
100 ms
RESET
Reset inactive
after 100 msif
DCDC 1 AND DCDC 2
in regulation
Reset inactive if
DCDC 1 XOR DCDC 2
disabled
Reset active if
DCDC1 AND DCDC 2
Enabled but
DCDC 1 OR DCDC 2
out of regulation
Reset active if
DCDC1 AND DCDC 2
disabled
Figure 19. RESET Pulse Circuit
SHORT-CIRCUIT PROTECTION
All outputs are short circuit protected with a maximum output current as defined in the Electrical Characteristics.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds typically 150°C for the DCDC converters, the device goes into
thermal shutdown. In this mode, the P and N-Channel MOSFETs are turned-off. The device continues its
operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown
for one of the DCDC converters will disable both converters simultaneously.
16
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The thermal shutdown temperature for the LDOs are set to typically 140°C. Therefore, a LDO which is used to
power an external voltage will never heat up the chip to a temperature high enough to turn off the DCDC
converters. If one LDO exceeds the thermal shutdown temperature, all LDOs will turn off simultaneously.
Low Dropout Voltage Regulators
The low dropout voltage regulators are designed to operate with low value ceramic input and output capacitors.
They operate with input voltages down to 1.5V. The LDOs offer a maximum dropout voltage of 280mV at rated
output current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1, ENLDO2,
and EN_LDO3 pin. The output voltage of LDO1, LDO2 and LDO3 can be selected by the DEF_LDO pin
according to Table 1.
For noise and stability reasons, X5R or X7R type ceramic capacitors are recommended to limit degeneration of
°C over temperature and Vout.
OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)
Inductor Selection
The two converters operate typically with 2.2µH output inductor. Larger or smaller inductor values can be used to
optimize the performance of the device for specific operation conditions. For output voltages higher than 2.8V, an
inductor value of 3.3µH minimum should be selected, otherwise the inductor current will ramp down too fast
causing imprecise internal current measurement, and therefore, increased output voltage ripple under some
operating conditions in PFM mode.
The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the
inductance will directly influence the efficiency of the converter. Therefore, an inductor with lowest DC resistance
should be selected for highest efficiency.
Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is
recommended because during heavy load transient the inductor current will rise above the calculated value.
1 - Vout
DI
Vin
DIL = Vout x
ILmax = Iout max + L
Lxf
2
(4)
with:
f = Switching Frequency (2.25 MHz typical)
L = Inductor Value
ΔIL = Peak to Peak inductor ripple current
ILmax = Maximum Inductor current
The highest inductor current will occur at maximum Vin.
Open core inductors have a soft saturation characteristic, and usually handle higher inductor currents versus a
comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. A consideration to be considered is that the core material from inductor to inductor
differs, and has an impact on the efficiency, especially at high switching frequencies.
See Table 2 and the typical applications for possible inductors.
Table 2. Tested Inductors
INDUCTOR TYPE
INDUCTOR VALUE
SUPPLIER
LPS3010
2.2 µH
Coilcraft
LPS3015
3.3 µH
Coilcraft
LPS4012
2.2 µH
Coilcraft
VLF4012
2.2 µH
TDK
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Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the two converters allow the use of small ceramic
capacitors with a typical value of 22µF, without having large output voltage under and overshoots during heavy
load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple and are
recommended. SeeTable 3 for recommended components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application
requirements. Just for completeness the RMS ripple current is calculated as:
1 * Vout
Vin
1
I RMSCout + Vout
L ƒ
2 Ǹ3
(5)
At nominal load, current the inductive converters operate in PWM mode. The overall output voltage ripple is the
sum of the voltage spike, caused by the output capacitor ESR plus the voltage ripple, caused by charging and
discharging the output capacitor:
1 * Vout
Vin
1
DVout + Vout
) ESR
8 Cout ƒ
L ƒ
(6)
ǒ
Ǔ
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents, the converters operate in Power Save Mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering, and minimizing the interference with other circuits caused by high input
voltage spikes. The converters need a ceramic input capacitor of 10µF. The input capacitor can be increased
without any limit for better input voltage filtering.
Table 3. Possible Capacitors
18
22 µF
0805
TDK
C2012X5R0J226MT
Ceramic
22 µF
0805
Taiyo Yuden
JMK212BJ226MG
Ceramic
10 µF
0805
Taiyo Yuden
JMK212BJ106M
Ceramic
10uF
0805
TDK C2012X5R0J106M
Ceramic
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APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUIT
10 W
VIN
VINDCDC1/2
VCC
22 mF
1 mF
ENABLE
VIN
2.2 mH
EN_DCDC1
DCDC1 (I/O)
STEP-DOWN
CONVERTER
600 mA
MODE
L1
3.3 V
FB_DCDC1
10 mF
PGND1
PGOOD1
2.2 mF
DCDC2 (core)
ENABLE
Voltage
Switching (1/0)
EN_DCDC2
DEF_DCDC2
1.8V / 1.2V
L2
FB_DCDC2
STEP-DOWN
CONVERTER
1A
10 mF
PGND2
PGOOD2
VIN
2.2 mF
ENABLE
Voltage
Switching (1/0)
VIN
2.2 mF
ENABLE
ENABLE
VLDO1
VIN_LDO1
3.3 V / 3.3 V
VLDO1
4.7 mF
EN_LDO1
400 mA LDO
DEF_LDO
VIN_LDO2/3
VLDO2
EN_LDO2
VLDO2
1.8 V / 1.2 V
2.2 mF
200 mA LDO
EN_LDO3
VLDO3
VLDO3
1.8 V / 1.3 V
2.2 mF
200 mA LDO
I/O Voltage
RESET
R19
RESET
AGND
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPS65058RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65058
TPS65058RGERG4
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65058
TPS65058RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65058
TPS65058RGETG4
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65058
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS65058RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
TPS65058RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65058RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
TPS65058RGET
VQFN
RGE
24
250
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
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