TPS650830ZCGT

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 TPS650830 Simple and Flexible Wide Input Voltage PMU for Mobile Computers 1 Device Overview 1.1 Features 1 • 5 Reconfigurable Voltage Regulators: – High Efficiency over a Wide Input Voltage and Wide Output Current Range – Voltage, Current, and Sequence can be Changed to Optimize the System – 4 Variable Output Voltage Step-Down Controllers using External Power MOSFETs: • VR1 = 1 V; VR3 = 3.3 V , VR4 = 1.2 V/1.35 V/1.1 V for DDRx VDDQ , VR5 = 5 V • VIN Range from 5.4 V to 24 V – 1 Variable Output Voltage Step-Down Converter with Internal Power MOSFETs: • VR2 = 1.8 V • VIN Range from 3 V to 3.6 V • Up to 2 A of Continuous Output Current – Output Voltage DC Accuracy ±1%; with Differential Output Voltage Sensing – Ultra Low Quiescent Current Mode, Typical 30µA Quiescent Current per Controller or Converter • 3 Fixed LDO Voltage Regulators: – LDO1: Fixed Output Voltage LDO for DDRx VTT (Vout = VDDQ/2) • Up to 1 A of Continuous Output Current, 1.2 • • • • • • • • • Applications NVDC or Non-NVDC 2, 3, or 4 Series-Cell Li Battery Powered Products 1.3 • DC+AC Accuracy ±5%, 2 A Peak – LDO3: 3.3-V Fixed Output Voltage LDO, DC Accuracy ±1%, < 40 mA • High Precision Reference Supply for External ADC • 3.3-V Load Switch for EC_VCC Rail – LDO5: 5-V Fixed Output Voltage LDO, DC Accuracy ±1%, < 100 mA • Automatic Switch to 5-V Regulator for Higher Efficiency 7 Powergood Comparators and Sequence Logic for External Voltage Regulators, Load Switches, or LDOs Power-Button Logic Supported with Programmable Response Time 3 General Purpose Level Shifters Backup Battery / 3.1-V LDO Selector Output for RTC Power Source Detection and Monitoring: Adapter, Battery1, Battery2 Board Temperature Monitoring 1-Hz EC-Wake Clock Output Advanced System Reset Control I2C Interface: Standard-Mode (100 kHz), FastMode (400 kHz), Fast-Mode Plus (1000 kHz) • • Tablet, Ultrabook, 2in1, and Notebook Computers Mobile PC's, All-in-Ones, Mobile Internet Devices Description The TPS650830 is a single-chip solution Power Management IC designed specifically for the latest Intel Processors targeted for Tablets, Ultrabooks, and Notebooks with NVDC or non-NVDC power architectures, using 2S, 3S, or 4S Lithium-Ion battery packs. The TPS650830 is used for Volume systems with the low voltage rails merged for the smallest footprint and lowest cost system power solution. The TPS650830 can provide the complete power solution based on the Intel Reference Designs. Five highly efficient step-down voltage regulators (VRs) and a sink/source LDO, are used along with power-up sequence logic managing external load switches to provide the proper power rails, sequencing, and protection - including DDR3 and DDR4 memory power. The regulators support dynamic voltage scaling (DVS) for maximum efficiency including Connected Standby. The high frequency voltage regulators use small inductors and capacitors to achieve a small solution size. Output power is adjustable on four VR controllers. An I2C interface allows simple control by the embedded controller (EC). Each version is available in a 7x7 NFBGA package and a 9x9 NFBGA package. The 7x7 NFBGA package can be used in Type 4 PCB boards for the smallest area implementation. The 9x9 NFBGA package can be used in Type 3 and Type 4 PCB boards allowing to minimize cost and area. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com For the Skylake and Kabylake Power Map implementation, the five PMIC voltage regulators and LDO1 are assigned with the low-voltage rails merged or split according to the configuration. For the Volume (merged low voltage rails) configuration six external load switches are controlled and monitored by using six powergood comparator logic blocs. Device Information PART NUMBER PACKAGE TPS650830 (1) 1.4 (1) BODY SIZE (NOM) NFBGA (168) 7.00 mm x 7.00 mm NFBGA (159) 9.00 mm x 9.00 mm For more information, see Section 11, Mechanical Packaging and Orderable Information. Simplified System Diagram TPS650830 PMIC Non-NVDC ADAPTOR FET FET VBATA FET CHARGER NVDC VR5, 5V FET FET VR3, 3.3V FET FET FET FET + LOAD SWITCH BAT1 - LOAD SWITCH FET FET LOAD SWITCH + VR2, 1.8V BAT2 LOAD SWITCH - SKYLAKE/ KABYLAKE PLATFORM LOAD SWITCH VR1, 1V FET FET LOAD SWITCH VR4, 1.2V FET FET LDO1, 0.6V RTC, 3.1V + I/O - I2C Copyright © 2016, Texas Instruments Incorporated Figure 1-1. Simplified System Diagram 2 Device Overview Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Table of Contents 1 Device Overview ......................................... 1 Register Map ........................................ 75 Features .............................................. 1 1.2 Applications ........................................... 1 7.1 Application Information 1.3 Description ............................................ 1 7.2 Typical Application ................................. 127 1.4 Simplified System Diagram ........................... 2 .................................. ................................... Power Supply Recommendations ................. Layout ................................................... 9.1 Layout Guidelines .................................. 9.2 Layout Example .................................... 9.3 Thermal Considerations ........................... Device and Documentation Support .............. 10.1 Device Support..................................... 10.2 Documentation Support ............................ 10.3 Receiving Notification of Documentation Updates. 10.4 Community Resources............................. 10.5 Trademarks ........................................ 10.6 Electrostatic Discharge Caution ................... 10.7 Glossary............................................ 2 3 4 Revision History ......................................... 3 Device Options ........................................... 6 Pin Configuration and Functions ..................... 7 5 Specifications ........................................... 14 4.1 5.1 7 8 9 Pin Functions ......................................... 9 Absolute Maximum Ratings ......................... 14 ........................................ 5.3 Recommended Operating Conditions ............... 5.4 Thermal Information ................................. 5.5 Electrical Characteristics ............................ 5.6 Timing Requirements ............................... 5.7 Typical Characteristics .............................. Detailed Description ................................... 6.1 Overview ............................................ 6.2 Functional Block Diagram ........................... 6.3 Feature Description ................................. 6.4 Device Functional Modes ........................... 6.5 Programming ....................................... 5.2 6 6.6 1.1 ESD Ratings 16 16 18 18 43 46 50 50 51 52 70 10 Application and Implementation ................... 127 7.3 System Example 7.4 Do's and Don'ts ............................ 127 142 142 143 144 144 146 148 149 149 149 149 149 149 149 149 11 Mechanical, Packaging, and Orderable Information ............................................. 150 11.1 Packaging Information ............................. 150 72 2 Revision History Changes from Original (December 2014) to Revision A • • • • • • • • • • • • • • • • • • • • • • • • • • • Page Changed from data sheet format to data manual format ........................................................................ 1 Changed Applications ............................................................................................................... 1 Changed Skylake to Skylake and Kabylake throughout data manual ......................................................... 2 Added Device Options section ...................................................................................................... 6 Changed pinout diagrams ........................................................................................................... 7 Added TYPE column to pin functions tables ...................................................................................... 9 Added Switch pins - controllers (transient 1.05V in bit 6:3 description in Table 6-48 ................................................................ 111 Changed ? 1V to >1.05V in bit 6:3 description in Table 6-49 ................................................................ 112 Changed ? 1V to >1.05V in bit 6:3 description in Table 6-50 ................................................................ 113 Changed ? 1V to >1.05V in bit 6:3 description in Table 6-51 ................................................................ 114 Revision History Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com • • • • • • SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Changed ? 1V to >1.05V in bit 6:3 description in Table 6-52 ................................................................ Changed ? 1V to >1.05V in bit 6:3 description in Table 6-53 ................................................................ Changed O to Ω in bit 7 description in Table 6-54 ........................................................................... Changed ? 1V to >1.05V in bit 6:3 description in Table 6-54 ................................................................ Changed O to Ω in bit 0 description in Table 6-59 ........................................................................... Deleted last two paragraphs and equation from Section 7.2.2.1.2 ......................................................... Revision History Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 115 116 117 117 122 130 5 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 3 Device Options Table 3-1. Voltage Regulator and Powergood Comparator Logic Assignment for Skylake and Kabylake Platforms SWITCHING FREQUENCY, Fsw NVDCZ = 1 / 0 LPM VOLTAGE, Vout Default POWER GOOD OUTPUT SETTING, (PGVRx or PGx is PP or OD) TPS650830 Skylake and Kabylake PLATFORM POWER SYSTEM VOLTAGE RAIL VOLUME (Merged Low Voltage Rails) OUTPUT VOLTAGE, Vout DEFAULT, or COMPARATOR INPUT VR1 V1.00A / V 0.85A 1.00 V 500 kHz / 800 kHz LPM = 1.00 V PP VR2 V1.8A 1.8 V 2 MHz / 2 MHz LPM = 1.8 V PP LPM = 3.3 V PP VR3 V3.3A_DSW 3.3 V 800 kHz / 800 kHz VR4 V1.2U 1.2 V,1.35 V,1.1 V 500 kHz / 800 kHz LPM = 1.2 V,1.35 V,1.1 V OD VR5 V5A_DS3 5V 800 kHz / 800 kHz LPM = 5.0 V PP LDO1 V0.6Dx 0.6 V, 0.675 V, 0.55 V - LPM = DDR_VTT_ CTRL = Off NA External VR_a none - - - -- External VR_b none - - - -- Powergood Comparator Logic a V3.3A_PCH Enable/Sense External Load Switch 3.3 V, Comparator Analog Input – – PP Powergood Comparator Logic b V1.8U_2.5U Enable/Sense External Load Switch 1.8 V, Comparator Analog Input – – PP Powergood Comparator Logic c Generic Comparator - Comparator Disabled – – - Powergood Comparator Logic d VCCIO Enable/Sense External Load Switch 1.00 V, Comparator Analog Input – – PP Powergood Comparator Logic e V3.3S Sense External Load Switch 3.3 V, Comparator Analog Input – – PP Powergood Comparator Logic f V1.8S Sense External Load Switch 1.8 V, Comparator Analog Input – – PP Powergood Comparator Logic g V1.0S Sense External Load Switch 1.00 V, Comparator Analog Input – – OD 6 Device Options Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 4 Pin Configuration and Functions D E F G H J K L M N 13 A13 NC B13 VBATTBK UP C13 V3P3A_RT C D13 AGND4 E13 VREGVR2 F13 VINVR2 G13 PGNDVR2 H13 SWVR2 J13 END K13 DS3_VREN L13 AGND3 M13 VDDIO N13 NC 12 A12 DRVHVR3 B12 ENA C12 ENC D12 PMIC_INT # E12 PGVR2 F12 VINVR2 G12 PGNDVR2 H12 SWVR2 J12 ENF K12 DPWROK L12 LVA M12 ENVR1 N12 DRVHVR1 11 A11 SWVR3 B11 VBSTVR3 C11 ENB D11 ACOK E11 PCH_PWR OK F11 ENVR2 G11 ALL_SYS_P WRGD H11 SYS_PWR OK J11 RSMRST#_ PWRGD K11 1HZ L11 ENH M11 VBSTVR1 N11 SWVR1 10 A10 PGNDVR3 B10 ENG C10 FBVR3 D10 ILIMVR3H S E10 FBVR2N F10 ENE G10 FBVR2P H10 TRIP# J10 VSG K10 FBVR1P L10 LVB M10 VREGVR1 N10 PGNDVR1 9 A9 DRVLVR3 B9 PGVR1 C9 ILIMVR3LS D9 STANDBY# E9 ENVR3 F9 VINLDO1S G9 VINVR3 H9 NVDC# J9 FBVR1N K9 VSB L9 ILIMVR1 M9 PGVR1 N9 DRVLVR1 8 A8 VOUTLDO 1 B8 VOUTLDO 1 C8 RESET# D8 FBLDO1 E8 VSF F8 AGND G8 AGND H8 AGND J8 AGND K8 VSC L8 VDDLV M8 VINLDO3 N8 LDO3V 7 A7 PGNDLDO 1 B7 PGNDLDO 1 C7 SHUTDWO N# D7 FBVR3N E7 VSA F7 AGND G7 AGND H7 AGND J7 AGND K7 AGND L7 VINVR5 M7 VOUT3V3 SW N7 LDO5V 6 A6 VINLDO1 B6 VINLDO1 C6 PGC D6 PGA E6 VSD F6 AGND G6 AGND H6 AGND J6 AGND K6 AGND L6 ENLVA M6 PGH N6 VIN 5 A5 DRVLVR4 B5 PGVR4 C5 PGB D5 FBVR4N E5 VINPP F5 VSH G5 AGND H5 AGND J5 AGND K5 ILIMVR5H S L5 ILIMVR5LS M5 EN5VSW N5 VIN5VSW 4 A4 PGNDVR4 B4 VREGVR4 C4 PGE D4 DDRID E4 VCCST_P WRGD F4 VSE G4 FBVR5P H4 PGF J4 VCOMP K4 EN_ONOF F# L4 FBVR5N M4 PGVR5 N4 DRVLVR5 3 A3 SWVR4 B3 VBSTVR4 C3 FBVR4P D3 VPROGOT P E3 DDR_VTT_ CTRL F3 PGG G3 VDCSNS H3 PGD J3 EC_RST# K3 EN3V3SW L3 SLAVEADD R M3 VBSTVR5 N3 PGNDVR5 2 A2 DRVHVR4 C2 ENVR4 D2 ILIMVR4 E2 ACIN F2 BAT1SWO N# G2 BAT2SWO N# H2 PWRBTNI N J2 ACSWON# K2 PCH_PWR BTN# L2 TEMP_ALE RT# M2 ENVR5 N2 SWVR5 1 A1 NC C1 AGND1 D1 VDDPG E1 VDDIO F1 BAT1 G1 BAT2 H1 SDA J1 SCLK K1 AGND2 L1 ECVCC M1 DRVHVR5 N1 NC VR4 LDO1 VR3 C B1 VREF1V25 VR5 B VR1 A Legend Color Type Power Critical Analog / Sensitve Digital AGND No Connect Figure 4-1. 168-Pin 7x7 ZAJ NFBGA (Top View) Pin Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 7 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com VR2 C D E F G H J K L M N P R T 16 A16 NC B16 NC C16 VBATTBK UP D16 V3P3A_RT C E16 AGND4 F16 RSMRST#_ PWRGD G16 VREGVR2 H16 VINVR2 J16 PGNDVR2 K16 SWVR2 L16 END M16 DS3_VREN N16 AGND3 P16 VDDIO R16 NC T16 NC 15 A15 NC B15 ENA H15 VINVR2 J15 PGNDVR2 K15 SWVR2 R15 ENVR1 T15 NC 14 A14 DRVHVR3 R14 VBSTVR1 T14 DRVHVR1 13 A13 SWVR3 12 A12 PGNDVR3 11 A11 DRVLVR3 10 A10 PGB 9 A9 VOUTLDO 1 B9 VOUTLDO 1 8 A8 PGNDLDO 1 B8 PGNDLDO 1 7 A7 VINLDO1 B7 VINLDO1 6 A6 DRVLVR4 5 A5 PGNDVR4 4 A4 SWVR4 3 A3 DRVHVR4 2 A2 NC B2 ENVR4 C2 DDRID 1 A1 NC B1 NC C1 VCCST_P WRGD F15 ALL_SYS_P WRGD D15 ENC E14 PMIC_INT # C14 ENG B13 VBSTVR3 D13 ENB B11 PGVR3 F13 ACOK D11 ENVR3 C10 STANDBY# G12 FBVR2N E10 ILIMVR3LS C8 SHUTDOW N# D7 PGC C6 PGVR4 E6 FBVR4N E4 DDR_VTT_ CTRL C4 VBSTVR4 D3 VPROGOT P E1 AGND1 F1 VDDIO G1 VDCSNS K3 BAT2SWO N# J1 BAT2 L1 EN3V3SW R4 VBSTVR5 N2 PCH_PWR BTN# M1 SCLK N1 AGND2 P1 ECVCC T6 DRVLVR5 T5 PGNDVR5 P3 TEMP_ALE RT# M3 ACSWON# L2 PWRBTNI N K1 SDA P5 ENLVA N4 SLAVEADD R T8 VIN T7 VIN5VSW R6 PGVR5 N6 ILIMVR5LS L4 EC_RST# J2 BAT1SWO N# H1 BAT1 P7 EN5VSW M5 EN_ONOF F# J4 PGD G2 VDDPG D1 VREF1V25 L6 VCOMP T10 LDO3V T9 LDO5V R8 PGH N8 VINVR5 K5 PGF H3 ACIN P9 VOUT3V3 SW M7 ILIMVR5H S J6 FBVR5P G4 PGG F3 ILIMVR4 L8 VSC T12 PGNDVR1 T11 DRVLVR1 R10 VINLDO3 N10 VDDLV K7 VSG H5 FBVR5N P11 PGVR1 M9 VSB J8 VSF G6 VSE F5 FBVR4P L10 VSD T13 SWVR1 R12 VREGVR1 N12 LVB M11 ILIMVR1 K9 NVDC# H7 VINPP P13 ENH VR5 D5 PGE K11 FBVR1N H9 VINLDO1S F7 VSA L12 TRIP# J10 FBVR1P G8 VSH N14 LVA M13 1HZ J12 ENE G10 FBVR2P E8 FBVR3N L14 ENF K13 SYS_PWR OK H11 VINVR3 F9 FBLDO1 M15 DPWROK J14 ENVR2 H13 PGVR2 F11 FBVR3P D9 RESET# B5 VREGVR4 G14 PCH_PWR OK E12 ILIMVR3H S C12 PGA VR4 LDO1 VR3 B VR1 A T4 SWVR5 T3 DRVHVR5 R2 ENVR5 T2 NC R1 NC T1 NC Legend Color Type Power Critical Analog / Sensitve Digital AGND No Connect Figure 4-2. 159-Pin 9x9 ZCG NFBGA (Top View) 8 Pin Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com 4.1 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Pin Functions Table 4-1. Pin Functions PIN NAME ZAJ PACKAGE NUMBER ZCG PACKAGE NUMBER I/O TYPE (1) ACIN E2 H3 I AS DESCRIPTION AC Adaptor voltage sense ACOK D11 F13 I D ACOK input ACSWONZ J2 M3 O D AC adaptor switch ON power-path (Open-drain output) (active low) AGND F8, G8, H8, J8, F7, G7, H7, J7, K7, F6, G6, H6, J6, K6, G5, H5, J5 - - A Analog GND - tie directly to the ground plane AGND1 C1 E1 - A Analog GND1 - tie directly to the ground plane AGND2 K1 N1 - A Analog GND2 - tie directly to the ground plane AGND3 L13 N16 - A Analog GND3 - tie directly to the ground plane AGND4 D13 E16 - A Analog GND4 - tie directly to the ground plane ALL_SYS_PWRGD G11 F15 O D Non-core rails powergood, All PMIC and specified monitored VRs power good (Open-drain output) BAT1 F1 H1 I AS Battery 1 voltage sense input BAT2 G1 J1 I AS Battery 2 voltage sense input BAT1SWONZ F2 J2 O D Battery 1 switch ON power-path (Open-drain output) (active low) BAT2SWONZ G2 K3 O D Battery 2 switch ON power-path (Open-drain output) (active low) DDRID D4 C2 I D VR4 Output voltage selection. Low = 1.2 V, High = 1.35 V, Float = 1.1 V. DDR_VTT_CTRL E3 E4 I D LDO1 Enable, and DVS control of VR4 Delayed version of V3.3A_DSW_PG (Open-drain output) (1) DPWROK K12 M15 O D DRVHVR1 N12 T14 O VR VR1 High side gate drive output (external power FET) DRVHVR3 A12 A14 O VR VR3 High side gate drive output (external power FET) DRVHVR4 A2 A3 O VR VR4 High side gate drive output (external power FET) DRVHVR5 M1 T3 O VR VR5 High side gate drive output (external power FET) DRVLVR1 N9 T11 O VR VR1 Low side gate drive output (external power FET) DRVLVR3 A9 A11 O VR VR3 Low side gate drive output (external power FET) DRVLVR4 A5 A6 O VR VR4 Low side gate drive output (external power FET) DRVLVR5 N4 T6 O VR VR5 Low side gate drive output (external power FET) DS3_VREN K13 M16 O D DS3 VR enable (enables external power switches) (Push-pull output) ECVCC L1 P1 I AS EC_ONOFFZ K4 M5 O D EC VCC supply Debounced version of PWRBTNIN (Open-drain output) (active low) EC_RSTZ J3 L4 O D EC reset (Open-drain output) (active low) ENA B12 B15 I D Enable for VSA powergood comparator ENB C11 D13 I D Enable for VSB powergood comparator ENC C12 D15 I D Enable for VSC powergood comparator END J13 L16 I D Enable for VSD powergood comparator ENE F10 J12 I D Enable for VSE powergood comparator ENG B10 C14 I D Enable for VSG powergood comparator ENF J12 L14 I D Enable for VSF powergood comparator ENH L11 P13 I D Input to Level Shifter B general purpose level shifter. ENLVA L6 P5 I D Enable level shifter A. Pin not used for TPS650830. Connect to ground if unused. (Level Shifter A input is ACOK pin) VR – VR Critical, AS – Analog Sensitive, D – Digital, A - AGND Pin Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 9 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Table 4-1. Pin Functions (continued) PIN 10 NAME ZAJ PACKAGE NUMBER ZCG PACKAGE NUMBER I/O TYPE (1) ENVR1 M12 R15 I D VR1 Enable ENVR2 F11 J14 I D VR2 Enable ENVR3 E9 D11 I D VR3 Enable ENVR4 C2 B2 I D VR4 Enable ENVR5 M2 R2 I D VR5 Enable DESCRIPTION EN3V3SW K3 L1 I D Enable for load switch from LDO3V pin to VOUT3V3SW output pin EN5VSW M5 P7 I D Enable Internal load switch from 5-V switching regulator to LDO5V output through VIN5VSW. Connect to powergood of 5-V switching regulator. FBLDO1 D8 F9 I AS LDO1 Feedback voltage kelvin sense, (Connect to vout of LDO1 at output load capacitor) FBVR1N J9 K11 I AS VR1 Negative feedback remote sense (Connect to GND of VR1 at output load capacitor) FBVR1P K10 J10 I AS VR1 Positive feedback remote sense (Connect to vout of VR1 at output load capacitor) FBVR2N E10 G12 I AS VR2 Negative feedback remote sense (Connect to GND of VR2 at output load capacitor) FBVR2P G10 G10 I AS VR2 Positive feedback remote sense (Connect to vout of VR2 at output load capacitor) FBVR3N D7 E8 I AS VR3 Negative feedback remote sense (Connect to GND of VR3 at output load capacitor) FBVR3P C10 F11 I AS VR3 Positive feedback remote sense (Connect to vout of VR3 at output load capacitor) FBVR4N D5 E6 I AS VR4 Negative feedback remote sense (Connect to GND of VR4 at output load capacitor) FBVR4P C3 F5 I AS VR4 Positive feedback remote sense (Connect to vout of VR4 at output load capacitor) FBVR5N L4 H5 I AS VR5 Negative feedback remote sense (Connect to GND of VR5 at output load capacitor) FBVR5P G4 J6 I AS VR5 Positive feedback remote sense (Connect to vout of VR5 at output load capacitor) ILIMVR1 L9 M11 I AS VR1 Current limit setting, low-side FET valley current limit ILIMVR3HS D10 E12 I AS VR3 Current limit setting, high-side FET peak current limit ILIMVR3LS C9 E10 I AS VR3 Current limit setting, low-side FET valley current limit ILIMVR4 D2 F3 I AS VR4 Current limit setting, low-side FET valley current limit ILIMVR5HS K5 M7 I AS VR5 Current limit setting, high-side FET peak current limit ILIMVR5LS L5 N6 I AS VR5 Current limit setting, low-side FET valley current limit LDO3V N8 T10 O AS 3.3-V LDO used as a reference voltage, and as a pull-up supply. LDO5V N7 T9 O AS 5-V internal supply used primarily for the gate drives LVA L12 N14 O D Level shifter A open-drain output, used for BC_ACOK output level shifted to EC_VCC. Input is from ACOK pin LVB L10 N12 O D Level shifter B push-pull output, level shifted to VDDLV. Input is from ENH pin NVDC# H9 K9 I D NVDC select [two-level: Low = NVDC, High = non-NVDC]. Connect NVDC# to GND for NVDC, Connect NVDC# to LDO3V for non-NVDC PCH_PWRBTNZ K2 N2 O D Power button signal to PCH (Open-drain output) (active low) PCH_PWROK E11 G14 O D Core and Non Core powergood, Delayed version of ALL_SYS_PWRGD, (Open-drain output) PGA D6 C12 O D Powergood comparator output, push-pull to VDDPG PGB C5 A10 O D Powergood comparator output, push-pull to VDDPG Pin Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Table 4-1. Pin Functions (continued) PIN NAME ZAJ PACKAGE NUMBER ZCG PACKAGE NUMBER I/O TYPE (1) PGC C6 D7 O D Powergood comparator output, push-pull to VDDPG PGD H3 J4 O D Powergood comparator output, push-pull to VDDPG PGE C4 D5 O D Powergood comparator output, push-pull to VDDPG PGF H4 K5 O D Powergood comparator output, push-pull to VDDPG PGG F3 G4 O D Powergood comparator output, open-drain output Powergood comparator output, open-drain output DESCRIPTION PGH M6 R8 O D PGNDLDO1 A7, B7 A8, B8 - VR LDO1 Power GND PGNDVR1 N10 T12 - VR VR1 Power GND PGNDVR2 G12, G13 J15, J16 - VR VR2 Power GND PGNDVR3 A10 A12 - VR VR3 Power GND PGNDVR4 A4 A5 - VR VR4 Power GND VR5 Power GND PGNDVR5 N3 T5 - VR PGVR1 M9 P11 O D VR1 powergood comparator output (Push-pull output) PGVR2 E12 H13 O D VR2 powergood comparator output (Push-pull output) PGVR3 B9 B11 O D VR3 powergood comparator output (Push-pull output) PGVR4 B5 C6 O D VR4 powergood comparator output (Open-drain output) PGVR5 M4 R6 O D VR5 powergood comparator output (Push-pull output) PMIC_INTZ D12 E14 O D PMIC to EC interrupt (Open-drain output) (active low) PWRBTNIN H2 L2 I AS RESETZ C8 D9 O D Global disable output for external converters/power tree (active low) RSMRSTZ_PWRGD J11 F16 O D Resume Reset powergood (Open-drain output) (active low) SCLK J1 M1 I D I2C Clock SDA H1 K1 I/O D I2C Data SHUTDOWNZ C7 C8 I D Set shutdown mode (all supplies off) (active low) SLAVEADDR L3 N4 I D I2C Slave Address select (low = 0x30, high = 0x32, open = float = 0x34). Keep same connection during operation. STANDBYZ D9 C10 I D Set rails in standby when low (low power mode) SWVR1 N11 T13 I VR VR1 Switch node connection SWVR2 H12, H13 K15, K16 I VR VR2 Switch node connection SWVR3 A11 A13 I VR VR3 Switch node connection SWVR4 A3 A4 I VR VR4 Switch node connection SWVR5 N2 T4 I VR VR5 Switch node connection Power button input (internal pull-up to LDO3V) (active low) SYS_PWROK H11 K13 O D Delayed version of ALL_SYS_PWRGD (Open-drain output) TEMP_ALERTZ L2 P3 O D Open-drain output of silicon temperature sensor. Input to Power Monitor Unit (connect to PROCHOT# of system). Active low, recommended pull-up to V1.00S with 50 Ω. VCOMP comparator push-pull output (active low) TRIPZ H10 L12 O D VBATTBKUP B13 C16 I AS RTC backup battery supply connection VBSTVR1 M11 R14 I VR VR1 Bootstrap pin VBSTVR3 B11 B13 I VR VR3 Bootstrap pin VBSTVR4 B3 C4 I VR VR4 Bootstrap pin VBSTVR5 M3 R4 I VR VR5 Bootstrap pin VCCST_PWRGD E4 C1 O D VCOMP J4 L6 I AS VCOMP comparator input VDCSNS G3 G1 I AS VDC voltage monitor VCCST powergood (Open-drain output) Pin Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 11 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Table 4-1. Pin Functions (continued) PIN NAME ZAJ PACKAGE NUMBER ZCG PACKAGE NUMBER I/O TYPE (1) VDDIO E1, M13 F1, P16 I VR Voltage supply input for I/O buffers. VDDIO should be tied to LDO3V (3.3 V) DESCRIPTION VDDLV L8 N10 I VR LVx buffer supply, sets output level for Level Shifter pins VDDPG D1 G2 I VR PGx supply, sets output level for PG pins for A-H, if PG pin is pushpull VDD5 VPROGOTP D3 D3 I AS Always connect to LDO5V. supply voltage for OTP programming (must be connected to LDO5V in normal operation) 12 VIN N6 T8 I VR IC input voltage VINLDO1 A6, B6 A7, B7 I VR LDO1 Input supply VINLDO3 M8 R10 I VR LDO3V input supply VINLDO1S F9 H9 I AS LDO1 Input voltage reference sense (Connect to vout of VR4 at output load capacitor) VINPP E5 H7 I AS VIN for Power Path Domain. Connect to external diode OR from: AC, BAT1, BAT2. VINVR2 F12, F13 H15, H16 I VR VR2 Power Input voltage. Connect to a 3.3-V voltage regulator, such as V3.3A_DSW . VINVR3 G9 H11 I AS VR3 Input voltage sense and high-side current-sense (Kelvin connect to drain of high-side FET) VINVR5 L7 N8 I AS VR5 Input voltage sense and high-side current-sense (Kelvin connect to drain of high-side FET) VIN5VSW N5 T7 I VR Internal load switch from 5-V switching regulator to LDO5Voutput. Connect VIN5VSW to 5-V switching regulator output. VOUTLDO1 A8, B8 A9, B9 O VR LDO1 Output voltage, VOUTLDO1 = (1/2 * VINLDO1SNS) VOUT3V3SW M7 P9 O VR EC domain load switch output and discharge path from LDO3V VREF1V25 B1 D1 O AS Decoupling cap connection for internal voltage reference VREGVR1 M10 R12 I VR 5-V drive supply input (shorted on board with LDO5V), supply for VR1 and VR5 VREGVR2 E13 G16 I VR VR2 5-V drive supply input (shorted on board with LDO5V) VREGVR4 B4 B5 I VR VR4 5-V drive supply input (shorted on board with LDO5V), shared with VR3 VSA E7 F7 I AS Powergood comparator input and discharge path for external rail VSB K9 M9 I AS Powergood comparator input and discharge path for external rail VSC K8 L8 I AS Powergood comparator input and discharge path for external rail VSD E6 L10 I AS Powergood comparator input and discharge path for external rail VSE F4 G6 I AS Powergood comparator input and discharge path for external rail VSF E8 J8 I AS Powergood comparator input and discharge path for external rail VSG J10 K7 I AS Powergood comparator input and discharge path for external rail VSH F5 G8 I AS Powergood comparator input and discharge path for external rail V3P3A_RTC C13 D16 O AS PCH RTC power supply 1HZ K11 M13 O D 1-Hz clock output for waking up embedded controller, EC. Pin Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Table 4-1. Pin Functions (continued) PIN ZAJ PACKAGE NUMBER ZCG PACKAGE NUMBER DEPOPULATED BALL - FOR VIAS No Depopulate d Balls for Vias in 7x7. Type 4 PC put microvias under each ball pad B3, B4, B6, DEP B10, B12, OPU B14, C3, LAT C5, C7, C9, ED C11, C13, BAL C15, D2, L D4, D6, D8, D10, D12, D14, E2, E3, E5, E7, E9, E11, E13, E15, F2, F4, F6, F8, F10, F12, F14, G3, G5, G7, G9, G11, G13, G15, H2, H4, H6, H8, H10, H12, H14, J3, J5, J7, J9, J11, J13, K2, K4, K6, K8, K10, K12, K14, L3, L5, L7, L9, L11, L13, L15, M2, M4, M6, M8, M10, M12, M14, N3, N5, N7, N9, N11, N13, N15, P2, P4, P6, P8, P10, P12, P14, P15, R3, R5, R7, R9, R11, R13, - VIA PLACEMENT FOR INTERNAL BALL ROUTES - For Type3 PCBs, put a plated through-hole (PTH) via at each depopulated ball, to connect to the internal row balls. DEPOPULATED BALL - PICK-NPLACE INDICATOR B2 C3 (also DEP used for via OPU - see below) LAT ED BAL L - PICK-N-PLACE INDICATOR NC POPULATED BALL - CORNERS A1, A13, N1, N13 A1, A2, B1, A15, A16, B16, R16, T16, T15, R1, T1, T2 - CORNERS - solder to PCB for mechanical strength NAME I/O POP ULA TED BAL L TYPE (1) DESCRIPTION Pin Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 13 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT CHIP Power input pins VIN, VINLDO3 -0.3 28 V Analog ground pins AGND1, AGND2, AGND3, AGND4, AGND (16 center pins) -0.3 0.3 V Input pins - controllers VINVR3, VINVR5 -0.3 28 V Switch pins - controllers SWVR1 , SWVR3 , SWVR4 , SWVR5 -1 28 V Switch pins - controllers (transient UVLO, 3.3-V and 5-V LDOs up, Measured at the V3P3A_RTC pin with respect to AGND. Place a 1-µF capacitor at V3P3A_RTC. (Do not exceed 2 µF actual capacitance). I3v1LDO Maximum 3V1 LDO output current Maximum output current out of 3V3RTC. IQ_bkup_no_Vsys VBATTBKUP quiescent current, when no adapter and no main battery connected to system, automatically VBATTBKUP internally selected, internal 3.1-V LDO automatically off VVDC < UVLO, VBBC = 2.0 V to 3.0 V, VVDC = 0 V IQ_bkup_with_Vsys VBATTBKUP quiescent current, when adapter or main battery connected to system, automatically VVDC > UVLO, VBBC = 2.0 V to 3.0 V, VBATTBKUP internally not VVDC = 7.4 V selected, internal 3.1-V LDO automatically on and selected. (1) 42 3.0 3.1 3.2 V 1 mA 0.03 0.45 μA 0.15 0.85 μA All values referred to VIH min and VIH max levels. Specifications Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Electrical Characteristics (continued) Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted) PARAMETER TEST CONDITIONS External resistor in series with backup battery Rext_bkup MIN TYP Place between backup battery and VBATTBKUP pin, for limiting current out of backup battery MAX UNIT 1 kΩ I2C INTERFACE VIL SDA, SCL input low voltage VIH SDA, SCL input high voltage Cb 0.4 V SDA, SCL input current Clamped on 3.3 V 0.01 0.3 SDA output low voltage ISDA = 5 mA (using a 354 Ω or larger external pull-up resistor) 0.04 0.4 Capacitive load for SDA and SCL 5.6 V 1.2 μA V 400 pF MAX UNIT Timing Requirements PARAMETER TEST CONDITIONS MIN TYP I2C INTERFACE tI2C_Rdy Minimum time for I2C to be ready after VIN > UVLO5V rising Time after VIN rising above > VUVLO_5V_Main + VHys_5V_Mainuntil OTP is loaded and I2C is ready to communicate 1 Standard-mode f(SCL) SCL clock frequency 100 Fast-mode 400 Fast-mode Plus Bus free time between a STOP and START condition tBUF STA tSU; STA 4.7 Fast-mode 1.3 Fast-mode Plus 0.5 tSU; DAT tHD; DAT Data setup time Data hold time 4 μs ns Fast-mode Plus 260 ns Standard-mode 4.7 μs Fast-mode 600 ns Fast-mode Plus 260 ns Standard-mode 250 Fast-mode 100 Rise time of SCL signal 50 Standard-mode 0 3.45 Fast-mode 0 0.9 Fast-mode Plus 0 Fast-mode Fast-mode (using an 885 Ω or smaller external pull-up resistor) Fast-mode Plus (using a 354 Ω or smaller external pull-up resistor) 300 Submit Documentation Feedback Product Folder Links: TPS650830 ns 1000 20 300 ns 120 Specifications Copyright © 2014–2016, Texas Instruments Incorporated μs ns 120 Standard-mode (using a 2.95 kΩ or smaller external pull-up resistor) Rise time of SDA signal μs 1000 20 Fast-mode Plus trDA ns Fast-mode Plus Standard-mode trCL μs 600 Hold time (repeated) START condition Fast-mode Setup time for a repeated START condition kHz 1000 Standard-mode Standard-mode tHD; ms 43 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Timing Requirements (continued) PARAMETER TEST CONDITIONS MIN Standard-mode tfDA Fall time of SDA signal 44 Setup time for STOP condition MAX UNIT 300 Fast-mode 20 x (VDD / 5.5 V) 300 Fast-mode Plus 20 x (VDD / 5.5 V) 120 Standard-mode tSU; STO TYP ns 4 µs Fast-mode 600 ns Fast-mode Plus 260 ns Specifications Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 VOLUME Application Block Diagram: VR1 = V1.00A (V11), & V085A (V12), VR2 = V1.8A (V8), VR3 = V33ADSW (V6), VR4 = V1.2U (V10), VR5 = V5ADS3 (V5) COMPA = V3.3A_PCH (V7), COMPB = V1.8U_2.5U (V9), COMPC = Generic Comparator, COMPD = VCCIO (V4), COMPE = V3.3S, COMPF = V1.8S, COMPG = V1.00S TPS650830 ± VOLUME S5/S4 G3 ÆS5/S4 G3 VOL#1 S5/S4 Æ S0 VDC (BAT/ADP Insertion ) VREF1V25 UVLO3# [UVLO2#_LDO3EN] LDO3 LDO3_PG UVLO5# [UVLO1#_LDO5EN] (Power On Dig Reset ) LDO5 LDO5_PGD xxxx xxxx xxxx 1ms from UVLO5/Dig Reset to OTP Loaded OTP_LOAD I2C Ready PMIC I2C V3P3A_RTC 3.2V [V3P3A_RTC] 2.0V 3.1V LDO Vcoin_cell_battery V3.3A_DSW_EN (V6) [ENVR3] (Tie to LDO 3) V33ADSW (V6) [FBVR3P] PG V3.3A_DSW_PG (V6) [PGVR3] 16ms >10ms delay from PG V3.3A_DSW to DPWROK DPWROK [DPWROK] ext V1.8A_EN (V8) [ENVR2] Assumes V1.8A enabled by DPWROK. Could also be enabled by SLP _SUS# later. V1.8A (V8) [FBVR2P] PG V1.8A_PG [PGVR2] DPWROK to SLP_SUS# takes 95ms from PCH 95ms SLP_SUS# [ENE] ext V5ADS3_EN [ENVR5] V5ADS3_EN is copy of SLP _SUS# DS3_VREN [DS3_VREN] xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx DS3VREN is gated by V5ADS3_EN ~ 1us delay V5ADS3 (V5) [FBVR5P] PG V5ADS3_PG [PGVR5] V5A_DS3_PG to V 1.00A_PG 10mSec RSMRST#_PWRGD [RSMRST#_PWRGD] external SLP_S4# [ENB] V1.8U_2.5U_EN [PGB] SLP_S4# to V1.8U_2.5U ramp = 0.5ms ” tdelay +tramp-up ” 2ms [Load Sw turn-on time] V1.8U_2.5U (V9) [VSB] ext PG V1.8U_2.5U_PG [PMIC internal ] V1.2U_EN [ENVR4] SLP_S4# to V1.2U ramp >2.5ms [4ms] V1.2U (V10) [FBVR4P] PG V1.2U_PG [PGVR4] SLP_S3# [ENF] for powergood tree only ext V100S_EN [ENG] ± to Load Switch V1.00S [VSG] ext PG V1.00S_PG [PGG] V3.3S_EN [ENG] ± to Load Switch V3.3S [VSE] PG V3.3S_PG [PMIC internal ] V1.8S_EN [ENG] ± to Load Switch ext V1.8S [VSF] ext PG V1.8S_PG [PGF] ext VCCIO_EN [PGD] ± to Load Switch SLP_S3# & V1.2U_PG & V1.00S_PG [V1.2U_PG & V1.00S_PG open-drain outputs drive same ENVR3 pin, with single pull-up resistor] No direct SLP_S3# connection VCCIO (V4) [VSD] PG VCCIO_PG [PMIC internal ] 2ms (from the last PG ) ALL_SYS_PWRGD [ALL_SYS_PWRGD] 1.00V VCCST_PWRGD [VCCST_PWRGD] PCH_PWROK [PCH_PWROK] Prog SYS_PWROK [SYS_PWROK] Prog Figure 5-1. TPS650830 Volume Timing Diagram Specifications Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 45 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 5.7 www.ti.com Typical Characteristics 1.05 1.89 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 1.04 1.03 1.85 1.84 VR2 Vout (V) VR1 Vout (V) 1.02 1.01 1.00 0.99 1.82 1.80 1.78 0.98 1.76 0.97 1.75 0.96 1.73 0.95 1.71 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 Iout (A) D001 0 1.5 2 2.5 D001 1.272 Vin=5.40 Vin=8.10 Vin=8.70 Vin=13.50 3.432 3.399 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 1.260 1.248 1.236 3.366 1.224 VR4 Vout (V) VR3 Vout (V) 1 Figure 5-3. VR2 Output Voltage Load Regulation, NVDC 3.465 3.333 3.300 3.267 1.212 1.200 1.188 3.234 1.176 3.201 1.164 3.168 1.152 3.135 1.140 0 1 2 3 4 5 6 Iout (A) 7 0 1 2 3 D001 Figure 5-4. VR3 Output Voltage Load Regulation, NVDC 4 Iout (A) 5 6 7 8 D001 Figure 5-5. VR4 Output Voltage Load Regulation, NVDC 5.25 100 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 5.20 5.15 90 80 VR1 Efficiency (%) 5.10 VR5 Vout (V) 0.5 Iout (A) Figure 5-2. VR1 Output Voltage Load Regulation, NVDC 5.05 5.00 4.95 4.90 70 60 50 40 30 4.85 20 4.80 10 4.75 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 0 0 0.5 1 1.5 2 Iout (A) 2.5 3 3.5 4 0 1 D001 Figure 5-6. VR5 Output Voltage Load Regulation, NVDC 46 Vin=2.97 Vin=3.30 Vin=3.63 1.87 2 3 4 Iout (A) 5 6 7 D001 Figure 5-7. VR1 Efficiency vs Load, NVDC Specifications Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 100 100 90 90 80 80 VR3 Efficiency (%) VR2 Efficiency (%) Typical Characteristics (continued) 70 60 50 40 30 10 0.0 0.5 1.0 1.5 2.0 50 40 30 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Iout (A) D001 2.5 Iout (A) 60 20 Vin=2.97V Vin=3.30V Vin=3.63V 20 70 D001 Figure 5-9. VR3 Efficiency vs Load, NVDC 100 100 90 90 80 80 70 70 VR5 Efficiency (%) VR4 Efficiency (%) Figure 5-8. VR2 Efficiency vs Load, NVDC 60 50 40 30 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 20 10 1 2 3 4 Iout (A) 5 6 50 40 30 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 20 10 0 0 60 0 0.00 7 Figure 5-10. VR4 Efficiency vs Load, NVDC 1.00 1.50 2.00 Iout (A) 2.50 3.00 3.50 D001 Figure 5-11. VR5 Efficiency vs Load, NVDC 900000 800000 800000 700000 700000 600000 600000 VR3 fsw (Hz) VR1 fsw (Hz) 0.50 D001 500000 400000 300000 100000 400000 300000 200000 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 200000 500000 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 100000 0 0 0 1 2 3 4 Iout (A) 5 6 7 0 0.5 D001 Figure 5-12. VR1 Switching Frequency vs Load, NVDC 1 1.5 2 2.5 3 3.5 Iout (A) 4 4.5 5 5.5 6 6.5 D001 Figure 5-13. VR3 Switching Frequency vs Load, NVDC Specifications Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 47 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Typical Characteristics (continued) 800000 800000 700000 700000 600000 600000 VR5 fsw (Hz) 500000 400000 300000 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 200000 100000 500000 400000 300000 200000 100000 0 0 1 2 3 4 Iout (A) 5 6 0 7 0 2.00 0.75 3 0.50 2 0.25 1 0.00 Vout VR2 (V) 4 Iout (VR1) Actual (A) Vout VR1 (V) 1.00 2 3 4 5 6 Iout (VR1) Programmed (A) 7 2.5 3 3.5 D001 3.5 8 3.0 2.0 2.5 1.6 2.0 1.2 1.5 0.8 1.0 0.4 0.5 0.0 0.0 0 1 2 Iout (A) Vout (Vin=2.97V) Vout (Vin=3.30V) Vout (Vin=3.63V) Iout (Vin=2.97V) Iout (Vin=3.30V) Iout (Vin=3.63V) 2.4 6 5 1.5 2.8 7 1.25 0 1 Figure 5-15. VR5 Switching Frequency vs Load, NVDC 8 Vout (Vin=5.4V) Vout (Vin=8.7V) Vout (Vin=15V) Vout (Vin=24V) Iout (Vin=5.4V) Iout (Vin=8.7V) Iout (Vin=15V) Iout (Vin=24V) 1.50 0.5 D001 Figure 5-14. VR4 Switching Frequency vs Load, NVDC 1.75 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 0.5 1.0 1.5 2.0 2.5 Iout(VR2) Programmed (A) D001 Iout(VR2) Actual (A) VR4 fsw (Hz) 900000 0.0 3.5 3.0 D001 Figure 5-16. VR1 Current Limit: Vout and Iout vs Load, Non-NVDC Figure 5-17. VR2 Current Limit: Vout and Iout vs Load, Non-NVDC 9 Vout (Vin=5.40V) Vout (Vin=8.70V) Vout (Vin=15.00V) Vout (Vin=24.00V) Iout (Vin=5.40V) Iout (Vin=8.70V) Iout (Vin=15.00V) Iout (Vin=24.00V) 7 2.1 3.6 6 1.8 6 3 5 1.5 5 2.4 4 1.2 4 1.8 3 0.9 3 1.2 2 0.6 2 0.6 1 0.3 1 0 0 0 0 1 2 3 4 5 6 Iout (VR4) Programmed (A) 7 8 9 Vout VR4 (V) 2.4 4.2 Vout VR4 (V) 9 Vout (Vin=5.40V) Vout (Vin=8.70V) Vout (Vin=13.50V) Vout (Vin=24.00V) Iout (Vin=5.40V) Iout (Vin=8.70V) Iout (Vin=13.50V) Iout (Vin=24.00V) 8 Iout (VR4) Actual (A) 4.8 2.7 8 7 Iout (VR4) Actual (A) 5.4 0 0 1 D001 2 3 4 5 6 Iout (VR4) Programmed (A) 7 8 9 D001 Figure 5-18. VR3 Current Limit: Vout and Iout vs Load, Non-NVDC Figure 5-19. VR4 Current Limit: Vout and Iout vs Load, Non-NVDC 48 Specifications Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Typical Characteristics (continued) 10 Vout VR5 (V) 7 0.675 3.5 3.0 5 2.5 4 2.0 3 1.5 2 1.0 1 0 0.0 0.700 4.0 6 0.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Iout (VR5) Programmed (A) 4.0 4.5 Vin=1.05V Vin=1.20V Vin=1.35V 0.725 4.5 0.0 5.0 LDO1 Vout (V) 8 0.750 Iout (VR5) Actual (A) 9 5.0 Vout (Vin=5.40V) Vout (Vin=8.70V) Vout (Vin=13.50V) Vout (Vin=24.00V) Iout (Vin=5.40V) Iout (Vin=8.70V) Iout (Vin=13.50V) Iout (Vin=24.00V) 0.650 0.625 0.600 0.575 0.550 0.525 0.500 0.475 -1.25 -1 -0.75 -0.5 -0.25 0 0.25 Iout (A) 0.5 0.75 1 1.25 D001 Positive current = sinking from load. Negative current = sourcing to load. Inherent droop reduces transient ripple response D001 Figure 5-20. VR5 Current Limit: Vout and Iout vs Load, Non-NVDC Figure 5-21. LDO1 Load Regulation: Vout vs Iout Specifications Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 49 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6 Detailed Description 6.1 Overview The TPS650830 is a single-chip solution Power Management IC designed specifically for the latest Intel Processors targeted for Tablets, Ultrabooks, and Notebooks with NVDC or non-NVDC power architectures, using 2S, 3S, or 4S Lithium-Ion battery packs. The TPS650830 is used for Volume systems with the low voltage rails merged for the smallest footprint and lowest cost system power solution. The TPS650830 can provide the complete power solution based on the Intel Reference Designs. Five highly efficient step-down voltage regulators (VRs) and a sink/source LDO, are used along with power-up sequence logic managing external load switches to provide the proper power rails, sequencing, and protection - including DDR3 and DDR4 memory power. The regulators support dynamic voltage scaling (DVS) for maximum efficiency including Connected Standby. The high frequency voltage regulators use small inductors and capacitors to achieve a small solution size. Output power is adjustable on four VR controllers. An I2C interface allows simple control by the embedded controller (EC). Each version is available in a 7x7 NFBGA package and a 9x9 NFBGA package. The 7x7 NFBGA package can be used in Type 4 PCB boards for the smallest area implementation. The 9x9 NFBGA package can be used in Type 3 and Type 4 PCB boards allowing to minimize cost and area. The Powergood Comparator Logic allows controlling and monitoring up to eight external load switches within the sequence. All the VR and Load Switch Powergood signals are used in the Powergood Tree of which the outputs are shown with open-drain outputs. Enable inputs allow connecting externally to set the sequence, and it also allows using various Sleep Mode State signals. The STANDBYZ allows entering a Deep Sleep Mode, in which the out put voltages of the voltage regulators can be reduced to save power by DVS. The Power Monitoring comparators are used to detect and monitor up to three input power sources (adapter, battery1, battery2, or any other combination). Over temperature of the PMIC self-protects, and outputs a Status output, TEMPALERTZ; plus there is a dedicated comparator that can monitor system over temperature with multiple stacked PTC thermistors, or an NTC thermistor. The PMIC automatically switches between an internal 3.1-V LDO when a power source is connected; or to a Backup Battery (Coin Cell) when all power sources are removed. This output RTC rail is used to maintain the always-on RTC rails for critical register data. 50 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com VDDIO OD TTL PP VDCSNS PGVR4 VDDIO EC_VCC BAT2SWONZ BAT1SWONZ POWER MONITOR HV OD ACIN ACSWONZ BAT2 BAT1 VINPP EC_RSTZ EC_ONOFFZ PCH_PWRBTNZ DPWROK RSMRSTZ_PWRGD PMIC_INTZ TTL VDDIO HIV VREF RAM VDDIO TTL TTL PCH_PWROK ALL_SYS_PWRGD VDDIO PWRBTNIN ACOK ECVCC SHUTDOWNZ STANDBYZ 1HZ VCCST_PWRGD SYS_PWROK Functional Block Diagram DS3_VREN 6.2 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 OD/PP VREGVR4 ILIMVR4 VDDIO FBVR4N PP PPATH LOGIC VDDIO RESETZ PP VSA VSB VSC VSD VSE VSF VSG VSH ENA ENB ENC END ENE ENF ENG ENH PGA PGB PGC PGD PGE PGF PGG PGH VDDPG REF PG EN VSET EN/ PGOOD LOGIC VDDIO DCH VBSTVR4 DRVHVR4 SWVR4 DRVLVR4 PGNDVR4 VDDIO TTL ENVR4 TTL SEQ + INTEL AND OEM LOGIC VDDIO TTL DDR_VTT_CTRL VINDLO1S VINLDO1[2X] EN EN LOGIC VDDPG LDO1 SINK/SRC LDO VOUTLDO1[2X] V0.6DX/0.675DX FBLDO1 /0.525DX Vout= (VR1)/2 1A max PGNDLDO1[2X] OD/PP VINVR2 [2X] ENLVA SWVR2 [2X] VR2 Converter Out range: 0.85v-3.3v Vout INTEL PG EN VSET TTL VDDLVS FBVR2P VREGVR2 FBVR2N OD/PP LVB PGNDVR2 [2X] EN/ PGOOD LOGIC VDDLV DIGCORE VREGVR1 VDDIO VDDIO FBVR1P DRVHVR1 SWVR1 ENVR2 TTL VR1 Controller Vout range 0.85v-5v Vout INTEL VBSTVR1 EN VSET V33ARTC RTC DIG EN/ PGOOD LOGIC PG DRVLVR1 VBATTBKUP BACKUP BATTERY SELECTOR OEM VCOMP PGNDVR1 V3P3A_RTC TRIPZ OD/PP VCOMP VDDIO ENVR1 TTL VDDIO OD/PP VINVR5 EN VSET FBVR3N FBVR3P VBSTVR3 DRVHVR3 VR5 Controller Out range: 0.85v-5v Vout INTEL SWVR3 SWVR5 DRVLVR3 VDDIO PGNDVR3 TTL DRVLVR5 VREGVR1 PGNDVR5 ENVR3 VDDIO OTP PGA PGB PGC PGD 3L TTL OD REFSYS VOUT3V3SW AGND [4] VINLDO3 DFT AND AMUX VPROGOTP VDDIO [2X] DIETEMP SDA OD TTL ENVR5 VIN UVLO SLAVEADDR TTL SCLK VDDIO VDDIO ILIMVR5LS TEMP_ALERTZ VR3 Controller Out range: 0.85v-5v Vout INTEL I2C AND REGFILE EN3V3SW DRVHVR5 ILIMVR3LS PG EN VSET DTMODE FBVR5P VBSTVR5 VREGVR4 VINVR3 ILIMVR3HS EN/ PGOOD LOGIC EN/ PGOOD LOGIC ILIMVR5HS FBVR5N NVDCZ TTL VDDIO PGVR3 OD/PP VDDIO VDDIO OD/PP PGVR5 PGVR2 OD/PP ILIMVR1 FBVR1N PGVR1 DDRID 3L VDDIO VDDIO LVA FBVR4P VR4 Controller V12U/135U/ 1.05U Vout=1.05V1.2V 10A max LDO5V VREF1V25 LDO3V VIN5VSW SW EN5VSW TTL SW TTL EN3V3SW Copyright © 2016, Texas Instruments Incorporated Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 51 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.3 www.ti.com Feature Description 6.3.1 Voltage Regulator Assignment and Powergood Comparator Logic Assignment (External Voltage Regulator or Load Switch) for Skylake and Kabylake Platform For the Skylake and Kabylake Power Map implementation, the five PMIC voltage regulators and LDO1 are assigned with the low -voltage rails merged or split according to the configuration. For the Volume (merged low voltage rails) configuration six external load switches are controlled and monitored by using six powergood comparator logic blocs. Table 6-1. Voltage Regulator and Powergood Comparator Logic Assignment for Skylake and Kabylake Platforms SWITCHING FREQUENCY, Fsw NVDC# = 1 / 0 LPM VOLTAGE, Vout DEFAULT POWER GOOD OUTPUT SETTING, (PGVRx or PGx is PP or OD) TPS650830 Skylake and Kabylake PLATFORM POWER SYSTEM VOLTAGE RAIL VOLUME (Merged Low Voltage Rails) OUTPUT VOLTAGE, Vout DEFAULT, or COMPARATOR INPUT VR1 V1.00A / V0.85A 1.00 V 500 kHz / 800 kHz LPM = 1.00 V PP VR2 V1.8A 1.8 V 2 MHz / 2 MHz LPM = 1.8 V PP LPM = 3.3 V PP VR3 V3.3A_DSW 3.3 V 800 kHz / 800 kHz VR4 V1.2U 1.2 V,1.35 V,1.1 V 500 kHz / 800 kHz LPM = 1.2 V,1.35 V,1.1 V OD VR5 V5A_DS3 5V 800 kHz / 800 kHz LPM = 5.0 V PP LDO1 V0.6Dx 0.6 V, 0.675 V, 0.55 V - LPM = DDR_VTT_C TRL = Off NA External VR_a none - - - NA External VR_b none - - - NA Powergood Comparator Logic a V3.3A_PCH Enable/Sense External Load Switch 3.3 V, Comparator Analog Input – – PP Powergood Comparator Logic b V1.8U_2.5U Enable/Sense External Load Switch 1.8 V, Comparator Analog Input – – PP Powergood Comparator Logic c Generic Comparator - – – -- Powergood Comparator Logic d VCCIO Enable/Sense External Load Switch 1.00 V, Comparator Analog Input – – PP Powergood Comparator Logic e V3.3S Sense External Load Switch 3.3 V, Comparator Analog Input – – PP Powergood Comparator Logic f V1.8S Sense External Load Switch 1.8 V, Comparator Analog Input – – PP Powergood Comparator Logic g V1.0S Sense External Load Switch 1.00 V, Comparator Analog Input – – OD 52 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com 6.3.2 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Generic Powergood Window Comparator with Open-Drain Output The generic powergood comparator monitors the output voltage to ensure it is within ±10% of the nominal target voltage there is a 30-µs deglitch on both rising and falling edges of all comparators (converter, controller, comparators). The open-drain output requires an external pull-up resistor - typically in the 100kΩ range. Open-Drain outputs can be combined to create an "AND" logic function. GENERIC POWERGOOD COMPARATOR LOGIC DIGITAL FOR EXTERNAL VR or LOAD SW ENABLE QUALIFIED_ ENABLE OD/ PP ANALOG COMP_PG_ENB Logic A 0 Comp 1 Comp_ Mode INPUT En Ref ANA_ PGOOD ANA_ PGOODL From Digital Type 0 1 0 DIG_ PGOOD 1 PGOOD Deglitch 1 0 Logic B OD / PP COMP_PG_ Mode Copyright © 2016, Texas Instruments Incorporated Figure 6-1. Generic Powergood Window Comparator with Open-Drain Output Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 53 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.3.3 www.ti.com Powergood Window Comparator All the powergood comparators (converter, controller, comparators) can be configured for either OpenDrain outputs or Push-Pull outputs. All the powergood comparators (converter, controller, comparators) in analog configuration monitors the output voltage to ensure it is within ±10% of the nominal target voltage. A 30-µs deglitch exists on the output of all the powergood comparators (converter, controller, comparators). The open-drain output requires an external pull-up resistor - typically in the 100-kΩ range. Open-Drain outputs can be combined to create an "AND" logic function. The push-pull output internally pulls up to VDDIO pin rail, or other noted input rail. Care should be taken to minimize series impedance on the PCB and providing adequate bulk and decoupling capacitance for the load switch rails. The Intel Skylake and Kabylake specification is ±5% at each rail, including those provided by load switches, therefore the load switch rails are still protected for ±10% powergood, as required by Intel Skylake and Kabylake specification. ENABLE 1.10*VREF + - ENA + - VSENSE 0.90*VREF PWRGD 30us deglitch ENA + - + - N U T 1.10*VREF 1.08*VREF 1.05*VREF VO VOUT Copyright © 2016, Texas Instruments Incorporated VREF 0.95*VREF 0.92*VREF 0.90*VREF 30us PWRGD 30us 30us Good 30us Good time Figure 6-2. Powergood Window Comparator with Open-Drain Output 54 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 VDDIO ENABLE 1.10*VREF + - ENA VSENSE 0.90*VREF P + - PWRGD 30us deglitch ENA + - + - N U T 1.10*VREF 1.08*VREF 1.05*VREF VO VOUT Copyright © 2016, Texas Instruments Incorporated VREF 0.95*VREF 0.92*VREF 0.90*VREF 30us PWRGD 30us 30us Good 30us Good time Figure 6-3. Powergood Window Comparator with Push-Pull Output 6.3.4 3.3-V LDO and 3V3SW Load Switch The LDO3V powers up when Vin_LDO3V pin goes above the UVLO3V threshold. The LDO3V powers the internal digital blocks and analog blocks of the PMIC. It is also used as the positive rail of the powergood comparator and level-shifter outputs. The 3V3 load switch is optional to connect or disconnect the VOUT3V3SW output to a load. The load switch is enabled by the EN3V3SW pin. Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 55 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com LDO3V VIN VDC VLDO3 LDO3V AGND AGND EN3V3SW EC N VOUT3V3SW VOUT3V3SW AGND Copyright © 2016, Texas Instruments Incorporated Figure 6-4. LDO3V and 3V3SW Load Switch 6.3.5 5-V LDO and 5VSW Load Switch The LDO5V powers up when Vin pin goes above the UVLO5V threshold. The LDO5V powers the gate drives for all the five VRs of the PMIC. The 5-V load switch is used to switch the gate drive source from the internal LDO5V LDO to the 3.3-V PWM VR output as soon as the 3.3-V VR powergood signal indicates it is good. This significantly improves the efficiency of the VRs whose effect is more significant at lower VR load current, and VR input voltage. The load switch is enabled by the EN5VSW pin. Connect the V5A_PG signal to the EN5VSW pin. When the EN5VSW pin is high, the LDO5V internal reference drops to 4.5 V to ensure the 5-V VR drives all the gate drive current, but also ensures the gate drive never falls below 4.5 V. When EN5VSW is low, the LDO resumes to 5-V internal reference and the load switch is turned off to disconnect the 5-V VR. VDC PG_V5ADS3 V5ADS3 EN5VSW VIN5VSW VREGVR1 VREGVR2 VDC LDO5V VIN VLDO5 LDO5V VREGVR4 Copyright © 2016, Texas Instruments Incorporated Figure 6-5. 5-V LDO and 5VSW Load Switch 56 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com 6.3.6 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 RTC Selector and 3.1-V LDO The RTC selector is used to select between the coincell backup battery or the internal 3.3-V LDO to power the 3P3A_RTC output rail for the RTC domain rail. If the Vin is below the UVLo5V threshold, the coincell battery is selected. If the Vin is greater than the UVLO5V, then the internal 3.1-V LDO is selected. The backup battery selector logic has a very low current draw when battery is selected to extend the charge life of the backup battery. This rail allows keeping the RTC registers' data even when the adapter and main battery is removed from the system. If the coincell voltage falls below the minimum threshold, the RTC registers will be reset to the default values. The 3.1-V LDO is at 3.1 V to ensure the PCH voltage is always below 3.2 V maximum to protect the PCH. 1kW VBATTBKUP VBATTBKUP Coincell Battery UVLO 3.1V LDO VDC V3P3A_RTC VIN LDO5V LDO3P1V V3P3A_RTC RTC DIG Copyright © 2016, Texas Instruments Incorporated Figure 6-6. RTC Selector and 3.1-V LDO 6.3.7 Power Path Comparators The Power Path comparators are high voltage comparators rated at 28 V both input and output that are independent of the rest of the PMIC. These can be used even when the PMIC is powered down, as long as the VINPP pin is above the UVLO5V threshold. Connect a resistor divider from the source to set the 1.25-V trigger threshold. These comparators can be used to detect adapter, and up to two batteries. An open-drain pin can detect the status, and a status register detects the status, that can issue an interrupt to the EC. The high voltage rated outputs can be used to turn on external P-channel power MOSFETs to control the power source path. A diode "OR" connection from all the power sources used is recommended to ensure the VINPP is up when a source is available. If these comparators are not used tie the VINPP pin to VIN and VIN_LDO3. Do not ground the VINPP pin when the VIN pin is powered up. These comparators can also be used a general purpose comparators. Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 57 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com ADAPTOR ACIN BATTERY1 VINPP VINPP ADAPTOR BATTERY2 FET FET POWER PATH REFSYS BAT1 + - VCCPP ADAPTOR VBATA NVDC CHARGER FET FET FET FET + BAT2 ACSWONZ ACIN VCCPP ACIN 1.25V + - ACSWONZ - + N LOWBATTDET[3] Address 0x6A PWRSRCINT[4] Address 0x04 BATTERY1 BAT1SWONZ BAT1 VCCPP BAT1 1.25V + - BAT1SWONZ + N LOWBATTDET[4] Address 0x6A PWRSRCINT[5] Address 0x04 BATTERY2 BAT2SWONZ BAT2 VCCPP BAT2 1.25V + - BAT2SWONZ + N LOWBATTDET[5] Address 0x6A PWRSRCINT[6] Address 0x04 Copyright © 2016, Texas Instruments Incorporated Figure 6-7. Power Path Comparators 6.3.8 UVLO Comparators The UVLO comparators are high voltage comparators rated at 28-V input are powered by the VIN pin for LDO5V and 1.25-V LDO, and the VIN_LDO3V pin for th LDO3V. The VDCSNS input is also a high voltage input pin to detect if VBATA is above a programmable voltage. The Vin and VIN_LDO3 pin are tied directly to VBATA, while the VDCSNS pin requires a resistor divider to set the proper detection gain. 58 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 VIN VBATA VINLDO3 PMIC REFSYS 1.25V LDO3 LDO3 VINLDO3 VBATA UVLO 3.75V Internal + - + - UVLO_3V LDO3 VIN VBATA LDO5 UVLO 5.3V Internal + - + - UVLO_5V_Main VBATA 4R VDCSNS R LDO3 VDCSNS VDLMTCRT[3:0] Address 0x51 1.08V, 1.10V, 1.12V (default), 1.14V, 1.16V 1.18V 1.20V + - + - Internal PMUINT[2] Address 0x05 Copyright © 2016, Texas Instruments Incorporated Figure 6-8. UVLO Comparators Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 59 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.3.9 www.ti.com Temperature Comparator The temperature comparator is used to detect either several PTC thermisters stacked in series string, or a single NTC thermister. The PTC thermisters allow an inexpensive overtemperature detection of any fault throughout several points on the motherboard with each PTC thermister selected to have its own temperature threshold trigger point. An internal current source can be enabled to drive the PTC thermisters to minimize noise sensitivity. The current source can be disabled to drive with a voltage source such as the LDO3V to allow a tighter accuracy. Only a single NTC thermister can be detected at a time, but the NTC allows tracking several temperature profiles. This comparator can also be used as a general purpose comparator. LDO3V 10uA TRIPZ TRIPZ LDO3 VCOMP VCOMP R 1.25V + - + - N PTC1 PTC2 PTCn LDO3V OFF LDO3V R1 TRIPZ LDO3 VCOMP VCOMP R2 + - 1.25V TRIPZ + N PTC1 PTC2 PTCn LDO3V OFF LDO3V R1 TRIPZ LDO3 VCOMP VCOMP NTC R2 1.25V + - TRIPZ + N Copyright © 2016, Texas Instruments Incorporated Figure 6-9. Temperature Comparator 60 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.3.10 Low Power Mode (LPM) / Connected Standby / Instant Go of VRs All the Voltage regulators from the PMIC can be programmed by register to change the voltage in active mode, or to change to a lower voltage or decay in the low power mode. This can be used to save system power and extend battery life. And such capability is useful to meet the Connected Standby and Instant Go specifications. The STANDBYZ pin triggers low power mode (LPM) when low. The STANDBYZ triggers active mode (not in LPM) when high. Connect the SLP_S0# signal from the PCH to the STANDBYZ pin to trigger the low power mode, LPM. The default settings can be changed by the user with the I2C register at any time. When SLP_S0# is Lo, the device is in Connected Standby Mode, which is now called Instant GO mode. SLP_S0# SLP_S0# (STANDBYZ) Vout Normal Mode STANDBYZ All VRs * Select Vout * Control PWM Low Power Mode Optimized Ramp-down FLT OFF: VIN > UVLO Startup: LDO3V, LDO5V and VREF1V25 ramp up, OTP loads from default (backup battery saves RTC register values) VIN > UVLO VIN < UVLO Backup Battery or G3: All rails off, RTC = backup battery, RTC registers saved (VIN < UVLO) && (no backup battery) (VIN < UVLO) && (backup battery present) LDO3V and LDO5V power goods = HIGH Exit Emergency Shutdown: Emergency Shutdown: ACOK transitions from LOW to HIGH or PWRBTNIN falling edge detected DPWROK transitions LOW, All rails turn off with discharge resister ramp down Ready: Reference LDOs are on, I2C is active, Waiting for EN signals Emergency Shutdown Initiated Emergency Shutdown Initiated ENVR3 = LOW ENVR3 = HIGH DSx: VR3 (V3.3A_DSW) and VR2 (V1.8A) turn on. DPWROK asserted HIGH STANDBY: SLP_SUS# = LOW or EC_SLP_DS4 or EC_DS4 = 1 SLP_SUS# = HIGH, At ENE and ENVR5 DVS and Decay on programmed rails STANDBY# = HIGH (SLP_S0#) S5/S4: STANDBY# = LOW (SLP_S0#) VR5 (V5A_DS3), LS-PGE (V3.3A_PCH), VR1 (V0.85A & V1.00A) turn on. DS3_VREN, RSMRST#_PWRGD and EC_RST# asserted HIGH STANDBY# = HIGH (SLP_S0#) STANDBY# = LOW (SLP_S0#) LDO1 ON: LDO1 (VTT) turns on DDR_VTT_CTRL = LOW SLP_S4# = HIGH, At ENB and ENVR4 S0: SLP_S4# = LOW S3: VR4 (VDDQ) and LS-PGB (V1.8U) turn on. SLP_S3# = LOW LS-PGD (VCCIO) turns on. ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK_SYS_PWROK asserted HIGH DDR_VTT_CTRL = HIGH (SLP_S3# = HIGH, at ENF and ENG) && (valid 3.3V, 1.8V, and 1.0V detected on VSE, VSF, and VSG) Figure 6-16. Sequence of Function Modes - Assuming the TPS650830 Application Configuration Connections 70 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com 6.4.1 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 OFF State - No VIN and No Backup Battery If the VIN and the VBATTBKUP battery are both lower than their respective UVLOs then, the device will be in the OFF state. In this state the device will not be able to turn on or enable any VRs or discrete load switches / regulators. The clock and I2C are not active in this state. In the OFF state, the power path switch comparators, ACIN, BAT1, and BAT2 are the only block available for use. In order to use these comparators the VINPP must be supplied with the highest of the 3 input voltages from AC, BAT1, and BAT2. In all other states the VINPP must be supplied from the same source as VIN. 6.4.2 Startup The device enters STARTUP once the VIN > UVLO. During STARTUP LDO3V, LDO5V, and VREF1V25 ramp up. Once both LDO3V and LDO5V reach their nominal voltage and their powergoods assert HIGH, the OTP loads into the I2C registers. After the LDO5V_PG asserts HIGH, the RTC LDO is turned on and the V3.3A_RTC is regulated to 3.1 V powered from the LDO5V. Once the OTP is loaded and the RTC is regulated to 3.1 V the device enters READY state. 6.4.3 Ready State The device is considered to be in the READY state once, all of the internal supplies and RTC are regulated and the OTP is loaded into the registers. In this state the device is ready for enable commands. The comparators, level shifters and all other blocks are available for use. 6.4.4 S5/S4 State The S5/S4 states are entered when the V3.3A_DSW, V1.8A, V5A_DS3, V3.3A_PCH, V0.85A, and V1.00A are all enabled and regulating with valid powergoods. In this state the RSMRST#_PWRGD will be asserted HIGH. 6.4.5 S3 State To enter S3 state the SLP_S4# signal must be asserted HIGH. Upon SLP_S4# assertion the VDDQ (VR4), and V1.8U rails are turned on. 6.4.6 S0 State To enter S0 state the SLP_S3# signal must be asserted HIGH in addition to valid 3.3-V, 1.8-V, and 1.0-V signals on VSE, VSF, and VSG pins. Upon PGG = 1 and PGVR4 = 1 the VCCIO and rail is turned on and the device transitions to S0 state. ALL_SYS_PWRGD asserts HIGH in this state. 6.4.7 Standby Standby is entered when the STANDBYZ pin transitions from HIGH to LOW provided that ALL_SYS_PWRGD is HIGH. During the STANDBY state the device will DVS and/or decay the VRs that are programmed to DVS or decay from the I2C register definitions, (registers x30 - x38). 6.4.8 DSx State The DSx state is entered from STARTUP by the enabling of V3.3A_DSW. From the S5/S4 states it can be entered by either pulling the SLP_SUS# signal LOW or writing to VREN, EC_SLP_S4 = EC_DS4 = 1. In this state, the V5A_DS3 and V1.8A may be turned off. 6.4.9 Emergency Shutdown Emergency Shutdown is a protection feature for the system loads. It reduces the risk of reverse bias in the processor or other devices from once rail to another. Once Emergency Shutdown is initiated the DPWROK pin is pulled LOW, discharge resistors are enabled for all rails, and all rails are disabled at the same time. The PMIC remains in Emergency Shutdown until any of the follow occurs: Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 71 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 • • • www.ti.com PWRBTNIN falling edge detected ACOK transitions from LOW to HIGH VIN < UVLO Emergency Shutdown is initiated when: • VR Fault detected - Read RESETIRQ1 to determine if VR fault caused shutdown. • Hardware force shutdown • Software force shutdown • Die Thermal Fault - Read RESETIRQ2 to determine if thermal fault caused shutdown. • PWRBTN held longer than defined time by FLT[5:0] - Read RESETIRQ1 to determine if push button caused shutdown. • VIN < UVLO - Read IRQLVL1 bit 2 to determine if VIN < UVLO caused shutdown. 6.4.10 Backup Battery / G3 - No VIN G3 is an Intel defined state where the VIN < UVLO to the device but, a valid backup battery is present on VBATTBKUP pin. In this state, the backup battery is passed to the RTC output and the RTC domain I2C register values are saved. Once the VIN > UVLO these register retain their value and can be read once I2C is ready. In this state, all VRs and internal LDOs are off and I2C access is not available. 6.5 Programming I2C - Interface 6.5.1 I2C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I2C-Bus Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The TPS650830 works as a slave and supports the following data transfer modes, as defined in the I2CBus Specification: standard mode (100 kbps), fast mode (400 kbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents are loaded when voltage is applied to TPS650830 higher than the undervoltage lockout threshold. The I2C interface is running from an internal oscillator that is automatically enabled when there is an access to the interface. The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as F/S-mode in this document. The TPS650830 supports 7-bit addressing; 10-bit addressing and general call address are not supported. The default device address is defined by the status of the SLAVEADDR pin. 3 different slave addresses are possible, 0x30 (SLAVEADDR 0 V), 0x32 (SLAVEADDR 3.3 V) and 0x34 (SLAVEADDR floating). All registers are set to their default value when the supply voltage is below the UVLO threshold. 6.5.1.1 F/S-Mode Protocol The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, see Figure 6-17. All I2C-compatible devices should recognize a start condition. 72 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse, see Figure 618. All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge, see Figure 6-19, by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that the communication link with a slave has been established. The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data from the slave (R/W bit = 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master low to high while the SCL line is high, see communication link with the addressed slave. condition. Upon the receipt of a stop condition, all a start condition followed by a matching address generates a stop condition by pulling the SDA line from Figure 6-17. This releases the bus and stops the All I2C compatible devices must recognize the stop devices know that the bus is released, and they wait for Attempting to read data from register addresses not listed in this section results in FFh being read out. FS I2C operation does not support repeated start Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 73 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.5.1.2 www.ti.com Diagrams of I2C Protocol SDA SCL S P Start Condition Stop Condition Figure 6-17. START and STOP Conditions SDA SCL data line stable; data valid change of data allowed Figure 6-18. Bit Transfer on the I2C-bus Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgement START Condition Figure 6-19. Acknowledge on the I2C-Bus recognize START or REPEATED START condition recognize STOP or REPEATED START condition generate ACKNOWLEDGE signal P SDA MSB acknowledgement signal from slave Sr Address R/W SCL S or Sr 1 2 7 8 9 ACK byte complete, interrupt within slave 1 2 3−8 9 ACK clock line held low while interrupts are serviced START or repeated START condition Sr or P STOP or repeated START condition Figure 6-20. Bus Protocol 74 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 SCL ... SDA A6 A5 A4 ... ... A0 R/W ACK 0 R7 R6 ... R5 R0 ACK 0 D7 D5 ... D6 0 Slave Address Start ... D0 ACK 0 Register Address Data Stop NOTE: SLAVE=This Device Figure 6-21. I2C Interface WRITE to Device in F/S Mode SCL ... SDA A6 .. ... A0 R/W ACK 0 R7 .. ... R0 A6 .. ACK 0 ... A0 R/W ACK 1 0 Start Slave Address Register Address Slave Address D7 D0 ACK 0 Slave Drives the Data Repeated Start NOTE: SLAVE=This Device .. Stop Master Drives ACK and Stop Figure 6-22. I2C Interface READ from Device in F/S Mode 6.6 Register Map Table 6-3. Register Summary Register Address Register Name Domain Short Description x00 VENDORID UVLO Code that indicated a Texas Instruments' PMIC device. x01 REVID UVLO Code to identify device revision and programming revision. x02 IRQLVL1 RTC Top level interrupts x04 PWRSRCINT RTC Input power interrupts x05 PMUINT RTC PMU interrupts x08 RESETIRQ1 RTC Emergency Shutdown interrupts x09 RESETIRQ2 RTC Emergency Shutdown interrupts x0B MPMUINT RTC Mask PMU interrupts x0C MPWRSRCNT RTC Mask input power interrupts x11 RESETIRQ1MASK RTC Mask Emergency Shutdown interrupts x12 RESETIRQ2MASK RTC Mask Emergency Shutdown interrupts x13 IRQLVL1MSK RTC Mask top level interrupt x14 PBCONFIG RTC Power Button configuration x15 PBSTATUS RTC Power Button Status x16 PWRSTAT1 RTC VR Fault Reporting x17 PWRSTAT2 RTC VR Fault Reporting x18 PGMASK1 RTC Mask VR PGs from System Power Good Tree x19 PGMASK2 RTC Mask VR PGs from System Power Good Tree x30 VCCIOCNT UVLO VCCIO (PGD ) Control Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 75 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Table 6-3. Register Summary (continued) 76 Register Address Register Name Domain Short Description x31 V5ADS3CNT UVLO V5A_DS3 (VR5 ) Control x32 V33ADSWCNT UVLO V3.3A_DSW (VR3 ) Control x33 V33APCHCNT UVLO V3.3A_PCH (PGE) Control x34 V18ACNT UVLO V1.8A (VR2 ) Control x35 V18U25UCNT UVLO V1.8U_2.5U (PGB) Control x36 V1P2UCNT UVLO V1.2U / VDDQ (VR4) Control x37 V100ACNT UVLO V1.00A (VR1) Control x38 V08ACNT UVLO V0.85A (VR1 ) Control x3B VRMODECTRL UVLO Force Low Power Mode x3C DISCHCNT1 UVLO Discharge Resistors Settings x3D DISCHCNT2 UVLO Discharge Resistors Settings x3E DISCHCNT3 UVLO Discharge Resistors Settings x3F DISCHCNT4 UVLO Discharge Resistors Settings x40 PWRGDCNT1 UVLO System Level Power Goods x41 VREN UVLO Deep Sleep Enable x42 REGLOCK UVLO Lock for Control Registers, x30 - x38 x43 VRENPINMASK UVLO Mask hardware enable pins x48 RSTCTRL RTC Reset Control x49 SDWNCTRL UVLO Software Force Shutdown x51 VDLMTCRT UVLO VDCSNS Settings x69 ACOKDBDM UVLO ACOK Settings x6A LOWBATTDET UVLO Battery Detection Settings x6F SPWRSRCINT UVLO Input power Statuses xD0 CLKCTRL1 RTC Clock Control xDD COMPA_REF UVLO Comparator A Settings xDE COMPB_REF UVLO Comparator B Settings xDF COMPC_REF UVLO Comparator C Settings xE0 COMPD_REF UVLO Comparator D Settings xE1 COMPE_REF UVLO Comparator E Settings xE2 COMPF_REF UVLO Comparator F Settings xE3 COMPG_REF UVLO Comparator G Settings xE4 COMPH_REF UVLO Comparator H Settings xE5 PWRFAULT_MASK1 UVLO Mask VR Faults from Emergency Shutdown xE6 PWRFAULT_MASK2 UVLO Mask VR Faults from Emergency Shutdown xE7 PGOOD_STAT1 UVLO VR PGs Statuses xE8 PGOOD_STAT2 UVLO VR PGs Statuses xE9 MISC_BITS UVLO Misc. Bits xEA STDY_CTRL RTC VCOMP and Standby Control xEB TEMPCRIT RTC VR Critical Temperature xEC TEMPHOT RTC VR Hot Temperature xED OVERCURRENT RTC VR Overcurrent xEE VREN_PIN_OVR UVLO VR Enable Override with Software Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com 6.6.1 6.6.1.1 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Registers VENDORID Register (address = 0x00) [reset = 00100010] Figure 6-23. VENDORID Register Format B7 VENDORID[7] 0 RW B6 VENDORID[6] 0 RW B5 VENDORID[5] 1 RW B4 VENDORID[4] 0 RW B3 VENDORID[3] 0 RW B2 VENDORID[2] 0 RW B1 VENDORID[1] 1 RW B0 VENDORID[0] 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-4. VENDORID Register Field Descriptions Bit Field Type Reset Description 7:0 VENDORID[7:0] RW 00100010 Vendor ID 6.6.1.2 REVID Register (address = 0x01) [reset = 00000000] Figure 6-24. REVID Register Format B7 DNUM[3] 0 RW B6 DNUM[2] 0 RW B5 DNUM[1] 0 RW B4 DNUM[0] 1 RW B3 OTPREV[3] 0 RW B2 OTPREV[2] 0 RW B1 REVID[1] 0 RW B0 REVID[0] 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-5. REVID Register Field Descriptions Bit Field Type Reset Description 7:4 DNUM[3:0] RW 0000 Major revision ID 1010: A 1011: B 1100: C 1101: D 1110: E 1111: F 3:2 OTPREV[1:0] RW 00 Minor revision ID 0000: 0 0001: 1 0010: 2 0011: 3 0100: 4 0101: 5 0110: 6 0111: 7 1:0 REVID[1:0] RW 00 Minor revision ID 0000: 0 0001: 1 0010: 2 0011: 3 0100: 4 0101: 5 0110: 6 0111: 7 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 77 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.3 www.ti.com IRQLVL1 Register (address = 0x02) [reset = 00000000] Figure 6-25. IRQLVL1 Register Format B7 RESET B6 RESERVED2 B5 PMU 0 RW 0 R 0 RW B4 B3 RESERVED1[1 RESERVED1[0 ] ] 0 0 R R B2 PWRSRC B1 RESERVED B0 PWRBTN 0 RW 0 R 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-6. IRQLVL1 Register Field Descriptions Bit Field Type Reset Description 7 RESET R 0 RESET interrupt 0: Not asserted 1: Asserted 6 RESERVED2 R 0 5 PMU R 0 4:3 78 RESERVED1[1:0] R 00 2 PWRSRC R 0 1 RESERVED R 0 0 PWRBTN RW 0 Power monitor interrupt 0: Not asserted 1: Asserted Power source interrupt 0: Not asserted 1: Asserted Power button interrupt 0: Not asserted 1: Asserted, write '1' to clear Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com 6.6.1.4 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 PWRSRCINT Register (address = 0x04) [reset = 00000000] Figure 6-26. PWRSRCINT Register Format B7 RESERVED1_ PWRSRCINT 0 R B6 LOWBATT2 B5 LOWBATT1 B4 ACOK B3 PMICHOT B2 RESERVED[2] B1 RESERVED[1] B0 RESERVED[0] 0 RW 0 RW 0 RW 0 RW 0 R 0 R 0 R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-7. PWRSRCINT Register Field Descriptions Bit Field Type Reset 7 RESERVED1_PWRSRCINT R 0 6 LOWBATT2 RW 0 Low battery2 interrupt [rising-edge detect threshold = 1.25 V; falling-edge hysteresis = 125 mV] 0: No battery2 detected 1: Battery2 detected 5 LOWBATT1 RW 0 Low battery1 interrupt [rising-edge detect threshold =1.25 V; falling-edge hysteresis = 125 mV] 0: No battery1 detected 1: Battery1 detected 4 ACOK RW 0 AC/DC adapter detection interrupt. [rising-edge detect threshold =1.25 V; falling-edge hysteresis = 125 mV] 0: No adapter detected 1: Adapter detected 3 PMICHOT RW 0 PMIC internal temperature interrupt 0: PMIC temperature normal 1: PMIC temperature hot RESERVED[2:0] R 000 2:0 6.6.1.5 Description PMUINT Register (address = 0x05) [reset = 00000000] Figure 6-27. PMUINT Register Format B7 B6 B5 RESERVED2[2 RESERVED2[1 RESERVED2[0 ] ] ] 0 0 0 R R R B4 PMUACOK 0 RW B3 RESERVED1_ PMUINT 0 R B2 PMUVDC 0 RW B1 RESERVED_P MUINT[1] 0 R B0 RESERVED_P MUINT[0] 0 R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-8. PMUINT Register Field Descriptions Bit Field Type Reset 7:5 RESERVED2[2:0] R 000 4 PMUACOK RW 0 3 RESERVED1_PMUINT R 0 2 PMUVDC RW 0 RESERVED_PMUINT[1:0] R 00 1:0 Description Adapter detection interrupt 0: No Interrupt Pending 1: AC Adapter removed (SACOK H -> L) Power monitor critical supply voltage interrupt 0: Critical supply voltage over threshold limit 1: Critical supply voltage below threshold limit Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 79 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.6 www.ti.com RESETIRQ1 Register (address = 0x08) [reset = 00000000] Figure 6-28. RESETIRQ1 Register Format B7 RESERVED1_ RESETIRQ1[1] 0 R B6 RESERVED1_ RESETIRQ1[0] 0 R B5 FCO B4 VRFAULT B3 RESERVED[3] B2 RESERVED[2] B1 RESERVED[1] B0 RESERVED[0] 0 RW 0 RW 0 R 0 R 0 R 0 R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-9. RESETIRQ1 Register Field Descriptions Bit Field Type Reset 7:6 Description RESERVED1_RESETIRQ1[1:0] R 00 5 FCO RW 0 Power button triggered reset interrupt 0: Power button counter has not forced an emergency reset 1: Power button counter has forced an emergency reset 4 VRFAULT RW 0 Voltage regulator triggered reset interrupt 0: Voltage regulator fault has not triggered an emergency reset 1: Voltage regulator fault has triggered an emergency reset RESERVED[3:0] R 0000 3:0 6.6.1.7 RESETIRQ2 Register (address = 0x09) [reset = 00000000] Figure 6-29. RESETIRQ2 Register Format B7 B6 B5 B4 B3 B2 RESERVED1[5 RESERVED1[4 RESERVED1[3 RESERVED1[2 RESERVED1[1 RESERVED1[0 ] ] ] ] ] ] 0 0 0 0 0 0 R R R R R R B1 CRITTEMP 0 RW B0 RESERVED_R ESETIRQ2 0 R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-10. RESETIRQ2 Register Field Descriptions 80 Bit Field Type Reset 7:2 RESERVED1[5:0] R 000000 1 CRITTEMP RW 0 0 RESERVED_RESETIRQ2 R 0 Description Temperature triggered reset interrupt 0: Critical temperature not reached 1: Critical temperature reached, forcing emergency shutdown Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com 6.6.1.8 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 MPMUINT Register (address = 0x0B) [reset = 00010100] Figure 6-30. MPMUINT Register Format B7 RESERVED2_ MPMUINT[2] 0 R B6 RESERVED2_ MPMUINT[1] 0 R B5 RESERVED2_ MPMUINT[0] 0 R B4 MPMUACOK 1 RW B3 RESERVED1_ MPMUINT 0 R B2 MPMUVDC 1 RW B1 B0 RESERVED_M RESERVED_M PMUINT[1] PMUINT[0] 0 0 R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-11. MPMUINT Register Field Descriptions Bit Field Type Reset 7:5 RESERVED2_MPMUINT[2:0] R 000 4 MPMUACOK RW 1 3 RESERVED1_MPMUINT R 0 2 MPMUVDC RW 1 RESERVED_MPMUINT[1:0] R 00 1:0 6.6.1.9 Description Power monitor critical supply voltage (adapter) mask interrupt 0: Not masked 1: Masked Power monitor critical supply voltage mask interrupt 0: Not masked 1: Masked MPWRSRCINT Register (address = 0x0C) [reset = 01111000] Figure 6-31. MPWRSRCINT Register Format B7 RESERVED1_ MPWRSRCINT B6 MLOWBAT2 B5 MLOWBAT1 B4 MACOK B3 MPMICHOT 0 R 1 RW 1 RW 1 RW 1 RW B2 B1 B0 RESERVED_M RESERVED_M RESERVED_M PWRSRCINT[2 PWRSRCINT[1 PWRSRCINT[0 ] ] ] 0 0 0 R R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-12. MPWRSRCINT Register Field Descriptions Bit Field Type Reset 7 RESERVED1_MPWRSRCINT R 0 6 MLOWBAT2 RW 1 Low battery voltage mask interrupt 0: Not masked 1: Masked 5 MLOWBAT1 RW 1 Low battery voltage mask interrupt 0: Not masked 1: Masked 4 MACOK RW 1 AC/DC adapter detection mask interrupt 0: Not masked 1: Masked 3 MPMICHOT RW 1 PMIC internal temperature mask interrupt 0: Not masked 1: Masked RESERVED_MPWRSRCINT[2:0] R 000 2:0 Description 6.6.1.10 RESETIRQ1MASK Register (address = 0x11) [reset = 00110000] Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 81 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Figure 6-32. RESETIRQ1MASK Register Format B7 RESERVED1_ RESETIRQ1M ASK[1] 0 R B6 RESERVED1_ RESETIRQ1M ASK[0] 0 R B5 MFCO B4 MVRFAULT 1 RW 1 RW B3 B2 B1 B0 RESERVED_R RESERVED_R RESERVED_R RESERVED_R ESETIRQ1MAS ESETIRQ1MAS ESETIRQ1MAS ESETIRQ1MAS K[3] K[2] K[1] K[0] 0 0 0 0 R R R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-13. RESETIRQ1MASK Register Field Descriptions Bit Field 7:6 RESERVED1_RESETIRQ1MASK[1: R 0] 00 5 MFCO RW 1 Power button triggered reset mask interrupt 0: Not masked 1: Masked 4 MVRFAULT RW 1 Voltage regulator triggered reset mask interrupt 0: Not masked 1: Masked 3:0 Type RESERVED_RESETIRQ1MASK[3:0 R ] Reset Description 0000 6.6.1.11 RESETIRQ2MASK Register (address = 0x12) [reset = 00000010] Figure 6-33. RESETIRQ2MASK Register Format B7 RESERVED1_ RESETIRQ2M ASK[5] 0 R B6 RESERVED1_ RESETIRQ2M ASK[4] 0 R B5 RESERVED1_ RESETIRQ2M ASK[3] 0 R B4 RESERVED1_ RESETIRQ2M ASK[2] 0 R B3 RESERVED1_ RESETIRQ2M ASK[1] 0 R B2 RESERVED1_ RESETIRQ2M ASK[0] 0 R B1 MCRITTEMP 1 RW B0 RESERVED_R ESETIRQ2MAS K 0 R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-14. RESETIRQ2MASK Register Field Descriptions 82 Bit Field Type Reset 7:2 RESERVED1_RESETIRQ2MASK[5: R 0] 000000 1 MCRITTEMP RW 1 0 RESERVED_RESETIRQ2 MASK R 0 Description Temperature triggered reset mask interrupt 0: Not masked 1: Masked Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.12 IRQLVL1msK Register (address = 0x13) [reset = 10100101] Figure 6-34. IRQLVL1msK Register Format B7 MRESET 1 RW B6 RESERVED2_I RQLVL1msK 0 R B5 MPMU B4 B3 RESERVED1_I RESERVED1_I RQLVL1msK[1] RQLVL1msK[0] 0 0 R R 1 RW B2 MPWRSRC 1 RW B1 RESERVED_IR QLVL1msK 0 R B0 MPWRBTN 1 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-15. IRQLVL1msK Register Field Descriptions Bit Field Type Reset Description 7 MRESET RW 1 RESET mask interrupt 0: Not masked 1: Masked 6 RESERVED2_IRQLVL1msK R 0 5 MPMU RW 1 4:3 RESERVED1_IRQLVL1msK[1:0] R 00 2 MPWRSRC RW 1 1 RESERVED_IRQLVL1msK R 0 0 MPWRBTN RW 1 Power monitor mask interrupt 0: Not masked 1: Masked Power source mask interrupt 0: Not masked 1: Masked Power button mask interrupt 0: Not masked 1: Masked Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 83 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.13 PBCONFIG Register (address = 0x14) [reset = 00011111] Figure 6-35. PBCONFIG Register Format B7 PWRBTNDBN 0 RW B6 CLRHT 0 RW B5 FLT[5] 0 RW B4 FLT[4] 1 RW B3 FLT[3] 1 RW B2 FLT[2] 1 RW B1 FLT[1] 1 RW B0 FLT[0] 1 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-16. PBCONFIG Register Field Descriptions Bit 84 Field Type Reset Description 7 PWRBTNDBN RW 0 Power button debounce 0: 30 ms 1: 0 ms (no debounce) 6 CLRHT RW 0 Reset of power button timer logic 0: No action 1: Reset of HT, bit is self clearing 5:0 FLT[5:0] RW 011111 Time that the button must be held to force an emergency reset 000000: 0 s 000001: 1 s 000010: 2 s 000011: 3 s 000100: 4 s 000101: 5 s 000110: 6 s 000111: 7 s 001000: 8 s 001001: 9 s 001010: 10 s .. 011111: 31 s ... 111100: 60 s 111101: 61 s 111110: 62 s 111111: 63 s Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.14 PBSTATUS Register (address = 0x15) [reset = 00000000] Figure 6-36. PBSTATUS Register Format B7 RESERVED_P BSTATUS 0 R B6 LVL B5 HT[5] B4 HT[4] B3 HT[3] B2 HT[2] B1 HT[1] B0 HT[0] 0 R 0 R 0 R 0 R 0 R 0 R 0 R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-17. PBSTATUS Register Field Descriptions Bit Field Type Reset 7 RESERVED_PBSTATUS R 0 6 LVL R 0 Power button present level 0: Power button held 1: Power button released HT[5:0] R 000000 Time that the button has been held 00000: Disabled 00001: Disabled 000010: 2 s 000011: 3 s 000100: 4 s 000101: 5 s 000110: 6 s 000111: 7 s 001000: 8 s 001001: 9 s 001010: 10 s .. ... 111100: 60 s 111101: 61 s 111110: 62 s 111111: 63 s 5:0 Description Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 85 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.15 PWRSTAT1 Register (address = 0x16) [reset = 00000000] Figure 6-37. PWRSTAT1 Register Format B7 B6 VCCIO_FAULT V5A_DS3_FAU LT 0 0 RW RW B5 V33A_DSW_F AULT 0 RW B4 V33A_PCH_FA ULT 0 RW B3 V18A_FAULT 0 RW B2 V18U_25U_FA ULT 0 RW B1 V12U_FAULT B0 V06DX_FAULT 0 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-18. PWRSTAT1 Register Field Descriptions Bit 86 Field Type Reset Description 7 VCCIO_FAULT RW 0 These bits indicate that the VR has lost regulation 0: Clears register 1: Indicates power fault 6 V5A_DS3_FAULT RW 0 These bits indicate that the VR has lost regulation 0: Clears register 1: Indicates power fault 5 V33A_DSW_FAULT RW 0 These bits indicate that the VR has lost regulation 0: Clears register 1: Indicates power fault 4 V33A_PCH_FAULT RW 0 These bits indicate that the VR has lost regulation 0: Clears register 1: Indicates power fault 3 V18A_FAULT RW 0 These bits indicate that the VR has lost regulation 0: Clears register 1: Indicates power fault 2 V18U_25U_FAULT RW 0 These bits indicate that the VR has lost regulation 0: Clears register 1: Indicates power fault 1 V12U_FAULT RW 0 These bits indicate that the VR has lost regulation 0: Clears register 1: Indicates power fault 0 V06DX_FAULT RW 0 These bits indicate that the VR has lost regulation 0: Clears register 1: Indicates power fault Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.16 PWRSTAT2 Register (address = 0x17) [reset = 00000000] Figure 6-38. PWRSTAT2 Register Format B7 RESERVED[5] 0 R B6 RESERVED[4] 0 R B5 RESERVED[3] 0 R B4 RESERVED[2] 0 R B3 RESERVED[1] 0 R B2 RESERVED[0] 0 R B1 V100A_FAULT 0 RW B0 V085A_FAULT 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-19. PWRSTAT2 Register Field Descriptions Bit Field Type Reset 7:2 RESERVED[5:0] R 000000 Description 1 V100A_FAULT RW 0 These bits indicate that the VR has lost regulation 0: Clears register 1: Indicates power fault 0 V085A_FAULT RW 0 These bits indicate that the VR has lost regulation 0: Clears register 1: Indicates power fault Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 87 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.17 PGMASK1 Register (address = 0x18) [reset = 00000000] Figure 6-39. PGMASK1 Register Format B7 MVCCIOPG 0 RW B6 MV085APG 0 RW B5 MV100APG 0 RW B4 MV18APG 0 RW B3 MV33APCHPG 0 RW B2 MV5ADS3PG 0 RW B1 MV33ADSWPG 0 RW B0 MV100SPG 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-20. PGMASK1 Register Field Descriptions Bit 88 Field Type Reset Description 7 MVCCIOPG RW 0 VCCIO PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) 6 MV085APG RW 0 V0.85A PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) 5 MV100APG RW 0 V100A PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) 4 MV18APG RW 0 V1.8A PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) 3 MV33APCHPG RW 0 V3.3A PCH PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) 2 MV5ADS3PG RW 0 V5A DS3 PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) 1 MV33ADSWPG RW 0 V3.3A DSW PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) 0 MV100SPG RW 0 V100S PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.18 PGMASK2 Register (address = 0x19) [reset = 00000000] Figure 6-40. PGMASK2 Register Format B7 RESERVED_P GMASK2[3] 0 R B6 RESERVED_P GMASK2[2] 0 R B5 RESERVED_P GMASK2[1] 0 R B4 RESERVED_P GMASK2[0] 0 R B3 V18U25UPG B2 MV12UPG B1 MV33SPG B0 MV18SPG 0 RW 0 RW 0 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-21. PGMASK2 Register Field Descriptions Bit Field Type Reset 7:4 Description RESERVED_PGMASK2[3:0] R 0000 3 V18U25UPG RW 0 V1.8_2.5U PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) 2 MV12UPG RW 0 V1.2U PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) 1 MV33SPG RW 0 V3.3S PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) 0 MV18SPG RW 0 V1.8S PG is part of the power good tree 0: Power Good function is enabled 1: Power Good function is masked and set to 1 (not part of the Power Good tree) Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 89 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.19 VCCIOCNT Register (address = 0x30) [reset = 00001010] Figure 6-41. VCCIOCNT Register Format B7 RESERVED_V CCIOCNT 0 R B6 CSDECAYEN B5 VCCIOVSEL[1] 0 RW 0 RW B4 B3 B2 B1 VCCIOVSEL[0] AOACCNTVCC AOACCNTVCC CTLVVCCIO[1] IO[1] IO[0] 0 1 0 1 RW RW RW RW B0 CTLVVCCIO[0] 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-22. VCCIOCNT Register Field Descriptions Bit 90 Field Type Reset Description 7 RESERVED_VCCIOCNT R 0 6 CSDECAYEN RW 0 Enables VCCIO decay when SLP_S0# is asserted. [wait 2us after removing FPWM, before entering DECAY mode. Direct FPWM to DECAY by SLP0Z may cause ringing. Decay exit time within 100us not guaranteed for Vout > 1V.] 0: VCCIO stays at voltage set by VCCIOVSEL independent of state of SLP_S0# 1: VCCIO decays to 0V, PGOOD is maintained when SLP_S0# is asserted (low) 5:4 VCCIOVSEL[1:0] RW 00 Output voltage select 00: 0.975V 01: 0.950V 10: 0.875V 11: 0.850V 3:2 AOACCNTVCCIO[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) changes bits D[1:0] on exit 00: No change in bits D[1:0] - fast change mode disabled 01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM) 10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM) 11: Bits D[1:0] set to 11, forced PWM operation 1:0 CTLVVCCIO[1:0] RW 10 Mode control (V4) 00: Converter disabled 01: Auto Mode, (automatic transition from PFM to PWM) 10: Auto Mode, (automatic transition from PFM to PWM) 11: Forced PWM operation Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.20 V5ADS3CNT Register (address = 0x31) [reset = 00101010] Figure 6-42. V5ADS3CNT Register Format B7 B6 V5ADS3LVSEL V5ADS3LVSEL [1] [0] 0 0 RW RW B5 V5ADS3VSEL[ 1] 1 RW B4 V5ADS3VSEL[ 0] 0 RW B3 AOACCNTV5A DS3[1] 1 RW B2 AOACCNTV5A DS3[0] 0 RW B1 CTLV5ADS3[1] B0 CTLV5ADS3[0] 1 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-23. V5ADS3CNT Register Field Descriptions Bit Field Type Reset Description 7:6 V5ADS3LVSEL[1:0] RW 00 V5ADS3 low power mode output voltage set point - set at assertion of SLP_S0# 00: Disabled, voltage stays at value set by V5ADS3VSEL[1:0] 01: Vnom - 4% 10: Vnom - 3% 11: Vnom - 2% 5:4 V5ADS3VSEL[1:0] RW 10 Output voltage select 00: Vnom + 3% 01: Vnom + 2% 10: Vnom 11: Vnom - 2% 3:2 AOACCNTV5ADS3[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) changes bits D[1:0] on exit 00: No change in bits D[1:0] - fast change mode disabled 01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM) 10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM) 11: Bits D[1:0] set to 11, forced PWM operation 1:0 CTLV5ADS3[1:0] RW 10 Mode control (V5) 00: Converter disabled 01: Auto Mode, (automatic transition from PFM to PWM) 10: Auto Mode, (automatic transition from PFM to PWM) 11: Forced PWM operation Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 91 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.21 V33ADSWCNT Register (address = 0x32) [reset = 00101010] Figure 6-43. V33ADSWCNT Register Format B7 V33ADSWLVS EL[1] 0 RW B6 V33ADSWLVS EL[0] 0 RW B5 V33ADSWVSE L[1] 1 RW B4 V33ADSWVSE L[0] 0 RW B3 AOACCNTV33 ADSW[1] 1 RW B2 AOACCNTV33 ADSW[0] 0 RW B1 B0 CTLV33ADSW[ CTLV33ADSW[ 1] 0] 1 0 RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-24. V33ADSWCNT Register Field Descriptions 92 Bit Field Type Reset Description 7:6 V33ADSWLVSEL[1:0] RW 00 V33A_DSW low power mode output voltage set point - set at assertion of SLP_S0# 00: Disabled, voltage stays at value set by V33ADSWVSEL[1:0] 01: Vnom - 4% 10: Vnom - 3% 11: Vnom - 2% 5:4 V33ADSWVSEL[1:0] RW 10 Output voltage select 00: Vnom + 3% 01: Vnom + 2% 10: Vnom 11: Vnom - 2% 3:2 AOACCNTV33ADSW[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) changes bits D[1:0] on exit 00: No change in bits D[1:0] - fast change mode disabled 01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM) 10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM) 11: Bits D[1:0] set to 11, forced PWM operation 1:0 CTLV33ADSW[1:0] RW 10 Mode control (V6) 00: Converter disabled 01: Auto Mode, (automatic transition from PFM to PWM) 10: Auto Mode, (automatic transition from PFM to PWM) 11: Forced PWM operation Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.22 V33APCHCNT Register (address = 0x33) [reset = 00001010] Figure 6-44. V33APCHCNT Register Format B7 B6 B5 B4 RESERVED_V RESERVED_V RESERVED_V RESERVED_V 33APCHCNT[3] 33APCHCNT[2] 33APCHCNT[1] 33APCHCNT[0] 0 0 0 0 RW RW RW RW B3 AOACCNTV33 APCH[1] 1 RW B2 AOACCNTV33 APCH[0] 0 RW B1 CTLV33APCH[ 1] 1 RW B0 CTLV33APCH[ 0] 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-25. V33APCHCNT Register Field Descriptions Bit Field Type Reset Description 7:4 RESERVED_V33APCHCNT[3:0] RW 0000 3:2 AOACCNTV33APCH[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) changes bits D[1:0] on exit 00: No change in bits D[1:0] - fast change mode disabled 01: Bits D[1:0] set to 01 10: Bits D[1:0] set to 10 11: Bits D[1:0] set to 11 1:0 CTLV33APCH[1:0] RW 10 Mode control (V7) 00: Disabled 01: Enabled 10: Enabled 11: Enabled Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 93 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.23 V18ACNT Register (address = 0x34) [reset = 00101010] Figure 6-45. V18ACNT Register Format B7 V18ALVSEL[1] B6 V18ALVSEL[0] B5 V18AVSEL[1] B4 V18AVSEL[0] 0 RW 0 RW 1 RW 0 RW B3 AOACCNTV18 A[1] 1 RW B2 AOACCNTV18 A[0] 0 RW B1 CTLV18A[1] B0 CTLV18A[0] 1 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-26. V18ACNT Register Field Descriptions 94 Bit Field Type Reset Description 7:6 V18ALVSEL[1:0] RW 00 V18A low power mode output voltage set point - set at assertion of SLP_S0# 00: Disabled, voltage stays at value set by V18AVSEL[1:0] 01: Vnom - 4% 10: Vnom - 3% 11: Vnom - 2% 5:4 V18AVSEL[1:0] RW 10 Output voltage select 00: Vnom + 3% 01: Vnom + 2% 10: Vnom 11: Vnom - 2% 3:2 AOACCNTV18A[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) changes bits D[1:0] on exit 00: No change in bits D[1:0] - fast change mode disabled 01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM) 10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM) 11: Bits D[1:0] set to 11, forced PWM operation 1:0 CTLV18A[1:0] RW 10 Mode control (V8) 00: Converter disabled 01: Auto Mode, (automatic transition from PFM to PWM) 10: Auto Mode, (automatic transition from PFM to PWM) 11: Forced PWM operation Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.24 V18U25UCNT Register (address = 0x35) [reset = 00001010] Figure 6-46. V18U25UCNT Register Format B7 RESERVED_V 18U25UCNT[3] 0 R B6 RESERVED_V 18U25UCNT[2] 0 R B5 RESERVED_V 18U25UCNT[1] 0 R B4 RESERVED_V 18U25UCNT[0] 0 R B3 AOACCNTV18 U25U[1] 1 RW B2 AOACCNTV18 U25U[0] 0 RW B1 B0 CTLV18U25U[1 CTLV18U25U[0 ] ] 1 0 RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-27. V18U25UCNT Register Field Descriptions Bit Field Type Reset Description 7:4 RESERVED_V18U25UCNT[3:0] R 0000 3:2 AOACCNTV18U25U[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) changes bits D[1:0] on exit 00: No change in bits D[1:0] - fast change mode disabled 01: Bits D[1:0] set to 01 10: Bits D[1:0] set to 10 11: Bits D[1:0] set to 11 1:0 CTLV18U25U[1:0] RW 10 Mode control (V9) 00: Disabled 01: Enabled 10: Enabled 11: Enabled Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 95 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.25 V1P2UCNT Register (address = 0x36) [reset = 00111010] Figure 6-47. V1P2UCNT Register Format B7 V1P2ULVSEL B6 V1P2UVSEL[2] B5 V1P2UVSEL[1] B4 V1P2UVSEL[0] 0 RW 0 RW 1 RW 1 RW B3 AOACCNTV1P 2U[1] 1 RW B2 AOACCNTV1P 2U[0] 0 RW B1 CTLV1P2U[1] B0 CTLV1P2U[0] 1 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-28. V1P2UCNT Register Field Descriptions Bit Field Type Reset Description V1P2ULVSEL RW 0 V1.2U low power mode output voltage set point - set at assertion of SLP_S0# 0: Disabled, voltage stays at value set by V1P2UVSEL 1: Vnom - 3% 6:4 V1P2UVSEL[2:0] RW 011 Output voltage select 000: Vnom + 3% 001: Vnom + 2% 010: Vnom + 1% 011: Vnom + 0% 100: Vnom - 1% 101: Vnom - 2% 110: Vnom - 3% 111: Vnom -4% 3:2 AOACCNTV1P2U[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) changes bits D[1:0] on exit 00: no change in bits D[1:0] - fast change mode disabled 01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM) 10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM) 11: Bits D[1:0] set to 11, forced PWM operation 1:0 CTLV1P2U[1:0] RW 10 Mode control (V10) 00: Converter disabled 01: Auto Mode, (automatic transition from PFM to PWM) 10: Auto Mode, (automatic transition from PFM to PWM) 11: Forced PWM operation 7 96 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.26 V100ACNT Register (address = 0x37) [reset = 00011010] Figure 6-48. V100ACNT Register Format B7 B6 V100ALVSEL[1 V100ALVSEL[0 ] ] 0 0 RW RW B5 V100AVSEL[1] B4 V100AVSEL[0] 0 RW 1 RW B3 AOACCNTV10 0A[1] 1 RW B2 AOACCNTV10 0A[0] 0 RW B1 CTLV100A[1] B0 CTLV100A[0] 1 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-29. V100ACNT Register Field Descriptions Bit Field Type Reset Description 7:6 V100ALVSEL[1:0] RW 00 V100A low power mode output voltage set point - set at assertion of SLP_S0# 00: Disabled, voltage stays at value set by V100AVSEL[1:0] 01: Vnom - 4% 10: Vnom - 3% 11: Vnom - 2% 5:4 V100AVSEL[1:0] RW 01 Output voltage select 00: Vnom + 5% (1.05 V) 01: Vnom (1 V) 10: Vnom - 2.5% (0.975 V) 11: Vnom - 5% (0.95V) 3:2 AOACCNTV100A[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) changes bits D[1:0] on exit 00: No change in bits D[1:0] - fast change mode disabled 01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM) 10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM) 11: Bits D[1:0] set to 11, forced PWM operation 1:0 CTLV100A[1:0] RW 10 Mode control (V11) 00: Converter disabled 01: Auto Mode, (automatic transition from PFM to PWM) 10: Auto Mode, (automatic transition from PFM to PWM) 11: Forced PWM operation Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 97 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.27 V085ACNT Register (address = 0x38) [reset = 00101010] Figure 6-49. V085ACNT Register Format B7 B6 V085ALVSEL[1 V085ALVSEL[0 ] ] 0 0 RW RW B5 V085AVSEL[1] B4 V085AVSEL[0] 1 RW 0 RW B3 AOACCNTV08 5A[1] 1 RW B2 AOACCNTV08 5A[0] 0 RW B1 CTLV085A[1] B0 CTLV085A[0] 1 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-30. V085ACNT Register Field Descriptions 98 Bit Field Type Reset Description 7:6 V085ALVSEL[1:0] RW 00 V085A low power mode output voltage set point - set at assertion of SLP_S0# 00: Disabled, voltage stays at value set by V085AVSEL[1:0] 01: 0.70 V 10: 0.75 V 11: 0.80 V 5:4 V085AVSEL[1:0] RW 00 Output voltage select 00: 0.95 V 01: 0.90 V 10: 0.85 V 11: 0.80 V 3:2 AOACCNTV085A[1:0] RW 10 Mode control for exit standby (rising edge of SLP_S0#) changes bits D[1:0] on exit 00: No change in bits D[1:0] - fast change mode disabled 01: Bits D[1:0] set to 01, Auto Mode, (automatic transition from PFM to PWM) 10: Bits D[1:0] set to 10, Auto Mode, (automatic transition from PFM to PWM) 11: Bits D[1:0] set to 11, forced PWM operation 1:0 CTLV085A[1:0] RW 10 Mode control (V12) 00: Converter disabled 01: Auto Mode, (automatic transition from PFM to PWM) 10: Auto Mode, (automatic transition from PFM to PWM) 11: Forced PWM operation Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.28 VRMODECTRL Register (address = 0x3B) [reset = 00111111] Figure 6-50. VRMODECTRL Register Format B7 RESERVED_V RMODECTRL[ 1] 0 R B6 RESERVED_V RMODECTRL[ 0] 0 R B5 V33ADSW_LP M B4 VCCIO_LPM B3 V085A_LPM B2 V12U_LPM B1 V100A_LPM B0 V5ADS3_LPM 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-31. VRMODECTRL Register Field Descriptions Bit Field Type Reset 7:6 RESERVED_VRMODECTRL[1:0] R 00 Description 5 V33ADSW_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLV33ADSW [1:0] bits of V33ADSWCNT register. 0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register V33ADSWCNT, bits CTLV33ADSW [1:0] when STANDBY# is low} 1: Mode set by CTLV33ADSW [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLV33ADSW [1:0] when STANDBY# is low} 4 VCCIO_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLVCCIO [1:0] bits of VCCIOCNT register. 0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register VCCIOCNT, bits CTLVCCIO [1:0] when STANDBY# is low} 1: Mode set by CTLVCCIO [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLVCCIO [1:0] when STANDBY# is low} 3 V085A_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLV085A [1:0] register. 0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register V085ACNT, bits CTLV085A [1:0] when STANDBY# is low} 1: Mode set by CTLV085A [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLV085A [1:0] when STANDBY# is low} 2 V12U_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLV12U [1:0] bits in V12UCNT register. 0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register V12UCNT, bits CTLV12U [1:0] when STANDBY# is low} 1: Mode set by CTLV12U [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLV12U [1:0] when STANDBY# is low} 1 V100A_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLV100A [1:0] bits in V100ACNTregister. 0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register V100ACNT, bits CTLV100A [1:0] when STANDBY# is low} 1: Mode set by CTLV100A [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLV100A[1:0] when STANDBY# is low} 0 V5ADS3_LPM RW 1 Force low power mode (Auto mode). This is only used if forcing PWM in CTLV5ADS3 [1:0] bits in V5ADS3CNT register. 0: Force Auto mode when STANDBY# (SLP_S0#) is asserted (low) {Over-rides setting of register V5ADS3,CNT bits CTLVV33ADSW [1:0] when STANDBY# is low} 1: Mode set by CTLV5ADS3 [1:0] bits when STANDBY# (SLP_S0#) {Does what is setting of register bits CTLV5ADS3 [1:0] when STANDBY# is low} Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 99 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.29 DISCHCNT1 Register (address = 0x3C) [reset = 00000000] Figure 6-51. DISCHCNT1 Register Format B7 B6 B5 B4 B3 B2 B1 B0 RESERVED_DI RESERVED_DI RESERVED_DI RESERVED_DI RESERVED_DI RESERVED_DI VCCIODISCHG VCCIODISCHG SCHCNT1[5] SCHCNT1[4] SCHCNT1[3] SCHCNT1[2] SCHCNT1[1] SCHCNT1[0] [1] [0] 0 0 0 0 0 0 0 0 R R R R R R RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-32. DISCHCNT1 Register Field Descriptions Bit Field Type Reset 7:2 RESERVED_DISCHCNT1[5:0] R 000000 1:0 VCCIODISCHG[1:0] RW 00 Description VCCIO discharge resistance at VSD, (TPS650831 at FBVR3P) 00: >1000 kΩ 01: 125 Ω 10: 225 Ω 11: 550 Ω 6.6.1.30 DISCHCNT2 Register (address = 0x3D) [reset = 00000000] Figure 6-52. DISCHCNT2 Register Format B7 B6 V5ADS3DISCH V5ADS3DISCH G[1] G[0] 0 0 RW RW B5 V33ADSWDIS CHG[1] 0 RW B4 V33ADSWDIS CHG[0] 0 RW B3 B2 V33PCHDISCH V33PCHDISCH G[1] G[0] 0 0 RW RW B1 V18ADISCH[1] B0 V18ADISCH[0] 0 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-33. DISCHCNT2 Register Field Descriptions 100 Bit Field Type Reset Description 7:6 V5ADS3DISCHG[1:0] RW 00 V5ADS3 discharge resistance at FBVR5P, (TPS650831 at VSC) 00: No discharge 01: 100 Ω 10: 200 Ω 11: 500 Ω 5:4 V33ADSWDISCHG[1:0] RW 00 V33A_DSW discharge resistance at FBVR3P, (TPS650831 at VSD) 00: No discharge 01: 100 Ω 10: 200 Ω 11: 500 Ω 3:2 V33PCHDISCHG[1:0] RW 00 V33A_PCH discharge resistance at VSA 00: No discharge 01: 100 Ω 10: 200 Ω 11: 500 Ω 1:0 V18ADISCH[1:0] RW 00 V18A discharge resistance at FBVR2P, (TPS650831 at FBVR5P) 00: 860 Ω 01: 100 Ω 10: 200 Ω 11: 500 Ω Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.31 DISCHCNT3 Register (address = 0x3E) [reset = 00000000] Figure 6-53. DISCHCNT3 Register Format B7 V18U25UDISC HG[1] 0 RW B6 V18U25UDISC HG[0] 0 RW B5 V12UDISCHG[ 1] 0 RW B4 V12UDISCHG[ 0] 0 RW B3 B2 B1 B0 V100ADISCHG V100ADISCHG V085ADISCH[1 V085ADISCH[0 [1] [0] ] ] 0 0 0 0 RW RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-34. DISCHCNT3 Register Field Descriptions Bit Field Type Reset Description 7:6 V18U25UDISCHG[1:0] RW 00 V1.8U_2.5U discharge resistance at VSB 00: No discharge 01: 100 Ω 10: 200 Ω 11: 500 Ω 5:4 V12UDISCHG[1:0] RW 00 V1.2U discharge resistance at FBVR4P 00: >1000 kΩ 01: 125 Ω 10: 225 Ω 11: 550 Ω 3:2 V100ADISCHG[1:0] RW 00 V100A discharge resistance at FBVR1P 00: >1000 kΩ 01: 125 Ω 10: 225 Ω 11: 550 Ω 1:0 V085ADISCH[1:0] RW 00 V085A discharge resistance, (TPS650831 at FBVR2P) 00: >1000 kΩ 01: 150 Ω 10: 250 Ω 11: 575 Ω Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 101 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.32 DISCHCNT4 Register (address = 0x3F) [reset = 00000000] Figure 6-54. DISCHCNT4 Register Format B7 B6 RESERVED_DI RESERVED_DI SCHCNT4[1] SCHCNT4[0] 0 0 R R B5 V33SDISCHG[ 1] 0 RW B4 V33SDISCHG[ 0] 0 RW B3 V18SDISCHG[ 1] 0 RW B2 V18SDISCHG[ 0] 0 RW B1 B0 V100SDISCH[1 V100SDISCH[0 ] ] 0 0 RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-35. DISCHCNT4 Register Field Descriptions 102 Bit Field Type Reset Description 7:6 RESERVED_DISCHCNT4[1:0] R 00 5:4 V33SDISCHG[1:0] RW 00 V3.3S discharge resistance at VSE 00: No discharge 01: 100 Ω 10: 200 Ω 11: 500 Ω 3:2 V18SDISCHG[1:0] RW 00 V18S discharge resistance at VSF 00: No discharge 01: 100 Ω 10: 200 Ω 11: 500 Ω 1:0 V100SDISCH[1:0] RW 00 V100S discharge resistance at VSG 00: No discharge 01: 100 Ω 10: 200 Ω 11: 500 Ω Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.33 PWRGDCNT1 Register (address = 0x40) [reset = 01011111 ] Figure 6-55. PWRGDCNT1 Register Format B7 B6 B5 B4 RESERVED_P RSMRSTN_PW RSMRSTN_PW PCH_PWROK[ WRGDCNT1 RGD[1] RGD[0] 1] 0 1 0 1 R RW RW RW B3 PCH_PWROK[ 0] 1 RW B2 DEL_ALL_SYS _PWRGD[2] 1 RW B1 DEL_ALL_SYS _PWRGD[1] 1 RW B0 DEL_ALL_SYS _PWRGD[0] 1 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-36. PWRGDCNT1 Register Field Descriptions Bit 7 Field Type Reset Description RESERVED_PWRGDCNT1 R 0 6:5 RSMRSTN_PWRGD[1:0] RW 10 Delay of RSMRSTN_PWRGD, [RTC = 30.5 µs ±10%] 00: No Delay 01: 164x RTC (5.5 ms) 10: 360x RTC (11 ms) 11: 721x RTC (22 ms) 4:3 PCH_PWROK[1:0] RW 11 Delay of PCH_PWROK compared to ALL_SYS_PWRGD, [RTC = 30.5 µs ±10%] 00: 82x RTC (2.5 ms) 01: 164x RTC (5 ms) 10: 328x RTC (10 ms) 11: 656x RTC (20 ms) 2:0 DEL_ALL_SYS_PWRGD[2:0] RW 111 Delay of SYS_PWR_OK compared to ALL_SYS_PWRGD, [RTC = 30.5 µs ±10%] 000: 82x RTC (2.5 ms) 001: 164x RTC (5 ms) 010: 328x RTC (10 ms) 011: 492x RTC (15 ms) 100: 656x RTC (20 ms) 101: 1640x RTC (50 ms) 110: 2460x RTC (75 ms) 111: 3280x RTC (100 ms) Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 103 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.34 VREN Register (address = 0x41) [reset = 00000000] Figure 6-56. VREN Register Format B7 RESERVED_V REN[5] 0 RW B6 RESERVED_V REN[4] 0 RW B5 RESERVED_V REN[3] 0 RW B4 RESERVED_V REN[2] 0 RW B3 RESERVED_V REN[1] 0 RW B2 RESERVED_V REN[0] 0 RW B1 EC_SLP_S4 B0 EC_DS4 0 RW 0 RW B1 RESERVED[0] 0 R B0 CNTLOCK 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-37. VREN Register Field Descriptions Bit Field Type Reset 7:2 Description RESERVED_VREN[5:0] RW 000000 1 EC_SLP_S4 RW 0 0: Disable 1: Enable 0 EC_DS4 RW 0 0: Disable 1: Enable 6.6.1.35 REGLOCK Register (address = 0x42) [reset = 00000000] Figure 6-57. REGLOCK Register Format B7 RESERVED[6] 0 R B6 RESERVED[5] 0 R B5 RESERVED[4] 0 R B4 RESERVED[3] 0 R B3 RESERVED[2] 0 R B2 RESERVED[1] 0 R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-38. REGLOCK Register Field Descriptions Bit Field Type Reset 7:1 RESERVED[6:0] R 0000000 CNTLOCK RW 0 0 104 Description Locks all V*CNT registers 0: All V*CNT registers are unlocked and can be overwritten 1: All V*CNT registers are locked and cannot be overwritten Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.36 VRENPINMASK Register (address = 0x43) [reset = 00000000] Figure 6-58. VRENPINMASK Register Format B7 MV12EN 0 RW B6 MV11EN 0 RW B5 MV10EN 0 RW B4 MV9EN 0 RW B3 MV8EN 0 RW B2 MV7EN 0 RW B1 MV5EN 0 RW B0 MV4EN 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-39. VRENPINMASK Register Field Descriptions Bit Field Type Reset Description 7 MV12EN RW 0 V12 Enable Pin Mask 0: VR Enable Pin controls VR enable 1: VR Enable Pin masked V*CTLV controls VR enable 6 MV11EN RW 0 V11 Enable Pin Mask 0: VR Enable Pin controls VR enable 1: VR Enable Pin masked V*CTLV controls VR enable 5 MV10EN RW 0 V10 Enable Pin Mask 0: VR Enable Pin controls VR enable 1: VR Enable Pin masked V*CTLV controls VR enable 4 MV9EN RW 0 V9 Enable Pin Mask 0: VR Enable Pin controls VR enable 1: VR Enable Pin masked V*CTLV controls VR enable 3 MV8EN RW 0 V8 Enable Pin Mask 0: VR Enable Pin controls VR enable 1: VR Enable Pin masked V*CTLV controls VR enable 2 MV7EN RW 0 V7 Enable Pin Mask 0: VR Enable Pin controls VR enable 1: VR Enable Pin masked V*CTLV controls VR enable 1 MV5EN RW 0 V5 Enable Pin Mask 0: VR Enable Pin controls VR enable 1: VR Enable Pin masked V*CTLV controls VR enable 0 MV4EN RW 0 V4 Enable Pin Mask 0: VR Enable Pin controls VR enable 1: VR Enable Pin masked V*CTLV controls VR enable Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 105 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.37 RSTCTRL Register (address = 0x48) [reset = 00011100] Figure 6-59. RSTCTRL Register Format B7 RESERVED_R STCTRL[2] 0 R B6 RESERVED_R STCTRL[1] 0 R B5 RESERVED_R STCTRL[0] 0 R B4 TRST[1] B3 TRST[0] B2 VTHRST[2] B1 VTHRST[1] B0 VTHRST[0] 1 RW 1 RW 1 RW 0 RW 0 RW B1 RESERVED_S DWNCTRL[0] 0 R B0 SDWN LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-40. RSTCTRL Register Field Descriptions Bit Field Type Reset Description 7:5 RESERVED_RSTCTRL[2:0] R 000 4:3 TRST[1:0] RW 11 Reset time duration 00: 20 ms 01: 40 ms 10: 80 ms 11: 200 ms 2:0 VTHRST[2:0] RW 100 Reset voltage threshold 000: 1.4 V 001: 1.5 V 010: 1.6 V 011: 1.7 V 100: 2.4 V 101: 2.6 V 110: 2.8 V 111: 3.0 V 6.6.1.38 SDWNCTRL Register (address = 0x49) [reset = 00000000] Figure 6-60. SDWNCTRL Register Format B7 RESERVED_S DWNCTRL[6] 0 R B6 RESERVED_S DWNCTRL[5] 0 R B5 RESERVED_S DWNCTRL[4] 0 R B4 RESERVED_S DWNCTRL[3] 0 R B3 RESERVED_S DWNCTRL[2] 0 R B2 RESERVED_S DWNCTRL[1] 0 R 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-41. SDWNCTRL Register Field Descriptions Bit Field Type Reset 7:1 RESERVED_SDWNCTRL[6:0] R 0000000 SDWN RW 0 0 106 Description Forced emergency reset, bit is self clearing 0: No action 1: Force emergency reset Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.39 VDLMTCRT Register (address = 0x51) [reset = 00000101] Figure 6-61. VDLMTCRT Register Format B7 RESERVED_V DLMTCRT 0 RW B6 VDLMTCOMP 0 RW B5 TDBNCVDLMT CRT[1] 0 RW B4 B3 B2 B1 B0 TDBNCVDLMT VDLMTCRTH[3 VDLMTCRTH[2 VDLMTCRTH[1 VDLMTCRTH[0 CRT[0] ] ] ] ] 0 0 1 0 1 RW RW RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-42. VDLMTCRT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED_VDLMTCRT RW 0 6 VDLMTCOMP RW 0 Critical supply voltage comparator for VDCSNS pin input voltage sense. Connect voltage divider resistors from VIN to detect when input voltage is low 0: disable 1: enable 5:4 TDBNCVDLMTCRT[1:0] RW 00 Supply voltage monitor debounce of VDCSNS input voltage sense pin 00: No Deglitch 01: 10 µs 10: 1x RTC (30us) 11: 2x RTC (60us) 3:0 VDLMTCRTH[3:0] RW 0101 Critical supply voltage falling threshold on VDCSNS pin. Connect voltage divider resistors from VIN to detect when input voltage is low. For 2S should be 4X top resistor, X bottom resistor. [rising hysteresis = 20 mV] 0000: no limit 0001: 1.2 V 0010: 1.18 V 0011: 1.16 V 0100: 1.14 V 0101: 1.12 V 0110: 1.10 V 0111: 1.08 V 1xxx: NA Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 107 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.40 ACOKDBDM Register (address = 0x69) [reset = 00001111] Figure 6-62. ACOKDBDM Register Format B7 RESERVED_A COKDBDM[3] 0 RW B6 RESERVED_A COKDBDM[2] 0 RW B5 RESERVED_A COKDBDM[1] 0 RW B4 RESERVED_A COKDBDM[0] 0 RW B3 ACOKDB[1] B2 ACOKDB[0] B1 ACOKDM[1] B0 ACOKDM[0] 1 RW 1 RW 1 RW 1 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-43. ACOKDBDM Register Field Descriptions Bit Field Type Reset Description 7:4 RESERVED_ACOKDBDM[3:0] RW 0000 3:2 ACOKDB[1:0] RW 11 Adapter detection debounce time 00: 81 µs 01: 10 ms 10: 20 ms 11: 30 ms 1:0 ACOKDM[1:0] RW 11 Adapter detection mode 00: reserved 01: low-to-high 10: high-to-low 11: both, low-to-high and high-to-low 6.6.1.41 LOWBATTDET Register (address = 0x6A) [reset = 11111000] Figure 6-63. LOWBATTDET Register Format B7 B6 LOWBATTDB[1 LOWBATTDB[0 ] ] 1 RW 1 RW B5 LOWBATT2_E N B4 LOWBATT1_E N B3 ACIN_EN 1 RW 1 RW 1 RW B2 B1 B0 RESERVED_L RESERVED_L RESERVED_L OWBATTDET[2 OWBATTDET[1 OWBATTDET[0 ] ] ] 0 0 0 RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-44. LOWBATTDET Register Field Descriptions Bit Field Type Reset Description 7:6 LOWBATTDB[1:0] RW 11 Low battery detection debounce time 00: 4 RTC periods (120 µs) 01: 32 RTC periods (960 µs) 10: 64 RTC periods (1920 µs) 11: 128 RTC periods (3840 µs) 5 LOWBATT2_EN RW 1 Low battery Two detection Enable 0: Disable 1: Enable 4 LOWBATT1_EN RW 1 Low battery One detection Enable 0: Disable 1: Enable 3 ACIN_EN RW 1 AC IN Comparator 0: Disable 1: Enable RESERVED_LOWBATTDET[2:0] RW 000 2:0 108 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.42 SPWRSRCINT Register (address = 0x6F) [reset = 00000000] Figure 6-64. SPWRSRCINT Register Format B7 RESERVED1_ SPWRSRCINT B6 SLOWBATT2 B5 SLOWBATT1 B4 SACOK 0 R 0 R 0 R 0 R B3 B2 B1 B0 RESERVED_S RESERVED_S RESERVED_S RESERVED_S PWRSRCINT[3 PWRSRCINT[2 PWRSRCINT[1 PWRSRCINT[0 ] ] ] ] 0 0 0 0 R R R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-45. SPWRSRCINT Register Field Descriptions Bit Field Type Reset 7 RESERVED1_SPWRSRCINT R 0 6 SLOWBATT2 R 0 LOWBATT2 detection status 0: BATT2 above threshold 1: BATT2 below threshold 5 SLOWBATT1 R 0 LOWBATT1 detection status 0: BATT1 above threshold 1: BATT1 below threshold 4 SACOK R 0 AC adapter (ACOK) detection status 0: Adapter removed 1: Adapter inserted RESERVED_SPWRSRCINT[3:0] R 0000 3:0 Description 6.6.1.43 CLKCTRL1 Register (address = 0xD0) [reset = 00000000] Figure 6-65. CLKCTRL1 Register Format B7 RESERVED_C LKCTRL1[6] 0 RW B6 RESERVED_C LKCTRL1[5] 0 RW B5 RESERVED_C LKCTRL1[4] 0 RW B4 RESERVED_C LKCTRL1[3] 0 RW B3 RESERVED_C LKCTRL1[2] 0 RW B2 RESERVED_C LKCTRL1[1] 0 RW B1 RESERVED_C LKCTRL1[0] 0 RW B0 ECWAKEEN 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-46. CLKCTRL1 Register Field Descriptions Bit Field Type Reset 7:1 RESERVED_CLKCTRL1[6:0] RW 0000000 ECWAKEEN RW 0 0 Description 1 Hz clock 0: clock OFF 1: Clock ON Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 109 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.44 COMPA_REF Register (address = 0xDD) [reset = 00000000] Figure 6-66. COMPA_REF Register Format B7 COMPA_MOD E X RW B6 B5 B4 B3 B2 B1 B0 COMPA_DVS[3 COMPA_DVS[2 COMPA_DVS[1 COMPA_DVS[0 COMPA_VSEL[ COMPA_VSEL[ COMPA_VSEL[ ] ] ] ] 2] 1] 0] X X X X X X X RW RW RW RW RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-47. COMPA_REF Register Field Descriptions Bit Field Type Reset Description COMPA_Mode RW 0 Comparator Mode: 0: PGOOD Mode 1: Comparator Mode 6:3 COMPA_DVS[3:0] RW 0000 Comparator Window Voltage Shifting: % deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V 0000 = + 3% or 1.05 V 0001 = + 2% or 1 V 0010 = + 1% or 0.975 V 0011 = + 0% or 0.95 V 0100 = - 1% or 0.9 V 0101 = - 2% or 0.875 V 0110 = - 3% or 0.85 V 0111 = - 4% or 0.8 V 1000 = 0.75 V 1001 = 0.7 V 2:0 COMPA_VSEL[2:0] RW 000 Comparator Window Voltage Select: 000 = 1 V 001 = 1.2 V 010 = 1.5 V 011 = 1.8 V 100 = 1.1 V 101 = 1.35 V 110 = 3.3 V 111 = 2.5 V / 5 V 7 110 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.45 COMPB_REF Register (address = 0xDE) [reset = 00000000] Figure 6-67. COMPB_REF Register Format B7 COMPB_MOD E X RW B6 B5 B4 B3 B2 B1 B0 COMPB_DVS[3 COMPB_DVS[2 COMPB_DVS[1 COMPB_DVS[0 COMPB_VSEL[ COMPB_VSEL[ COMPB_VSEL[ ] ] ] ] 2] 1] 0] X X X X X X X RW RW RW RW RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-48. COMPB_REF Register Field Descriptions Bit Field Type Reset Description COMPB_Mode RW 0 Comparator Mode: 0: PGOOD Mode 1: Comparator Mode 6:3 COMPB_DVS[3:0] RW 0000 Comparator Window Voltage Shifting: % deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V 0000 = + 3% or 1.05 V 0001 = + 2% or 1 V 0010 = + 1% or 0.975 V 0011 = + 0% or 0.95 V 0100 = - 1% or 0.9 V 0101 = - 2% or 0.875 V 0110 = - 3% or 0.85 V 0111 = - 4% or 0.8 V 1000 = 0.75 V 1001 = 0.7 V 2:0 COMPB_VSEL[2:0] RW 000 Comparator Window Voltage Select: 000 = 1 V 001 = 1.2 V 010 = 1.5 V 011 = 1.8 V 100 = 1.1 V 101 = 1.35 V 110 = 3.3 V 111 = 2.5 V / 5 V 7 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 111 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.46 COMPC_REF Register (address = 0xDF) [reset = 00000000] Figure 6-68. COMPC_REF Register Format B7 COMPC_MOD E 1 RW B6 COMPC_DVS[ 3] 0 RW B5 COMPC_DVS[ 2] 0 RW B4 COMPC_DVS[ 1] 0 RW B3 COMPC_DVS[ 0] 1 RW B2 B1 B0 COMPC_VSEL[ COMPC_VSEL[ COMPC_VSEL[ 2] 1] 0] 0 0 0 RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-49. COMPC_REF Register Field Descriptions Bit Field Type Reset Description COMPC_Mode RW 0 Comparator Mode: 0: PGOOD Mode 1: Comparator Mode 6:3 COMPC_DVS[3:0] RW 0000 Comparator Window Voltage Shifting: % deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V 0000 = + 3% or 1.05 V 0001 = + 2% or 1 V 0010 = + 1% or 0.975 V 0011 = + 0% or 0.95 V 0100 = - 1% or 0.9 V 0101 = - 2% or 0.875 V 0110 = - 3% or 0.85 V 0111 = - 4% or 0.8 V 1000 = 0.75 V 1001 = 0.7 V 2:0 COMPC_VSEL[2:0] RW 000 Comparator Window Voltage Select: 000 = 1 V 001 = 1.2 V 010 = 1.5 V 011 = 1.8 V 100 = 1.1 V 101 = 1.35 V 110 = 3.3 V 111 = 2.5 V / 5 V 7 112 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.47 COMPD_REF Register (address = 0xE0) [reset = 00000000] Figure 6-69. COMPD_REF Register Format B7 COMPD_MOD E X RW B6 COMPD_DVS[ 3] X RW B5 COMPD_DVS[ 2] X RW B4 COMPD_DVS[ 1] X RW B3 COMPD_DVS[ 0] X RW B2 B1 B0 COMPD_VSEL[ COMPD_VSEL[ COMPD_VSEL[ 2] 1] 0] X X X RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-50. COMPD_REF Register Field Descriptions Bit Field Type Reset Description COMPD_Mode RW 0 Comparator Mode: 0: PGOOD Mode 1: Comparator Mode 6:3 COMPD_DVS[3:0] RW 0000 Comparator Window Voltage Shifting: % deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V 0000 = + 3% or 1.05 V 0001 = + 2% or 1 V 0010 = + 1% or 0.975 V 0011 = + 0% or 0.95 V 0100 = - 1% or 0.9 V 0101 = - 2% or 0.875 V 0110 = - 3% or 0.85 V 0111 = - 4% or 0.8 V 1000 = 0.75 V 1001 = 0.7 V 2:0 COMPD_VSEL[2:0] RW 000 Comparator Window Voltage Select: 000 = 1 V 001 = 1.2 V 010 = 1.5 V 011 = 1.8 V 100 = 1.1 V 101 = 1.35 V 110 = 3.3 V 111 = 2.5 V / 5 V 7 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 113 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.48 COMPE_REF Register (address = 0xE1) [reset = 00000000] Figure 6-70. COMPE_REF Register Format B7 COMPE_MOD E X RW B6 B5 B4 B3 B2 B1 B0 COMPE_DVS[3 COMPE_DVS[2 COMPE_DVS[1 COMPE_DVS[0 COMPE_VSEL[ COMPE_VSEL[ COMPE_VSEL[ ] ] ] ] 2] 1] 0] X X X X X X X RW RW RW RW RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-51. COMPE_REF Register Field Descriptions Bit Field Type Reset Description COMPE_Mode RW 0 Comparator Mode: 0: PGOOD Mode 1: Comparator Mode 6:3 COMPE_DVS[3:0] RW 0000 Comparator Window Voltage Shifting: % deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V 0000 = + 3% or 1.05 V 0001 = + 2% or 1 V 0010 = + 1% or 0.975 V 0011 = + 0% or 0.95 V 0100 = - 1% or 0.9 V 0101 = - 2% or 0.875 V 0110 = - 3% or 0.85 V 0111 = - 4% or 0.8 V 1000 = 0.75 V 1001 = 0.7 V 2:0 COMPE_VSEL[2:0] RW 000 Comparator Window Voltage Select: 000 = 1 V 001 = 1.2 V 010 = 1.5 V 011 = 1.8 V 100 = 1.1 V 101 = 1.35 V 110 = 3.3 V 111 = 2.5 V / 5 V 7 114 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.49 COMPF_REF Register (address = 0xE2) [reset = 00000000] Figure 6-71. COMPF_REF Register Format B7 COMPF_MOD E X RW B6 B5 B4 B3 B2 B1 B0 COMPF_DVS[3 COMPF_DVS[2 COMPF_DVS[1 COMPF_DVS[0 COMPF_VSEL[ COMPF_VSEL[ COMPF_VSEL[ ] ] ] ] 2] 1] 0] X X X X X X X RW RW RW RW RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-52. COMPF_REF Register Field Descriptions Bit Field Type Reset Description COMPF_Mode RW 0 Comparator Mode: 0: PGOOD Mode 1: Comparator Mode 6:3 COMPF_DVS[3:0] RW 0000 Comparator Window Voltage Shifting: % deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V 0000 = + 3% or 1.05 V 0001 = + 2% or 1 V 0010 = + 1% or 0.975 V 0011 = + 0% or 0.95 V 0100 = - 1% or 0.9 V 0101 = - 2% or 0.875 V 0110 = - 3% or 0.85 V 0111 = - 4% or 0.8 V 1000 = 0.75 V 1001 = 0.7 V 2:0 COMPF_VSEL[2:0] RW 000 Comparator Window Voltage Select: 000 = 1 V 001 = 1.2 V 010 = 1.5 V 011 = 1.8 V 100 = 1.1 V 101 = 1.35 V 110 = 3.3 V 111 = 2.5 V / 5 V 7 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 115 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.50 COMPG_REF Register (address = 0xE3) [reset = 00000000] Figure 6-72. COMPG_REF Register Format B7 COMPG_MOD E X RW B6 COMPG_DVS[ 3] X RW B5 COMPG_DVS[ 2] X RW B4 COMPG_DVS[ 1] X RW B3 COMPG_DVS[ 0] X RW B2 B1 B0 COMPG_VSEL COMPG_VSEL COMPG_VSEL [2] [1] [0] X X X RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-53. COMPG_REF Register Field Descriptions Bit Field Type Reset Description COMPG_Mode RW 0 Comparator Mode: 0: PGOOD Mode 1: Comparator Mode 6:3 COMPG_DVS[3:0] RW 0000 Comparator Window Voltage Shifting: % deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V 0000 = + 3% or 1.05 V 0001 = + 2% or 1 V 0010 = + 1% or 0.975 V 0011 = + 0% or 0.95 V 0100 = - 1% or 0.9 V 0101 = - 2% or 0.875 V 0110 = - 3% or 0.85 V 0111 = - 4% or 0.8 V 1000 = 0.75 V 1001 = 0.7 V 2:0 COMPG_VSEL[2:0] RW 000 Comparator Window Voltage Select: 000 = 1 V 001 = 1.2 V 010 = 1.5 V 011 = 1.8 V 100 = 1.1 V 101 = 1.35 V 110 = 3.3 V 111 = 2.5 V / 5 V 7 116 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.51 COMPH_REF Register (address = 0xE4) [reset = 00000000] Figure 6-73. COMPH_REF Register Format B7 COMPH_DISC HG 0 RW B6 COMPH_DVS[ 3] X RW B5 COMPH_DVS[ 2] X RW B4 COMPH_DVS[ 1] X RW B3 COMPH_DVS[ 0] X RW B2 B1 B0 COMPH_VSEL[ COMPH_VSEL[ COMPH_VSEL 2] 1] 0] X X X RW RW RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-54. COMPH_REF Register Field Descriptions Bit Field Type Reset Description 7 COMPH_DISCHG RW 0 Comparator H Discharge value 0: No discharge 1: 100 Ω 6:3 COMPH_DVS[3:0] RW 0000 Comparator Window Voltage Shifting: % deviation from VSEL if VSEL >1.05V or second voltage option if VSEL = 1 V 0000 = + 3% or 1.05 V 0001 = + 2% or 1 V 0010 = + 1% or 0.975 V 0011 = + 0% or 0.95 V 0100 = - 1% or 0.9 V 0101 = - 2% or 0.875 V 0110 = - 3% or 0.85 V 0111 = - 4% or 0.8 V 1000 = 0.75 V 1001 = 0.7 V 2:0 COMPH_VSEL[2:0] RW 000 Comparator Window Voltage Select: 000 = 1 V 001 = 1.2 V 010 = 1.5 V 011 = 1.8 V 100 = 1.1 V 101 = 1.35 V 110 = 3.3 V 111 = 2.5 V / 5 V Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 117 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.52 PWFAULT_MASK1 Register (address = 0xE5) [reset = 00000000] Figure 6-74. PWFAULT_MASK1 Register Format B7 V4_FLTmsK 0 RW B6 V5_FLTmsK 0 RW B5 V6_FLTmsK 0 RW B4 V7_FLTmsK 0 RW B3 V8_FLTmsK 0 RW B2 V9_FLTmsK 0 RW B1 V10_FLTmsK 0 RW B0 V13_FLTmsK 1 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-55. PWFAULT_MASK1 Register Field Descriptions Bit 118 Field Type Reset Description 7 V4_FLTmsK RW 0 V4 Power Fault Masked 0: Not Masked 1: Masked 6 V5_FLTmsK RW 0 V5 Power Fault Masked 0: Not Masked 1: Masked 5 V6_FLTmsK RW 0 V6 Power Fault Masked 0: Not Masked 1: Masked 4 V7_FLTmsK RW 0 V7 Power Fault Masked 0: Not Masked 1: Masked 3 V8_FLTmsK RW 0 V8 Power Fault Masked 0: Not Masked 1: Masked 2 V9_FLTmsK RW 0 V9 Power Fault Masked 0: Not Masked 1: Masked 1 V10_FLTmsK RW 0 V10 Power Fault Masked 0: Not Masked 1: Masked 0 V13_FLTmsK RW 0 V13 Power Fault Masked 0: Not Masked 1: Masked Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.53 PWFAULT_MASK2 Register (address = 0xE6) [reset = 00000000] Figure 6-75. PWFAULT_MASK2 Register Format B7 RESERVED_P WFAULT_MAS K2[5] 0 RW B6 RESERVED_P WFAULT_MAS K2[4] 0 RW B5 RESERVED_P WFAULT_MAS K2[3] 0 RW B4 RESERVED_P WFAULT_MAS K2[2] 0 RW B3 RESERVED_P WFAULT_MAS K2[1] 0 RW B2 RESERVED_P WFAULT_MAS K2[0] 0 RW B1 V11_FLTmsK B0 V12_FLTmsK 0 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-56. PWFAULT_MASK2 Register Field Descriptions Bit Field Reset Description 7:2 RESERVED_PWFAULT_MASK2[5: 0] Type 000000 Read Always Returns '1' 1 V11_FLTmsK 0 V11 Power Fault Masked 0: Not Masked 1: Masked 0 V12_FLTmsK 0 V12 Power Fault Masked 0: Not Masked 1: Masked Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 119 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.54 PGOOD_STAT1 Register (address = 0xE7) [reset = 00000000] Figure 6-76. PGOOD_STAT1 Register Format B7 V13_PGOOD 0 R B6 V10_PGOOD 0 R B5 V9_PGOOD 0 R B4 V8_PGOOD 0 R B3 V7_PGOOD 0 R B2 V6_PGOOD 0 R B1 V5_PGOOD 0 R B0 V4_PGOOD 0 R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-57. PGOOD_STAT1 Register Field Descriptions Bit 120 Field Type Reset Description 7 V13_PGOOD R 0 V13 PGOOD STATUS 0: Fail 1: Pass 6 V10_PGOOD R 0 V10 PGOOD STATUS 0: Fail 1: Pass 5 V9_PGOOD R 0 V9 PGOOD STATUS 0: Fail 1: Pass 4 V8_PGOOD R 0 V8 PGOOD STATUS 0: Fail 1: Pass 3 V7_PGOOD R 0 V7 PGOOD STATUS 0: Fail 1: Pass 2 V6_PGOOD R 0 V6 PGOOD STATUS 0: Fail 1: Pass 1 V5_PGOOD R 0 V5 PGOOD STATUS 0: Fail 1: Pass 0 V4_PGOOD R 0 V4 PGOOD STATUS 0: Fail 1: Pass Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.55 PGOOD_STAT2 Register (address = 0xE8) [reset = 00000000] Figure 6-77. PGOOD_STAT2 Register Format B7 B6 B5 RESERVED_P RESERVED_P RESERVED_P GOOD_STAT2[ GOOD_STAT2[ GOOD_STAT2[ 2] 1] 0] 0 0 0 R R R B4 V12_PGOOD B3 V11_PGOOD B2 V11_SPGD B1 V8_SPGD B0 V6_SPGD 0 R 0 R 0 R 0 R 0 R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-58. PGOOD_STAT2 Register Field Descriptions Bit Field Type Reset Description 7:5 RESERVED_PGOOD_STAT2[2:0] R 000 Read Always Returns '1' 4 V12_PGOOD R 0 V12 PGOOD STATUS 0: Fail 1: Pass 3 V11_PGOOD R 0 V11 PGOOD STATUS 0: Fail 1: Pass 2 V11_SPGD R 0 V11S PGOOD STATUS 0: Fail 1: Pass 1 V8_SPGD R 0 V8S PGOOD STATUS 0: Fail 1: Pass 0 V6_SPGD R 0 V6S PGOOD STATUS 0: Fail 1: Pass Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 121 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.56 MISC_BITS Register (address = 0xE9) [reset = 00010000] Figure 6-78. MISC_BITS Register Format B7 V13_PIN_OVR B6 MV13EN B5 V6_PIN_OVR B4 MV6EN B3 msLP_S3ZPG 0 RW 0 RW 0 RW 0 RW 0 RW B2 msLP_SUSZP G 0 RW B1 BC_ACOK_EN B0 V13DISCHG 1 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-59. MISC_BITS Register Field Descriptions Bit 122 Field Type Reset Description 7 V13_PIN_OVR RW 0 V13 ENABLE PIN Over Ride 0: V13 is OFF if MV13EN is '1' 1: V13 is ON if MV13EN is '1' 6 MV13EN RW 0 V13 Enable Pin Mask 0: DDR_VT_CTRL Pin controls V13 1: V13_EN_PIN Bit [Bit(3)] controls V13 5 V6_PIN_OVR RW 0 V6 ENABLE PIN Over Ride 0: V6 Pin controls V6 1: V6 is ON if VREN PIN MASK = '0' 4 MV6EN RW 1 V6 Enable Pin Mask 0: VR Enable Pin controls VR enable 1: VR Enable Pin masked V*CTLV controls VR enable 3 msLP_S3ZPG RW 0 SLP_S3Z is part of the power good tree 0: SLP_S3Z is part of Power Good Tree 1: SLP_S3Z is masked and set to 1 (not part of the Power Good tree) 2 msLP_SUSZPG RW 0 SLP_SUSZ is part of the power good tree 0: SLP_SUSZ is part of Power Good Tree 1: SLP_SUSZ is masked and set to 1 (not part of the Power Good tree) 1 BC_ACOK_EN RW 1 Enables BC_ACOK output out of LVA pin. The in put is ACOK pin, instead of ENLVA pin. 0: LVA pin is not BC_ACOK, and ENLVA is the input for LVA output, behaving as a general purpose level-shifter. 1: LVA pin is BC_ACOK, and ACOK is the input, and ENLVA is not functional. BC_ACOK is a level-shifted version of ACOK. 0 V13DISCHG RW 0 V0.6DX discharge resistance (V13) 0: No discharge 1: 100 Ω Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.57 STDBY_CTRL Register (address = 0xEA) [reset = 11111110] Figure 6-79. STDBY_CTRL Register Format B7 B6 B5 B4 B3 RESERVED_S RESERVED_S RESERVED_S RESERVED_S RESERVED_S TDBY_CTRL[4] TDBY_CTRL[3] TDBY_CTRL[2] TDBY_CTRL[1] TDBY_CTRL[0] 1 1 1 1 1 R R R R R B2 EN_VCOMP_1 0U 1 RW B1 VCOMPEN 1 RW B0 QLSLPS0_ACT IVE 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-60. STDBY_CTRL Register Field Descriptions Bit Field Type Reset Description 7:3 RESERVED_STDBY_CTRL[4:0] R 11111 Read Always Returns '1' 2 EN_VCOMP_10U RW 1 VCOMP Current Source Control bit: 0: Disable 1: Enable 1 VCOMPEN RW 1 VCOMP Enable Control bit: 0: Disable 1: Enable 0 QLSLPS0_ACTIVE RW 0 SLP_S0 & DDR_VTT_CTRL Detect logic Control 0: Normal Operation DELAY_ALL_SYS_PG is used in QSTANDBY# (SLP_S0#) 1: DELAY_ALL_SYS_PG is ignored for QSTANDBY# (SLP_S0#) Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 123 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.58 TEMPCRIT Register (address = 0xEB) [reset = 00000000] Figure 6-80. TEMPCRIT Register Format B7 RESERVED_T EMPCRIT[1] 0 R B6 RESERVED_T EMPCRIT[0] 0 R B5 LDO1_CRIT B4 VR5_CRIT B3 VR4_CRIT B2 VR3_CRIT B1 VR2_CRIT B0 VR1_CRIT 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-61. TEMPCRIT Register Field Descriptions 124 Bit Field Type Reset Description 7:6 RESERVED_TEMPCRIT[1:0] R 00 Read Always Returns '0' 5 LDO1_CRIT RW 0 LDO1 CRITTEMP 0: Not asserted, 1: Asserted, Regulator at critical temperature, write '1' to clear 4 VR5_CRIT RW 0 VR5 CRITTEMP 0: Not asserted 1: Asserted, Regulator at critical temperature, write '1' to clear 3 VR4_CRIT RW 0 VR4 CRITTEMP 0: Not asserted 1: Asserted, Regulator at critical temperature, write '1' to clear 2 VR3_CRIT RW 0 VR3 CRITTEMP 0: Not asserted 1: Asserted, Regulator at critical temperature, write '1' to clear 1 VR2_CRIT RW 0 VR2 CRITTEMP 0: Not asserted 1: Asserted, Regulator at critical temperature, write '1' to clear 0 VR1_CRIT RW 0 VR1 CRITTEMP 0: Not asserted 1: Asserted, Regulator at critical temperature, write '1' to clear Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 6.6.1.59 TEMPHOT Register (address = 0xEC) [reset = 00000000] Figure 6-81. TEMPHOT Register Format B7 RESERVED_T EMPHOT[1] 0 R B6 RESERVED_T EMPHOT[0] 0 R B5 LDO1_HOT B4 VR5_HOT B3 VR4_HOT B2 VR3_HOT B1 VR2_HOT B0 VR1_HOT 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-62. TEMPHOT Register Field Descriptions Bit Field Type Reset Description 7:6 RESERVED_TEMPHOT[1:0] R 00 Read Always Returns '1' 5 LDO1_HOT RW 0 LDO1 HOT TEMP 0: Not asserted 1: Asserted, write '1' to clear 4 VR5_HOT RW 0 VR5 HOT TEMP 0: Not asserted 1: Asserted, write '1' to clear 3 VR4_HOT RW 0 VR4 HOT TEMP 0: Not asserted 1: Asserted, write '1' to clear 2 VR3_HOT RW 0 VR3 HOT TEMP 0: Not asserted 1: Asserted, write '1' to clear 1 VR2_HOT RW 0 VR2 HOT TEMP 0: Not asserted 1: Asserted, write '1' to clear 0 VR1_HOT RW 0 VR1 HOT TEMP 0: Not asserted 1: Asserted, write '1' to clear Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 125 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 6.6.1.60 VREN_PIN_OVR Register (address = 0xEE) [reset = 00000000] Figure 6-82. VREN_PIN_OVR Register Format B7 V12_PIN_OVR 0 RW B6 V11_PIN_OVR 0 RW B5 V10_PIN_OVR 0 RW B4 V9_PIN_OVR 0 RW B3 V8_PIN_OVR 0 RW B2 V7_PIN_OVR 0 RW B1 V5_PIN_OVR 0 RW B0 V4_PIN_OVR 0 RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-63. VREN_PIN_OVR Register Field Descriptions Bit 126 Field Type Reset Description 7 V12_PIN_OVR RW 0 V12 ENABLE PIN Over Ride 0: V12 Pin controls V12 1: V12 is ON if VREN PIN MASK = '0' 6 V11_PIN_OVR RW 0 V11 ENABLE PIN Over Ride 0: V11 Pin controls V11 1: V11 is ON if VREN PIN MASK = '0' 5 V10_PIN_OVR RW 0 V10 ENABLE PIN Over Ride 0: V10 Pin controls V10 1: V10 is ON if VREN PIN MASK = '0' 4 V9_PIN_OVR RW 0 V9 ENABLE PIN Over Ride 0: V9 Pin controls V9 1: V9 is ON if VREN PIN MASK = '0' 3 V8_PIN_OVR RW 0 V8 ENABLE PIN Over Ride 0: V8 Pin controls V8 1: V8 is ON if VREN PIN MASK = '0' 2 V7_PIN_OVR RW 0 V7 ENABLE PIN Over Ride 0: V7 Pin controls V7 1: V7 is ON if VREN PIN MASK = '0' 1 V5_PIN_OVR RW 0 V5 ENABLE PIN Over Ride 0: V5 Pin controls V5 1: V5 is ON if VREN PIN MASK = '0' 0 V4_PIN_OVR RW 0 V4 ENABLE PIN Over Ride 0: V4 Pin controls V4 1: V4 is ON if VREN PIN MASK = '0' Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 7 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 7.1 Application Information The TPS65083x can be used in several different applications from computing, industrial interfacing and much more. This section describes the general application information and provides more detailed description on the TPS65083x powering the Intel SkyLake and Kabylake system. 7.2 Typical Application The TPS65083x can be used in any system that needs multiple voltage rails. A DC supply voltage in between 5.4 V and 21 V is required. If the supply voltage is less than this range then a small boost can be added to supply the VIN and VINLDO3. Along with the 5 DCDCs and 1 LDO, the TPS65083x has 8 general purpose comparators, 2 level shifters, board temperature monitoring system and 3 power path comparators. Latter 2 can be used as simple comparators if desired increasing the total comparators available for use to 12 on the TPS65083x. Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 127 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Adaptor / AC VIN Battery1 Battery2 BAT2SWONZ BAT1SWONZ ACSWONZ VIN Cin ACIN BAT1 BAT2 Power Path Comparators PTC DRVHVR1 VBSTVR1 System Level Power Goods, INT, and Resets SWVR1 Vout 0.1 PF VCOMP VR1 Controller VCOMP TRIPZ Cout DRVLVR1 PGNDVR1 Comparator Block Pull-up source VSx [A-H] FBVR1P FBVR1N 8 ILIMVR1 ENx [A-H] Rcs VIN Cin 8 DRVHVR3 VBSTVR3 PGx [A-H] 8 SWVR3 VR3 Controller 2 2 Level Shifters Vout 0.1 PF Cout DRVLVR3 PGNDVR3 FBVR3P FBVR3N ILIMVR3LS Digital & Control Block VIN5VSW Rcs ILIMVR3HS VIN Cin Rcs (HS) EN5VSW DRVHVR5 VBSTVR5 Load Switches EN3V3SW SWVR5 Vout 0.1 PF VOUT3V3SW VIN VR5 Controller VINLDO3 VIN 1 PF LDO3V 4.7 PF Cout DRVLVR5 PGNDVR5 FBVR5P FBVR5N Internal LDOs & Supplies ILIMVR5LS LDO5V 10 PF DRVHVR4 VBSTVR4 SWVR4 PGNDVR2 Vout 0.1 PF Cout DRVLVR4 PGNDVR4 FBVR4N FBVR4P FBVR4N VINLDO1 VINLDO1S PGNDLDO1 SWVR2 LDO1 VOUTLDO1 Lout FBVR2N FBVR2P VR2 Converter SCL SDA SLAVEADDR Cout VR4 Controller VINVR2 Cin Vout Cin I2C Block VREF1V25 100 Q VIN Rcs (HS) 0.47 PF 3.3V Rcs ILIMVR5HS ILIMVR4 Rcs Cout Vout Cin Copyright © 2016, Texas Instruments Incorporated Figure 7-1. Simplifed General Block Diagram 128 Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com 7.2.1 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Design Requirements The TPS65083x requires decoupling caps on the supply pins. Refer to the Electrical Characteristics for recommended capacitance on these supplies. The controllers, converter, LDO, and some other features can be adjusted to meet the application needs. The following describes how to design and adjust the external components to achieve desired performances. 7.2.2 Detailed Design Procedure 7.2.2.1 Controller Design Procedure Designing the controller breaks down into several steps: designing the output filter, selecting the FETs, bootstrap capacitor, and input capacitors and setting the current limits. Controllers VR1 and VR4 require VREG supply and capacitors. VREG should be connected to the 5-V LDO and a 1-µF, X5R, 20%, 10-V or similar capacitor should be used for decoupling. VIN DRVHVRx VBSTVRx Cin Lout LDO5V VREGVRx SWVRx Vout 0.1 PF 1 PF Controller Cout DRVLVRx PGNDVRx ILIMVRx Rcs PGNDVRx ENVRx FBVRxP FBVRxN PGVRx Copyright © 2016, Texas Instruments Incorporated Figure 7-2. Controller Diagram 7.2.2.1.1 Selecting the Inductor An inductor is required to be placed between the external FETs and the output capacitors. The inductor and output capacitors together make the double-pole which contributes towards stability. In addition, the inductor is directly responsible for the output ripple, efficiency, and transient performance. With an increase in inductance used the ripple current decreases which, typically increases efficiency. However, with an increase in inductance used, the transient performance decreases. Finally, the inductor selected has to be rated for appropriate saturation current, core losses, and DC resistance (DCR). Use the equation below to calculate the recommended inductance for the controller. Let KIND be the ratio of ILripple to the IoutMAX. It is recommended that KIND is set to a value between 0.2 and 0.4. .= 8+0 8176 × :8+0 F 8176 ; × B59 × +KQP/#: × -+0& (1) Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 129 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com With the chosen inductance value, the peak current for the inductor in steady state operation, ILmax, can be calculated using the equation below. The rated saturation current of the inductor must be higher than the ILmax current. :8+0 F 8176 ; × 8176 +.I=T = +KQPI=T + J K 2 × 8+0 × B59 × . (2) Following these equations the preferred inductor selected for the controllers are listed below in Table 7-1. Table 7-1. Recommended Inductors MANUFACTURER PART NUMBER VALUE SIZE HEIGHT Cyntec PIME031B 0.47 µH - 1 µH 3.3 mm x 3.7 mm 1.2 mm Cyntec PIMB041B 0.33 µH - 2.2 µH 4.45 mm x 4.75 mm 1.2 mm Cyntec PIMB051B 1 µH - 3.3 µH 5.4 mm x 5.75 mm 1.2 mm Cyntec PIME051E 0.33 µH - 4.7 µH 5.4 mm x 5.75 mm 1.5 mm Cyntec PIMB051H 0.47 µH - 4.7 µH 5.4 mm x 5.75 mm 1.8 mm Cyntec PIME061B 0.56 µH - 3.3 µH 6.8 mm x 7.3 mm 1.2 mm Cyntec PIME061E 0.33 µH - 4.7 µH 6.8 mm x 7.3 mm 1.5 mm Cyntec PIMB061H 0.1 µH - 4.7 µH 6.8 mm x 7.3 mm 1.8 mm 7.2.2.1.2 Selecting the Output Capacitors Ceramic capacitors with low ESR values provide the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on the output capacitor value and the PFM peak inductor current. Higher output capacitor values minimize the voltage ripple in PFM Mode. In order to achieve specified regulation performance and low output voltage ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic capacitors drops with increasing DC bias voltage. For the output capacitors of the DCDC controller the use of a small ceramic capacitors placed as close as possible to the inductor and the respective PGND pins of the IC is recommended. This solution typically, provides the smallest and lowest cost solution available for DCAP2 controllers. 7.2.2.1.3 Selecting the FETs This controller is designed to drive NMOS FETs. Typically, the lower RDSon for the high and low side FETs the better but, be sure to size the FETs, inductor and output capacitors appropriately as the RDSon for the low side FET decreases, the minimum current limit increases. The Texas Instruments CSD87381P is recommended for the controllers. 130 Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 7.2.2.1.4 Bootstrap Capacitor To make sure that the internal high side gate drivers are supplied with a stable low noise supply voltage, a capacitor must be connected between the VBSTVRx pins and the respective SWVRx pins. Using ceramic capacitors with the value of 0.1 µF are recommended for the converters and the controllers, respectfully. For testing, a 0.1-µF, size 0402, 10-V capacitor was used for the controllers. It is recommended to reserve a small resistor in series with the bootstrap capacitor in case the turn on / off of the FETs need to be slowed in order to reduce voltage ringing on the switch node. This is common practice for controller design. 7.2.2.1.5 Setting the Current Limits The controller has a Valley Current Limit topology, also known as a Low Side Current Limit. This type of current limit works by limiting the current only when the low side FET is on. If the current being sourced by the low side FET is greater than the set low side current limit, ILS, the controller will hold the low side FET on and the high side off until the current through the low side FET decreases below the set ILS. Only if the current through the low side FET is less than the ILS will the low side FET be allowed to turn off and the high side FET to turn on. A fast current increase is limited by the maximum on time for the high side FET. This forces the low side FET to turn on every period. Once the low side FET turns on, the Low Side Current Limit can control the FETs until the current decreases below the ILS. The maximum on time for the high side FET limits the current increase to maximum on time multiplied by the di/dt of the inductor until the low side FET is switched on. IOCL is the average current when the valley current is consistently the ILS. IOCL ILS Figure 7-3. IOCL Depiction The low side current limit for the controllers is set by a resistor, RCS, at the ILIMx pin. A current, ITRIP, is sourced across the RCS to set the voltage for the current limit comparator. Use the equation below to determine the RCS resistor. It is recommended to set IOCL to 130% of IOUTmax and use a resistor with ±1% or less tolerance for best results. Since the current limit is when the inductor current is near its maximum it is recommended to use the saturation derating of the inductor when calculating the RCS. 4%5 = 8 × 4&5KJ × 1.3 × l+1%. F :8+0 F 8176 ; × 8176 p 2 × . × B59 × 8+0 +64+2 (3) There is a minimum and a maximum IOCL that can be achieved for the given parameters used in the equation above. To ensure that the RCS has been sized correctly, the following equation must be true across the application temperature range. 8%5IEJ < +64+2 × 4%5 < 8%5I=T (4) Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 131 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com If the controller has high side current limit then, use Equation 5 to calculate the high side RCS resistor. The high side current limit must be set higher than the low side current limit. Again, since the current limit is when the inductor current is near its maximum it is recommended to use the saturation derating of the inductor when calculating the RCS. 4%5 (*5) = :8 F 8176 ; × 8176 l4&5KJ × l+1%. + +0 pp 2 × . × B59 × 8+0 n F 8µ#r × 20GÀ 3200À +64+2 (5) 7.2.2.1.6 Selecting the Input Capacitors Because of the nature of the switching converter and controller with a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For the controller, 12 µF of input capacitance is recommended for most applications. To achieve the low ESR requirement, a ceramic capacitor is recommended. However, the voltage rating and DC bias characteristic of ceramic capacitors need to be considered. The input capacitor can be increased without any limit for better input voltage filtering. Be sure to size the ceramic capacitor to achieve the recommended input capacitance. A ceramic capacitor placed as close as possible to the respective VINx and PGNDx pins of the FETs is recommended. The preferred capacitors for the controllers are two muRata GRM21BR61E106MA73: 10 μF, 0805, 25 V, ±20% or similar. 7.2.2.2 Converter Design Procedure Designing the converter has only 2 steps: designing the output filter and selecting the input capacitors. The converter must be supplied by a 3.3-V source which can be provided by one of the TPS65083x controllers. The converter requires VREG supply and capacitors. VREG should be connected to the 5-V LDO and a 1µF, X5R, 20%, 10-V or similar capacitor should be used for decoupling. Lout VINVR2 3.3V Vout SWVR2 LDO5V Cin VREGVRx 1 PF Cout FBVR2P FBVR2N Converter 100 PGVRx ENVRx PGNDVR2 Copyright © 2016, Texas Instruments Incorporated Figure 7-4. Converter Diagram 132 Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 7.2.2.2.1 Selecting the Inductor An inductor is required to be placed between the SWVRx and the output capacitors. The inductor and output capacitors together make the double-pole which contributes towards stability. In addition, the inductor is directly responsible for the output ripple, efficiency, and transient performance. With an increase in inductance used the ripple current decreases which, typically increases efficiency. However, with an increase in inductance used, the transient performance decreases. Finally, the inductor selected has to be rated for appropriate saturation current, core losses and DC resistance (DCR). Use the equation below to calculate the recommended inductance for the controller. Let K IND be the ratio of I Lripple to the Iout MAX. It is recommended that K IND is set to a value between 0.2 and 0.4. .= 8+0 8176 × :8+0 F 8176 ; × B59 × +KQP/#: × -+0& (6) With the chosen inductance value, the peak current for the inductor in steady state operation, I - Lmax , can be calculated using the equation below. The rated saturation current of the inductor must be higher than the I Lmax current. :8+0 F 8176 ; × 8176 +.I=T = +KQPI=T + J K 2 × 8+0 × B59 × . (7) Following these equations the preferred inductors selected for the converter are listed below in Table 7-2. Table 7-2. Recommended Inductors MANUFACTURER PART NUMBER VALUE SIZE HEIGHT Cyntec PIFE32251B-R68MS 0.68 µH 3.2 mm x 2.5 mm 1.2 mm Würth 744383230068 0.68 µH 2.5 mm x 2 mm 1.0 mm 7.2.2.2.2 Selecting the Output Capacitors Ceramic capacitors with low ESR values provide the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on the output capacitor value and the PFM peak inductor current. Higher output capacitor values minimize the voltage ripple in PFM Mode. In order to achieve specified regulation performance and low output voltage ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic capacitors drops with increasing DC bias voltage. For the output capacitors of the DCDC converters the use of a small ceramic capacitors placed as close as possible to the inductor and the respective PGND pins of the IC is recommended. If, for any reason, the application requires the use of large capacitors which can not be placed close to the IC, use a smaller ceramic capacitor in parallel to the large capacitor. The small capacitor should be placed as close as possible to the inductor and the respective PGND pins of the IC. At the DCDC converters the recommended capacitor for use is the muRata GRM188R60J226MEAO: 22 µF, 0603, 6.3 V, ±20% or similar. This capacitor was selected to achieve the highest derated capacitance in a small 0603 package. If the selected output voltage is greater than 3.3 V then the muRata GRM21BR61A226ME44: 22 µF, 0805, 10 V, ±20%, or similar is recommended for use. This capacitor is recommended to maintain the actual capacitance as DC bias increases. Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 133 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 7.2.2.2.3 Selecting the Input Capacitors Because of the nature of the switching converter and controller with a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For the controller, 12 µF of input capacitance is recommended for most applications. To achieve the low ESR requirement, a ceramic capacitor is recommended. However, the voltage rating and DC bias characteristic of ceramic capacitors need to be considered. The input capacitor can be increased without any limit for better input voltage filtering. Be sure to size the ceramic capacitor to achieve the recommended input capacitance. A ceramic capacitor placed as close as possible to the respective VINx and PGNDx pins of the IC is recommended. The preferred capacitors for the controllers are two muRata GRM21BR61E106MA73: 10 μF, 0805, 25 V, ±20% or similar. 7.2.2.3 LDO Design Procedure The LDO must handle the fast load transients from the DDR memory for termination. Therefore, it is important to maintain a high amount of capacitance with low ESR on the LDO outputs and inputs. Ceramic capacitors are ideal for this. Below is the recommended capacitors. The preferred output capacitor for the LDO is muRata GRM188R60J476M: 47 μF, 0603, 6.3 V, ±20% or similar. The preferred input capacitor for the LDO is muRata GRM155R60J106ME44: 10 μF, 0402, 6.3 V, ±20% or similar. 7.2.2.4 Board Temperature Monitoring Design Procedure Board temperature monitoring requires only 1 thermistor if only 1 sense point is desired. It can be scaled by adding as many thermistors as sense points desired. Simply connect a PTC thermistor that has an exponential coefficient curve from the VCOMP pin to GND and a pull up to desired voltage source on the TRIPZ pin. Place thermistor where desired. If multiple sense points are desired string the thermistors together in a series connection while placing the thermistors where desired. 10µA 100k VCOMP Pin TRIPZ Pin RT1 + ± VREF = 1.25V RT2 RT3 RT4 Copyright © 2016, Texas Instruments Incorporated Figure 7-5. Board Temperature Monitoring Circuit Example 134 Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 The thermistors should have low room and mid temperature resistances in the range of 1 kΩ to 10 kΩ. The hot point resistance should be roughly 10x mid temperature resistance in the range of 100 kΩ to 200 kΩ. There is an internal 10-µA current source that provides a voltage across the thermistors. Once this voltage exceeds the comparator threshold of 1.25 V the TRIPZ pin switches to LOW indicating a HOT board temperature. Therefore, the resistance required for HOT board temperature is 125 kΩ. Select thermistors that align this resistance with the desired HOT temperature setpoint. The recommended thermistors for this feature is the muRata PRF15BG102RB6RC. 7.2.2.5 Power Path Design Procedure The TPS65083x has power path comparators and outputs to control the power path switches. Simply connect a voltage divider to the adaptor and batteries to set the threshold to the desired value. The outputs of the comparators require a pull up since they are open-drain outputs. In-order for the power path comparators to work without VIN supplied connect the VINPP to the power rails that are being monitored by using a diode to select the highest voltage among the sources. Adaptor Battery 1 Battery 2 R1a R1b VINPP Pull Up R1c Pull Up Pull Up TPS65083x ACIN BAT1IN BAT2IN R2a R2b ACOUT BAT1OUT BAT2OUT R2c Copyright © 2016, Texas Instruments Incorporated Figure 7-6. Power Path Comparators and VINPP Supply Example: Desired is to measure a battery and an adaptor to decide when to switch over from battery to adaptor. The voltages desired for thresholds are 9 V and 6 V respectively. Using Equation 8 the resistors required to set the 9-V threshold are R1a = and R2a = . The resistors required to set the 6-V threshold are R1b = and R2b = . 8+0 41 = 42 × l F 1p 86DNAO DKH@ (8) Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 135 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 7.2.3 www.ti.com Application Performance Curves Table 7-3. Application Curves Overview TYPE DESCRIPTION AND ASSUMPTIONS FIGURE NUMBER Efficiency VR1 Using CSD87381P FET Block, PIME051H-1R0MS, 3 x GRM31CR60G227ME11 + 1 x GRM21BR60J107M, NDVCZ = HIGH, Vout = 1 V Figure 7-7 Efficiency VR2 Using PIFE32251B-R68MS, 4 x ZRB18AR60G476ME01, NDVCZ = HIGH, Vout = 1.8 V Figure 7-8 Efficiency VR3 Using CSD87381P FET Block, PIMB061H-1R5MS, 3 x GRM21BR60J107M , NDVCZ = HIGH, Vout = 3.3 V Figure 7-9 Efficiency VR4 Using CSD87381P FET Block, PIME051H-1R0MS, 2 x GRM31CR60G227ME11 + 1 x GRM21BR60J107M, NDVCZ = HIGH, Vout = 1.2 V Figure 7-10 Efficiency VR5 Using CSD87381P FET Block, PIMB051H-3R3MS, 11 x GRM21BR61A476ME15, NDVCZ = HIGH, Vout = 5 V Figure 7-11 100 100 90 90 80 80 70 70 VR2 Efficiency (%) VR1 Efficiency (%) spacing 60 50 40 30 Vin=5.40V Vin=8.70V Vin=15.00V Vin=24.00V 20 10 1 2 3 4 5 6 Iout (A) 50 40 30 20 Vin=2.97V Vin=3.30V Vin=3.63V 10 0 0 60 0 0.0 7 90 80 80 70 70 VR4 Efficiency (%) VR3 Efficiency (%) 100 90 60 50 40 30 Vin=5.40V Vin=8.70V Vin=15.00V Vin=24.00V 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Iout (A) D001 Figure 7-9. Typical Efficiency for VR3 136 1.5 2.0 2.5 D001 Figure 7-8. Typical Efficiency for VR2 100 10 1.0 Iout (A) Figure 7-7. Typical Efficiency for VR1 20 0.5 D001 60 50 40 30 Vin=5.40V Vin=8.70V Vin=13.50V Vin=24.00V 20 10 0 0 1 2 3 4 Iout (A) 5 6 7 D001 Figure 7-10. Typical Efficiency for VR4 Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 100 90 VR5 Efficiency (%) 80 70 60 50 40 30 Vin=5.40V Vin=8.70V Vin=13.50V Vin=24.00V 20 10 0 0 0.5 1 1.5 2 Iout (A) 2.5 3 3.5 D001 Figure 7-11. Typical Efficiency for VR5 Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 137 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 7.2.4 www.ti.com Specific Application - TPS650830 Powering the Intel SkyLake and Kabylake Platform Volume Configuration Volume configuration is the lowest cost and smallest solution for SkyLake and Kabylake power. It combines multiple same voltage rails into one rail reducing cost and size. Load switches are utilized to separate the rails and power the system with correct sequencing. The PMIC controls these load switches with the power good comparators. The TPS65083x also supports Premium configurations, see TPS650831 and TPS650832 or literature numbers: SLVSCS5 and SLVSCS6. All Pullup Resistors 100kohm, unless noted VDDIO Comp_PG_mod e COMP A 1 - COMP B 1 0 Enable Logic ENB & V18U25UCNT ENB & V18U25UCNT COMP C - - ENC COMP D 1 0 END & VCCIOCNT END & VCCIOCNT COMP E 1 0 ENE ENA & V33APCHCNT PGOOD C COMP F 1 0 ENF V33APCH V18U25U COMPIN_C V33S PGOOD F V18S V100S COMP G 1 - ENG PGOOD G LS_INC V5ADS3_PG V12U_PG V100S_PG SLP_S4Z COMPEN_C V12U_PG & V100S_PG SLP_SUSZ SLP_S3Z LS_INB V33APCH_PG V18U25ULSW COMPOUT_C VCCIOLSW Rpull-up Shared with V12U_PG V33A_DSW V33A_DSW V33APCHLSW V1.8S_PG V100S_PG LS_OUTC ENA ENB ENC END ENE ENF ENG ENH PGA PGB PGC PGD PGE PGF PGG PGH VDDPG REF DCH V33A_DSW TTL PG EN VSET TTL OD/PP EN/ PGOOD LOGIC DIGCORE FBVR2P VR1 Controller PGNDVR2 VDDIO V18A_PG DRVHVR1 Vout range 0.95v-1.05v ENVR2 EN VSET OEM VCOMP V3P3A_RTC TRIPZ OD/PP TTL VDDIO FBVR5P PG I2C AND REGFILE VR3 Controller DTMODE Vout 5V FBVR3P VBSTVR3 Vout 3.3V DRVHVR3 VDDIO PGNDVR3 ENVR3 VDDIO REFSYS LDO5V VLDO5 VREF1V25 PGA PGB PGC PGD LDO3V VOUT3V3SW EN3V3SW VDC VINLDO3 DFT AND AMUX 3L TTL SLAVEADDR AGND [4] OD DIETEMP VLDO3 VIN5VSW SW EN5VSW TTL SW TTL EN3V3SW EC FROM EC LEGEND TTL = TTL LEVEL INPUT BUFFER 3L = 3 LEVEL (HI/LO/HI-Z) INPUT BUFFER PP = PUSH-PULL OUTPUT BUFFER PPB = PUSH PULL OUTPUT BUFFER WITH HI-Z MODE (TEST ONLY) OD = OPEN DRAIN OUTPUT BUFFER TR = PUSH-PULL WITH CONTROLLED Tr OD/PP = OPEN-DRAIN OR PUSH PULL PGNDVR3 VLDO3 VIN UVLO VPROGOTP VDDIO [2X] OD SDA VLDO3 TEMP_ALERTZ TTL V100S ENVR5 SCLK VDDIO VDDIO TTL 50ohm V33A_DSW DRVLVR3 OTP ILIMVR5LS SLP_SUSZ VDC TTL DRVLVR5 VREGVR1 PGNDVR5 PGNDVR5 V33APCH SWVR3 Vout range 4.9v-5.1v SWVR5 V33S FBVR3N Vout range 3.23v-3.34v VBSTVR5 DRVHVR5 V33APCHLSW SLP_S3Z VDC ILIMVR3LS EN VSET EN VSET VR5 Controller V33ADSW_PG VREGVR4 VINVR3 ILIMVR3HS EN/ PGOOD LOGIC EN/ PGOOD LOGIC THERMs NVDCZ TTL VDDIO V18U25U TH_HOTZ VCOMP PGVR3 OD/PP VDDIO VDDIO ILIMVR5HS FBVR5N V5ADS3 V18U25ULSW V18S VBATTBKUP BACKUP BATTERY SELECTOR V33ARTC RTC DIG EN/ PGOOD LOGIC PG Vout 1.00V ENVR1 V18A_EN/ DPWROK TTL VINVR5 VDC PGVR2 OD/PP VDDIO OD/PP AGND VLDO5 FBVR2N PGNDVR2 [2X] SLP_S3Z VBSTVR1 OD/PP VCCIO(V0975) V18A VREGVR2 Vout 1.8V 2A max c VDDLV PGVR5 VDCSNS V33A_DSW SWVR2 [2X] Vout range 1.76v-1.85v VDDLVS SLP_S3Z V5ADS3_PG BAT2SWONZ PGNDLDO1 VINVR2 [2X] VDDIO V33APCH_PG HV OD ACIN LDO1 SINK/SRC LDO VOUTLDO1[2X] V0.6DX/0.675DX FBLDO1 /0.55DX Vout= (VR4)/2 1A max PGNDVR1 VCCIOLSW BAT1SWONZ BAT2 VINLDO1[2X] EN EN LOGIC PGNDVR1 V100S SLP_S4Z DDR_VTT_CTRL PGNDLDO1[2X] DRVLVR1 V085A ENVR4 VR2 Converter LVB PGVR1 DDRID DDR_VTT_CTRL OD/PP SWVR1 VR1_PG DDRID VINDLO1S VDDPG FBVR1P V100A PGNDVR4 PGNDVR4 ILIMVR1 FBVR1N VDC DRVLVR4 Vout 1.2V/ 1.35V/1.1V TTL SEQ + INTEL AND OEM LOGIC VREGVR1 VLDO5 V9,V4,V33S PGOOD DO NOT HAVE PINS! VDC SWVR4 3L VDDIO LVA V12U DRVHVR4 VDDIO ENLVA BCACOK LS_OUTB VBSTVR4 VDDIO VDDIO AGND FBVR4P TTL V33A_DSW V33A_DSW (EC_VCC) PG EN VSET EN/ PGOOD LOGIC VDDIO FBVR4N VR4 Controller Vout Range 1.056V1.391V PP VSA VSB VSC VSD VSE VSF VSG VSH VCCIO(V0975) ACSWONZ VDDIO VDDIO RESETZ V33A_DSW VLDO5 ILIMVR4 PPATH LOGIC PGOOD A BAT1 VREGVR4 Pgood_logic ENA & V33APCHCNT V12U_PG OD/PP PP Comp_Mode Rpull-up Shared with V100S_PG PGVR4 VDDIO Volume #1 COMP COMP VOLUME #1 Application Block Diagram: V12(V085A) = No Load Sw, V11 (V1.00A) = No Load Sw DPWROK VINPP EC_RSTZ EC_ONOFFZ PCH_PWRBTNZ DPWROK RSMRSTZ_PWRGD PMIC_INTZ POWER MONITOR OD TTL EC_VCC PCH_PWROK ALL_SYS_PWRGD VDDIO ACOK 1HZ VCCST_PWRGD SYS_PWROK TTL VDDIO HIV VREF RAM VDDIO TTL TTL PP STANDBYZ V33A_DSW (EC_VCC) V100S PWRBTNIN ECVCC DS3_VREN SHUTDOWNZ LDO3 SLP_S0Z V33A_DSW V33A_DSW V3.3S ACOK TPS650830 V5ADS3_PG VLDO5 V5A_DS3 AGND AGND AGND GROUND PLANE AGND PGNDVR2 PGNDVR1 PGNDVR4 PGNDVR3 PGNDLDO1 PGNDVR5 Copyright © 2016, Texas Instruments Incorporated Figure 7-12. TPS650830 Volume Application Diagram 138 Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com 7.2.4.1 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Design Requirements The deisgn requirements are set by the Intel SkyLake and Kabylake Platform. Below are the requirements of the power supply system. This procedure assumes the system is a 2S NVDC system but, the TPS65083x supports 3S NVDC, as well as non-NVDC systems. 2S NVDC system has an input voltage range of 5.4 V to 8.7 V. • There must be 9 separate voltage rails: – V5A_DS3 - 5 V, IMAX = 3.5 A – V3.3A_DSW - 3.3 V, IMAX = 3.5 A – V3.3A_PCH - 3.3 V, IMAX = 3 A – V1.00A - 1.0 V, IMAX = 4.9 A – VCCIO - 1.0 V, IMAX = 2.9 A – V1.8A - 1.8 V, IMAX = 1 A – V1.8U - 1.8 V, IMAX = 1 A – VDDQ - 1.2 V, IMAX = 7.5 A – VTT - 0.6 V, IMAX = ±1A • All rails must have maximum tolerance of ±5% of the nominal voltage at all times with load transients. – Load Transients are defined as 0% to 70%, 70% to 0%, 30% to 100% and 100% to 30% load current steps relative of the IMAX current defined for each rail. • Maximum height of components = 1.8 mm. • Sequence in the order below: – V3.3A_DSW with VIN supplied – V1.8A with VIN supplied – V5A_DS3 with SLP_SUS# transition to HIGH – V3.3A_PCH with SLP_SUS# transition to HIGH – V1.00A with SLP_SUS# transition to HIGH – VDDQ with SLP_S4# transition to HIGH – V1.8U with SLP_S4# transition to HIGH – VCCIO with SLP_S3# transition to HIGH – VTT with DDR_VTT_CTRL / SLP_S0# transition to HIGH 7.2.4.2 Detailed Design Procedure The TPS650830 supplies 6 voltage rails and controls 3 load switches to meet the sequence order for the V3.3A_PCH, V1.8U, and VCCIO rails. • VR1 supplies the V1.00A rail and the VCCIO rail with a load switch. • VR2 supplies the V1.8A rail and the V1.8U rail with a load switch. • VR3 supplies the V3.3A_DSW rail and the V3.3A_PCH rail with a load switch. • VR4 supplies the VDDQ rail and the VINLDO1 for termination. • VR5 supplies the V5A_DS3 rail. • VLDO1 supplies the VTT rail. To meet the sequencing requirement the power goods of the VRs and PG comparators are feed back into the enables for the VRs and comparators. The 5 external control signals SLP_SUS#, _S4#, _S3#, _S0#, and DDR_VTT_CTRL are responsible for transitioning the system from sleep state to sleep state and the reverse sequencing. Since, the requirements are for a 2S NVDC system the NVDCZ pin should be tied LOW. Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 139 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 7.2.4.2.1 Output Inductance and Capacitance Following the recommend design procedure in Section 7.2.2 will yield output inductance and capacitance similar to Table 7-4. Table 7-4. SkyLake and Kabylake Volume Configuration Output L and C VRx OUTPUT INDUCTANCE MINIMUM OUTPUT CAPACITANCE RECOMMENDED OUTPUT CAPACITORS CAPACITOR MANUFACTURER VR1 0.56 µH 160 µF 1 x GRM31CR60G227ME11 and 1 x ZRB18AR60G476ME01 muRata VR2 0.68 µH 47 µF 4 x ZRB18AR60G476ME01 muRata VR3 1 µH 87 µF 2 x GRM31CR60G227ME11 muRata VR4 0.56 µH 117 µF 1 x GRM31CR60G227ME11 muRata VR5 2.2 µH 76 µF 8 x GRM21BR61A476ME15 muRata 7.2.4.3 Application Performance Curves Table 7-5. Application Curves Overview TYPE DESCRIPTION AND ASSUMPTIONS FIGURE NUMBER Efficiency VR1 Using CSD87381P FET Block, PIMB051H-0R56M, 1 x GRM31CR60G227ME11 + 1 x ZRB18AR60G476ME01, NDVCZ = LOW, Vout = 1 V Figure 7-13 Efficiency VR2 Using PIFE32251B-R68MS, 4 x ZRB18AR60G476ME01, NDVCZ = LOW, Vout = 1.8 V Figure 7-14 Efficiency VR3 Using CSD87381P FET Block, PIME051H-1R0MS, 2 x GRM31CR60G227ME11, NDVCZ = LOW, Vout = 3.3 V Figure 7-15 Efficiency VR4 Using CSD87381P FET Block, PIMB051H-0R56M, 1 x GRM31CR60G227ME11, NDVCZ = LOW, Vout = 1.2 V Figure 7-16 Efficiency VR5 Using CSD87381P FET Block, PIME051B-2R2MS, 8 x GRM21BR61A476ME15, NDVCZ = LOW, Vout = 5 V Figure 7-17 100 100 90 90 80 80 70 VR2 Efficiency (%) VR1 Efficiency (%) space 60 50 40 30 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 20 10 1 2 3 4 Iout (A) 5 6 50 40 Vin=2.97V Vin=3.30V Vin=3.63V 20 10 0.0 7 0.5 1.0 1.5 2.0 Iout (A) D001 Figure 7-13. Typical Efficiency for VR1 140 60 30 0 0 70 2.5 D001 Figure 7-14. Typical Efficiency for VR2 Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 100 100 90 90 80 80 70 70 VR4 Efficiency (%) VR3 Efficiency (%) www.ti.com 60 50 40 30 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 20 10 60 50 40 30 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Iout (A) D001 0 0 Figure 7-15. Typical Efficiency for VR3 1 2 3 4 Iout (A) 5 6 7 D001 Figure 7-16. Typical Efficiency for VR4 100 90 VR5 Efficiency (%) 80 70 60 50 40 30 Vin=5.40V Vin=8.10V Vin=8.70V Vin=13.50V 20 10 0 0.00 0.50 1.00 1.50 2.00 Iout (A) 2.50 3.00 3.50 D001 Figure 7-17. Typical Efficiency for VR5 Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 141 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 7.3 www.ti.com System Example Below is a diagram of the SkyLake and Kabylake Platform System Power Delivery. The PMIC is flexible and adjusts well across SkyLake and Kabylake platforms. TPS650830 VOLUME AC/DC Adaptor FET FET NVDC Charger 6V - 8.4V 2S Battery Pack FET Vcore FET Driver FET FET Driver FET FET FET SMBus VCCSA SKYLAKE KABYLAKE PLATFORM SVID ALERT# TPS650830 - PMIC FET VCORE VCCGT V5ADS3 5V, 3.55A FET FET 3.3V, 6.6A FET FET FET V3.3A_DSW LOAD V3.3S SWITCH Protection V1.8A 1.8V, 1.8A EC Embedded Controller SMBus Gas Gauge 1.00V, 6.81A FET FET 1.2V, 7.47A FET FET LOAD V3.3A_PCH SWITCH 1.00V LOAD V1.8U_V2.5U SWITCH LOAD V1.8S SWITCH V0.85A Legend: V1.2U Power bus Signal Wire I2C 0.6V, 1.2A V0.6DX V1.00A LOAD VCCIO SWITCH LOAD V1.0S SWITCH Integrated FET regulator External FET regulator Copyright © 2016, Texas Instruments Incorporated Figure 7-18. TPS650830 Volume Simplified System Power Configuration Diagram 7.4 Do's and Don'ts • • 142 Always either float or connect the VINPP to the same voltage as VIN. Never ground VINPP. If not using a voltage regulator connect the enable to ground and float the output. Application and Implementation Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 8 Power Supply Recommendations Any power supply capable of delivering the required input power is acceptable provided that there is a source within the recommended operating conditions for VIN and VINLDO3. The input voltage for the VR2 converter must be 3.3 V always. The input voltage of the controllers may vary from the VIN and VINLDO3 voltage. Ensure that VINPP is connected to the VIN or floated but not grounded. Power Supply Recommendations Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 143 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 9 Layout 9.1 Layout Guidelines For all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC. There are 2 packages available for the TPS65083x, the ZAJ and ZCG. The ZAJ is a 7-mm x 7-mm BGA with 0.5-mm ball pitch. The ZCG is a 9-mm x 9-mm BGA with 0.5-mm ball pitch but, some of the inner balls have been removed for easier routing. Both packages preform relatively the same and the decision between which package is best for the application depends on the space constraints and routing technology used. 9.1.1 Fanout for ZAJ using Type 4 Routing This small 7-mm x 7-mm package utilizes the Type 4 routing technique to decrease system board area as much as possible. This Type 4 routing has vias in pad, blind and buried vias, and minimum trace width / spacing of 4 mils. = Ball Pad = Via, with 10 mil pad and 6 mil drill 4 mil = Top Layer Trace 6 mil Inner Balls 10 mil 10 mil = Inner 1 / Bottom Layer Trace = Inner 2 / Bottom Layer Trace Inner Balls Figure 9-1. Fanout for ZAJ Package Using Type 4 Routing 144 Layout Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com 9.1.2 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Fanout for ZCG using Type 3 Routing The ZCG has some of the inner balls removed to essentially create a 0.1-mm ball pitch for the inner balls of the package. This feature allows for Type 3 routing of the board. This Type 3 routing has no vias in pad, no blind and buried vias, and minimum trace width / spacing of 4 mils. = Ball Pad = Via, with 20 mil pad and 10 mil drill = Top Layer Trace 10 mil Inner Balls 4 mil = Inner 1 / Bottom Layer Trace = Inner 2 / Bottom Layer Trace 20 mil Inner Balls Figure 9-2. Fanout for ZCG Package using Type 3 Routing Layout Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 145 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 9.1.3 Layout Checklist • • • • • • • 9.2 9.2.1 www.ti.com All inductors, input/output caps and FETs for the converters and controller should be on the same board layer as the IC. Place feedback connection points near the output capacitors and minimize the control feedback loop as much as possible to achieve the best regulation performance. Bootstrap capacitors must be place close to the IC from the SWVRx to VBSTVRx pins. DRVLVRx signals must be routed on the same layer as the IC and the FETs and minimize the length and parasitic inductance of the trace as much as possible. Each converter and controller should have their own separate ground and each ground should connect to the common ground separately. The input capacitors, output capacitors, and FET grounds for each VRx converter and controller must be connected to the ground plane for the respective VRx rail. Since, the PGNDs for each rail are not connect to each other or AGND, it is required to use the PGNDVRx pins for the input and output capacitors for each VRx rail. This ground plane should connect in one place to the common ground close to the input and output capacitor ground pads. See the figure below for a visual representation of the converter layout scheme. The internal reference regulators must have their input and output caps close to the IC pins. Route the FBVRxP and FBVRxN signals as a differential pair. Layout Example Controller Layout The routing of the controllers is critical to the performance of the power supply. To reduce the risk of the controller effecting other sensitive circuits on the board, it is recommended to place all of the controller components on the same layer are the PMIC. In addition to component placement, the DRV, SW, and PGND signals should be routed on the same layer or as few of layers possible. It is recommended to place the FETs as close as possible to the PMIC but, it is imperative that the input capacitors are placed with minimal distance from the VIN and PGND pads of the FETs. The feedback signals should be routed differentially to the furthest output capacitor, which should be placed close to the load. Be sure to not route the feedback or any analog sensitive signals under the inductor, next to the SW node, or between the CIN and the FETs due to the high frequency switching from the edges. If the FETs of the controller are to be place far away from the PMIC the layout of the DRV, SW and PGND signals becomes extremely critical. The loop inductance of the the traces must be minimized as much as possible. In-order to do this, pair the DRVH and SW traces together and pair the DRVL and PGND traces together. PGND is best routed as a plane. To reduce the loop inductance of the DRVL, DRVL trace should be routed one layer above the PGND. Generally, the SW, DRVL and DRVH traces should be 20 mils or larger assuming the PGND is a plane underneath the DRVL trace. 146 Layout Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Input Voltage www.ti.com PGND CIN COUT COUT COUT CIN Inductor VR Output SW FETs NC DRVHVR1 FBVR1P FBVR1N ILIMVR1 VBSTVR1 SWVR1 VREGVR1 PGNDVR1 Feedback Signals DRVLVR1 PMIC Figure 9-3. Controller Layout Diagram 9.2.2 ZAJ Package Figure 9-4. Top Layer ZAJ Layout Figure 9-5. Bottom Layer ZAJ Layout Layout Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 147 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 9.2.3 www.ti.com ZCG Package Figure 9-6. Top Layer ZCG Layout Figure 9-7. Bottom Layer ZCG Layout 9.3 Thermal Considerations Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below. • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB by soldering the PowerPAD™ • Introducing airflow in the system For more details on how to use the thermal parameters in the dissipation ratings table please check the Thermal Characteristics Application Note (SZZA017) and the IC Package Thermal Metrics Application Note (SPRA953). 148 Layout Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 10 Device and Documentation Support 10.1 Device Support For device support, please submit questions to the E2E forum here:e2e.ti.com 10.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 10.1.2 Development Support For frequently asked questions, FAQs, on the TPS65083x, please refer to the FAQ here: http://e2e.ti.com/support/power_management/pmu/w/design_notes/2898.tps65083x-faqs 10.2 Documentation Support 10.2.1 Related Documentation For related documentation see the following: • Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Report SZZA017 • Semiconductor and IC Package Thermal Metrics Application Report SPRA953 10.3 Receiving Notification of Documentation Updates To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com. In the upper right-hand corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document. 10.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support. Quickly find helpful E2E forums along with design support tools and contact information for technical support. 10.5 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 10.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 10.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support Copyright © 2014–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS650830 149 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com 11 Mechanical, Packaging, and Orderable Information 11.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 150 Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: TPS650830 Copyright © 2014–2016, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS650830ZAJR ACTIVE NFBGA ZAJ 168 2000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS650830 TPS650830ZAJT ACTIVE NFBGA ZAJ 168 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS650830 TPS650830ZCGR ACTIVE NFBGA ZCG 159 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS650830 TPS650830ZCGT ACTIVE NFBGA ZCG 159 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS650830 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of