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TPS65090
SLVSBO6B – JANUARY 2013 – REVISED JULY 2015
TPS65090 Front-End PMU With Switched-Mode Charger for 2 to 3 Cells In Series
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
Wide Input Voltage Charger and Power Path
Management:
– VIN Range From 6 V to 17 V
– Up to 4-A Output Current on the Power Path
– Switched-Mode Charger; up to 4-A Maximum
Charge Current
– JEITA Compliant Charging Control
– Thermal Regulation, Safety Timers
– 2 Temperature Sense Inputs
3 Step-Down Converters:
– High Efficiency Over a Wide Output Current
Range
– VIN Range From 6 V to 17 V
– 2 Fixed Output Voltages (5 V and 3.3 V)
– Up to 5 A of Continuous Output Current
– 1 Adjustable Output Voltage (From 1 V to 5 V)
– Up to 4 A of Continuous Output Current
– Output Voltage Accuracy ±1%
– Typical 30-μA Quiescent Current Per
Converter
2 Always-On LDOs:
– 2 Fixed Output Voltages (5 V and 3.3 V)
– Output Voltage Accuracy ±1%
– Typical 10-μA Quiescent Current per LDO
7 Current-Limited Load Switches:
– One System Voltage Switch With 1-A Current
Limit
– One 5-V Switch With 200-mA Current Limit,
Reverse-Voltage Protected
– One 3.3-V Switch With 3-A Current Limit
– Four 3.3-V Switches With 1-A Current Limit
– All Switches Controlled by I2C Interface
I2C Interface
– Standard-Mode (100 kHz) Supported
– Fast-Mode (400 kHz) Supported
– Fast-Mode Plus (1000 kHz) Supported
– High-Speed (3.4 MHz) Supported
16-Channel, 10-Bit Analog-to-Digital Converter
(ADC)
Available in a 9-mm × 9-mm, VQFN-100 Package
Battery-Powered Products Using 2 to 3 Li-Cells in
Series
Notebook Computers
Mobile PCs and Mobile Internet Devices
Industrial Metering Equipment
Personal Medical Products
•
•
•
•
3 Description
The TPS65090A device is a single-chip power
management IC for portable applications consisting of
a battery charger with power path management for a
dual or triple Li-Ion or Li-Polymer cell battery pack.
The charger can be directly connected to an external
wall adapter. Three highly efficient step-down
converters are targeted for providing a fixed 5-V
system voltage, a fixed 3.3-V system voltage, and an
adjustable voltage rail. The step-down converters
enter a low power mode at light load for maximum
efficiency across the widest possible range of load
currents. The step-down converters allow the use of
small inductors and capacitors to achieve a small
solution size. The TPS65090A also integrates two
general-purpose always-on LDOs for powering circuit
blocks which control the system while shut down.
Each LDO operates with an input voltage range from
6 V to 17 V, allowing the LDOs to be supplied from
the wall adapter or directly from the main battery
pack.
Seven load switches are built into the device. These
load switches can be used to control the power
supply individually for certain circuit blocks in the
application circuit. The current flowing through the
load switches, as well as the output current of the
step-down converters, the input current from the AC
adapter and the charge current is monitored and can
be read out using the digital interface.
Device Information(1)
PART NUMBER
TPS65090A
PACKAGE
BODY SIZE (NOM)
VQFN-MR (100)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DC-DC Block Diagram
CBx
CB
VSYSx
CIN
ENx
DCDCx
Step-Down Converter
Control
Lx
VDCDCx
L
VDCDCx
RFB1
COUT
FBx
PGNDx
RFB2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65090
SLVSBO6B – JANUARY 2013 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
1
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics - Power Path Control ........ 8
Electrical Characteristics - Charger .......................... 9
Electrical Characteristics - DC-DC Converters ....... 11
Electrical Characteristics - Linear Regulators ......... 13
Electrical Characteristics - Load Switches .............. 13
Electrical Characteristics - Control........................ 15
Timing Requirements - I2C Interface .................... 16
Typical Characteristics .......................................... 18
Detailed Description ............................................ 25
7.1 Overview ................................................................. 25
7.2 Functional Block Diagram ....................................... 26
7.3
7.4
7.5
7.6
8
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
27
33
33
37
Application and Implementation ........................ 49
8.1 Application Information............................................ 49
8.2 Typical Applications ................................................ 49
9 Power Supply Recommendations...................... 59
10 Layout................................................................... 59
10.1 Layout Guidelines ................................................. 59
10.2 Layout Example .................................................... 60
10.3 Thermal Considerations ........................................ 61
11 Device and Documentation Support ................. 62
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
62
62
62
62
62
62
12 Mechanical, Packaging, and Orderable
Information ........................................................... 62
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2013) to Revision B
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Original (January 2013) to Revision A
Page
•
Added Differential Voltage spec condition "between CBC and LC", –0.3 MIN and 7 MAX ................................................... 6
•
Changed text in ALWAYS ON LDOs and POWER PATH CONTROL sections for clarification. ......................................... 27
•
Changed text in CHARGER section for clarification............................................................................................................. 29
•
Added INTERRUPTS section for clarification....................................................................................................................... 33
•
Added text to REVERSE VOLTAGE PROTECTION section for clarification....................................................................... 53
•
Changed graph title from "ADAPTER INPUT POWER UP AND POWER DOWN" to "SUPPLEMENT MODE
OPERATION" ....................................................................................................................................................................... 56
•
Added text to THERMAL INFORMATION section for clarification. ...................................................................................... 61
2
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SLVSBO6B – JANUARY 2013 – REVISED JULY 2015
5 Pin Configuration and Functions
A40
A41
C4
B37
A42
B38
A43
B39
A44
B40
A45
B41
A46
B42
A47
B43
A48
B44
A49
B45
A50
B46
A51
B48
C1
B47
A52
RVN Package
100-Pin VQFN-MR
Top View
A1
A39
B1
B36
B2
B35
B3
B34
B4
B33
A2
A38
A3
A37
A36
d
A4
A35
er
Pa
A5
B5
A6
B6
A7
A34
B31
A33
B30
w
B7
B32
A8
A32
B29
Po
B8
A9
B9
A10
A31
B28
A30
B10
B27
B11
B26
B12
B25
A11
A29
A12
A28
B24
C3
A26
B23
A25
A24
B22
B21
A23
A22
B20
B19
A21
A20
B18
A19
B17
B16
A18
A17
B15
A16
A15
A14
C2
B14
A27
B13
A13
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
POWER PATH CONTROL
ACG
A51
O
Gate connection for AC adapter input switches
ACN
A50
I
Shunt resistor sense connection for input current sensing
ACP
B47
I
Shunt resistor sense connection for input current sensing
ACS
B48
I
Source connection for AC adapter input switches
BATG
A2
O
Gate connection for the battery switch
VAC
A13
I
AC adapter supply input for charger control
VACS
A14
I
AC adapter sense input for the charger
CBC
B2
I
Bootstrap capacitor connection for charger step-down converter
ENC
A41
I
Enable input for charger (1: enabled, 0: disabled), must be connected to a valid logic signal
FBC
A52
I
Voltage feedback input for charger step-down converter. Must be connected to an external feedback
divider to program charge voltage.
A5, B4, B5
O
Inductor connection for switched-mode battery charger step-down converter
Power Ground
CHARGER
LC
PGNDC
A6, B6
—
SRN
B1
I
Shunt resistor connection for battery charge current sensing
SRP
A1
I
Shunt resistor connection for battery charge current sensing
STAT
B13
O
Charge status pin, open-drain (charge in progress, charge complete, sleep mode, fault)
TS1
A24
I
Temperature sensor input for temperature sensor 1
TS2
B23
I
Temperature sensor input for temperature sensor 2
VACG
A39
O
VAC good pin, open drain (1, high impedance : voltage good; 0 : voltage not available)
VBAT
A15
I
Battery sense connection
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SLVSBO6B – JANUARY 2013 – REVISED JULY 2015
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
VBATG
A38
O
VBAT good pin, open drain (1, high impedance : voltage good; 0 : voltage not available), pullup
voltage should not be higher than voltage connected to
VREFT
A25
I
Reference voltage output for temperature measurements
VSYSC
A3, A4, B3
I
Switched-mode battery charger step-down converter supply voltage
VSYSG
B36
O
VSYS good pin, open drain (1, high impedance : voltage good; 0 : voltage not available)
CB1
B44
I
Bootstrap capacitor connection for DCDC1
EN1
B38
I
Enable input for DCDC1 (1: enabled, 0: disabled), must be connected to a valid logic signal
FB1
B37
I
Output voltage sense input for DCDC1
L1
A45, B41,
B42
O
Inductor connection for DCDC1 step-down converter
PGND1
A43, A44,
B40
—
Power Ground
DCDC1
VDCDC1
A48
I
Output voltage connection of DCDC1
A46, A47,
B43
I
Supply voltage input for DCDC1 step-down converter
CB2
B17
I
Bootstrap capacitor connection for DCDC2
EN2
A42
I
Enable input for DCDC2 (1: enabled, 0: disabled), must be connected to a valid logic signal
FB2
B24
I
Output voltage sense input for DCDC2
L2
A21, B19,
B20
O
Inductor connection for DCDC2 step-down converter
PGND2
A22, A23,
B21, B22
—
Power Ground
VSYS1
DCDC2
VDCDC2
A18
I
Output voltage connection of DCDC2
A19, A20,
B18
I
Supply voltage input for DCDC2 step-down converter
CB3
A12
I
Bootstrap capacitor connection for DCDC3
EN3
A26
I
Enable input for DCDC3 (1: enabled, 0: disabled), must be connected to a valid logic signal
FB3
B14
I
Output voltage feedback input for DCDC3, a resistive feedback divider must be connected
VSYS2
DCDC3
L3
A9, B8, B9
O
Inductor connection for DCDC3 step-down converter
PGND3
A7, A8, B7
—
Power Ground
A16
I
Output voltage sense input for DCDC3
A10, A11,
B10, B11
I
Supply voltage input for DCDC3 step-down converter
FB_L1
B46
I
Output voltage sense input for LDO1
VLDO1
B45
O
Output of the LDO1 linear regulator
VSYS_L1
A49
I
Supply voltage input for LDO1 linear regulator
VDCDC3
VSYS3
LDO1
LDO2
FB_L2
B15
I
Output voltage sense input for LDO2
VLDO2
B16
O
Output of the LDO2 linear regulator
VSYS_L2
A17
I
Supply voltage input for LDO2 linear regulator
FET1
INFET1
B28
I
Supply voltage input for load switch FET1, connect to GND, if not used
VFET1
A30
O
Output of load switch FET1, leave unconnected if not used
B29
I
Supply voltage input for load switch FET2, connect to GND, if not used
FET2
INFET2
4
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SLVSBO6B – JANUARY 2013 – REVISED JULY 2015
Pin Functions (continued)
PIN
I/O
DESCRIPTION
A31
O
Output of load switch FET2, leave unconnected if not used
INFET3
A34, B31
I
Supply voltage input for load switch FET3, connect to GND, if not used
VFET3
A32, B30
O
Output of load switch FET3, leave unconnected if not used
INFET4
B34
I
Supply voltage input for load switch FET4, connect to GND, if not used
VFET4
A37
O
Output of load switch FET4, leave unconnected if not used
NAME
NO.
VFET2
FET3
FET4
FET5
INFET5
B33
I
Supply voltage input for load switch FET5, connect to GND, if not used
VFET5
A36
O
Output of load switch FET5, leave unconnected if not used
FET6
INFET6
B32
I
Supply voltage input for load switch FET6, connect to GND, if not used
VFET6
A35
O
Output of load switch FET6, leave unconnected if not used
FET7
INFET7
B27
I
Supply voltage input for load switch FET7, connect to GND, if not used
VFET7
A29
O
Output of load switch FET7, leave unconnected if not used
DIGITAL INTERFACE/CONTROL
AGND
A33
—
Analog ground
GND
A40
—
Logic ground
IRQ
B12
O
Interrupt output, open drain, (1, high impedance : no interrupt; 0 : interrupt) details on events
available through I2C
C1, C2, C3,
C4
—
Internally connected to PowerPAD™
—
Must be soldered to achieve appropriate power dissipation. Must be connected to PGND.
SCL
B25
I/O
Clock input for the I2C interface
SDA
A27
I/O
Data line for the I2C interface
VCTRL
B39
O
Internal control supply decoupling capacitor connection
VREF
B35
O
Reference voltage decoupling capacitor connection
VREFADC
B26
O
ADC reference voltage decoupling capacitor connection
PGND
PowerPAD
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SLVSBO6B – JANUARY 2013 – REVISED JULY 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VAC, VACS
–0.3
30
ACP, ACN, ACS, BATG
–0.3
20
between ACP and ACN
–0.5
0.5
between ACG and ACS
–0.3
7
VSYSC, VBAT, LC, SRP, SRN, STAT
–0.3
20
FBC, TS1, TS2, VREFT
–0.3
7
ENC
–0.3
3.6
between SRP and SRN
–0.5
0.5
between CBC and LC
–0.3
7
VSYS1, L1
–0.3
20
FB1, VDCDC1
–0.3
7
EN1
–0.3
3.6
between CB1 and L1
–0.3
7
VSYS2, L2
–0.3
20
FB2, VDCDC2
–0.3
3.6
EN2
–0.3
3.6
between CB2 and L2
–0.3
7
VSYS3, L3
–0.3
20
FB3, VDCDC3
–0.3
7
EN3
–0.3
3.6
between CB3 and L3
–0.3
7
VSYS_L1
–0.3
20
VLDO1, FB_L1
–0.3
7
VSYS_L2
–0.3
20
VLDO2, FB_L2
–0.3
3.6
INFET1, VFET1
–0.3
20
V
INFET2, VFET2
–0.3
6
V
INFET3, VFET3
–0.3
6
V
INFET4, VFET4
–0.3
6
V
POWER PATH CONTROL
Voltage (2)
Differential Voltage
V
V
CHARGER
Voltage
(2)
Differential Voltage
V
V
DCDC1
Voltage (2)
Differential Voltage
V
V
DCDC2
Voltage (2)
Differential Voltage
V
V
DCDC3
Voltage (2)
Differential Voltage
V
V
LDO1
Voltage (2)
V
LDO2
Voltage (2)
V
FET1
Voltage (2)
FET2
Voltage (2)
FET3
Voltage (2)
FET4
Voltage (2)
(1)
(2)
6
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
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SLVSBO6B – JANUARY 2013 – REVISED JULY 2015
Absolute Maximum Ratings (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
INFET5, VFET5
–0.3
6
V
INFET6, VFET6
–0.3
6
V
INFET7, VFET7
–0.3
6
V
FET5
Voltage (2)
FET6
Voltage (2)
FET7
Voltage (2)
DIGITAL INTERFACE/CONTROL
Voltage (2)
SDAT, SCLK, IRQ, VCTRL, VCTRL2, VACG, VSYSG, VBATG
–0.3
7
VREFADC, VREF
–0.3
3.6
Operating junction, TJ
–40
150
Storage temperature, Tstg
–65
150
V
GENERAL
Temperature
°C
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
POWER PATH CONTROL
Supply voltage at VAC
Differential voltage between ACP and ACN
6
17
V
–0.2
0.2
V
CHARGER
Supply voltage at VSYSC, VBAT
Differential voltage between SRP and SRN
6
17
V
–0.2
0.2
V
6
17
V
6
17
V
6
17
V
6
17
V
6
17
V
5
17
V
4.5
5.5
V
3
5.5
V
3
5.5
V
DCDC1
Supply voltage at VSYS1
DCDC2
Supply voltage at VSYS2
DCDC3
Supply voltage at VSYS3
LDO1
Supply voltage at VSYS_L1
LDO2
Supply voltage at VSYS_L2
FET1
Supply voltage at INFET1
FET2
Supply voltage at INFET2
FET3
Supply voltage at INFET3
FET4
Supply voltage at INFET4
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Recommended Operating Conditions (continued)
MIN
NOM
MAX
UNIT
FET5
Supply voltage at INFET5
3
5.5
V
3
5.5
V
3
5.5
V
3
5.5
V
FET6
Supply voltage at INFET6
FET7
Supply voltage at INFET7
CONTROL
Supply voltage at VCTRL2
GENERAL
Operating free-air temperature, TA
–40
85
°C
Operating junction temperature, TJ
–40
125
°C
6.4 Thermal Information
TPS65090A
THERMAL METRIC (1)
RVN [VQFN-MR]
UNIT
100 PINS
RθJA
Junction-to-ambient thermal resistance
24.8
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
5.6
°C/W
RθJB
Junction-to-board thermal resistance
3.9
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
3.9
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
0.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics - Power Path Control
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VAC overvoltage disconnect
MIN
TYP
MAX
UNIT
17
17.6
18.2
V
VAC overvoltage hysteresis
550
VAC undervoltage lockout
VAC voltage decreasing
5
VAC undervoltage lockout hysteresis
1000
(VACP - VACN) voltage to maximum input DPM
current gain
Maximum battery discharge current
comparator threshold
V
mV
4000
100
mA
A/V
VACP - VACN, IACSET = 0
40
44
48
mV
VACP - VACN, IACSET = 1
36
40
44
mV
VBAT - VSRN, IBATSET = 0, TA = 25°C
17.5
20
21
mV
VBAT - VSRN, IBATSET = 1, TA = 25°C
15
17.5
18.5
mV
VACS input impedance
VAC input impedance
Gate drive current on ACG
1000
kΩ
25
kΩ
μA
12
Gate drive current on BATG
Turnon
500
μA
Gate drive current on BATG
Turnoff
25
mA
BATG turnoff delay time after adapter is
detected
8
mV
6
550
Maximum input DPM current programming
range
Input DPM current regulation
5.5
30
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Electrical Characteristics - Power Path Control (continued)
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Quiescent current into VAC
Leakage current into ACP and ACN
VSUPPL
TYP
MAX
Charging enabled, VAC = 11.5 V
MIN
2.5
5
mA
Charging disabled, VAC = 11.5 V
1
1.5
mA
Charging disabled
Supplement threshold to turn on battery switch VSRN - VACN rising
13
VSUPPL_ Supplement mode hysteresis to turn off battery
VSRN - VACN falling
switch
HYS
IACRC
Reverse adapter current threshold
VACN - VACP rising
VSLEEP
SLEEP mode threshold
VAC – VSRN falling
VSLEEP_
SLEEP mode hysteresis
VAC – VSRN rising
HYS
45
UNIT
80
μA
84
mV
20
mV
45
20
90
mV
150
mV
200
mV
6.6 Electrical Characteristics - Charger
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.02
UNIT
CHARGER - POWER
VFBC
Charger feedback voltage
VSET = 00, default for T01 and T40
1.98
2
VSET = 01, default for T12
2.03
2.05
2.07
VSET = 10, default for T34
2.055
2.075
2.095
VSET = 11, default for T23
2.08
2.1
2.12
VSET = 00, ENRECG = 1
1.925
1.950
1.975
VSET = 01, ENRECG = 1
1.975
2
2.025
VSET = 10, ENRECG = 1
2
2.025
2.05
VSET = 11, ENRECG = 1
2.025
2.05
2.075
Leakage current into FBC
VFBCR
Charger feedback voltage for automatic
charge restart
1000
(VSRP - VSRN) voltage to maximum charge
current gain
Charge current sense regulation voltage
25%
ISET = 010
37.5%
ISET = 011, default for T12 and T34 battery
temperature range
A/V
50%
ISET = 100
62.5%
ISET = 101
75%
ISET = 110
87.5%
ISET = 111, default for T23 battery
temperature range
100%
VSRP - VSRN = 40 mV typical, TJ < 100 °C
38.5
40
VSRP - VSRN = 20 mV typical, TJ < 100 °C
18.5
20
22
VSRP - VSRN = 4 mV typical, TJ < 100 °C
2.3
4
5.9
42.5
100
Precharge current
0.1 *
ICHARGE
Termination current
0.1 *
ICHARGE
Leakage current into SRN and SRP
mA
0%
ISET = 001
Minimum programmable charge current
V
4000
100
ISET = 000
I C programmable charge current
μA
0.1
ICHARGE Maximum charge current programming
2
V
VBAT < 12 V
mA
45
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Electrical Characteristics - Charger (continued)
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Switching frequency
MIN
TYP
MAX
UNIT
1360
1600
1840
kHz
RDSON
High-side switch ON-resistance
25
mΩ
RDSON
Low-side switch ON-resistance
60
mΩ
CHARGER - CONTROL
Precharge timer
1600
Fast-charge safety timer programming
1800
2
Fast-charge safety timer accuracy
I C programmable values for fast-charge
safety timer
FASTTIME = 000, default setting
2
FASTTIME = 001
3
FASTTIME = 010
4
FASTTIME = 011
5
FASTTIME = 100
6
FASTTIME = 101
7
FASTTIME = 110
8
FASTTIME = 111
10
Battery detection discharge timer
5
Battery detection discharge current after
timer fault
s
20
mA
mA
Battery detection discharge feedback
voltage threshold for battery OK
1.43
1.45
1.47
V
Battery feedback voltage threshold for
precharge to fast-charge transition
1.43
1.45
1.47
V
0.5
Battery detection charge current sense
regulation voltage
VSRP - VSRN = 2 mV typical, TJ < 100 °C
Battery detection charge feedback voltage
threshold for battery OK
10
h
2
Battery detection charge timer
T2
h
1
Battery detection discharge current
T1
s
10
10%
2
VFBCL
2000
s
0.5
2
3.8
VSET = 00
1.925
1.95
1.975
VSET = 01
1.975
2
2.025
VSET = 10
2
2.025
2.05
VSET = 11
2.025
2.05
2.075
mV
V
Minimum battery feedback voltage for
battery good detection
Voltage at FBC increasing
1.44
1.5
1.54
V
Maximum battery feedback voltage for
battery good detection
Voltage at FBC increasing
2.18
2.25
2.28
V
Battery cell temperature measurement, ratio
of VTS1,2 compared to VREFTS, I2C
programming option for T1
Sensor temperature is -10°C, T_SET = 000
Voltage ratio threshold hysteresis
Sensor temperature is -10°C, voltage
decreasing
Battery cell temperature measurement, ratio
of VTS1,2 compared to VREFTS
Default value, Sensor temperature is 0°C,
T_SET = 001
Voltage ratio threshold hysteresis
Sensor temperature is 0°C, voltage
decreasing
Battery cell temperature measurement, ratio
of VTS1,2 compared to VREFTS
Default value, Sensor temperature is 10°C,
T_SET = 010
Voltage ratio threshold hysteresis
Sensor temperature is 10°C, voltage
decreasing
Battery cell temperature measurement, ratio
of VTS1,2 compared to VREFTS, I2C
programming option for T2
Sensor temperature is 15°C, T_SET = 011
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71.9%
72.4% 72.9%
0.2%
70.4%
71% 71.5%
0.2%
68.1%
68.7% 69.2%
0.4%
67%
67.4% 67.9%
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Electrical Characteristics - Charger (continued)
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
T3
T4
TEST CONDITIONS
MIN
Voltage ratio threshold hysteresis
Sensor temperature is 15°C, voltage
decreasing
Battery cell temperature measurement, ratio
of VTS1,2 compared to VREFTS, I2C
programming option for T3
Sensor temperature is 40°C, T_SET = 100
Voltage ratio threshold hysteresis
Sensor temperature is 40°C, voltage
increasing
Battery cell temperature measurement, ratio
of VTS1,2 compared to VREFTS
Default value, Sensor temperature is 45°C,
T_SET = 101
Voltage ratio threshold hysteresis
Sensor temperature is 45°C, voltage
increasing
Battery cell temperature measurement, ratio
of VTS1,2 compared to VREFTS, I2C
programming option for T3 or T4
Sensor temperature is 50°C, T_SET = 110
Voltage ratio threshold hysteresis
Sensor temperature is 50°C, voltage
increasing
Battery cell temperature measurement, ratio
of VTS1,2 compared to VREFTS
Default value, Sensor temperature is 60°C,
T_SET = 111
Voltage ratio threshold hysteresis
Sensor temperature is 60°C, voltage
increasing
Output voltage at VREFT
Internally connected to VLDO2
TYP
Charging active
Quiescent current into VBAT
Charging suspended
VIL
ENC input low voltage
VIH
ENC input high voltage
ENC input current
59.3%
59.7% 60.1%
0.9%
57.1%
57.6% 57.9%
0.9%
54.7%
55.2% 55.8%
1.1%
49.6%
50.1% 50.5%
1.1%
3.3
V
4
kΩ
25
μA
150
μA
0.4
V
1.2
V
Clamped on GND or 3.3V
0.01
Charge current derating starting temperature Junction temperature increasing
Charge current derating starting voltage
UNIT
0.4%
Output impedance of VREFT
Quiescent current into VBAT
MAX
VSYSC decreasing
Overtemperature protection
μA
0.1
100
°C
6.7
7.3
7.6
V
125
140
150
°C
Overtemperature hysteresis
20
°C
6.7 Electrical Characteristics - DC-DC Converters
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5
5.05
5.125
UNIT
DCDC1 - POWER
Output voltage
Power save mode disabled
Switch valley current limit
TA = 25°C
5500
High-side switch ON-resistance
Low-side switch ON-resistance
20
mΩ
20
mΩ
Maximum line regulation
0.5%
Maximum load regulation
0.5%
Output auto-discharge resistance
300
FB1 input impedance
VEN1 = 1
Shutdown current into VSYS1
VSYS1 = 7.2 V, EN1 = 0
V
mA
400
1
Ω
MΩ
1
μA
0.4
V
DCDC1 - CONTROL
VIL
EN1 input low voltage
VIH
EN1 input high voltage
1.2
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Electrical Characteristics - DC-DC Converters (continued)
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
EN1 input current
TEST CONDITIONS
MIN
Clamped on GND or 3.3 V
TYP
MAX
0.01
0.1
UNIT
μA
Overtemperature protection
140
°C
Overtemperature hysteresis
20
°C
DCDC2 - POWER
Output voltage
Power save mode disabled
Switch valley current limit
TA = 25°C
3.3
3.333
3.383
5500
V
mA
High-side switch ON-resistance
20
mΩ
Low-side switch ON-resistance
20
mΩ
Maximum line regulation
0.5%
Maximum load regulation
0.5%
Output auto-discharge resistance
300
FB2 input impedance
VEN2 = 1
Shutdown current into VSYS2
VSYS2 = 7.2 V, EN2 = 0
400
1
Ω
MΩ
1
μA
0.4
V
0.1
μA
DCDC2 - CONTROL
VIL
EN2 input low voltage
VIH
EN2 input high voltage
EN2 input current
1.2
Clamped on GND or 3.3 V
V
0.01
Overtemperature protection
140
°C
Overtemperature hysteresis
20
°C
DCDC3 - POWER
Feedback voltage
Switch valley current limit
792
TA = 25°C
800
808
4200
mV
mA
High-side switch ON-resistance
20
mΩ
Low-side switch ON-resistance
20
mΩ
Maximum line regulation
0.5%
Maximum load regulation
0.5%
Output auto-discharge resistance
300
Leakage current into FB3
Shutdown current into VSYS3
VSYS3 = 7.2 V, EN3 = 0
400
Ω
0.1
μA
1
μA
0.4
V
0.1
μA
DCDC3 - CONTROL
VIL
EN3 input low voltage
VIH
EN3 input high voltage
EN3 input current
12
1.2
Clamped on GND or 3.3 V
V
0.01
Overtemperature protection
140
°C
Overtemperature hysteresis
20
°C
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6.8 Electrical Characteristics - Linear Regulators
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.90
4.95
5
30
50
120
UNIT
LDO1
Output voltage
IOUTLDO1 = 1 mA
LDO1 current limit
TA = 25°C
LDO1 maximum output current
DCDC1 active (bypass switch turned on),
VSYS = 7.5 V
V
mA
120
Maximum line regulation
0.5%
Maximum load regulation
0.5%
FB_L1 input impedance
mA
1
Quiescent current into VSYS_L1 and VSYS_L2
DCDC1 and DCDC2 are enabled
MΩ
μA
35
Overtemperature protection
140
°C
Overtemperature hysteresis
20
°C
LDO2
Output voltage
IOUTLDO2 = 1 mA
LDO2 current limit
TA = 25°C
LDO2 maximum output current
DCDC2 active (bypass switch turned on),
VSYS = 7.5 V
3.233
3.267
3.3
V
30
50
120
mA
120
Maximum line regulation
0.5%
Maximum load regulation
0.5%
FB_L2 input impedance
mA
1
Quiescent current into VSYS_L2 and VSYS_L1
DCDC1 and DCDC2 are enabled
MΩ
μA
35
Overtemperature protection
140
°C
Overtemperature hysteresis
20
°C
6.9 Electrical Characteristics - Load Switches
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1200
mA
120
mΩ
FET1
Overcurrent detect threshold
TA = 25°C
1000
Switch ON-resistance
Output auto-discharge resistance
Ω
800
Maximum output voltage slew rate after turnon
0.1
0.5
1
V / μs
Switch current limit - time-out
Multiplier set to 1, WTFET1 = 00
200
250
μs
Switch current limit - time-out
Multiplier set to 4, WTFET1 = 01
800
1000
μs
Switch current limit - time-out
Multiplier set to 8, WTFET1 = 10
1600
2000
μs
Switch current limit - time-out
Multiplier set to 16, WTFET1 = 11
3200
4000
μs
Leakage current into INFET1
FET1 disabled, VFET1 = 0 V
Overcurrent detect threshold
TA = 25°C
μA
1
FET2
200
Switch ON-resistance
Output auto-discharge resistance
240
mA
500
mΩ
Ω
300
Maximum output voltage slew rate after turnon
0.1
0.5
1
V / μs
Switch current limit - time-out
Multiplier set to 1, WTFET2 = 00
200
250
μs
Switch current limit - time-out
Multiplier set to 4, WTFET2 = 01
800
1000
μs
Switch current limit - time-out
Multiplier set to 8, WTFET2 = 10
1600
2000
μs
Switch current limit - time-out
Multiplier set to 16, WTFET2 = 11
3200
4000
μs
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Electrical Characteristics - Load Switches (continued)
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Shutdown current into INFET2
FET2 disabled, VFET2 = 0 V
Reverse leakage current
FET disabled, VFET2 > INFET2
Overcurrent detect threshold
TA = 25°C
TYP
MAX
UNIT
5
μA
10
μA
FET3
3000
Switch ON-resistance
Output auto-discharge resistance
3600
mA
45
mΩ
1
V / μs
Ω
300
Maximum output voltage slew rate after turnon
0.1
0.5
200
250
μs
Multiplier set to 4, WTFET3 = 01
800
1000
μs
Multiplier set to 8, WTFET3 = 10
1600
2000
μs
Switch current limit - time-out
Multiplier set to 16, WTFET3 = 11
3200
4000
μs
Leakage current into INFET3
FET3 disabled, VFET3 = 0 V
Overcurrent detect threshold
TA = 25°C
Switch current limit - time-out
Multiplier set to 1, WTFET3 = 00
Switch current limit - time-out
Switch current limit - time-out
μA
3
FET4
1000
Switch ON-resistance
Output auto-discharge resistance
1200
mA
80
mΩ
1
V / μs
Ω
300
Maximum output voltage slew rate after turnon
0.1
0.5
200
250
μs
Multiplier set to 4, WTFET4 = 01
800
1000
μs
Multiplier set to 8, WTFET4 = 10
1600
2000
μs
Switch current limit - time-out
Multiplier set to 16, WTFET4 = 11
3200
4000
μs
Leakage current into INFET4
FET4 disabled, VFET4 = 0 V
Overcurrent detect threshold
TA = 25°C
Switch current limit - time-out
Multiplier set to 1, WTFET4 = 00
Switch current limit - time-out
Switch current limit - time-out
μA
1
FET5
1000
Switch ON-resistance
Output auto-discharge resistance
1200
mA
80
mΩ
1
V / μs
Ω
300
Maximum output voltage slew rate after turnon
0.1
0.5
200
250
μs
Multiplier set to 4, WTFET5 = 01
800
1000
μs
Multiplier set to 8, WTFET5 = 10
1600
2000
μs
Switch current limit - time-out
Multiplier set to 16, WTFET5 = 11
3200
4000
μs
Leakage current into INFET5
FET5 disabled, VFET5 = 0 V
Overcurrent detect threshold
TA = 25°C
Switch current limit - time-out
Multiplier set to 1, WTFET5 = 00
Switch current limit - time-out
Switch current limit - time-out
μA
1
FET6
1000
Switch ON-resistance
Output auto-discharge resistance
1200
mA
80
mΩ
1
V / μs
Ω
300
Maximum output voltage slew rate after turnon
0.1
0.5
200
250
μs
Multiplier set to 4, WTFET6 = 01
800
1000
μs
Multiplier set to 8, WTFET6 = 10
1600
2000
μs
Switch current limit - time-out
Multiplier set to 16, WTFET6 = 11
3200
4000
μs
Leakage current into INFET6
FET6 disabled, VFET6 = 0 V
Overcurrent detect threshold
TA = 25°C
Switch current limit - time-out
Multiplier set to 1, WTFET6 = 00
Switch current limit - time-out
Switch current limit - time-out
μA
1
FET7
Switch ON-resistance
14
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1000
1200
mA
80
mΩ
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Electrical Characteristics - Load Switches (continued)
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Output auto-discharge resistance
TYP
MAX
UNIT
Ω
300
Maximum output voltage slew rate after turnon
0.1
0.5
1
V / μs
Switch current limit - time-out
Multiplier set to 1, WTFET7 = 00
200
250
μs
Switch current limit - time-out
Multiplier set to 4, WTFET7 = 01
800
1000
μs
Switch current limit - time-out
Multiplier set to 8, WTFET7 = 10
1600
2000
μs
Switch current limit - time-out
Multiplier set to 16, WTFET7 = 11
3200
4000
Leakage current into INFET7
FET7 disabled, VFET7 = 0 V
μs
μA
1
6.10 Electrical Characteristics - Control
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.04
0.4
V
0.01
0.4
μA
0.04
0.4
V
0.6
V
0.01
0.1
μA
5.6
5.7
SYSTEM - CONTROL
VBATG, VACG, VSYSG, IRQ output low voltage
IVxxxGL = 1 mA
VBATG, VACG, VSYSG, IRQ output leakage
current
STAT output low voltage
ISTAT = 1 mA
STAT output low voltage
ISTAT = 5 mA
STAT output leakage current
System undervoltage lockout threshold
VSYS voltage decreasing
5.5
System undervoltage lockout threshold
hysteresis
300
LDO undervoltage lockout threshold
VSYS voltage decreasing
4.4
LDO undervoltage lockout threshold hysteresis
VIL
SDA, SCL input low voltage
VIH
SDA, SCL input high voltage
4.6
V
mV
4.7
300
V
mV
0.4
V
1.2
V
SDA, SCL input current
Clamped on GND or 3.3 V
0.01
0.3
μA
SDA output low voltage
ISDA = 5 mA
0.04
0.4
V
AD - CONVERTER
ADC resolution
10
Bits
Differential linearity error
±1
LSB
Offset error
1
Offset error, voltage
5
12.7
Gain error
Sampling time
Conversion time
Wait time after enable
Time needed to stabilize the internal
voltages
Quiescent current, ADC enabled by I2C
includes current needed for I2C block
LSB
mV
±8
LSB
150
μs
20
μs
10
ms
μA
500
AD - CONVERTER - MEASUREMENT RANGES
Voltage on VAC
0
17
V
Battery voltage VBAT
0
17
V
Input current IAC
VACP - VACN is measured
0
33
mV
Battery charge current IBAT
VSRP - VSRN is measured
0
40
mV
DCDC1 output current IDCDC1
0
4
A
DCDC2 output current IDCDC2
0
4
A
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Electrical Characteristics - Control (continued)
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4
UNIT
DCDC3 output current IDCDC3
0
A
FET1 output current IFET1
0
1.1
A
FET2 output current IFET2
0
220
mA
FET3 output current IFET3
0
3.3
A
FET4 output current IFET4
0
1.1
A
FET5 output current IFET5
0
1.1
A
FET6 output current IFET6
0
1.1
A
FET7 output current IFET7
0
1.1
A
AD - CONVERTER - SIGNAL CONDITIONING
Voltage sense error referenced to maximum
value
2%
Current sense error referenced to maximum
value for IAC and IBAT
20%
Current sense error referenced to maximum
value for DC-DC converter currents
Measurements at VSYS > 7.2 V, low side
switch duty cycle at DCDC1-3 > 30%
15%
Current sense error referenced to maximum
value for load switch currents
10%
6.11 Timing Requirements - I2C Interface
over recommended free-air temperature range and over recommended input voltage range (unless otherwise noted) (1)
MIN
f(SCL)
Bus free time between a STOP
and START condition
tBUF
tHD;
SCL clock frequency
STA
tLOW
Hold time (repeated) START
condition
LOW period of the SCL clock
MAX
UNIT
Standard-mode
100
kHz
Fast-mode
400
kHz
1000
kHz
High-speed mode, Cb – 100 pF maximum
3.4
MHz
High-speed mode, Cb – 400 pF maximum (2)
1.7
MHz
Fast-mode Plus
Standard-mode
4.7
μs
Fast-mode
1.3
μs
Fast-mode Plus
0.5
μs
Standard-mode
4
μs
Fast-mode
600
ns
Fast-mode Plus
260
ns
High-speed mode
160
ns
Standard-mode
4.7
μs
Fast-mode
1.3
μs
Fast-mode Plus
0.5
μs
High-speed mode, Cb – 100 pF maximum
160
ns
High-speed mode, Cb – 400 pF maximum
(2)
320
ns
4
μs
Fast-mode
600
ns
Fast-mode Plus
260
ns
60
ns
120
ns
Standard-mode
tHIGH
HIGH period of the SCL clock
High-speed mode, Cb – 100 pF maximum
High-speed mode, Cb – 400 pF maximum (2)
(1)
(2)
16
All values referred to VIH min and VIH max levels.
For bus line loads Cb from 100 pF to 400 pF, the timing parameters must be linearly interpolated.
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Timing Requirements - I2C Interface (continued)
over recommended free-air temperature range and over recommended input voltage range (unless otherwise noted)(1)
MIN
tSU; STA
tSU; DAT
tHD;
DAT
Setup time for a repeated
START condition
Data setup time
Data hold time
4.7
μs
Fast-mode
600
ns
Fast-mode Plus
260
ns
High-speed mode
160
ns
Standard-mode
250
ns
Fast-mode
100
ns
Fast-mode Plus
50
ns
High-speed mode
10
1
3450
ns
Fast-mode
1
900
ns
Fast-mode Plus
1
1 (3)
70
ns
High-speed mode, Cb – 400 pF maximum (2)
1 (3)
150
ns
1000
ns
300
ns
120
ns
40
ns
20
Fast-mode Plus
High-speed mode, Cb – 400 pF maximum
10
(2)
20
Standard-mode
trCL1
Fast-mode
20
Fast-mode Plus
Fall time of SCL signal
ns
ns
High-speed mode, CB – 400 pF maximum (2)
20
160
ns
300
ns
Fast-mode
20 × (VDD / 5.5 V)
300
ns
Fast-mode Plus
20 × (VDD / 5.5 V)
120
ns
10
40
ns
(2)
Fast-mode
20
20
Fast-mode Plus
(3)
ns
ns
80
ns
High-speed mode, Cb – 400 pF maximum (2)
20
160
ns
300
ns
Fast-mode
20 × (VDD / 5.5 V)
300
ns
Fast-mode Plus
20 × (VDD / 5.5 V)
120
ns
10
80
ns
20
160
(2)
ns
4
μs
Fast-mode
600
ns
Fast-mode Plus
260
ns
High-speed mode
160
ns
Standard-mode
Cb
ns
300
120
High-speed mode, Cb – 400 pF maximum
Setup time for STOP condition
ns
10
High-speed mode, Cb – 100 pF maximum
tSU; STO
80
1000
High-speed mode, Cb – 100 pF maximum
Standard-mode
Fall time of SDA signal
ns
80
Standard-mode
tfDA
ns
300
120
High-speed mode, Cb – 400 pF maximum
Rise time of SDA signal
ns
10
High-speed mode, Cb – 100 pF maximum
trDA
80
1000
High-speed mode, CB – 100 pF maximum
Standard-mode
tfCL
ns
High-speed mode, Cb – 100 pF maximum
High-speed mode, Cb – 100 pF maximum
Rise time of SCL signal after a
repeated START condition and
after an acknowledge bit
ns
Standard-mode
Fast-mode
Rise time of SCL signal
UNIT
Standard-mode
Standard-mode
trCL
MAX
Capacitive load for SDA and
SCL
400
pF
A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
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DATA
t( BUF)
th(STA)
t(LOW)
tr
tf
CLK
t h(STA)
t(HIGH)
tsu(STA)
th(DATA)
STO
tsu(STO)
tsu(DATA)
STA
STA
STO
Figure 1. Serial Interface Timing Diagram
6.12 Typical Characteristics
Table of Graphs
FIGURE
Efficiency
Efficiency
Efficiency
Efficiency
Switching frequency
18
vs Output Current, DCDC1, VOUT = 5 V
Figure 2
vs Output Current, DCDC2, VOUT = 3.3 V
Figure 3
vs Output Current, DCDC3, VOUT = 1 V
Figure 4
vs Output Current, DCDC3, VOUT = 1.35 V
Figure 5
vs Output Current, DCDC3, VOUT = 1.8 V
Figure 6
vs Output Current, DCDC3, VOUT = 3.3 V
Figure 7
vs Output Current, DCDC3, VOUT = 4 V
Figure 8
vs Output Current, DCDC3, VOUT = 5 V
Figure 9
vs Output Current, Charger, VOUT = 8.4 V
Figure 10
vs Output Current, Charger, VOUT = 12.6 V
Figure 11
vs Input Voltage, DCDC1, VOUT = 5 V
Figure 12
vs Input Voltage, DCDC2, VOUT = 3.3 V
Figure 13
vs Input Voltage, DCDC3, VOUT = 1 V
Figure 14
vs Input Voltage, DCDC3, VOUT = 1.35 V
Figure 15
vs Input Voltage, DCDC3, VOUT = 1.8 V
Figure 16
vs Input Voltage, DCDC3, VOUT = 3.3 V
Figure 17
vs Input Voltage, DCDC3, VOUT = 4 V
Figure 18
vs Input Voltage, DCDC3, VOUT = 5 V
Figure 19
vs Battery Voltage, Charger, IOUT = 1 A
Figure 20
vs Battery Voltage, Charger, IOUT = 2 A
Figure 21
vs Battery Voltage, Charger, IOUT = 3 A
Figure 22
vs Battery Voltage, Charger, IOUT = 4 A
Figure 23
vs Output Current, DCDC1, VOUT = 5 V
Figure 24
vs Output Current, DCDC2, VOUT = 3.3 V
Figure 25
vs Output Current, DCDC3, VOUT = 1.35 V
Figure 26
vs Input Voltage, DCDC1, VOUT = 5 V
Figure 27
vs Input Voltage, DCDC2, VOUT = 3.3 V
Figure 28
vs Input Voltage, DCDC3, VOUT = 1.35 V
Figure 29
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Typical Characteristics (continued)
Table of Graphs (continued)
FIGURE
Figure 30
vs Output Current, DCDC2, VOUT = 3.3 V
Figure 31
vs Output Current, DCDC3, VOUT = 1.35 V
Figure 32
vs Input Voltage, DCDC1, VOUT = 5 V
Figure 33
vs Input Voltage, DCDC2, VOUT = 3.3 V
Figure 34
vs Input Voltage, DCDC3, VOUT = 1.35 V
Figure 35
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Inductor current ripple
vs Output Current, DCDC1, VOUT = 5 V
60
50
40
30
50
40
30
20
10
60
20
DCDC1, VOUT = 5 V
0
0.0001
0.001
0.01
0.1
Output Current (A)
VIN = 7.4 V
VIN = 11.6 V
1
10
DCDC2, VOUT = 3.3 V
0
0.0001
5
0.01
0.1
Output Current (A)
1
5
G001
Figure 3. Efficiency vs Output Current
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Figure 2. Efficiency vs Output Current
100
60
50
40
30
60
50
40
30
20
10
0.001
G001
VIN = 7.4 V
VIN = 11.6 V
20
DCDC3, VOUT = 1.0 V
0
0.0001
0.001
0.01
0.1
Output Current (A)
VIN = 7.4 V
VIN = 11.6 V
1
10
5
DCDC3, VOUT = 1.35 V
0
0.0001
G001
Figure 4. Efficiency vs Output Current
0.001
0.01
0.1
Output Current (A)
VIN = 7.4 V
VIN = 11.6 V
1
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G001
Figure 5. Efficiency vs Output Current
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
SLVSBO6B – JANUARY 2013 – REVISED JULY 2015
60
50
40
30
50
40
30
20
10
60
20
VIN = 7.4 V
VIN = 11.6 V
DCDC3, VOUT = 1.8 V
0
0.0001
0.001
0.01
0.1
Output Current (A)
1
10
0
0.0001
5
90
80
80
70
70
Efficiency (%)
Efficiency (%)
100
90
60
50
40
30
G001
60
50
40
VIN = 7.4 V
VIN = 11.6 V
DCDC3, VOUT = 4.0 V
0.001
0.01
0.1
Output Current (A)
1
10
0
0.0001
5
VIN = 7.4 V
VIN = 11.6 V
DCDC3, VOUT = 5.0 V
0.001
G001
Figure 8. Efficiency vs Output Current
0.01
0.1
Output Current (A)
1
5
G001
Figure 9. Efficiency vs Output Current
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
5
20
0
0.0001
60
50
40
30
60
50
40
30
20
20
VIN = 12 V
VIN = 15 V
Charger, VOUT = 8.4 V
0.5
1.0
1.5
2.0
2.5
Output Current (A)
3.0
3.5
10
4.0
VIN = 13.5 V
VIN = 15 V
Charger, VOUT = 12.6 V
0
0.0
G001
Figure 10. Efficiency vs Output Current
20
1
30
20
0
0.0
0.01
0.1
Output Current (A)
Figure 7. Efficiency vs Output Current
100
10
0.001
G001
Figure 6. Efficiency vs Output Current
10
VIN = 7.4 V
VIN = 11.6 V
DCDC3, VOUT = 3.3 V
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0.5
1.0
1.5
2.0
2.5
Output Current (A)
3.0
3.5
4.0
G001
Figure 11. Efficiency vs Output Current
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
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60
50
40
30
0
6.0
50
40
30
20
10
60
DCDC1, VOUT = 5.0 V
7.0
8.0
9.0 10.0 11.0 12.0
Input Voltage (V)
IOUT = 10 mA
IOUT = 1 A
IOUT = 5 A
13.0
14.0
20
10
DCDC2, VOUT = 3.3 V
0
6.0
15.0
7.0
100
100
90
90
80
80
70
70
60
50
40
30
DCDC3, VOUT = 1.0 V
7.0
8.0
9.0 10.0 11.0 12.0
Input Voltage (V)
IOUT = 10 mA
IOUT = 1 A
IOUT = 4 A
G001
40
13.0
14.0
20
10
DCDC3, VOUT = 1.35 V
0
6.0
15.0
7.0
8.0
G001
9.0 10.0 11.0 12.0
Input Voltage (V)
IOUT = 10 mA
IOUT = 1 A
IOUT = 4 A
13.0
14.0
15.0
G001
Figure 15. Efficiency vs Input Voltage
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
15.0
50
Figure 14. Efficiency vs Input Voltage
60
50
40
30
60
50
40
30
20
0
6.0
14.0
60
100
10
13.0
30
20
0
6.0
9.0 10.0 11.0 12.0
Input Voltage (V)
Figure 13. Efficiency vs Input Voltage
Efficiency (%)
Efficiency (%)
Figure 12. Efficiency vs Input Voltage
10
8.0
G001
IOUT = 10 mA
IOUT = 1 A
IOUT = 5 A
DCDC3, VOUT = 1.8 V
7.0
8.0
9.0 10.0 11.0 12.0
Input Voltage (V)
IOUT = 10 mA
IOUT = 1 A
IOUT = 4 A
13.0
14.0
20
10
15.0
DCDC3, VOUT = 3.3 V
0
6.0
G001
Figure 16. Efficiency vs Input Voltage
7.0
8.0
9.0 10.0 11.0 12.0
Input Voltage (V)
IOUT = 10 mA
IOUT = 1 A
IOUT = 4 A
13.0
14.0
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G001
Figure 17. Efficiency vs Input Voltage
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
SLVSBO6B – JANUARY 2013 – REVISED JULY 2015
60
50
40
30
60
50
40
30
20
10
DCDC3, VOUT = 4.0 V
0
6.0
7.0
8.0
9.0 10.0 11.0 12.0
Input Voltage (V)
IOUT = 10 mA
IOUT = 1 A
IOUT = 4 A
13.0
14.0
20
10
DCDC3, VOUT = 5.0 V
0
6.0
15.0
7.0
100
100
90
90
80
80
70
70
60
50
40
30
15.0
G001
60
50
40
VIN = 12 V
VIN = 15 V
Charger, ICHG = 1 A
3
4
5
6
7
8
9
Battery Voltage (V)
10
11
10
0
12
VIN = 12 V
VIN = 15 V
Charger, ICHG = 2 A
3
4
5
G000
Figure 20. Efficiency vs Battery Voltage
6
7
8
9
Battery Voltage (V)
10
11
12
G000
Figure 21. Efficiency vs Battery Voltage
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
14.0
20
10
60
50
40
30
60
50
40
30
20
20
10
VIN = 12 V
VIN = 15 V
Charger, ICHG = 3 A
3
4
5
6
7
8
9
Battery Voltage (V)
10
11
10
12
0
VIN = 12 V
VIN = 15 V
Charger, ICHG = 4 A
3
G000
Figure 22. Efficiency vs Battery Voltage
22
13.0
30
20
0
9.0 10.0 11.0 12.0
Input Voltage (V)
Figure 19. Efficiency vs Input Voltage
Efficiency (%)
Efficiency (%)
Figure 18. Efficiency vs Input Voltage
0
8.0
G001
IOUT = 10 mA
IOUT = 1 A
IOUT = 4 A
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4
5
6
7
8
9
Battery Voltage (V)
10
11
12
G000
Figure 23. Efficiency vs Battery Voltage
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1200
1200
DCDC1, VOUT = 5.0 V
DCDC2, VOUT = 3.3 V
1000
Frequency (kHz)
Frequency (kHz)
1000
800
600
400
200
0.1
Output Current (A)
1
600
400
200
VIN = 7.4 V
VIN = 11.6 V
0
0.01
800
VIN = 7.4 V
VIN = 11.6 V
0
0.01
5
0.1
Output Current (A)
G001
Figure 24. Switching Frequency vs Output Current
1
5
G001
Figure 25. Switching Frequency vs Output Current
1200
1200
DCDC3, VOUT = 1.35 V
1000
Frequency (kHz)
Frequency (kHz)
1000
800
600
400
200
0.1
Output Current (A)
1
400
0
6.0
5
1000
1000
Frequency (kHz)
1200
800
600
400
8.0
9.0 10.0 11.0 12.0
Input Voltage (V)
13.0
14.0
13.0
14.0
15.0
G001
800
600
400
IOUT = 1 A
IOUT = 4 A
DCDC3, VOUT = 1.35 V
15.0
0
6.0
G001
Figure 28. Switching Frequency vs Input Voltage
9.0 10.0 11.0 12.0
Input Voltage (V)
200
IOUT = 1 A
IOUT = 4 A
DCDC2, VOUT = 3.3 V
7.0
8.0
Figure 27. Switching Frequency vs Input Voltage
1200
0
6.0
7.0
G001
200
IOUT = 1 A
IOUT = 4 A
DCDC1, VOUT = 5.0 V
Figure 26. Switching Frequency vs Output Current
Frequency (kHz)
600
200
VIN = 7.4 V
VIN = 11.6 V
0
0.01
800
7.0
8.0
9.0 10.0 11.0 12.0
Input Voltage (V)
13.0
14.0
15.0
G001
Figure 29. Switching Frequency vs Input Voltage
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1400
1400
1200
1200
1000
1000
Current (mA)
Current (mA)
SLVSBO6B – JANUARY 2013 – REVISED JULY 2015
800
600
400
0
0.01
0.1
Output Current (A)
200
VIN = 7.4 V
VIN = 11.6 V
DCDC1, VOUT = 5.0 V
1
0
0.01
5
1
5
G001
Figure 31. Inductor Current Ripple vs Output Current
1600
1200
1400
1200
Current (mA)
1000
Current (mA)
0.1
Output Current (A)
G001
1400
800
600
400
1000
800
600
400
200
VIN = 7.4 V
VIN = 11.6 V
DCDC3, VOUT = 1.35 V
0
0.01
0.1
Output Current (A)
1
IOUT = 1 A
IOUT = 4 A
200
DCDC1, VOUT = 5.0 V
0
6.0
5
7.0
8.0
G001
Figure 32. Inductor Current Ripple vs Output Current
1400
1400
1200
1200
Current (mA)
1600
1000
800
600
400
9.0 10.0 11.0 12.0
Input Voltage (V)
13.0
14.0
15.0
G001
Figure 33. Inductor Current Ripple vs Input Voltage
1600
1000
800
600
400
IOUT = 1 A
IOUT = 4 A
200
DCDC2, VOUT = 3.3 V
0
6.0
VIN = 7.4 V
VIN = 11.6 V
DCDC2, VOUT = 3.3 V
Figure 30. Inductor Current Ripple vs Output Current
Current (mA)
600
400
200
7.0
8.0
9.0 10.0 11.0 12.0
Input Voltage (V)
13.0
14.0
IOUT = 1 A
IOUT = 4 A
200
DCDC3, VOUT = 1.35 V
15.0
0
6.0
G001
Figure 34. Inductor Current Ripple vs Input Voltage
24
800
7.0
8.0
9.0 10.0 11.0 12.0
Input Voltage (V)
13.0
14.0
15.0
G001
Figure 35. Inductor Current Ripple vs Input Voltage
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7 Detailed Description
7.1 Overview
The TPS65090A is a single-chip power management IC for portable applications consisting of a battery charger
with power path management for a dual or triple Li-Ion or Li-Polymer cell battery pack, three step-down
converters, two always-on LDOs, and seven load switches with independent inputs.
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7.2 Functional Block Diagram
ACG
ACS
ACN
ACP
VSYSC
VSYSC
VACS
BATG
VAC
VBAT
VREFT
TS1
Switchmode Charger
VLDO2
22uF
System Supply Control
22uF
TS2
STAT
J
J
FBC
ENC
SRN
VAC
VBAT
VACG
SRP
IAC
IBAT
VSYSG
IDCDC1
IDCDC2
IDCDC3
VBATG
IFET1
IFET2
IFET3
IFET4
IFET5
IFET6
IFET7
VREFADC
VSYSC
Analog
CBC
10 BIT ADC
Multiplexer
2.2uH
LC
22uF
PGNDC
VCTRL
VREF
Device Control
SCL
I²C
SDA
IRQ
GND
CB1
VSYS1
DCDC1
Step-Down Converter
Control
EN1
2.2uH
L1
VDCDC1
VDCDC1
22uF
FB1
PGND1
CB2
VSYS2
DCDC2
Step-Down Converter
Control
EN2
2.2uH
L2
VDCDC2
VDCDC2
22uF
FB2
PGND2
CB3
VSYS3
DCDC3
Step-Down Converter
Control
EN3
2.2uH
L3
VDCDC3
PGND3
22uF
FB3
VDCDC3
VSYS_L1
VDCDC1
VSYS_L2
Internal Biasing
Always On LDO‘s
VLDO1
FB_L1
2.2uF
VDCDC2
VLDO2
FB_L2
INFET1
2.2uF
Current Controlled
Load Switch
VFET1
Current Controlled
Load Switch
VFET2
Current Controlled
Load Switch
VFET3
Current Controlled
Load Switch
VFET4
Current Controlled
Load Switch
VFET5
Current Controlled
Load Switch
VFET6
Current Controlled
Load Switch
VFET7
INFET2
INFET3
INFET4
INFET5
INFET6
INFET7
26
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7.3 Feature Description
7.3.1 Always On LDOs
As soon as a valid voltage at VSYS is applied, the LDOs start operating and providing a regulated output voltage
at each of them. If DCDC1 is started, the output of the DCDC1 converter will be connected to the output of LDO1
with an internal bypass switch to ensure seamless transition. Finally, LDO1 will stop operating. LDO1 will restart
when the voltage at its output drops below its regulation voltage. In this case, both outputs will be disconnected
from each other. There will be no current flowing backward from the LDO1 output to the DCDC1 output. The
same function is implemented for DCDC2 and LDO2.
7.3.2 Power Path Control
The device automatically switches adapter or battery power to the system load. The battery is connected to the
system by default during power up or if the adapter power is not available. As soon as a valid voltage is detected
on VACS and the voltage at VAC is higher than the battery voltage, the battery is disconnected and the AC
power path switches controlled through the pins ACG and ACS are turned on. The system is powered through
the adapter input. If the voltage on VACS is higher than the overvoltage protection threshold the AC power path
switches are turned off or not turned on to protect the system from damage. Any voltage on VACS lower than the
input undervoltage lockout (UVLO) threshold voltage will cause the AC power path switches to be off.
To protect the device and the system against reverse voltage additional external components are required to
protect the pins VAC, VACS ACG and ACS which would be exposed to the reverse voltage. See the EVM
documentation SLVU778 for more details.
In case the maximum adapter output current is not high enough to supply the complete system, the system can
be powered through the adapter and the battery at the same time. If the adapter current is limited, the adapter
voltage will drop to the battery voltage level and the backgate diode of the battery switch will conduct current.
To minimize the losses in this mode of operation, the battery switch is turned on. To detect whether there is still a
power source connected at the AC input, the AC power path switches are turned off every 0.5 s for a few
milliseconds. While the AC power path switches are off, VAC is discharged through a 1-kΩ resistor to GND. If the
voltage at VACS did not drop below the input UVLO threshold voltage, the AC power path switches are turned on
again to allow the power source connected to the AC input to supply the system again.
7.3.3 Supply Status Outputs
The status of the power supply is indicated through the status pins VACG, VBATG and VSYSG. All pins are
open-drain outputs and need a pullup resistor to the respective logic supply voltage they are connected to.
VACG will be high if a voltage is detected at VAC and VACS which is in a useable window. This means the
voltage detected at VACS must be lower than the overvoltage threshold and it must be higher than the input
UVLO threshold voltage. Also, the voltage at VAC must be higher than battery voltage. If no battery is connected,
the minimum voltage is above the UVLO threshold.
VSYSG will be high as soon as the system voltage, detected at VSYS_L1 and VSYS_L2, is above its
undervoltage thresholds.
VBATG will be high if the voltage detected at FBC is between the minimum and the maximum voltage for battery
good detection and the differential voltage VSRN - VVBAT is lower than 20 mV. This indicates that the battery
discharge current is not exceeding the programmed maximum level.
7.3.4 Charger
Charging can be enabled by using the ENC pin or by programming the respective register through I2C. The
charger will then start working when VACG is detected. If the battery is completely charged or charging has been
terminated for any other reason, the charger will stay idle. Charging can be restarted by disabling the charger
and enabling it again.
As soon as the charger is enabled it starts with battery detection as shown in Figure 36. If no battery or a battery
short is detected the charger will continue with battery detection. If the battery is detected it will start charging.
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Feature Description (continued)
POR or RECHARGE
Apply 8–mA discharge
current, start 1–s timer
VFBC < VFBCL
No
1–s timer
expired
Yes
No
Yes
Battery Present,
Begin Charge
Disable 8–mA
discharge current
Enable 125–mA charge
current, start 0.5–s timer
VFBC > VFBCR
No
0.5–s timer
expired
Yes
Yes
Disable 125–mA
charge current
No
Battery Present,
Begin Charge
Battery Absent
Figure 36. Battery Detection
The charger controls a low constant-charge current during a precharge phase when the battery is at a very low
voltage and must be recovered. The charger controls a high fast-charge current if the battery voltage is greater
than the low voltage threshold and less than the charge termination voltage. If the battery voltage has reached
the charge termination voltage, the charger controls this voltage until the charge current has decayed below the
charge termination threshold or the fast-charge safety timer has timed out. Precharge current and charge
termination current are either 10% of the programmed fast-charge current if the fast-charge current is set to 1 A
or higher. Otherwise they will be controlled to 100 mA. A complete charging cycle is shown in Figure 37.
28
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Feature Description (continued)
Regulation Voltage
Recharge Voltage
Precharge
Current
Regulation
Phase
Fast–charge Current
Regulation Phase
Fast–charge Voltage
Regulation Phase
Termination
Fast–charge Current
Charge
Current
Charge
Voltage
Precharge to Fast–charge
Transition Voltage
Precharge Current
Precharge
Timer
Fast–charge Safety Timer
Figure 37. Charging Cycle
To support charging with weak power sources, the charger stays in operation even if it cannot control the charge
current at the programmed level. For this operating condition, the charge termination based on low charge
current can be turned off by programming the respective register.
The fast-charge safety timer is programmed to its lowest value by default. The time-out time can be increased by
programming higher values in the respective registers. It cannot be turned off.
All charge currents are defined depending on the current sense resistor connected between the pins SRN and
SRP. The maximum fast-charge current generates a 40 mV voltage drop across this resistor. All other currents
are lower.
The charge termination voltage is defined by a resistive voltage divider connected between battery, feedback
input of the charger (FBC), and GND. The maximum voltage at FBC which is controlled is typically 2.1 V.
The charger has also inputs to measure the battery cell temperature. It supports using two different temperature
sensors which can be placed at different locations in the battery pack. For more details on the temperature
sensing circuit, refer to Application and Implementation. For biasing the temperature sense resistor networks and
the internal comparator reference the voltage at the VREFT pin is used. It is turned off if the charger is disabled.
Charge current and charge termination voltage can be programmed to lower than the maximum values using the
digital interface. They are also controlled and forced to lower values depending on the measured battery cell
temperature. The respective values for the five different temperature regions can be programmed in the charge
control registers (CG_CTRLx) using the digital interface. Default settings for temperature thresholds and the
respective fast-charge current and charge termination voltages are defined according to JEITA recommendations
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Feature Description (continued)
for multicell battery packs. The definitions for the thresholds and temperature zones are shown in Figure 38.
Figure 38 also shows the default values for temperature thresholds, charge current and charge termination
voltage, which are programmed in TPS65090A. The optional values which can be programmed through the
digital interface, can be found in Electrical Characteristics. The actual temperature zones the charger operates in,
can be read out from the charge status register CG_STATUS1.
maximum Charge Current
100% charge current
Charge
Current
50% charge
current
50% charge
current
No charge
current
No charge
current
maximum Charge Voltage
Charge
Voltage
Temperature
Zones
FBC control
voltage 2.075 V
FBC control voltage 2.1 V
FBC control
voltage 2.05 V
FBC control
voltage 2.0 V
T01
FBC control
voltage 2.0 V
T12
T1 (0°C)
T34
T23
T2 (10°C)
T3 (45°C)
Temperature
T40
T4 (60°C)
Figure 38. JEITA Charging Profile
If the adapter current measured with a sense resistor between the pins ACN and ACP exceeds its programmed
value or the adapter voltage measured at VACS drops below a certain level (typically 7 V, see Electrical
Characteristics) the charge current is reduced automatically to avoid an overload condition of the AC adapter and
an undervoltage condition for the system. The charge current is also reduced if the charger temperature
measured in the IC is exceeding 100°C.
The charger indicates its current status of operation in two ways. One is the STAT output pin which can be used
to drive an LED. The STAT pin can have three different states as described in Table 1. To get details about the
current state of charging the charging status register CG_STATUS1 can be read.
Table 1. Charger Status Pin STAT
30
CHARGING STATE
STAT PIN STATE
Charging complete
Sleep mode
Charging disabled
HIGH
Charging in progress (including recharging)
LOW
Charging suspended
No battery detected
Safety timer fault (precharge, fast-charge)
Blinking with 0.5 Hz
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A status change from charging suspended to charging active and back sets the interrupt CGACT and charging
completed sets the interrupt CGCPL. Both interrupts can be masked. If not masked, they will trigger IRQ pin to
go low when they are set.
7.3.5 DC-DC Converters
The built in DC-DC converters are completely integrated except the required passive components. To maintain
high efficiency, they are implemented as synchronous step-down converters. At medium and heavy loads they
are operating in a PWM mode. As soon as the inductor current gets discontinuous, which means that the output
current gets lower than half of the inductor ripple current the converters enter Power Save Mode. In Power Save
Mode the switching frequency decreases linearly with the load current maintaining high efficiency. The transition
into and out of Power Save Mode happens within the entire regulation scheme and is seamless in both
directions.
All DC-DC converters can be enabled using their ENx pins. If they should be enabled using the digital interface
the enable pin function can be masked in the DCDCx_CTRL register. If masked enable only works by writing a 1
to the EN bit in the DCDCx_CTRL register.
As soon as the output voltage reaches 80% of the input voltage, the power good register bit for this converter is
set to 1. If the output voltage drops below this threshold the power good bit is set back to 0.
The start-up of the converter is controlled by an internal soft-start to make sure the output voltage is built up
smoothly and the inrush current during start-up is kept at minimum.
All converters are current limited. The current limit is controlling the maximum output current. If the current limit is
controlling the converter its respective OLDCDCx interrupt bits are set to 1. The OLDCDCx interrupt bits can be
masked. If not masked, they will trigger IRQ pin to go low when they are set.
To make sure that the output voltage of the DC-DC converters is decreasing fast to a safe low value a built in
output auto-discharge function can be enabled using the ADENDCDC bit in the respective DCDCx_CTRL
register. If enabled, the output capacitors are actively discharged as soon as the converter is disabled. While the
converter is enabled, its output discharge circuit is off to save power.
7.3.6 Load Switches
Load switches are turned on using the digital control interface by writing 1 in the ENFETx bit of their load switch
control register FETx_CTRL. They cannot be enabled before DCDC1 and DCDC2 have been started and their
output voltage is above their power good level. If DCDC1 or DCDC2 will be disabled, load switches will be
immediately disabled as well and enabled if both DC-DC converters are enabled again.
After being turned on, the output voltage of the load switch is ramped up with a controlled slope (
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