Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
TPS65094 PMIC for Intel™ Apollo Lake Platform
1 Device Overview
1.1
Features
1
• Wide VIN range from 5.6 V to 21 V
• Three variable-output voltage synchronous
Step-down controllers With D-CAP2™ Topology
– 5 A for BUCK1 (VNN), 7 A for BUCK6 (VDDQ),
and 21 A for BUCK2 (VCCGI) using external
FETs for typical applications
– I2C Dynamic Voltage Scaling (DVS) control
(0.5 V to 1.45 V in 10-mV Steps) for BUCK1 and
BUCK2
– OTP-Programmable default output voltage for
BUCK6 (VDDQ)
• Three variable-output voltage synchronous
Step-down converters with dcs-control topology
and I2C DVS capabilities
– VIN range from 4.5 V to 5.5 V
– 3 A of output current for BUCK3 (VCCRAM)
– 2 A of output current for BUCK4 (V1P8A) and
1.2
•
•
•
•
•
Applications
2-, 3-, or 4-Series cell li-ion battery-powered
products (NVDC or Non-NVDC)
Wall-powered designs, particularly from 12-V
supply
1.3
•
BUCK5 (V1P24A) for typical applications
Three LDO regulators with adjustable output
voltage
– LDOA1: I2C-Selectable output voltage from 1.35
V to 3.3 V for up to 200 mA of output current
– LDOA2 and LDOA3: I2C-Selectable output
voltage from 0.7 V to 1.5 V for up to 600 mA of
Output Current
VTT LDO for DDR memory termination
Three load switches with slew rate control
– Up to 400 mA of output current with voltage
drop less than 1.5% of nominal input voltage
– RDSON < 96 mΩ at input voltage of 1.8 V
I2C Interface (device address 0x5E) supports:
– Standard mode (100 kHz)
– Fast mode (400 kHz)
– Fast mode plus (1 MHz)
•
•
Tablets, Ultrabook™, and notebook computers
Mobile PCs and mobile internet devices
Description
The TPS65094 device is a single-chip solution, power-management integrated chip (PMIC) designed
specifically for the latest Intel™ processors targeted for tablets, ultrabooks, notebooks, industrial PCs, and
Internet-of-Things (IOT) applications using 2S, 3S, or 4S Li-Ion battery packs (NVDC or non-NVDC power
architectures), as well as wall-powered applications. The TPS65094 device is used for essential systems
with low-voltage rails merged for the smallest footprint and lowest-cost system-power solution. The
TPS65094 device provides the complete power solution based on the Intel Reference Designs. Six highly
efficient step-down voltage regulators (VRs), a sink or source LDO (VTT), and a load switch are controlled
by power-up sequence logic to provide the proper power rails, sequencing, and protection—including
DDR3 and DDR4 memory power. The two regulators (BUCK1 and BUCK2) support dynamic voltage
scaling (DVS) for maximum efficiency—including support for Connected Standby. The high-frequency VRs
use small inductors and capacitors to achieve a small solution size. An I2C interface allows simple control
by an embedded controller (EC) or by a system on chip (SoC).
The PMIC comes in an 8-mm × 8-mm single-row VQFN package with a thermal pad for good thermal
dissipation and ease of board routing.
Device Information (1)
PART NUMBER
TPS65094
(1)
PACKAGE
BODY SIZE (NOM)
VQFN (64)
8.00 mm × 8.00 mm
For all available packages, see the orderable addendum at the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
1.4
www.ti.com
Functional Block Diagram
PMICEN
SLP_S3B
LDOA1
1.35 V to 3.3 V
1.8 V(b)
200 mA
LDOLS_EN(a)
SWA1_EN(b)
BOOT1
DRVH1
BUCK1
Default: 1V
VSET
SLP_S4B
SLP_S0B
VSYS
DRV5V_1_6
EC
LDO5V
DRV5V_2_A1
LDOA1
Optional(a)
Required(b)
EN
EN
Control
Inputs
SW1
Typical
Application
Usage:
0.5 V to 1.45 V
(DVS)
5A
VNN
DRVL1
FBVOUT1
PGNDSNS1
ILIM1
THERMTRIPB
VSYS
V1P8A
BOOT2
DRVH2
CLK
SoC
DATA
I2C CTRL
BUCK2
Default: 0V
SW2
VSET
V1P8A
EN
Control
Outputs
PCH_PWROK
RSMRSTB
PROCHOT
Internal
Interrupt
Events
GPO
INTERRUPT_CNTL
IRQB
VCCGI
DRVL2
Typical
Application
Usage:
0.5 V to 1.45 V
(DVS)
21 A
FBVOUT2
PGNDSNS2
FBGND2
ILIM2
BUCK5V
PVIN3
TEST CTRL
VSET
OTP
EN
REGISTERS
LX3
BUCK3
Default: 1.05 V
3A
VCCRAM
FB3
BUCK5V
PVIN4
VSYS
VSYS
BUCK5V
Digital Core
V5ANA
VSET
EN
BUCK4
Default: 1.8 V
2A
LDO5
V1P8A
LDO5V
LDO3P3
LX4
FB4
REFSYS
nPUC
BUCK5V
PVIN5
VREF
VSET
EN
LX5
BUCK5
Default: 1.24 V
2A
V1P24A
FB5
AGND
VSYS
Thermal
monitoring
BOOT6
DRVH6
Thermal shutdown
VSET
EN
SW6
BUCK6
Default: OTP
Dependent
7A
VDDQ
DRVL6
FBVOUT6
PGNDSNS6
ILIM6
PVINVTT
(a) LDOA1 1RW ³$OZD\V 2Q´
(b) LDOA1 ³$OZD\V 2Q´
VTT
EN
PVINSWB1_B2
SWB1
VTT
VTTFB
LOAD SWB2
400 mA
SWB2
EN
EN
PVINSWA1
LOAD SWB1
400 mA
SWA1
V1P8U(1)
V1P8A(1)
0.5 V to 3.3 V(2)
0.5 V to 3.3 V
SWB1_2(2)
VSET
EN
LOAD SWA1
300 mA
SWA1
(1) LPDDR3 and LPDDR4
(2) DDR3L
LDOA3
0.7 V to 1.5 V
600 mA
0.5 V to 3.3 V
Dashed connections optional.
Refer to Pin Attributes for
connection if unused.
PVINLDOA2_A3
LDOA2
LDOA2
0.7 V to 1.5 V
600 mA
LDOA3
EN
VSET
EN
VTT_LDO
½ × VDDQ
ILIM set by OTP
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. PMIC Functional Block Diagram
2
Device Overview
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Table of Contents
1
2
3
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 1
1.3
Description ............................................ 1
1.4
Functional Block Diagram ............................ 2
Revision History ......................................... 3
Device Options ........................................... 5
OTP Comparison ..................................... 5
3.1
4
5
6
Pin Configuration and Functions ..................... 6
Specifications ........................................... 10
5.1
Absolute Maximum Ratings ......................... 10
5.2
ESD Ratings
........................................
Recommended Operating Conditions ...............
Thermal Information .................................
5.3
5.4
5.5
11
11
Electrical Characteristics: Total Current
Consumption ........................................ 11
Electrical Characteristics: Reference and Monitoring
System .............................................. 12
5.6
Electrical Characteristics: Buck Controllers ......... 13
Electrical Characteristics: Synchronous Buck
Converters ........................................... 17
5.7
5.8
....................
5.9
Electrical Characteristics: LDOs
5.10
Electrical Characteristics: Load Switches ........... 24
5.11
5.12
Digital Signals: I2C Interface ........................ 25
Digital Input Signals (LDOLS_EN, SWA1_EN,
THERMTRIPB, PMICEN, SLP_S3B, SLP_S4B,
SLP_S0B) ........................................... 25
Digital Output Signals (IRQB, RSMRSTB,
PCH_PWROK, PROCHOT)......................... 25
5.13
7
10
20
8
9
10
...............................
...........................
5.16 Typical Characteristics ..............................
Detailed Description ...................................
6.1
Overview ............................................
6.2
Functional Block Diagram ...........................
6.3
Feature Description .................................
6.4
Device Functional Modes ...........................
6.5
Programming ........................................
6.6
Register Maps .......................................
Application and Implementation ....................
7.1
Application Information ..............................
7.2
Typical Application ..................................
7.3
Specific Application for TPS650944 ................
7.4
Do's and Don'ts .....................................
Power Supply Recommendations ..................
Layout ....................................................
9.1
Layout Guidelines ...................................
9.2
Layout Example .....................................
Device and Documentation Support ...............
10.1 Device Support .....................................
10.2 Documentation Support .............................
10.3 Receiving Notification of Documentation Updates ..
10.4 Community Resources ..............................
10.5 Trademarks..........................................
10.6 Electrostatic Discharge Caution .....................
10.7 Glossary .............................................
5.14
Timing Requirements
5.15
Switching Characteristics
25
26
27
28
28
29
31
48
48
52
72
72
72
81
82
82
83
83
83
84
84
84
84
84
84
84
84
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2019) to Revision D
•
•
•
Page
Added "TPS650947" column to Summary of TPS65094x OTP Differences table ........................................... 5
Changed TPS650945 DEVICEID register to "Dh" and TPS650944 DEVICEID register to "Ch" in Summary of
TPS65094x OTP Differences table ................................................................................................. 5
Added TPS650947 settings to Section 6.6 ...................................................................................... 52
Changes from Revision B (February 2017) to Revision C
•
•
•
•
•
•
•
•
•
Page
Changed TPS65094x to TPS65094 in title ........................................................................................ 1
Deleted variants from top of each page ........................................................................................... 1
Added "BUCK3-5 Mode" row and "TPS650945" column to Summary of TPS65094x OTP Differences table ........... 5
Changed the description of the VTTFB pin in the Pin Functions table ........................................................ 8
Changed VSYS to PVIN in the efficiency graphs for BUCK3, BUCK4, and BUCK5 in the Typical Characteristics
section ................................................................................................................................ 27
Added to the description of the deassertion condition that causes an emergency shutdown in the Emergency
Shutdown section ................................................................................................................... 47
Added TPS650945 settings to Section 6.6 ...................................................................................... 52
Changed OCP event to power fault event in the OCP bit description in the OFFONSRC Register Field
Descriptions table ................................................................................................................... 54
Changed second reference of TPS650940 to TPS650944 for the bit reset values in the LDOA2VID Register
Field Descriptions and LDOA3VID Register Field Descriptions tables ....................................................... 62
Revision History
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
3
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
•
www.ti.com
Changed the bit values of the LDOA3_SLPVID[0] and LDOA3_VID[0] bits in the LDOA3VID Register figure ......... 63
Changes from Revision A (June 2016) to Revision B
•
•
•
•
•
Page
Updated the PROCHOT pin description in the Pin Functions table ............................................................ 9
Changed the values for LX3, LX4, LX5 from –1 V and 7 V to –2 V and 8 V in the Absolute Maximum Ratings table 10
Changed the reset value of the LDOA2 VID register (LDOA2VID) to OTP dependent .................................... 62
Added the Receiving Notification of Documentation Updates section ....................................................... 84
Changed the Electrostatic Discharge Caution statement ...................................................................... 84
Changes from September 11, 2015 to June 2, 2016 (from * Revision (September 2015) to A Revision)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4
Page
Released full data sheet as SWCS133A version from SWCS130B version .................................................. 1
Changed device status to PROD_DATA .......................................................................................... 1
Changed VIN recommended minimum ............................................................................................. 1
Changed Features to improve description of converters ....................................................................... 1
Changed Features to up to 400 mA of output current for load switches ...................................................... 1
Changed functional block diagram to include TPS65094x family ............................................................. 2
Changed the Functional Block Diagram to include an inverter on PROCHOT pin........................................... 2
Changed PROCHOTB to PROCHOT throughout the document ............................................................... 6
Changed minimum absolute-maximum-rating value for SW1, SW2, and SW6 in Section 5.1............................ 10
Changed VSYS in Section 5.3, Recommended Operating Conditions ...................................................... 11
Deleted nominal value from PVINVTT in Section 5.3, Recommended Operating Conditions ........................... 11
Deleted (nu = symbol for efficiency) ............................................................................................. 13
Changed BUCK1 DC output voltage step size to show full range and be consistent in Section 5.7 .................... 13
Changed typo to match correct default of 1 V for ΔVOUT_TR in Section 5.7 ................................................. 13
Changed BUCK2 DC output voltage to show full range and be consistent in Section 5.7 ................................ 14
Changed set condition for BUCK6 for VOUT range in Section 5.7 to match BUCK1 and BUCK2 ........................ 15
Updated formatting and added new OTP information for BUCK6 in Section 5.7 ........................................... 15
Updated formatting for BUCK3 DC output voltage in Section 5.8 ............................................................ 17
Changed DC output voltage formatting for BUCK4 in Section 5.8 ........................................................... 18
Changed maximum IOUT value for BUCK4 in Section 5.8 to match device capabilities ................................... 18
Changed IOUT and ΔVOUT/ΔIOUT for VTT LDO in Section 5.9 for new OTPs ................................................. 23
Changed test conditions for VTT LDO overcurrent protection in Section 5.9 ............................................... 23
Changed Section 5.10 to show SWB1_2 RDSON is specified per output .................................................... 24
Changed fSW values in Section 5.15 to provide more values ................................................................. 26
Changed current to 1.9 A to match SoC requirements in Table 6-1 ......................................................... 28
Changed BUCK6, LDOA2, LDOA3 typical output voltage range to: OTP Dependent in Table 6-1 ...................... 28
Changed table note to include additional DDR types in Table 6-1 ........................................................... 28
Changed PMIC Functional Block Diagram to match specifications table ................................................... 30
Changed PROCHOTB to PROCHOT in the Apollo Lake Power Map ....................................................... 30
Changed current ratings in Apollo Lake Power Map ........................................................................... 30
Deleted SWBx PG from PG of PCH_PWROK in Table 6-2 ................................................................... 31
Changed BUCK1–2 to all BUCKs and LDOAs in Section 6.3.3.3 ............................................................ 36
Added Table 6-5 and Table 6-6 to Section 6.3.4.2 ............................................................................. 38
Added more DDR values to the table note in Table 6-7 ....................................................................... 39
Changed Section 6.3.5 to include LDOA1 and reset information ............................................................. 40
Changed Section 6.6 to include multiple DDRs ................................................................................. 40
Changed Figure 6-7 and Figure 6-8 to include alternate SWB1_2 Timing .................................................. 42
Changed SWB1_2 from: V3P3A to: V1P8U in Table 6-10 .................................................................... 42
Changed VDDQ voltage to OTP Dependent and SWBx to SWB1_2 in Table 6-11 ....................................... 44
Updated Figure 6-10 to include alternate SWB1_2 Timing .................................................................... 45
Changed Section 6.3.5.5 to include alternate SWB1_2 Timing ............................................................... 46
Changed Section 6.3.5.6 to include THERMTRIPB ........................................................................... 47
Added the TPS65094x family OTP values to Section 6.6 ..................................................................... 52
Replaced VID values with link to full VID table in Table 6-18 and Table 6-19 .............................................. 55
Updated naming of bits in the TEMPHOT register.............................................................................. 71
Revision History
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
3 Device Options
3.1
OTP Comparison
Table 3-1 summarizes the differences between the various TPS65094x family OTPs.
Table 3-1. Summary of TPS65094x OTP Differences
TPS650940
TPS650941
TPS650942
TPS650944
TPS650945
TPS650947
LPDDR4
LPDDR3
DDR3L
LPDDR4
LPDDR4
DDR3L
1.1 V
1.2 V
1.35 V
1.1 V
1.1 V
1.35 V
Yes
No
No
Yes
Yes
No
0.95 A
0.95 A
1.8 A
1.8 A
0.95 A
1.8 A
SWB1_2 controlled by
SLP_S4B (V1P8U)
Yes
Yes
No
Yes
Yes
No
SWB1_2 controlled by
SLP_S3B
No
No
Yes
No
No
Yes
LDOLS_EN
LDOLS_EN
LDOLS_EN
SWA1_EN
LDOLS_EN
LDOLS_EN
No
No
No
Yes
No
No
3.3 V
3.3 V
3.3 V
1.8 V
3.3 V
3.3 V
DDR
BUCK6 Voltage
VTT Disabled
VTT IOCP (minimum)
Pin 14 Usage
LDOA1 Always On
LDOA1 Default Voltage
LDOA2 Default Voltage
1.2 V
1.2 V
1.2 V
0.7 V
1.2 V
1.2 V
LDOA3 Default Voltage
1.25 V
1.25 V
1.25 V
0.7 V
1.25 V
1.25 V
PMICEN Low Forces Reset
Yes
Yes
Yes
No
Yes
Yes
DEVICEID Register
8h
29h
1Ah
Ch
Dh
Fh
Auto
Auto
Auto
Auto
Forced PWM
Forced PWM
BUCK3-5 Mode
Device Options
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
5
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
4 Pin Configuration and Functions
ILIM2
SLP_S4B
SLP_S3B
SLP_S0B
THERMTRIPB
DATA
CLK
V5ANA
LDO5P0
VSYS
LDO3P3
VREF
AGND
LDOA2
PVINLDOA2_A3
LDOA3
RSK Package
64-Pin VQFN With Thermal Pad
Top View
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
FBGND2
1
48
VTTFB
FBVOUT2
2
47
VTT
DRVH2
3
46
PVINVTT
SW2
4
45
ILIM6
BOOT2
5
44
FBVOUT6
PGNDSNS2
6
43
DRVH6
DRVL2
7
42
SW6
DRV5V_2_A1
8
41
BOOT6
LDOA1
9
40
PGNDSNS6
LX3
10
39
DRVL6
PVIN3
11
38
DRV5V_1_6
FB3
12
37
DRVL1
PMICEN
13
36
PGNDSNS1
LDOLS_EN or
SWA1_EN
14
35
BOOT1
IRQB
15
34
SW1
RSMRSTB
16
33
DRVH1
28
29
30
31
32
PVINSWA1
27
SWA1
26
ILIM1
PVIN5
25
FBVOUT1
LX5
24
PROCHOT
SWB2
23
PCH_PWROK
PVINSWB1_B2
22
GPO
21
LX4
20
PVIN4
19
FB4
18
FB5
17
SWB1
TOP VIEW
PGND/Thermal Pad
NOTE: The thermal pad must be connected to the system power ground plane.
6
Pin Configuration and Functions
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Pin Functions
PIN
NO.
NAME
I/O
SUPPLY, OP
VOLTAGE
LEVEL
DESCRIPTION
SMPS REGULATORS
1
FBGND2
I
Remote negative feedback sense for BUCK2 controller. Connect to VCCGI VSS
SENSE sent from the SoC to the PMIC.
2
FBVOUT2
I
Remote positive feedback sense for BUCK2 controller. Connect to VCCGI VCC
SENSE sent from the SoC to the PMIC.
3
DRVH2
O
4
SW2
I
5
BOOT2
I
6
PGNDSNS2
I
7
DRVL2
O
5V
Low-side gate driver output for BUCK2 controller
8
DRV5V_2_A1
I
5V
5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF
(typical) ceramic capacitor. Shorted on board to LDO5P0 pin.
10
LX3
O
11
PVIN3
I
12
FB3
I
Remote feedback sense for BUCK3 converter. Connect to positive terminal of
output capacitor.
20
LX5
O
Switch node connection for BUCK5 converter. Connect to a 0.47-µH (typical)
inductor with less than 50-mΩ DCR.
21
PVIN5
I
22
FB5
I
Remote feedback sense for BUCK5 converter. Connect to positive terminal of
output capacitor.
23
FB4
I
Remote feedback sense for BUCK4 converter. Connect to positive terminal of
output capacitor.
24
PVIN4
I
25
LX4
O
Switch node connection for BUCK4 converter. Connect to a 0.47-µH (typical)
inductor with less than 50-mΩ DCR.
29
FBVOUT1
I
Remote feedback sense for BUCK1 controller. Connect to VNN VCC SENSE sent
from the SoC to the PMIC.
30
ILIM1
I
Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to
set current limit of external low-side FET.
33
DRVH1
O
34
SW1
I
35
BOOT1
I
36
PGNDSNS1
I
37
DRVL1
O
5V
Low-side gate driver output for BUCK1 controller
38
DRV5V_1_6
I
5V
5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF
(typical) ceramic capacitor. Shorted on board to LDO5P0 pin.
39
DRVL6
O
5V
Low-side gate driver output for BUCK6 controller
40
PGNDSNS6
I
41
BOOT6
I
42
SW6
I
43
DRVH6
O
VSYS + 5 V
High-side gate driver output for BUCK2 controller
Switch node connection for BUCK2 controller
VSYS + 5 V
Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between
this pin and SW2 pin.
Power GND connection for BUCK2. Connect to ground terminal of external lowside FET.
Switch node connection for BUCK3 converter. Connect to a 0.47-µH (typical)
inductor with less than 50-mΩ DCR.
Power input to BUCK3 converter. Bypass to ground with a 10-µF (typical) ceramic
capacitor.
5V
Power input to BUCK5 converter. Bypass to ground with a 10-µF (typical) ceramic
capacitor.
5V
Power input to BUCK4 converter. Bypass to ground with a 10-µF (typical) ceramic
capacitor.
5V
VSYS + 5 V
High-side gate driver output for BUCK1 controller
Switch node connection for BUCK1 controller
VSYS + 5 V
Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between
this pin and SW1 pin.
Power GND connection for BUCK1. Connect to ground terminal of external lowside FET.
Power GND connection for BUCK6. Connect to ground terminal of external lowside FET.
VSYS + 5 V
Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between
this pin and SW6 pin.
Switch node connection for BUCK6 controller
VSYS + 5 V
High-side gate driver output for BUCK6 controller
Pin Configuration and Functions
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
7
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
Pin Functions (continued)
PIN
NO.
NAME
I/O
SUPPLY, OP
VOLTAGE
LEVEL
DESCRIPTION
44
FBVOUT6
I
Remote feedback sense for BUCK6 controller. Connect to positive terminal of
output capacitor.
45
ILIM6
I
Current limit set pin for BUCK6 controller. Fit a resistor from this pin to ground to
set current limit of external low-side FET.
64
ILIM2
I
Current limit set pin for BUCK2 controller. Fit a resistor from this pin to ground to
set current limit of external low-side FET.
LDO and LOAD SWITCHES
9
LDOA1
O
1.35–3.3 V
LDOA1 output. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave
floating when not in use.
17
SWB1
O
0.5–3.3 V
(1.8-V
Typical)
Output of load switch B1. Bypass to ground with a 0.1-µF (typical) ceramic
capacitor. Short with SWB2.
18
PVINSWB1_B2
I
0.5–3.3 V
(1.8-V
Typical)
Power supply to load switch B1 and B2. Bypass to ground with a 1-µF (typical)
ceramic capacitor to improve transient performance. Connect to ground when not
in use.
19
SWB2
O
0.5–3.3 V
(1.8-V
Typical)
Output of load switch B2. Bypass to ground with a 0.1-µF (typical) ceramic
capacitor. Short with SWB1. Leave floating when not in use.
31
SWA1
O
0.5–3.3 V
Output of load switch A1. Bypass to ground with a 0.1-µF (typical) ceramic
capacitor. Leave floating when not in use.
32
PVINSWA1
I
0.5–3.3 V
Power supply to load switch A1. Bypass to ground with a 1-µF (typical) ceramic
capacitor to improve transient performance. Connect to ground when not in use.
46
PVINVTT
I
VDDQ
Power supply to VTT LDO. Bypass to ground with a 10-µF (minimum) ceramic
capacitor. Connect to ground when not in use.
47
VTT
O
VDDQ / 2
Output of load VTT LDO. Bypass to ground with 2× 22-µF (minimum) ceramic
capacitors. Leave floating when not in use.
48
VTTFB
I
VDDQ / 2
Remote feedback sense for VTT LDO. Connect to positive terminal of output
capacitor. Short to GND when not in use.
49
LDOA3
O
0.7–1.5 V
Output of LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
Leave floating when not in use.
50
PVINLDOA2_A3
I
1.8 V
Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7-µF (typical)
ceramic capacitor. Connect to ground when not in use.
51
LDOA2
O
0.7–1.5 V
Output of LDOA2. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
Leave floating when not in use.
54
LDO3P3
O
3.3 V
Output of 3.3-V internal LDO. Bypass to ground with a 4.7-µF (typical) ceramic
capacitor.
56
LDO5P0
O
5V
Output of 5-V internal LDO or an internal switch that connects this pin to V5ANA.
Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
57
V5ANA
I
5V
External 5-V supply input to internal load switch that connects this pin to LDO5P0
pin. Bypass this pin with an optional ceramic capacitor to improve transient
performance.
8
Pin Configuration and Functions
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Pin Functions (continued)
PIN
NO.
NAME
I/O
SUPPLY, OP
VOLTAGE
LEVEL
DESCRIPTION
INTERFACE
I
PMIC cold-boot pin. At assertion rising edge of the signal of this pin power state
transitions from G3 to S4/S5. Driving the pin to L shuts down all VRs.
14
LDOLS_EN or
SWA1_EN
I
Enable pin for LDOA2, LDOA3, and SWA1 when OTP is configured to
LDOLS_EN. Enable pin for just SWA1 when OTP is configured to SWA1_EN.
Resources turn on at assertion (H) and turn off at deassertion (L) of the pin.
Optionally, when the pin is pulled low, the host can write to enable bits in Reg
0xA0–Reg 0xA1 to control the rails.
15
IRQB
O
Open-drain output interrupt pin. Refer to Section 6.6.3, IRQ: PMIC Interrupt
Register, for definitions.
16
RSMRSTB
O
Open-drain output Always-ON-rail Power Good. It reflects a valid state whenever
VSYS is available.
26
GPO
O
Open-drain output controlled by an I2C register bit defined in Section 6.6.26,
GPO_CTRL: GPO Control Register, by the user, which then can be used as an
enable signal to an external VR.
27
PCH_PWROK
O
Open-drain output global Power Good. It reflects a valid state whenever VSYS is
available.
28
PROCHOT
O
Optional open-drain output for indicating PMIC thermal event. Invert before
connecting to SoC if used, otherwise leave floating. This pin is triggered when any
of the PMIC die temperature sensors detects the THOT temperature.
58
CLK
I
I2C clock
59
DATA
I/O
I2C data
60
THERMTRIPB
I
Thermal shutdown signal from SoC
61
SLP_S0B
I
Power state pin. PMIC goes into Connected Standby at falling edge and exits from
Connected Standby at rising edge.
62
SLP_S3B
I
Power state pin. PMIC goes into S3 at falling edge and exits from S3, transitions
into S0 at rising edge.
63
SLP_S4B
I
Power state pin. PMIC goes into S4 at falling edge and exits from S4, transitions
into S3 at rising edge.
53
VREF
O
52
AGND
—
55
VSYS
I
System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to
ground with a 1-µF (typical) ceramic capacitor.
Thermal pad
—
Connect to PCB ground plane using multiple vias for good thermal and electrical
performance.
13
PMICEN
REFERENCE
1.25 V
Band-gap reference output. Stabilize it by connecting a 100-nF (typical) ceramic
capacitor between this pin and quiet ground.
Analog ground. Do not connect to the thermal pad ground on top layer. Connect to
ground of VREF capacitor.
THERMAL PAD
—
Pin Configuration and Functions
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
9
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
5 Specifications
5.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
ANALOG
VSYS
–0.3
28
V
PVIN3, PVIN4, PVIN5, LDO5P0, DRV5V_1_6, DRV5V_2_A1, DRVL1, DRVL2, DRVL6
Input voltage from battery
–0.3
7
V
V5ANA
–0.3
6
V
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2
–0.3
0.3
V
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6
–0.3
34
V
SW1, SW2, SW6
–5 (2)
28
V
LX3, LX4, LX5
–2 (3)
8
V
BOOTx to SWx
–0.3
5.5
V
VREF, LDO3P3, FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5, ILIM1, ILIM2, ILIM6, PVINVTT,
VTT, VTTFB, PVINSWA1, SWA1, PVINSWB1_B2, SWB1, SWB2, LDOA1
Differential voltage
–0.3
3.6
V
PVINLDOA2_A3, LDOA2, LDOA3
–0.3
3.3
V
DATA, CLK, PCH_PWROK, RSMRSTB, GPO
–0.3
3.6
V
PMICEN, SLP_S4B, SLP_S3B, SLP_S0B, LDOLS_EN, SWA1_EN, THERMTRIPB, IRQB, PROCHOT
–0.3
7
V
Storage temperature, Tstg
–40
150
°C
DIGITAL IOs
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Transient for less than 5 ns.
Transient for less than 20 ns.
5.2
ESD Ratings
VALUE
VESD
(1)
(2)
10
Electrostatic
discharge
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
±1000
Charged Device Model (CDM), per JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
5.3
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
VSYS
5.6
13
VREF
–0.3
PVIN3, PVIN4, PVIN5, LDO5P0, V5ANA, DRV5V_1_6, DRV5V_2_A1
–0.3
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6
DRVL1, DRVL2, DRVL6
MAX
UNIT
ANALOG
21
V
1.3
V
5.5
V
–0.3
0.3
V
–0.3
26.5
V
–0.3
5.5
V
5
SW1, SW2, SW6
–1
21
V
LX3, LX4, LX5
–1
5.5
V
FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5
–0.3
3.6
V
LDO3P3, ILIM1, ILIM2, ILIM6, LDOA1
–0.3
3.3
V
PVINVTT
–0.3
VDDQ
V
VTT, VTTFB
–0.3
VDDQ / 2
V
PVINSWA1, SWA1
–0.3
3.6
V
PVINSWB1_B2, PVINLDOA2_A3, SWB1, SWB2
–0.3
1.8
V
LDOA2, LDOA3
–0.3
1.5
V
–0.3
3.3
V
3.3
DIGITAL IOs
DATA, CLK, PMICEN, SLP_S4B, SLP_S3B, LDOLS_EN, SWA1_EN,
SLP_S0B, THERMTRIPB, PROCHOT, IRQB, RSMRSTB, PCH_PWROK,
GPO
CHIP
TA
Operating ambient temperature
–40
27
85
°C
TJ
Operating junction temperature
–40
27
125
°C
5.4
Thermal Information
TPS65094x
THERMAL METRIC (1)
RSK (VQFN)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
25.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
11.3
°C/W
RθJB
Junction-to-board thermal resistance
4.4
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
4.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.7
°C/W
(1)
5.5
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
Electrical Characteristics: Total Current Consumption
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
ISD
PMIC shutdown current that includes IQ for
references, LDO5, LDO3P3, and digital core
TEST CONDITIONS
VSYS = 13 V, all functional output rails
are disabled
MIN
TYP
MAX
65
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
UNIT
µA
11
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
5.6
www.ti.com
Electrical Characteristics: Reference and Monitoring System
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
Band-gap reference voltage
VREF
1.25
Accuracy
–0.5%
CVREF
Band-gap output capacitor
VSYS_UVLO_5V
VSYS UVLO threshold for LDO5
VSYS falling
VSYS_UVLO_5V_HYS
VSYS UVLO threshold hysteresis for
LDO5
VSYS rising above
VSYS_UVLO_5V
VSYS_UVLO_3V
VSYS UVLO threshold for LDO3P3
VSYS falling
VSYS_UVLO_3V_HYS
VSYS UVLO threshold hysteresis for
LDO3P3
VSYS rising above
VSYS_UVLO_3V
TCRIT
Critical threshold of die temperature
TJ rising
TCRIT_HYS
Hysteresis of TCRIT
TJ falling
THOT
Hot threshold of die temperature
TJ rising
THOT_HYS
Hysteresis of THOT
TJ falling
V
0.5%
0.047
0.1
0.22
µF
5.24
5.4
5.56
V
200
3.45
3.6
mV
3.75
150
130
145
mV
160
10
110
115
V
°C
°C
120
10
°C
°C
LDO5
VIN
Input voltage at VSYS pin
VOUT
DC output voltage
IOUT
DC output current
IOCP
Overcurrent protection
Measured with output shorted to
ground
VTH_PG
Power Good assertion threshold in
percentage of target VOUT
VOUT rising
VTH_PG_HYS
Power Good deassertion hysteresis
VOUT rising or falling
IQ
Quiescent current
VIN = 13 V, IOUT = 0 A
COUT
External output capacitance
IOUT = 10 mA
4.9
13
21
5
5.1
V
100
180
mA
200
V
mA
94%
4%
20
2.7
4.7
µA
10
µF
1
Ω
V5ANA-to-LDO5P0 LOAD SWITCH
RDSON
On resistance
VIN = 5 V, measured from
V5ANA pin
to LDO5P0 pin at IOUT = 200
mA
VTH_PG
Power Good threshold for external
5-V supply
VV5ANA rising
4.7
V
VTH_HYS_PG
Power Good threshold hysteresis for
external 5-V supply
VV5ANA falling
100
mV
ILKG
Leakage current
Switch disabled,
VV5ANA = 5 V, VLDO5 = 0 V
10
µA
21
V
LDO3P3
VIN
Input voltage at VSYS pin
VOUT
IOUT
13
DC output voltage
IOUT = 10 mA
Accuracy
VIN = 13 V,
IOUT = 10 mA
3.3
–3%
3%
DC output current
40
IOCP
Overcurrent protection
Measured with output shorted to
ground
VTH_PG
Power Good assertion threshold in
percentage of target VOUT
VOUT rising
92%
VTH_PG_HYS
Power Good deassertion hysteresis
VOUT falling
3%
IQ
Quiescent current
VIN = 13 V,
IOUT = 0 A
20
COUT
External output capacitance
12
V
70
2.2
Specifications
mA
mA
4.7
µA
10
µF
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
5.7
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Electrical Characteristics: Buck Controllers
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5.6
13
21
UNIT
BUCK1
Power input voltage for
external HSD FET
VIN
Step size
10
0
BUCK1_VID[6:0] = 0000001
0.5
BUCK1_VID[6:0] = 0000010
0.51
⋮
⋮
BUCK1_VID[6:0] = 0110011 (default)
⋮
BUCK1_VID[6:0] = 1110101
1.66
BUCK1_VID[6:0] = 1110110–1111111
VOUT ≥ 1 V, IOUT = 100 mA to 5 A
DC output voltage
accuracy
V
1.00
⋮
VOUT
mV
BUCK1_VID[6:0] = 0000000
DC output voltage
1.67
–2%
2%
VOUT = 0.75 V, IOUT = 100 mA to 2.1 A
–2.5%
2.5%
VOUT ≤ 0.6 V, IOUT = 10 mA
–3.5%
3.5%
Total output voltage
IOUT = 10 mA, VOUT ≤ 0.785 V, VSYS = 13 V
accuracy (DC + ripple) in
IOUT = 10 mA, VOUT ≤ 0.785 V, VSYS = 21 V
DCM
–20
40
–20
55
SR(VOUT)
Output DVS slew rate
2.5
ILIM_LSD
Low-side output valley
current limit accuracy
See Section 6.3.3.4, Current Limit, for details.
(programmed by external
resistor RLIM)
VTH_ZC
Low-side current zero
crossing detection
threshold
ILIMREF
Source current out of
ILIM1 pin
T = 25°C
45
VLIM
Voltage at ILIM1 pin
VLIM = RLIM × ILIMREF
ΔVOUT/ΔVIN
Line regulation
VOUT ≥ 1 V, IOUT = 5 A
Load regulation
VIN = 13 V, VOUT ≥ 1 V,
IOUT = 0 A to 5 A,
referenced to VOUT at IOUT = 5 A
ΔVOUT/ΔIOUT
DC + AC at sense point, VIN = 13 V,
VOUT = 1.00 V,
IOUT = 1.5 A to 5 A and 5 A to 1.5 A with 1 µs of
tr and tf
ΔVOUT_TR (1)
Load transient regulation
VTH_PG
Power Good deassertion
threshold in percentage
of target VOUT
VTH_HYS_PG
Power Good reassertion
hysteresis entering back
into VTH_PG
VOUT rising or falling
COUT
External output
capacitance
Recommended amount to meet transient
specification
LSW
External output
inductance
(1)
DC + AC at sense point, VIN = 13 V,
VOUT = 0.75 V,
IOUT = 0.3 A to 1.5 A and 1.5 A to 0.3 A with 1 µs
of tr and tf
V
3.125
mV
mV/µs
–15%
15%
–11
11
mV
55
µA
0.2
2.25
V
–0.5%
0.5%
0%
1%
–50
50
50
VOUT rising
108%
VOUT falling
92%
mV
3%
180
220
0.376
0.47
µF
0.564
µH
Frequency of transient load current ranges from 0 to 1 MHz with duty cycle of 50%. For cases where duty cycle and frequency are
limited by tr and tf, the highest frequency is set by 1 / (tr + tf), where tr is rise time (0% to 100%) and tf is fall time (100% to 0%).
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
13
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
Electrical Characteristics: Buck Controllers (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
RDSON_DRVH
Driver DRVH resistance
RDSON_DRVL
Driver DRVL resistance
RDIS
Output auto-discharge
resistance
CBOOT
Bootstrap capacitance
RON_BOOT
Bootstrap switch ON
resistance
TEST CONDITIONS
MIN
TYP
Source, IDRVH = –50 mA
3
Sink, IDRVH = 50 mA
2
Source, IDRVL = –50 mA
MAX
Ω
3
Sink, IDRVL = 50 mA
0.4
BUCK1_DIS[1:0] = 01
100
BUCK1_DIS[1:0] = 10
200
BUCK1_DIS[1:0] = 11
500
UNIT
Ω
Ω
100
nF
20
Ω
21
V
BUCK2
Power input voltage for
external HSD FET
VIN
5.6
Step size
10
BUCK2_VID[6:0] = 0000000 (default)
DC output voltage
BUCK2_VID[6:0] = 0000001
0.5
BUCK2_VID[6:0] = 0000010
0.51
V
⋮
BUCK2_VID[6:0] = 1110101
1.66
BUCK2_VID[6:0] = 1110110–1111111
1.67
VOUT ≥ 1 V, IOUT = 100 mA to 21 A
DC output voltage
accuracy
mV
0
⋮
VOUT
13
–2%
2%
VOUT = 0.75 V, IOUT = 100 mA to 6.3 A
–2.5%
2.5%
VOUT ≤ 0.6 V, IOUT = 10 mA
–3.5%
3.5%
Total output voltage
accuracy (DC + ripple) in IOUT = 10 mA, VOUT ≤ 0.765 V
DCM
–20
40
SR(VOUT)
Output DVS slew rate
2.5
ILIM_LSD
Low-side output valley
current limit accuracy
See Section 6.3.3.4, Current Limit, for details.
(programmed by external
resistor RLIM)
VTH_ZC
Low-side current zero
crossing detection
threshold
ILIMREF
Source current out of
ILIM2 pin
T = 25°C
45
VLIM
Voltage at ILIM2 pin
VLIM = RLIM × ILIMREF
ΔVOUT/ΔVIN
Line regulation
VOUT ≥ 1 V, IOUT = 21 A
Load regulation
VIN = 13 V, 1 V ≤ VOUT ≤ 1.3 V,
IOUT = 0 A to 21 A,
referenced to VOUT at IOUT = 21 A
ΔVOUT/ΔIOUT
ΔVOUT_TR (1)
VTH_PG
(2)
14
Load transient regulation
Power Good deassertion
threshold in percentage
of target VOUT
DC + AC at sense point, VIN = 13 V, VOUT = 1 V,
IOUT = 1 A to 21 A and 21 A to 1 A with 1 µs of tr
and tf
DC + AC at sense point, VIN = 13 V,
VOUT = 0.75 V, IOUT = 1 A to 3.3 A and 3.3 A to
1 A with 1 µs of tr and tf
3.125
mV
mV/µs
–15%
15%
–11
11
mV
55
µA
0.2
2.25
V
–0.5%
0.5%
0%
1%
–160
30 (2)
–50
(2)
50
mV
50
VOUT rising
108%
VOUT falling
92%
Additional overshoot of up to 100 mV is allowed as long as it lasts less than 50 µs.
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Electrical Characteristics: Buck Controllers (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
VTH_HYS_PG
Power Good reassertion
hysteresis entering back
into VTH_PG
LSW
External output
inductance
COUT
External output
capacitance
RDSON_DRVH
Driver DRVH resistance
RDSON_DRVL
Driver DRVL resistance
RDIS
Output auto-discharge
resistance
CBOOT
Bootstrap capacitance
RON_BOOT
Bootstrap switch ON
resistance
TEST CONDITIONS
MIN
VOUT rising or falling
TYP
MAX
UNIT
0.264
µH
3%
Recommended amount to meet transient
specification
0.176
0.22
440
550
Source, IDRVH = –50 mA
3
Sink, IDRVH = 50 mA
2
Source, IDRVL = –50 mA
µF
Ω
3
Sink, IDRVL = 50 mA
0.4
BUCK2_DIS[1:0] = 01
100
BUCK2_DIS[1:0] = 10
200
BUCK2_DIS[1:0] = 11
500
Ω
Ω
100
nF
20
Ω
21
V
BUCK6
VIN
Power input voltage for
external HSD FET
5.6
Step size
10
0
BUCK6_VID[6:0] = 0000001
0.5
BUCK6_VID[6:0] = 0000010
0.51
⋮
BUCK6_VID[6:0] = 0111101 (TPS650940 and
TPS650944 default)
DC output voltage
1.1
⋮
⋮
BUCK6_VID[6:0] = 1000111 (TPS650941 default)
⋮
BUCK6_VID[6:0] = 1010110 (TPS650942 default)
1.35
⋮
⋮
BUCK6_VID[6:0] = 1110101
1.66
BUCK6_VID[6:0] = 1110110–1111111
1.67
VOUT ≥ 1 V, IOUT = 100 mA to 7 A
ILIM_LSD
Low-side output valley
current limit accuracy
See Section 6.3.3.4, Current Limit, for details.
(programmed by external
resistor RLIM)
VTH_ZC
Low-side current zero
crossing detection
threshold
ILIMREF
Source current out of
ILIM6 pin
T = 25°C
VLIM
Voltage at ILIM6 pin
VLIM = RLIM × ILIMREF
ΔVOUT/ΔVIN
Line regulation
VOUT ≥ 1 V, IOUT = 7 A
ΔVOUT/ΔIOUT
Load regulation
VIN = 13 V, VOUT ≥ 1 V, IOUT = 0 A to 7 A,
referenced to VOUT at IOUT = 7 A
ΔVOUT_TR
Load transient regulation
DC + AC at sense point, VIN = 13 V,
VOUT = 1.35 V, IOUT = 2.1 A to 7 A and 7 A to
2.1 A with 1.96 µs of tr and tf (2.5 A/µs)
V
1.2
⋮
DC output voltage
accuracy
mV
BUCK6_VID[6:0] = 0000000
⋮
VOUT
13
–2%
2%
–15%
15%
–11
11
mV
55
µA
V
45
50
0.2
2.25
–0.5%
0.5%
0%
1%
–5%
5%
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
15
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
Electrical Characteristics: Buck Controllers (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
VTH_PG
Power Good deassertion
threshold in percentage
of target VOUT
VTH_HYS_PG
Power Good reassertion
hysteresis entering back
into VTH_PG
LSW
External output
inductance
COUT
External output
capacitance
RDSON_DRVH
Driver DRVH resistance
RDSON_DRVL
Driver DRVL resistance
RDIS
Output auto-discharge
resistance
CBOOT
Bootstrap capacitance
RON_BOOT
Bootstrap switch ON
resistance
16
TEST CONDITIONS
MIN
TYP
VOUT rising
108%
VOUT falling
92%
VOUT rising or falling
Recommended amount to meet transient
specification
MAX
UNIT
0.564
µH
3%
0.376
0.47
150
220
Source, IDRVH = –50 mA
3
Sink, IDRVH = 50 mA
2
Source, IDRVL = –50 mA
3
Sink, IDRVL = 50 mA
0.4
BUCK6_DIS[1:0] = 01
100
BUCK6_DIS[1:0] = 10
200
BUCK6_DIS[1:0] = 11
500
µF
Ω
Ω
Ω
100
nF
20
Specifications
Ω
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
5.8
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Electrical Characteristics: Synchronous Buck Converters
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5
5.5
UNIT
BUCK3
VIN
Power input voltage
4.5
Step size
25
BUCK3_VID[6:0] = 0000000
VOUT
0
BUCK3_VID[6:0] = 0000001
0.65
BUCK3_VID[6:0] = 0000010
0.675
⋮
DC output voltage
⋮
BUCK3_VID[6:0] = 0010001 (default)
⋮
⋮
3.55
BUCK3_VID[6:0] = 1110110–1111111
VOUT = 1.05 V, IOUT = 1.5 A
VOUT = 1.05 V, IOUT = 100 mA
V
1.05
BUCK3_VID[6:0] = 1110101
DC output voltage
accuracy
3.575
–2%
2%
–2.5%
2.5%
SR(VOUT)
Output DVS slew rate
IOUT
Continuous DC output
current
IIND_LIM
HSD FET current limit
IQ
Quiescent current
VIN = 5 V, VOUT = 1 V
ΔVOUT/ΔVIN
Line regulation
VOUT = 1.05 V, IOUT = 1.5 A
–0.5%
0.5%
ΔVOUT/ΔIOUT
Load regulation
VIN = 5 V, VOUT = 1.05 V, IOUT = 0 A to 3 A,
referenced to VOUT at IOUT = 1.5 A
–0.2%
2%
ΔVOUT_TR (1)
Load transient
regulation
DC + AC at sense point,
VIN = 5 V, VOUT = 1.05 V, IOUT = 0.9 A to 3 A and 3 A
to 0.9 A with slew rate of 2.5 A/µs
–5%
7%
VTH_PG
Power Good
deassertion threshold
in percentage of
target VOUT
VTH_HYS_PG
Power Good
reassertion hysteresis
VOUT rising or falling
entering back into
VTH_PG
LSW
Output inductance
CIN
Input bypass
capacitance
COUT
Output filtering
capacitance
RDIS
BUCK3_DIS[1:0] = 01
Output auto-discharge
BUCK3_DIS[1:0] = 10
resistance
BUCK3_DIS[1:0] = 11
(1)
V
mV
2.5
3.125
4.3
mV/µs
3
A
7
A
35
VOUT rising
108%
VOUT falling
92%
µA
3%
0.376
0.47
0.564
µH
2.5
10
12
µF
61.6
88
110
µF
100
200
Ω
500
Frequency of transient load current ranges from 0 to 1 MHz with duty cycle of 50%. For cases where duty cycle and frequency are
limited by tr and tf, the highest frequency is set by 1 / (tr + tf), where tr is rise time (0% to 100%) and tf is fall time (100% to 0%).
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
17
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
Electrical Characteristics: Synchronous Buck Converters (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.5
5
5.5
UNIT
BUCK4
VIN
Power input voltage
Step size
25
BUCK4_VID[6:0] = 0000000
0
BUCK4_VID[6:0] = 0000001
0.65
BUCK4_VID[6:0] = 0000010
0.675
⋮
DC output voltage
VOUT
V
1.8
⋮
⋮
BUCK4_VID[6:0] = 1110101
3.55
BUCK4_VID[6:0] = 1110110–1111111
DC output voltage
accuracy
mV
⋮
BUCK4_VID[6:0] = 0101111 (default)
V
3.575
VOUT = 1.8 V, IOUT = 1.5 A
VOUT = 1.8 V, IOUT = 100 mA
–2%
2%
–2.5%
2.5%
IOUT
Continuous DC output
current
IIND_LIM
HSD FET current limit
IQ
Quiescent current
VIN = 5 V, VOUT = 1.8 V
ΔVOUT/ΔVIN
Line regulation
VOUT = 1.8 V, IOUT = 1.5 A
–0.5%
0.5%
ΔVOUT/ΔIOUT
Load regulation
VIN = 5 V, VOUT = 1.8 V, IOUT = 0 A to 1.5 A,
referenced to VOUT at IOUT = 0.75 A
–0.2%
0.65%
ΔVOUT_TR (1)
Load transient
regulation
DC + AC at sense point, VIN = 5 V, VOUT = 1.8 V,
IOUT = 0.45 A to 1.5 A and 1.5 A to 0.45 A with slew
rate of 2.5 A/µs
–5%
5%
VTH_PG
Power Good
deassertion threshold
in percentage of
target VOUT
VTH_HYS_PG
Power Good
reassertion hysteresis
VOUT rising or falling
entering back into
VTH_PG
LSW
Output inductance
0.376
0.47
0.564
µH
CIN
Input bypass
capacitance
2.5
10
12
µF
COUT
Output filtering
capacitance
46
66
110
µF
RDIS
BUCK4_DIS[1:0] = 01
Output auto-discharge
BUCK4_DIS[1:0] = 10
resistance
BUCK4_DIS[1:0] = 11
18
3
4.3
7
35
VOUT rising
108%
VOUT falling
92%
Specifications
A
A
µA
3%
100
200
Ω
500
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Electrical Characteristics: Synchronous Buck Converters (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.5
5
5.5
UNIT
BUCK5
VIN
Power input voltage
Step size
10
BUCK5_VID[6:0] = 0000000
0
BUCK5_VID[6:0] = 0000001
0.5
BUCK5_VID[6:0] = 0000010
0.51
⋮
DC output voltage
VOUT
⋮
BUCK5_VID[6:0] = 1110101
1.66
BUCK4_VID[6:0] = 1110110–1111111
DC output voltage
accuracy
VOUT = 1.24 V, IOUT = 100 mA
V
1.24
⋮
VOUT = 1.24 V, IOUT = 1.5 A
mV
⋮
BUCK5_VID[6:0] = 1001011 (default)
V
1.67
–2%
2%
–2.5%
2.5%
IOUT
Continuous DC output
current
IIND_LIM
HSD FET current limit
IQ
Quiescent current
VIN = 5 V, VOUT = 1.24 V
ΔVOUT/ΔVIN
Line regulation
VOUT = 1.24 V, IOUT = 1.5 A
–0.5%
0.5%
ΔVOUT/ΔIOUT
Load regulation
VIN = 5 V, VOUT = 1.24 V, IOUT = 0 A to 1.5 A,
referenced to VOUT at IOUT = 0.75 A
–0.2%
1%
ΔVOUT_TR (1)
Load transient
regulation
DC + AC at sense point, VIN = 5 V,
VOUT = 1.24 V, IOUT = 0.45 A to 1.5 A and 1.5 A to
0.45 A with slew rate of 2.5 A/µs
–5%
5%
VTH_PG
Power Good
deassertion threshold
in percentage of
target VOUT
VTH_HYS_PG
Power Good
reassertion hysteresis
VOUT rising or falling
entering back into
VTH_PG
LSW
Output inductance
0.376
0.47
0.564
µH
CIN
Input bypass
capacitance
2.5
10
12
µF
COUT
Output filtering
capacitance
31
44
110
µF
RDIS
BUCK5_DIS[1:0] = 01
Output auto-discharge
BUCK5_DIS[1:0] = 10
resistance
BUCK5_DIS[1:0] = 11
3.2
4.3
7
35
VOUT rising
108%
VOUT falling
92%
Submit Documentation Feedback
Product Folder Links: TPS65094
A
µA
3
100
200
Ω
500
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
A
19
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
5.9
www.ti.com
Electrical Characteristics: LDOs
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5
5.5
UNIT
LDOA1
VIN
Input voltage
4.5
IOUT = 10 mA, LDOA1_SEL[3:0] = 0000
VOUT
DC output voltage
LDOA1_SEL[3:0] = 0001
1.5
LDOA1_SEL[3:0] = 0010
1.6
LDOA1_SEL[3:0] = 0011
1.7
LDOA1_SEL[3:0] = 0100 (TPS650944 default)
1.8
LDOA1_SEL[3:0] = 0101
1.9
LDOA1_SEL[3:0] = 0110
2
LDOA1_SEL[3:0] = 0111
2.1
LDOA1_SEL[3:0] = 1000
2.3
LDOA1_SEL[3:0] = 1001
2.4
LDOA1_SEL[3:0] = 1010
2.5
LDOA1_SEL[3:0] = 1011
2.7
LDOA1_SEL[3:0] = 1100
2.85
LDOA1_SEL[3:0] = 1101
3
LDOA1_SEL[3:0] = 1110 (TPS650940,
TPS650941, and TPS650942 default)
Accuracy
IOUT
DC output current
ΔVOUT/ΔVIN
Line regulation
IOUT = 40 mA
ΔVOUT/ΔIOUT
Load regulation
IOUT = 10 mA to 200 mA
IOCP
Overcurrent protection
VIN = 5 V, Measured with output shorted to
ground
VTH_PG
Power Good deassertion
threshold in percentage of target
VOUT
VTH_HYS_PG
Power Good reassertion
hysteresis entering back into
VTH_PG
VOUT rising or falling
IQ
Quiescent current
IOUT = 0 A
RDIS
20
IOUT = 0 to 200 mA
–2%
2%
200
–0.5%
0.5%
–2%
2%
500
108%
VOUT falling
92%
3%
23
2.7
4.7
ESR
LDOA1_DIS[1:0] = 01
100
LDOA1_DIS[1:0] = 10
190
LDOA1_DIS[1:0] = 11
450
Specifications
mA
mA
VOUT rising
External output capacitance
Output auto-discharge resistance
V
3.3
VOUT
COUT
V
1.35
µA
10
µF
100
mΩ
Ω
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Electrical Characteristics: LDOs (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT +
VDROP (1)
1.8
1.98
V
LDOA2
VIN
Power input voltage
LDOA2_VID[3:0] = 0000 (TPS650944 default)
0.7
LDOA2_VID[3:0] = 0001
VOUT
DC output voltage in normal
operating mode
0.75
LDOA2_VID[3:0] = 0010
0.8
LDOA2_VID[3:0] = 0011
0.85
LDOA2_VID[3:0] = 0100
0.9
LDOA2_VID[3:0] = 0101
0.95
LDOA2_VID[3:0] = 0110
1
LDOA2_VID[3:0] = 0111
1.05
LDOA2_VID[3:0] = 1000
1.1
LDOA2_VID[3:0] = 1001
1.15
LDOA2_VID[3:0] = 1010 (TPS650940,
TPS650941, and TPS650942 default)
1.2
LDOA2_VID[3:0] = 1011
1.25
LDOA2_VID[3:0] = 1100
1.3
LDOA2_VID[3:0] = 1101
1.35
LDOA2_VID[3:0] = 1110
1.4
LDOA2_VID[3:0] = 1111
1.5
VOUT
DC output voltage accuracy
IOUT
DC output current
VDROP
Dropout voltage
VOUT = 0.99 × VOUT_NOM,
IOUT = 600 mA
ΔVOUT/ΔVIN
Line regulation
IOUT = 300 mA
–0.5%
0.5%
ΔVOUT/ΔIOUT
Load regulation
IOUT = 10 mA to 600 mA
–2%
2%
IOCP
Overcurrent protection
Measured with output shorted to ground
0.65
VTH_PG
Power Good assertion threshold
in percentage of target VOUT
VOUT rising
108%
VOUT falling
92%
VTH_HYS_PG
Power Good deassertion
hysteresis
VOUT falling
3%
IQ
Quiescent current
IOUT = 0 A
20
µA
f = 1 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF to 4.7 µF
48
dB
f = 10 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF to 4.7 µF
30
dB
PSRR
COUT
RDIS
(1)
Power supply rejection ratio
IOUT = 0 to 600 mA
V
External output capacitance
–2%
2.2
3%
mA
350
mV
1.25
4.7
ESR
Output auto-discharge resistance
600
LDOA2_DIS[1:0] = 01
80
LDOA2_DIS[1:0] = 10
180
LDOA2_DIS[1:0] = 11
475
A
10
µF
100
mΩ
Ω
The minimum value must be equal to or greater than 1.62 V.
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
21
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
Electrical Characteristics: LDOs (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT +
VDROP (1)
1.8
1.98
V
LDOA3
VIN
Power input voltage
LDOA3_VID[3:0] = 0000 (TPS650944 default)
0.7
LDOA3_VID[3:0] = 0001
DC output voltage in normal
operating mode
VOUT
0.75
LDOA3_VID[3:0] = 0010
0.8
LDOA3_VID[3:0] = 0011
0.85
LDOA3_VID[3:0] = 0100
0.9
LDOA3_VID[3:0] = 0101
0.95
LDOA3_VID[3:0] = 0110
1
LDOA3_VID[3:0] = 0111
1.05
LDOA3_VID[3:0] = 1000
1.1
LDOA3_VID[3:0] = 1001
1.15
LDOA3_VID[3:0] = 1010
1.2
LDOA3_VID[3:0] = 1011 (TPS650940,
TPS650941, and TPS650942 default)
1.25
LDOA3_VID[3:0] = 1100
1.3
LDOA3_VID[3:0] = 1101
1.35
LDOA3_VID[1:0] = 1110
1.4
LDOA3_VID[1:0] = 1111
1.5
VOUT
DC output voltage accuracy
IOUT
DC output current
IOCP
Overcurrent protection
Measured with output shorted to ground
VDROP
Dropout voltage
VOUT = 0.99 × VOUT_NOM,
IOUT = 600 mA
ΔVOUT/ΔVIN
Line regulation
IOUT = 300 mA
ΔVOUT/ΔIOUT
Load regulation
IOUT = 10 mA to 600 mA
VTH_PG
Power Good assertion threshold
in percentage of target VOUT
VOUT rising
108%
VOUT falling
92%
VTH_HYS_PG
Power Good deassertion
hysteresis
VOUT falling
3%
IQ
Quiescent current
IOUT = 0 A
20
f = 1 kHz, VIN = 1.8 V,
VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF to 4.7 µF
48
f = 10 kHz, VIN = 1.8 V,
VOUT = 1.2 V,
IOUT = 300 mA,
COUT = 2.2 µF to 4.7 µF
30
PSRR
COUT
RDIS
22
Power supply rejection ratio
IOUT = 0 to 600 mA
–2%
3%
600
External output capacitance
0.65
1.25
–0.5%
mV
0.5%
–2%
2%
µA
dB
2.2
4.7
LDOA3_DIS[1:0] = 01
80
LDOA3_DIS[1:0] = 10
180
LDOA3_DIS[1:0] = 11
475
Specifications
mA
A
350
ESR
Output auto-discharge resistance
V
10
µF
100
mΩ
Ω
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Electrical Characteristics: LDOs (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VDDQ
3.3
UNIT
VTT LDO
VIN
VOUT
IOUT
ΔVOUT/ΔIOUT
ΔVOUT_TR
IOCP
Power input voltage
DC output voltage
Measured at VTTFB pin
DC output voltage accuracy
Relative to VIN / 2, IOUT = 100 mA,
1.1 V ≤ VIN ≤ 1.5 V
DC Output Current (RMS Value
Over Operation)
1.1 V ≤ VIN ≤ 1.5 V
–500
source(+) and sink(–): LPDDR3 and LPDDR4
OTPs, 1.1 V ≤ VIN ≤ 1.5 V
–500
500
source(+) and sink(–): DDR3L OTPs, 1.1 V ≤
VIN ≤ 1.5 V
–1800
1800
Relative to VIN / 2, IOUT ≤ 10 mA,
1.1 V ≤ VIN ≤ 1.5 V
–10
10
Relative to VIN / 2, IOUT ≤ 500 mA,
1.1 V ≤ VIN ≤ 1.5 V
–20
20
Relative to VIN / 2, IOUT ≤ 1200 mA,
1.1 V ≤ VIN ≤ 1.5 V
–30
30
Relative to VIN / 2, IOUT ≤ 1800 mA,
1.1 V ≤ VIN ≤ 1.5 V
–40
40
DC + AC at sense point, 1.1 V ≤ VIN ≤ 1.5 V,
(IOUT = 0 to 350 mA and 350 mA to 0) AND
(0 to –350 mA and –350 mA to 0) with 1 µs of
rise and fall time
COUT = 40 µF
–5%
5%
Measured with output shorted to ground: OTPs
with VTT ILIM = 0.95 A
0.95
Measured with output shorted to ground: OTPs
with VTT ILIM = 1.8 A
1.8
Pulsed Current (Duty Cycle
Limited to Remain Below DC
RMS Specification)
Load regulation
Load transient regulation
Overcurrent protection
VIN / 2
–10
0
V
V
10
mV
500
mA
mA
mV
A
VTH_PG
Power Good deassertion
threshold in percentage of target
VOUT
VOUT rising
110%
VOUT falling
95%
VTH_HYS_PG
Power Good reassertion
hysteresis entering back into
VTH_PG
VOUT rising or falling
IQ
Total ground current
VIN = 1.2 V, IOUT = 0 A
ILKG
OFF leakage current
VIN = 1.2 V, disabled
CIN
External input capacitance
10
µF
COUT
External output capacitance
35
µF
5%
240
µA
1
µA
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
23
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
5.10 Electrical Characteristics: Load Switches
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.5
1.8
MAX
UNIT
SWA1
VIN
Input voltage range
IOUT
DC output current
RDSON
ON resistance
60
93
VIN = 3.3 V, measured from PVINSWA1 pin
to SWA1 pin at IOUT = IOUT(MAX)
100
165
108%
VOUT falling
92%
VTH_HYS_PG
Power Good reassertion hysteresis
entering back into VTH_PG
VOUT rising or falling
IINRUSH
Inrush current upon turnon
VIN = 3.3 V, COUT = 0.1 µF
ILKG
Leakage current
COUT
External output capacitance
RDIS
mΩ
VOUT rising
Power Good deassertion threshold in
percentage of target VOUT
Quiescent current
V
mA
VIN = 1.8 V, measured from PVINSWA1 pin
to SWA1 pin at IOUT = IOUT(MAX)
VTH_PG
IQ
3.3
300
2%
10
VIN = 3.3 V, IOUT = 0 A
10.5
VIN = 1.8 V, IOUT = 0 A
9
µA
Switch disabled, VIN = 1.8 V
7
370
Switch disabled, VIN = 3.3 V
10
900
0.1
Output auto-discharge resistance
SWA1_DIS[1:0] = 01
100
SWA1_DIS[1:0] = 10
200
SWA1_DIS[1:0] = 11
500
mA
nA
µF
Ω
SWB1_2
VIN
Input voltage range
IOUT
DC current per output
RDSON
0.5
ON resistance per output
VIN = 1.8 V, measured from PVINSWB1_B2
pin to SWB1 or SWB2 pin at IOUT =
IOUT(MAX)
68
VIN = 3.3 V, measured from PVINSWB1_B2
pin to SWB1 or SWB2 pin at IOUT =
IOUT(MAX)
75
108%
VOUT falling
92%
Power Good deassertion threshold in
percentage of target VOUT
VTH_HYS_PG
Power Good reassertion hysteresis
entering back into VTH_PG
VOUT rising or falling
IINRUSH
Inrush current upon turning on
VIN = 3.3 V, COUT = 0.1 µF
Quiescent current
ILKG
Leakage current
COUT
External output capacitance
RDIS
24
Output auto-discharge resistance
3.3
V
400
mA
92
mΩ
VOUT rising
VTH_PG
IQ
1.8
125
2%
10
VIN = 3.3 V, IOUT = 0 A
10.5
VIN = 1.8 V, IOUT = 0 A
9
µA
Switch disabled, VIN = 1.8 V
7
460
Switch disabled, VIN = 3.3 V
10
1150
0.1
SWBx_DIS[1:0] = 01
100
SWBx_DIS[1:0] = 10
200
SWBx_DIS[1:0] = 11
500
Specifications
mA
nA
µF
Ω
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
5.11 Digital Signals: I2C Interface
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
VOL
Low-level output voltage
VIH
High-level input voltage
VIL
Low-level input voltage
ILKG
Leakage current
RPULL-UP
Pullup resistance
TEST CONDITIONS
MIN
TYP
MAX
VPULL_UP = 1.8 V
V
1.2
VPULL_UP = 1.8 V
V
0.01
0.4
V
0.3
µA
Standard mode
8.5
Fast mode
2.5
Fast mode plus
COUT
UNIT
0.4
kΩ
1
Total load capacitance per pin
50
pF
5.12 Digital Input Signals (LDOLS_EN, SWA1_EN, THERMTRIPB, PMICEN, SLP_S3B,
SLP_S4B, SLP_S0B)
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.85
V
0.4
V
5.13 Digital Output Signals (IRQB, RSMRSTB, PCH_PWROK, PROCHOT)
Over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOL
Low-level output voltage
IOL < 2 mA
ILKG
Leakage current
VPULL_UP = 1.8 V
MIN
TYP
MAX
UNIT
0.4
V
0.35
µA
5.14 Timing Requirements
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
MIN
NOM
MAX
UNIT
2
I C INTERFACE
fCLK
tr
tf
Clock frequency (standard mode)
100
Clock frequency (fast mode)
400
Clock frequency (fast mode plus)
1000
Rise time (standard mode)
1000
Rise time (fast mode)
300
Rise time (fast mode plus)
120
Rise time (standard mode)
300
Rise time (fast mode)
300
Rise time (fast mode plus)
120
kHz
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
ns
ns
25
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
5.15 Switching Characteristics
over operating free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
550
850
µs
BUCK CONTROLLERS
tPG
Total turnon time
TON,MIN
Minimum ON time
of DRVH
TDEAD
Driver dead-time
fSW
Switching
frequency
Measured from enable going high to when output reaches 90% of
target value.
50
DRVH off to DRVL on
15
DRVL off to DRVH on
30
Continuous-conduction mode,
VIN = 13 V, VOUT ≥ 1 V
ns
ns
1000
kHz
BUCK CONVERTERS
tPG
Measured from enable going high to when output reaches 90% of
target value.
VOUT = 1 V, COUT = 88 µF
250
Continuous-conduction mode, BUCK3 VOUT = 1 V, IOUT = 1 A
1.6
Continuous-conduction mode, BUCK3 VOUT = 1.05 V, IOUT = 1 A
1.7
Continuous-conduction mode, BUCK4 VOUT = 1.8 V, IOUT = 1 A
2.5
Continuous-conduction mode, BUCK5 VOUT = 1.24 V, IOUT = 1 A
2.4
Continuous-conduction mode, BUCK5 VOUT = 1.35 V, IOUT = 1 A
2.5
Start-up time
Measured from enable going high to when output reaches 95% of
final value,
VOUT = 1.2 V, COUT = 4.7 µF
180
µs
Start-up time
Measured from enable going high to PG assertion,
VOUT = 0.675 V, COUT = 40 µF
22
µs
Total turnon time
Switching
frequency
fSW
1000
µs
MHz
LDOAx
tSTARTUP
VTT LDO
tSTARTUP
SWA1
tTURN-ON
Turnon time
Measured from enable going high to reach 95% of final value,
VIN = 3.3 V, COUT = 0.1 µF
0.85
Measured from enable going high to reach 95% of final value,
VIN = 1.8 V, COUT = 0.1 µF
0.63
Measured from enable going high to reach 95% of final value,
VIN = 3.3 V, COUT = 0.1 µF
1.1
Measured from enable going high to reach 95% of final value,
VIN = 1.8 V, COUT = 0.1 µF
0.82
ms
SWB1_2
tTURN-ON
26
Turnon time
Specifications
ms
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
5.16 Typical Characteristics
88%
88%
86%
86%
84%
84%
82%
80%
Efficiency
Efficiency
82%
78%
76%
80%
78%
76%
74%
72%
74%
VSYS = 5.4 V
VSYS = 13 V
VSYS = 18 V
70%
72%
70%
68%
0
0.5
1
1.5
2
2.5
3
Output Load (A)
3.5
4
4.5
0
5
3
6
9
12
Output Load (A)
D001
Figure 5-1. BUCK1 (VNN) Efficiency at VOUT = 1 V
15
18
21
D002
Figure 5-2. BUCK2 (VCCGI) Efficiency at VOUT = 1 V
92%
91%
VSYS = 5.4 V
VSYS = 13 V
VSYS = 18 V
90%
PVIN = 4.5 V
PVIN = 5 V
PVIN = 5.5 V
89%
87%
88%
85%
86%
83%
Efficiency
Efficiency
VSYS = 5.4 V
VSYS = 13 V
VSYS = 18 V
84%
82%
81%
79%
77%
75%
80%
73%
78%
71%
76%
69%
0
1
2
3
4
Output Load (A)
5
6
7
0
Figure 5-3. BUCK6 (VDDQ) Efficiency at VOUT = 1.2 V
1
1.5
2
Output Load (A)
2.5
3
D003
Figure 5-4. BUCK3 (VCCRAM) Efficiency at VOUT = 1.05 V
90%
92%
PVIN = 4.5 V
PVIN = 5 V
PVIN = 5.5 V
91%
90%
PVIN = 4.5 V
PVIN = 5 V
PVIN = 5.5 V
89%
88%
87%
Efficiency
89%
Efficiency
0.5
D011
88%
87%
86%
86%
85%
84%
83%
85%
82%
84%
81%
83%
80%
0
0.25
0.5
0.75
1
Output Load (A)
1.25
1.5
0
D004
Figure 5-5. BUCK4 (V1P8A) Efficiency at VOUT = 1.8 V
0.25
0.5
0.75
1
Output Load (A)
1.25
1.5
D005
Figure 5-6. BUCK5 (V1P24A) Efficiency at VOUT = 1.24 V
Specifications
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
27
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
6 Detailed Description
6.1
Overview
The TPS65094x device provides all the necessary power supplies for the Intel Reference Designs. For an
overview of the different OTP configurations, consult Table 3-1. The following VRs are integrated: three
step-down controllers (BUCK1, BUCK2, and BUCK6), three step-down converters (BUCK3, BUCK4, and
BUCK5), a sink and source LDO (VTT LDO), three low-voltage VIN LDOs (LDOA1–LDOA3), and three
load switches that are managed by power-up sequence logic to provide the proper power rails,
sequencing, and protection. All VRs have a built-in discharge resistor, and the value can be changed by
the DISCHCNT1–DISCHCNT3 and LDOA1_CTRL registers. When enabling a VR, the PMIC automatically
disconnects the discharge resistor for that rail without any I2C command. Table 6-1 summarizes the key
characteristics of the voltage rails.
Table 6-1. Summary of Voltage Regulators
RAIL
TYPE
INPUT VOLTAGE
(V)
OUTPUT VOLTAGE RANGE
(V)
MIN
MAX
MIN
TYP
MAX
TYPICAL
APPLICATION
CURRENT
(mA)
BUCK1 (VNN)
Step-down controller
4.5
21
0.5
1.05
1.67
5000
BUCK2 (VCCGI)
Step-down controller
4.5
21
0.5
1
1.67
21000
BUCK3
(VCCRAM)
Step-down converter
4.5
5.5
0.65
1.05
3.575
3000
BUCK4 (V1P8A)
Step-down converter
4.5
5.5
0.65
1.8
3.575
1500
BUCK5 (V1P24A) Step-down converter
4.5
5.5
0.5
1.24
1.67
1900
BUCK6 (VDDQ)
Step-down controller
4.5
21
0.5
OTP dependent
1.67
7000
LDOA1
LDO
4.5
5.5
1.35
OTP dependent
3.3
200 (1)
LDOA2
LDO
1.62
1.98
0.7
OTP dependent
1.5
600
LDOA3
LDO
1.62
1.98
0.7
OTP dependent
1.5
600
SWA1
Load switch
0.5
3.3
300
SWB1_2 (2)
Load switch
0.5
3.3
800 (combined)
VTT
Sink and source
LDO
(1)
(2)
28
BUCK6 output
VBUCK6 / 2
OTP dependent
When powered from a 5-V supply through the DRV5V_2_A1 pin. Otherwise, maximum current is limited by maximum IOUT of LDO5.
For LPDDR3 and LPDDR4 memory, SWB1_2 is configured to V1P8U and controlled by SLP_S4B. For DDR3L memory, SWB1_2 is
configured to either V3P3S or V1P8S and controlled by SLP_S3B.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.2
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Functional Block Diagram
Figure 6-1 shows a functional block diagram of the PMIC.
PMICEN
SLP_S3B
LDOA1
1.35 V to 3.3 V
1.8 V(b)
200 mA
LDOLS_EN(a)
SWA1_EN(b)
BOOT1
DRVH1
BUCK1
Default: 1V
VSET
SLP_S4B
SLP_S0B
VSYS
DRV5V_1_6
EC
LDO5V
DRV5V_2_A1
LDOA1
Optional(a)
Required(b)
EN
EN
Control
Inputs
SW1
Typical
Application
Usage:
0.5 V to 1.45 V
(DVS)
5A
VNN
DRVL1
FBVOUT1
PGNDSNS1
ILIM1
THERMTRIPB
VSYS
V1P8A
BOOT2
DRVH2
CLK
SoC
DATA
I2C CTRL
BUCK2
Default: 0V
SW2
VSET
V1P8A
EN
Control
Outputs
PCH_PWROK
RSMRSTB
PROCHOT
Internal
Interrupt
Events
GPO
INTERRUPT_CNTL
IRQB
VCCGI
DRVL2
Typical
Application
Usage:
0.5 V to 1.45 V
(DVS)
21 A
FBVOUT2
PGNDSNS2
FBGND2
ILIM2
BUCK5V
PVIN3
TEST CTRL
VSET
OTP
EN
REGISTERS
LX3
BUCK3
Default: 1.05 V
3A
VCCRAM
FB3
BUCK5V
PVIN4
VSYS
VSYS
BUCK5V
Digital Core
V5ANA
VSET
EN
BUCK4
Default: 1.8 V
2A
LDO5
V1P8A
FB4
LDO5V
LDO3P3
LX4
REFSYS
nPUC
BUCK5V
PVIN5
VREF
VSET
EN
LX5
BUCK5
Default: 1.24 V
2A
V1P24A
FB5
AGND
VSYS
Thermal
monitoring
BOOT6
DRVH6
Thermal shutdown
VSET
EN
SW6
BUCK6
Default: OTP
Dependent
7A
VDDQ
DRVL6
FBVOUT6
PGNDSNS6
ILIM6
PVINVTT
(a) LDOA1 1RW ³$OZD\V 2Q´
(b) LDOA1 ³$OZD\V 2Q´
EN
LOAD SWB2
400 mA
V1P8U(1)
SWB1_2(2)
SWA1
0.5 V to 3.3 V
(1) LPDDR3 and LPDDR4
(2) DDR3L
VTT
VTTFB
V1P8A(1)
0.5 V to 3.3 V(2)
0.5 V to 3.3 V
Dashed connections optional.
Refer to Pin Attributes for
connection if unused.
VTT
VTT_LDO
½ × VDDQ
ILIM set by OTP
SWB2
SWB1
LOAD SWB1
400 mA
SWA1
PVINSWA1
LOAD SWA1
300 mA
PVINSWB1_B2
LDOA3
0.7 V to 1.5 V
600 mA
EN
EN
EN
VSET
PVINLDOA2_A3
LDOA2
LDOA2
0.7 V to 1.5 V
600 mA
LDOA3
EN
VSET
EN
Copyright © 2016, Texas Instruments Incorporated
Figure 6-1. PMIC Functional Block Diagram
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
29
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
PMIC
VSYS
SoC
BUCK1 5 A
EXT FET
VSYS
VNN
BUCK2 21 A
EXT FET
VCCGI
LDO5P0
VSYS
www.ti.com
BUCK
5V
BUCK
3.3 V
BUCK3 3 A
VCCRAM
BUCK4 2 A
V1P8A
BUCK5 2 A
V1P24A
VSYS
BUCK6 7 A
PLATFORM
EXT FET
VDDQ
VDDQ
VTT LDO 1.5 A
VTT
LDOA2 0.6 A
0.7 V to 1.5 V
LDOA3 0.6 A
0.7 V to 1.5 V
0.5 V to 3.3 V
SWA1 0.3 A
0.5 V to 3.3 V
V1P8A(1)
0.5 V to 3.3 V(2)
SWB1 0.4 A
V1P8A
800 mA
V1P8U(1)
0.5 V to 3.3 V(2)
SWB2 0.4 A
1.35 V to 3.3 V(a)
1.8 V(b)
LDOA1 0.2 A
LDO5 0.18 A
VSYS
LDO5P0
+
REF
PG_5V
LDO3P3 0.04 A
PMICEN
IRQB
SLP_S4B
SLP_S3B
LDOLS_EN(a)
SWA1_EN(b)
SLP_S0B
RSMRSTB
PCH_PWROK
THERMTRIPB
(1) LPDDR3 and LPDDR4
(2) DDR3L
(a) LDOA1 1RW ³$OZD\V 2Q´
(b) LDOA1 ³$OZD\V 2Q´
PROCHOT
DATA
SCLK
Copyright © 2016, Texas Instruments Incorporated
Figure 6-2. Apollo Lake Power Map
30
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.3
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Feature Description
6.3.1
Power Good (PGOOD)
The TPS65094x device provides information on status of VRs through two Power Good signals or pins.
Table 6-2 defines which signals are required to assert the PGOOD signals.
Table 6-2. Power Good Summary
(1)
✓
✓
✓
✓
✓
✓
BUCK2_PG (VCCGI)
✓
BUCK3_PG (VCCRAM)
✓
BUCK6_PG (VDDQ)
✓
BUCK5_PG (V1P24A)
✓
✓
BUCK4_PG (V1P8A)
✓
✓
BUCK1_PG (VNN)
THERMTRIPB
✓
PCH_PWROK
SLP_S3B
PMICEN
RSMRSTB
POWER GOOD (1)
SLP_S4B
UVLO (VSYS > 5.6 V)
QUALIFYING SIGNALS (LOGICAL AND)
✓
✓
✓
All Power Good signals must immediately deassert at the loss of any of the qualifying signals, or at the occurrence of a fault condition.
6.3.2
Register Reset Conditions
All
•
•
•
•
•
•
registers are reset if any of the following conditions are met:
VSYS pin voltage drops below 5.4 V
Falling edge of PMICEN for OTPs where LDOA1 is not "Always On"
Falling edge of THERMTRIPB while RSMRSTB = 1
Power fault of any regulator where xx_FLTMSK = 0 (see Section 6.6.27, PWR_FAULT_MASK1
Register, and Section 6.6.28, PWR_FAULT_MASK2 Register)
PMIC critical temperature shutdown
Software shutdown (writing 1 to the SDWN bit in the FORCESHUTDN register, see Figure 6-35)
Additionally, BUCK1 and BUCK2 VID registers are reset on the falling edge of SLP_S0IXB and SLP_S3B.
6.3.3
SMPS Voltage Regulators
The buck controllers integrate gate drivers for external power stages with programmable current limit (set
by an external resistor at ILIMx pin), which allows for optimal selection of external passive components
based on the desired system load. The buck converters include integrated power stage and require a
minimum number of pins for power input, inductor, and output voltage feedback input. Combined with
high-frequency switching, all these features allow use of inductors in small form factor, thus reducing the
total cost and size of the system.
BUCK3–BUCK6 have selectable auto- and forced-PWM mode through the BUCKx_MODE bit in the
BUCKxCTRL register. In default auto mode, the VR automatically switches between PWM and PFM
depending on the output load to maximize efficiency. The host cannot select Forced PWM mode for other
SMPS VRs as they stay in auto mode at all times.
See Table 6-3 and Table 6-4 for the full voltage tables for all SMPS regulators.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
31
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
Table 6-3. 10-mV Step-Size VOUT Range (BUCK1, BUCK2, BUCK5, BUCK6)
32
VID Bits
VOUT
VID Bits
VOUT
VID Bits
VOUT
0000000
0
0101011
0.92
1010110
1.35
0000001
0.50
0101100
0.93
1010111
1.36
0000010
0.51
0101101
0.94
1011000
1.37
0000011
0.52
0101110
0.95
1011001
1.38
0000100
0.53
0101111
0.96
1011010
1.39
0000101
0.54
0110000
0.97
1011011
1.40
0000110
0.55
0110001
0.98
1011100
1.41
0000111
0.56
0110010
0.99
1011101
1.42
0001000
0.57
0110011
1.00
1011110
1.43
0001001
0.58
0110100
1.01
1011111
1.44
0001010
0.59
0110101
1.02
1100000
1.45
0001011
0.60
0110110
1.03
1100001
1.46
0001100
0.61
0110111
1.04
1100010
1.47
0001101
0.62
0111000
1.05
1100011
1.48
0001110
0.63
0111001
1.06
1100100
1.49
0001111
0.64
0111010
1.07
1100101
1.50
0010000
0.65
0111011
1.08
1100110
1.51
0010001
0.66
0111100
1.09
1100111
1.52
0010010
0.67
0111101
1.10
1101000
1.53
0010011
0.68
0111110
1.11
1101001
1.54
0010100
0.69
0111111
1.12
1101010
1.55
0010101
0.70
1000000
1.13
1101011
1.56
0010110
0.71
1000001
1.14
1101100
1.57
0010111
0.72
1000010
1.15
1101101
1.58
0011000
0.73
1000011
1.16
1101110
1.59
0011001
0.74
1000100
1.17
1101111
1.60
0011010
0.75
1000101
1.18
1110000
1.61
0011011
0.76
1000110
1.19
1110001
1.62
0011100
0.77
1000111
1.20
1110010
1.63
0011101
0.78
1001000
1.21
1110011
1.64
0011110
0.79
1001001
1.22
1110100
1.65
0011111
0.80
1001010
1.23
1110101
1.66
0100000
0.81
1001011
1.24
1110110
1.67
0100001
0.82
1001100
1.25
1110111
1.67
0100010
0.83
1001101
1.26
1111000
1.67
0100011
0.84
1001110
1.27
1111001
1.67
0100100
0.85
1001111
1.28
1111010
1.67
0100101
0.86
1010000
1.29
1111011
1.67
0100110
0.87
1010001
1.30
1111100
1.67
0100111
0.88
1010010
1.31
1111101
1.67
0101000
0.89
1010011
1.32
1111110
1.67
0101001
0.90
1010100
1.33
1111111
1.67
0101010
0.91
1010101
1.34
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Table 6-4. 25-mV Step-Size VOUT Range (BUCK3, BUCK4)
VID Bits
VOUT
VID Bits
VOUT
VID Bits
VOUT
0000000
0
0101011
1.700
1010110
2.775
0000001
0.650
0101100
1.725
1010111
2.800
0000010
0.675
0101101
1.750
1011000
2.825
0000011
0.700
0101110
1.775
1011001
2.850
0000100
0.725
0101111
1.800
1011010
2.875
0000101
0.750
0110000
1.825
1011011
2.900
0000110
0.775
0110001
1.850
1011100
2.925
0000111
0.800
0110010
1.875
1011101
2.950
0001000
0.825
0110011
1.900
1011110
2.975
0001001
0.850
0110100
1.925
1011111
3.000
0001010
0.875
0110101
1.950
1100000
3.025
0001011
0.900
0110110
1.975
1100001
3.050
0001100
0.925
0110111
2.000
1100010
3.075
0001101
0.950
0111000
2.025
1100011
3.100
0001110
0.975
0111001
2.050
1100100
3.125
0001111
1.000
0111010
2.075
1100101
3.150
0010000
1.025
0111011
2.100
1100110
3.175
0010001
1.050
0111100
2.125
1100111
3.200
0010010
1.075
0111101
2.150
1101000
3.225
0010011
1.100
0111110
2.175
1101001
3.250
0010100
1.125
0111111
2.200
1101010
3.275
0010101
1.150
1000000
2.225
1101011
3.300
0010110
1.175
1000001
2.250
1101100
3.325
0010111
1.200
1000010
2.275
1101101
3.350
0011000
1.225
1000011
2.300
1101110
3.375
0011001
1.250
1000100
2.325
1101111
3.400
0011010
1.275
1000101
2.350
1110000
3.425
0011011
1.300
1000110
2.375
1110001
3.450
0011100
1.325
1000111
2.400
1110010
3.475
0011101
1.350
1001000
2.425
1110011
3.500
0011110
1.375
1001001
2.450
1110100
3.525
0011111
1.400
1001010
2.475
1110101
3.550
0100000
1.425
1001011
2.500
1110110
3.575
0100001
1.450
1001100
2.525
1110111
3.575
0100010
1.475
1001101
2.550
1111000
3.575
0100011
1.500
1001110
2.575
1111001
3.575
0100100
1.525
1001111
2.600
1111010
3.575
0100101
1.550
1010000
2.625
1111011
3.575
0100110
1.575
1010001
2.650
1111100
3.575
0100111
1.600
1010010
2.675
1111101
3.575
0101000
1.625
1010011
2.700
1111110
3.575
0101001
1.650
1010100
2.725
1111111
3.575
0101010
1.675
1010101
2.750
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
33
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.3.3.1
www.ti.com
Controller Overview
The controllers are fast-reacting, high-frequency, scalable output power controllers capable of driving two
external N-MOSFETs. They use a D-CAP2 control scheme that optimizes transient responses at high load
currents for such applications as CORE and DDR supplies. The output voltage is compared with internal
reference voltage after divider resistors. The PWM comparator determines the timing to turn on the highside MOSFET. The PWM comparator response maintains a very small PWM output ripple voltage.
Because the device does not have a dedicated oscillator for control loop on board, switching cycle is
controlled by the adaptive ON time circuit. The ON time is controlled to meet the target switching
frequency by feed-forwarding the input and output voltage into the ON time one-shot timer.
The D-CAP2 control scheme has an injected ripple from the SW node that is added to the reference
voltage to simulate output ripple, which eliminates the need for ESR-induced output ripple from D-CAP™
mode control. Thus, low-ESR output capacitors (such as low-cost ceramic MLCC capacitors) can be used
with the controllers.
VDD
VREF ± VTH_PG
+
UV
PGOOD
±
PGOOD
FAULT
+
DCHG
VREF + VTH_PG
+
VFB
OV
±
EN
Control Logic
+
±
+
+
Ramp Generator
PWM
REF
BOOTx
SS Ramp Comp
HS
VSYS
DRVHx
SWx
50 µA
ILIM
±
XCON
±
OC
+
DRV5V_x_x
+
LS
±
NOC
+
GND
One-Shot
DRVLx
PGNDSNSx
+
ZC
±
PMIC Internal Signals
External Inputs/Outputs
Copyright © 2017, Texas Instruments Incorporated
Figure 6-3. Controller Block Diagram
34
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.3.3.2
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Converter Overview
The PMIC synchronous step-down DC-DC converters include a unique hysteretic PWM control scheme
which enables a high switching frequency converter, excellent transient and AC load regulation, as well as
operation with cost-competitive external components. The controller topology supports forced PWM mode
as well as power-save mode operation. Power-save mode operation, or PFM mode, reduces the quiescent
current consumption and ensures high conversion efficiency at light loads by skipping switch pulses. In
forced PWM mode, the device operates on a quasi-fixed frequency, avoids pulse skipping, and allows
filtering of the switch noise by external filter components. The PMIC device offers fixed output voltage
options featuring smallest solution size by using only three external components per converter.
A significant advantage of PMIC compared to other hysteretic PWM controller topologies is the excellent
capability of the AC load transient regulation. When the output voltage falls below the threshold of the
error comparator, a switch pulse is initiated, and the high-side switch is turned on. The high-side switch
remains turned on until a minimum ON-time of tONmin expires and the output voltage trips the threshold of
the error comparator or the inductor current reaches the high-side switch current limit. When the high-side
switch turns off, the low-side switch rectifier is turned on and the inductor current ramps down until the
high-side switch turns on again or the inductor current reaches zero. In forced PWM mode operation,
negative inductor current is allowed to enable continuous conduction mode even at no load condition.
PVINx
VREF
Bandgap
Current
Limit Comparator
0.40 V
Limit
High Side
MODE / EN
MODE
Softstart
VIN
EN
Min. ON Time
FB
Min. OFF Time
NMOS
Control
Logic
Gate Driver
Anti
Shoot-Through
LXx
NMOS
VREF
Limit
Low Side
FBx
Integrated
Feed Back
Network
Error
Comparator
Zero/Negative
Current Limit Comparator
PGND/Thermal Pad
PMIC Internal Signals
External Inputs/Outputs
Copyright © 2016, Texas Instruments Incorporated
Figure 6-4. Converter Block Diagram
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
35
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.3.3.3
www.ti.com
DVS
BUCK1–BUCK6 and LDOA1–3 support dynamic voltage scaling (DVS) for maximum system efficiency.
The VR outputs can slew up and down in either 10-mV or 25-mV steps using the 7-bit voltage ID (VID)
defined in Section 5.7, Electrical Characteristics: Buck Controllers, and Section 5.8, Electrical
Characteristics: Synchronous Buck Converters. DVS slew rate is minimum 2.5 mV/µs. To meet the
minimum slew rate, VID progresses to the next code at 3-µs (nom) interval per 10-mV step. When DVS is
active, the VR is forced into PWM mode to ensure the output keeps track of VID code with minimal delay.
Additionally, PGOOD is masked when DVS is in progress. Figure 6-5 shows an example of slew down
and up from one VID to another.
VID
Number of Steps × 3 µs
VOUT
Figure 6-5. DVS Timing Diagram I
As shown in Figure 6-6, if a BUCKx_VID[6:0] is set to 7b000 0000, the output voltage slews down to 0.5 V
first, and then drifts down to 0 V as the SMPS stops switching. Subsequently, if a BUCKx_VID[6:0] is set
to a value (neither 7b000 0000 nor 7b000 0001) when the output voltage is less than 0.5 V, the VR ramps
up to 0.5 V first with soft-start kicking in, then it slews up to the target voltage in the aforementioned slew
rate.
NOTE
A fixed 200 µs of soft-start time is reserved for VOUT to reach 0.5 V. In this case, however,
the SMPS is not forced into PWM mode because it otherwise could cause VOUT to droop
momentarily if VOUT is drifting above 0.5 V for any reason.
VID
VOUT
Number of
Steps × 3 µs
Load and Time
Dependent
200 µs
Figure 6-6. DVS Timing Diagram II
36
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.3.3.4
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Current Limit
The buck controllers (BUCK1, BUCK2, and BUCK6) have inductor-valley current-limit architecture and the
current limit is programmable by an external resistor at the ILIMx pin. Equation 1 shows the calculation for
a desired resistor value, depending on specific application conditions. ILIMREF is the current source out of
the ILIMx pin that is typically 50 µA, and RDSON is the maximum channel resistance of the low-side FET.
The scaling factor is 1.3 to take into account all errors and temperature variations of RDSON, ILIMREF, and
RILIM. Finally, 8 is another scaling factor associated with ILIMREF.
Iripple(min) ·
§
RDSON u 8 u 1.3 u ¨ ILIM
¸
2
©
¹
RILIM
ILIMREF
where
•
•
ILIM is the target current limit. An appropriate margin must be allowed when determining ILIM from
maximum output DC load current.
Iripple(min) is the minimum peak-to-peak inductor ripple current for a given VOUT.
Iripple(min)
VOUT (VIN(MIN)
(1)
VOUT )
Lmax u VIN(MIN) u fsw(max)
where
•
•
•
Lmax is maximum inductance
fsw(max) is maximum switching frequency
VIN(MIN) minimum input voltage to the external power stage
(2)
The buck converter limit inductor peak current cycle-by-cycle to IIND_LIM is specified in Section 5.8,
Electrical Characteristics: Synchronous Buck Converters.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
37
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.3.4
www.ti.com
LDOs and Load Switches
6.3.4.1
VTT LDO
Powered from the BUCK6 output (VDDQ), the VTT LDO tracks VDDQ and regulates to half of the VDDQ
voltage for proper DDR termination. The LDO current limit is OTP dependent, and it is designed
specifically to power DDR memory. The VTT LDO is enabled by assertion (L → H) of the SLP_S0B pin
and is disabled by deassertion (H → L) of the same pin. The LDO core is a transconductance amplifier
with large gain, and it drives a current output stage that either sources or sinks current depending on the
deviation of VTTFB pin voltage from the target regulation voltage.
6.3.4.2
LDOA1–LDOA3
The TPS65094x device integrates three optional general-purpose LDOs. LDOA1 is powered from a 5-V
supply through the DRV5V_2_A1 pin and it can be factory configured to be an Always-On rail as long as a
valid power supply is available at VSYS. See Table 6-5 for LDOA1 output voltage options. LDOA2 and
LDOA3 share a power input pin (PVINLDOA2_A3). The output regulation voltages are set by writing to
LDOAx_VID[3:0] bits (Reg 0x9A, 0x9B, and 0xAE). See Table 6-6 for LDOA2 and LDOA3 output voltage
options. LDOA1 is controlled by LDOA1CTRL register. LDOA2 and LDOA3 can be controlled either by the
LDOLS_EN pin or by writing to the LDOA2_EN bit (Reg 0xA0) and the LDOA3_EN bit (Reg 0xA1) as long
as LDOLS_EN is low.
Table 6-5. LDOA1 Output Voltage Options
VID Bits
VOUT
VID Bits
VOUT
VID Bits
VOUT
VID Bits
VOUT
0000
1.35
0100
1.8
1000
2.3
1100
2.85
0001
1.5
0101
1.9
1001
2.4
1101
3.0
0010
1.6
0110
2.0
1010
2.5
1110
3.3
0011
1.7
0111
2.1
1011
2.7
1111
Not Used
Table 6-6. LDOA2 and LDOA3 Output Voltage Options
38
VID Bits
VOUT
VID Bits
VOUT
VID Bits
VOUT
VID Bits
VOUT
0000
0.70
0100
0.90
1000
1.10
1100
1.30
0001
0.75
0101
0.95
1001
1.15
1101
1.35
0010
0.80
0110
1.00
1010
1.20
1110
1.40
0011
0.85
0111
1.05
1011
1.25
1111
1.50
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.3.4.3
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Load Switches
The PMIC features three general-purpose load switches. SWA1 has a power input pin (PVINSWA1), while
SWB1 and SWB2 share a power input pin (PVINSWB1_B2). All switches have built-in slew rate control
during start-up to limit the inrush current.
Table 6-7 lists the control signals for enabling and disabling each LDO and load switch.
Table 6-7. Summary of LDO and Load Switch Control
CONTROL SIGNAL
RAIL
SLP_S4B or SLP_S3B (1)
SWB1_2
LDOLS_EN (2)
LDOA2, LDOA3, SWA1
SWA1_EN (3)
SWA1
SLP_S0B (4)
VTT LDO
(1)
(2)
(3)
(4)
For LPDDR3 and LPDDR4 memory, SWB1_2 is configured to
V1P8U and controlled by SLP_S4B. For DDR3L memory, SWB1_2
is configured to either V3P3S or V1P8S and controlled by SLP_S3B.
When LDOLS_EN = 0, the user can write to enable bits in Reg
0xA0–Reg 0xA1 to enable or disable the rails. Alternatively, all of
them could be factory configured to be part of sequence along with
other voltage rails. Pin name changed to SWA1_EN when LDOA1 is
factory programmed to always on.
When SWA1_EN = 0, the user can write to enable bits in Reg
0xA0–Reg 0xA1 to enable or disable the rails. Alternatively, all of
them could be factory configured to be part of sequence along with
other voltage rails. Pin name changed to LDOLS_EN when LDOA1
is not factory programmed to always on.
BUCK6_PG should be asserted as well.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
39
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.3.5
www.ti.com
Power Sequencing and VR Control
When a valid power source is available at VSYS (VSYS ≥ 5.6 V), internal analog blocks including LDO5
and LDO3P3 are enabled. For part numbers with LDOA1 set as an always on rail, the PMIC leaves reset
and I2C communication is available as soon as LDO3P3 and LDO5 power goods are confirmed. For part
numbers with LDOA1 set as a general-purpose LDO, the PMIC remains in reset until PMICEN is set high.
Five input pins of the TPS65094x device are driven by a host or by external-controller (EC) defined power
states that transition from one to another in sequence.
Table 6-8 shows various system-level power states. Also, Table 6-9 summarizes a list of active rails in
each power state. The sequencing for the transitions between these states is described in the following
sections.
If a rail is either disabled by I2C or OTP programming, then it is not enabled by the following sequences.
For example, VTT LDO is not enabled for LPDDR4 OTPs.
Table 6-8. Power State and Corresponding I/O Status
POWER
STATE
SIGNALS TO PMIC
SIGNALS FROM PMIC
PMICEN
SLP_S4B (1)
SLP_S3B (1)
SLP_S0B (2)
THERMTRIPB (3)
RSMRSTB
PCH_PWROK
G3
0
0
0
0
0
0
0
S4/S5
1
0
0
1
1
1
0
S3
1
1
0
1
1
1
0
S0iX
1
1
1
0
1
1
1
S0
1
1
1
1
1
1
1
(1)
When PMIC is first enabled, SLP_S4B and SLP_S3B are to be treated as if they are low (actual state of signal ignored) until the
deassertion of RSMRSTB (L → H).
When PMIC is first enabled, SLP_S0B are to be treated as if they are high (actual state of signal ignored) until the assertion of
PCH_PWROK (L → H).
THERMTRIPB is to be treated as if it is high (actual state of signal ignored) until the deassertion of RSMRSTB (L → H).
(2)
(3)
Table 6-9. Active Rails in Each Power State
POWER STATE
ACTIVE RAILS
S4/S5
BUCK1 (VNN), BUCK4 (V1P8A), BUCK5 (V1P24A)
S3
Rails in S4/S5 + SWB1_2 (V1P8U) (1), BUCK6 (VDDQ)
S0
Rails in S3 + SWB1_2 (2), VTT, BUCK2 (VCCGI), BUCK3 (VCCRAM)
S0iX
Rails in S0 – BUCK1 (VNN), BUCK2 (VCCGI), BUCK3 (VCCRAM), VTT
(1)
(2)
For LPDDR3 and LPDDR4
For DDR3L
40
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.3.5.1
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Cold Boot
G3
VSYS
S5
S5/S4
S3
S0
5.6 V
LDO5V/3.3V
LDOA1(b)
Ext. 5V/3.3V VR
PMICEN
T0
BUCK1 (VNN)
T1
BUCK4 (V1P8A)
T2
BUCK5 (V1P24A)
T3 ™ 10ms
RSMRSTB
THERMTRIPB
SLP_S4B
T4
SWB1_2 (V1P8U)(1)
T5
BUCK6 (VDDQ)
SLP_S3B
SLP_S0B
SWB1_2(2)
T6 ˜ 100us
VTT
T7
BUCK3 (VCCRAM)
T8 = PWROKDELA Y
PCH_PWROK
SET VID by Host
BUCK2 (VCCGI)
(1) LPDDR3 and LPDDR4
(2) DDR3L
(a) LDOA1 1RW ³$OZD\V 2Q´
(b) LDOA1 ³$OZD\V 2Q´
Figure 6-7. Cold Boot Sequence
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
41
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
As VSYS crosses above VSYS_UVLO_5V + VSYS_UVLO+5V_HYS, the cold-boot sequence is initiated by pulling the
PMICEN pin high followed by driving the remaining control pins high in order. SLP_S3B and SLP_S4B
may go high at the same time. SLP_S0B is not defined until the first transition to S0 after RSMRSTB
deassertion. SLP_S0B is defined for all Sx power-state transitions after the first transition to S0.
Table 6-10 lists definitions of the timing delays. These timing delays also apply to the subsequent
sequences. T0 to T10 are factory programmable to 0 ms, 2 ms, 4 ms, 8 ms, 16 ms, 24 ms, 32 ms, or
64 ms.
Table 6-10. Definition of Delays During Cold Boot Sequence
DELAY
42
TYP VALUE
UNIT
T0
PMICEN to BUCK1 (VNN) enable
DESCRIPTION
0
ms
T1
PMICEN to BUCK4 (V1P8A) enable
4
ms
T2
BUCK4 PG to BUCK5 (V1P24A) enable
0
ms
T3
BUCK5 PG to RSMRSTB deassertion
10
ms
T4
SLP_S4B deassertion to SWB1_2 (V1P8U) enable
0
ms
T5
SLP_S4B deassertion to BUCK6 (VDDQ) enable
4
ms
T6
Logical AND of BUCK6 PG, SLP_S0B, SLP_S3B, and SLP_S4B to VTT enable
0
ms
T7
SLP_S0B deassertion to BUCK3 (VCCRAM) enable
2
ms
T8
Logical AND of all PGs (except BUCK2) to PCH_PWROK assertion. User selectable
from POK_DELAY register.
100
ms
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.3.5.2
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Cold OFF
S0
S3
S4/S5
G3
SLP_S0B
SLP_S3B
SLP_S4B
PMICEN
VTT
BUCK1 (VNN)
BUCK3 (VCCRAM)
BUCK2 (VCCGI)
PCH_PWROK
SWB1_2(2)
SWB1_2 (V1P8U)(1)
30ms to 60 ms
BUCK6 (VDDQ)
BUCK4 (V1P8A)
BUCK5 (V1P24A)
RSMRSTB
(1) LPDDR3 and LPDDR4
(2) DDR3L
Figure 6-8. Cold OFF Sequence
Cold OFF sequence is initiated by pulling the SLP_S3B pin low in the S0 state, followed by SLP_S4B,
SLP_S0B, and PMICEN.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
43
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.3.5.3
www.ti.com
Connected Standby Entry and Exit
S0
S0
S0iX
SLP_S0B
1.8 V
SLP_S3B
SLP_S4B
3.3 V
PCH_PWROK
VTT
˜ 100 µs
VID
BUCK1 (VNN)
1.05 V
Host sets VR to 0 V through I2C
0V
˜ 5 ms
BUCK3 (VCCRAM)
0V
SET VID by Host
VID
BUCK2 (VCCGI)
VID
Host sets VR to 0 V through I2C
0V
Figure 6-9. Connected Standby Entry and Exit Sequence
S0 to S0iX (Connected Standby) entry and exit occurs when SLP_S0B is pulled low and high,
respectively. In Connected Standby state, VTT LDO is turned off, but all PGOODs remain asserted.
BUCK1–BUCK3 are not disabled, but instead stop switching while BUCK4–BUCK6 remain in regulation.
SWB1_2 also stays enabled. On entry, BUCK2 and BUCK3 decay to 0 V with their VID registers retaining
the last programmed values to which the BUCKs ramp back up on exit. The host can write to
BUCK2CTRL and BUCK3CTRL registers regardless of the state of the SLP_S0B pin while SLP_S3B and
SLP_S4B are high, which means that BUCK2 and BUCK3 can be changed to ramp to a different voltage
upon exiting S0iX than they had when entering S0iX state. BUCK1 ramps back up to the default value
(1.05 V).
Table 6-11 summarizes status of each VR in Connected Standby state.
Table 6-11. Summary of Rails on Connected Standby Entry and Exit
S0 → S0IX
VR
44
S0IX → S0
BUCK1 (VNN)
0V
1.05 V
BUCK2 (VCCGI)
0V
0V
BUCK3 (VCCRAM) 0 V
1.05 V
BUCK4 (V1P8A)
VID value
VID value
BUCK5 (V1P24A)
VID value
VID value
BUCK6 (VDDQ)
OTP dependent
OTP dependent
VTT LDO (VTT)
OFF
VDDQ / 2
SWB1_2
ON
ON
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.3.5.4
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
S0 to S3 Entry and Exit
Assertion of SLP_S3B (H → L) triggers S3 entry. Deassertion of SLP_S3B causes S3 exit and S0 entry as
depicted in Figure 6-10. On S3 exit, BUCK1–BUCK3 behave exactly the same way as they do on S0iX
exit, which is explained in Section 6.3.5.3, Connected Standby Entry and Exit.
S0
S0
S3
1.8 V
SLP_S4B
SLP_S0B
SLP_S3B
T8
PCH_PWROK
˜ 100 µs
VTT
VID
1.05 V
BUCK1 (VNN)
0V
BUCK3 (VCCRAM)
˜ 5 ms
0V
SET VID by Host
BUCK2 (VCCGI)
0V
SWB1_2(2)
SWB1_2 (V1P8U)(1)
(1) LPDDR3 and LPDDR4
(2) DDR3L
Figure 6-10. S3 Entry and Exit Sequence
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
45
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.3.5.5
www.ti.com
S0 to S4/5 Entry and Exit
Assertion of the SLP_S4B (H → L) after the S3 entry pushes the sequence further down to S4/5 where
SWB1_2 (for LPDDR3 or LPDDR4) and BUCK6 are disabled. Any rails not shown are essentially the
same as the S0 to S3 entry and exit case described in Figure 6-11.
S0
S3
S5/S4
S0
S3
1.8 V
SLP_S0B
SLP_S3B
SLP_S4B
T8
PCH_PWROK
T5
BUCK6 (VDDQ)
VTT
˜ 100 µs
SWB1_2(2)
SWB1_2 (V1P8U)(1)
˜ 2 ms
30 ms to 60 ms
VID
1.05 V
BUCK1 (VNN)
0V
BUCK3 (VCCRAM)
˜ 5 ms
0V
SET VID by Host
BUCK2 (VCCGI)
0V
(1) LPDDR3 and LPDDR4
(2) DDR3L
Figure 6-11. S4/5 Entry and Exit Sequence
46
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.3.5.6
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Emergency Shutdown
When VSYS crosses below VSYS_UVLO_5V, all Power Good pins are deasserted; after 444 ns (nominal) of
delay, all VRs shut down (see Figure 6-12). Upon shutdown, all internal discharge resistors are set to 100
Ω to ensure timely decay of all VR outputs. VSYS crossing above VSYS_UVLO_5V + VSYS_UVLO_5V_HYS and
assertion of PMICEN is required to re-enable the VRs.
Other conditions that cause emergency shutdown are the following:
• The die temperature rising above the critical temperature threshold (TCRIT)
• Falling edge of THERMTRIPB
• Deassertion of Power Good of any rail or failure to reach power good within 10 ms of enable
(configurable)
5.4 V
VSYS
RSMRSTB
PCH_PWROK
444 ns (nominal with ±1% variation)
BUCKx
LDOAx
SWx
VTT
Figure 6-12. Emergency Shutdown Sequence
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
47
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.4
6.4.1
www.ti.com
Device Functional Modes
Off Mode
When power supply at the VSYS pin is less than VSYS_UVLO_5V (5.4-V nominal) + VSYS_UVLO_5V_HYS (0.2-V
nominal), the device is in off mode, where all output rails are disabled. If the supply voltage is greater than
VSYS_UVLO_3V (3.6-V nominal) + VSYS_UVLO_3V_HYS (0.15-V nominal) while it is still less than VSYS_UVLO_5V +
VSYS_UVLO_5V_HYS, then the internal band-gap reference (VREF pin) along with LDO3P3 are enabled and
regulated at target values.
6.4.2
Standby Mode
When power supply at the VSYS pin rises above VSYS_UVLO_5V + VSYS_UVLO_5V_HYS, the device enters
standby mode, where all internal reference and regulators (LDO3P3 and LDO5) are running, and I2C
interface and PMICEN pin are ready to respond. All default registers defined in Section 6.6, Register
Maps, should now have been loaded from one-time programmable (OTP) memory. Quiescent current
consumption in standby mode is specified in Section 5.5, Electrical Characteristics: Total Current
Consumption.
6.4.3
Active Mode
The device proceeds to active mode when any output rail is enabled either through an input pin as
discussed in Section 6.3.5, Power Sequencing and VR Control, or by writing to the EN bits through I2C.
Output regulation voltage can also be changed by writing to the VID bits defined in Section 6.6, Register
Maps.
6.5
6.5.1
Programming
I2C Interface
The I2C interface is a 2-wire serial interface developed by NXP™ (formerly Philips Semiconductor) (see
the I2C-Bus Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line
(SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are
pulled high. All the I2C compatible devices connect to the I2C bus through open-drain I/O pins, DATA and
CLK. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master
is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the start and stop of data transfer. A slave device receives and/or transmits data
on the bus under control of the master device.
The TPS65094x device works as a slave and supports the following data transfer modes, as defined in the
I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode
(1 Mbps). The interface adds flexibility to the power supply solution, enabling programming of most
functions to new values depending on the instantaneous application requirements. Register contents are
loaded when VSYS higher than VSYS_UVLO_5V is applied to the TPS65094x device. The I2C interface is
running from an internal oscillator that is automatically enabled when there is an access to the interface.
The data transfer protocol for standard and fast modes are exactly the same, therefore, they are referred
to as F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is
referred to as H/S-mode.
The TPS65094x device supports 7-bit addressing; however, 10-bit addressing and general call address
are not supported. The default device address is 0x5E.
48
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.5.1.1
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
F/S-Mode Protocol
The master initiates data transfer by generating a START condition. The START condition exists when a
high-to-low transition occurs on the SDA line while SCL is high (see Figure 6-13). All I2C-compatible
devices should recognize a START condition.
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse (see
Figure 6-14). All devices recognize the address sent by the master and compare it to their internal fixed
addresses. Only the slave device with a matching address generates an acknowledge (see Figure 6-15),
by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this
acknowledge, the master identifies that the communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data
from the slave (R/W bit = 1). In either case, the receiver must acknowledge the data sent by the
transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on
which one is the receiver. Any 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge
can continue as long as necessary.
To signal the end of the data transfer, the master generates a STOP condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 6-13). This STOP condition releases the bus and
stops the communication link with the addressed slave. All I2C-compatible devices must recognize the
STOP condition. Upon the receipt of a STOP condition, all devices detect that the bus is released, and
they wait for a START condition followed by a matching address.
SDA
SCL
S
P
START
Condition
STOP
Condition
Figure 6-13. START and STOP Conditions
SDA
SCL
Data Valid
Change of Data Allowed
Figure 6-14. Bit Transfer on the I2C Bus
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
49
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
Data Output at
Transmitter
Not ACK
Data Output at
Receiver
ACK
SCL from Master
1
2
8
9
S
START
Condition
Clock pulse for ACK
Figure 6-15. Acknowledge on the I2C Bus
Generate ACK Signal
SDA
MSB
ACK Signal From Slave
Address
R/ W
SCL
1
2
7
8
9
1
2
3-8
ACK
S or Sr
Byte Complete, Interrupt
Within Slave
9
ACK
Clock Line Held Low While
Interrupts Are Serviced
START or
Repeated START Condition
P or Sr
STOP or
Repeated START Condition
Figure 6-16. I2C Bus Protocol
50
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
SCL
SDA
A6
START
A5
A4
A0
R /W
ACK
0
0
R7
R6
R5
R0
ACK
D7
D6
D5
D0
0
Slave Address
ACK
0
Register Address
Data
STOP
Figure 6-17. I2C Interface WRITE to TPS65094x in F/S Mode
SCL
SDA
A6
A0
R/ W ACK
0
START
Slave Address
R7
0
R0
ACK
A6
A0
0
R/ W
ACK
1
0
Slave Address
Register Address
D7
D0
ACK
0
Slave Drives
the Data
Master
Drives ACK
and Stop
STOP
Repeated
START
Figure 6-18. I2C Interface READ from TPS65094x in F/S Mode
(Only Repeated START is Supported)
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
51
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.6
www.ti.com
Register Maps
Default value of RESERVED R/W bits must not be written to the opposite value.
6.6.1
VENDORID: PMIC Vendor ID Register (offset = 00h) [reset = 0010 0010]
Figure 6-19. VENDORID Register (offset = 00h) [reset = 0010 0010]
Bit
Bit Name
7
6
5
4
3
2
1
0
VENDORID[7]
VENDORID[6]
VENDORID[5]
VENDORID[4]
VENDORID[3]
VENDORID[2]
VENDORID[1]
VENDORID[0]
TPS65094x
0
0
1
0
0
0
1
0
Access
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-12. VENDORID Register Field Descriptions
Bit
Field
Type Reset
Description
7–0
VENDORID[7:0]
R
Vendor identification register
6.6.2
00100010
DEVICEID: PMIC Device and Revision ID Register (offset = 01h) [reset = OTP Dependent]
Figure 6-20. DEVICEID Register (offset = 01h) [reset = OTP Dependent]
Bit
7
6
5
4
3
2
1
0
REVID[1]
REVID[0]
OTP_
VERSION[1]
OTP_
VERSION[0]
PART_
NUMBER[3]
PART_
NUMBER[2]
PART_
NUMBER[1]
PART_
NUMBER[0]
TPS650940
0
0
0
0
1
0
0
0
TPS650941
0
0
1
0
1
0
0
1
TPS650942
0
0
0
1
1
0
1
0
TPS650944
0
0
0
0
1
1
0
0
TPS650945
0
0
0
0
1
1
0
1
TPS650947
0
0
0
0
1
1
1
1
Access
R
R
R
R
R
R
R
R
Bit Name
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-13. DEVICEID Register Field Descriptions
Bit
Field
Type Reset
Description
7–6
REVID[1:0]
R
OTP
Silicon revision ID
OTP
OTP variation ID
00: A
01: B
10: C
11: D
OTP
Device part number ID
1000: TPS650940
1001: TPS650941
1010: TPS650942
1011: TPS650943
1100: TPS650944
1101: TPS650945
1110: TPS650946
1111: TPS650947
0000: TPS650948
5–4
3–0
52
OTP_VERSION[1:0]
PART_NUMBER[3:0]
R
R
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.6.3
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
Figure 6-21. IRQ Register (offset = 02h) [reset = 0000 0000]
Bit
Bit Name
7
6
5
4
3
2
1
0
VENDOR_
IRQ
RESERVED
RESERVED
RESERVED
ONOFFSRC
RESERVED
RESERVED
DIETEMP
TPS65094x
Access
0
0
0
0
0
0
0
0
R/W
R
R
R
R/W
R
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-14. IRQ Register Field Descriptions
Bit
Field
Type Reset
Description
7
VENDOR_IRQ
R/W
0
Vendor-specific interrupt, indicating fault event occurrence. Asserted when
either one of following conditions occurs:
A. Deassertion of Power Good of any VR
B. Overcurrent detection from BUCK1, BUCK2, BUCK6, or VTT LDO
C. Die temperature crosses over the hot temperature threshold (THOT)
D. Die temperature crosses over the critical temperature threshold (TCRIT)
0: Not asserted
1: Asserted. Host to write 1 to clear.
3
ONOFFSRC
R/W
0
Asserted when PMIC shuts down.
0: Not asserted.
1: Asserted. Host to write 1 to clear.
0
DIETEMP
R/W
0
Die Temp interrupt. Asserted when PMIC die temperature crosses above the
hot temperature threshold (THOT).
0: Not asserted.
1: Asserted. Host to write 1 to clear.
6.6.4
IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
Figure 6-22. IRQ_MASK Register (offset = 03h) [reset = 1111 1111]
Bit
Bit Name
7
6
5
4
3
2
1
0
MVENDOR_IRQ
RESERVED
RESERVED
RESERVED
MONOFFSRC
RESERVED
RESERVED
MDIETEMP
TPS65094x
Access
1
1
1
1
1
1
1
1
R/W
R
R
R
R/W
R
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-15. IRQ_MASK Register Field Descriptions
Bit
Field
Type Reset
Description
7
MVENDOR_IRQ
R/W
1
Vendor-specific fault interrupt mask.
0: Not masked
1: Masked
3
MONOFFSRC
R/W
1
PMIC shutdown event interrupt mask
0: Not masked
1: Masked
0
MDIETEMP
R/W
1
Die temp interrupt mask.
0: Not masked
1: Masked
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
53
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.6.5
www.ti.com
PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
Figure 6-23. PMICSTAT Register (offset = 04h) [reset = 0000 0000]
Bit
Bit Name
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SDIETEMP
TPS65094x
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-16. PMICSTAT Register Field Descriptions
Bit
0
6.6.6
Field
Type Reset
Description
SDIETEMP
R
PMIC die temperature status.
0: PMIC die temperature is below THOT.
1: PMIC die temperature is above THOT.
0
OFFONSRC: PMIC Power Transition Event Register (offset = 05h) [reset = 0000 0000]
Figure 6-24. OFFONSRC Register (offset = 05h) [reset = 0000 0000]
Bit
Bit Name
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
COLDOFF
UVLO
OCP
CRITTEMP
TPS65094x
0
0
0
0
0
0
0
0
Access
R
R
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-17. OFFONSRC Register Field Descriptions
Bit
3
2
1
0
54
Field
Type Reset
Description
COLDOFF
R/W
0
Set by PMIC cleared by host. Host writes 1 to this bit to clear it.
0 = Cleared
1 = PMIC was shut down by host through PMIC_EN pin.
0
Set by PMIC cleared by host. Host writes 1 to this bit to clear it.
0 = Cleared
1 = PMIC was shut down due to a UVLO event (VSYS less 5.4 V). The setting
of this bit sets the ONOFFSRC bit in the PMIC_IRQ register.
0
Set by PMIC cleared by host. Host writes 1 to this bit to clear it.
0 = Cleared
1 = PMIC shut down due to a power fault event. The setting of this bit sets the
ONOFFSRC bit in the PMIC_IRQ register.
0
Set by PMIC cleared by host. Host writes 1 to this bit to clear it.
0 = Cleared
1 = PMIC shut down due to the rise of PMIC die temperature above critical
temperature threshold (TCRIT). The setting of this bit sets the ONOFFSRC bit in
the PMIC_IRQ register.
UVLO
OCP
CRITTEMP
R/W
R/W
R/W
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
6.6.7
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = 0011 1000]
Figure 6-25. BUCK1CTRL Register (offset = 20h) [reset = 0011 1000]
Bit
Bit Name
TPS65094x
Access
7
6
5
4
3
2
1
0
RESERVED
BUCK1_VID[6]
BUCK1_VID[5]
BUCK1_VID[4]
BUCK1_VID[3]
BUCK1_VID[2]
BUCK1_VID[1]
BUCK1_VID[0]
0
0
1
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-18. BUCK1CTRL Register Field Descriptions
Bit
6–0
6.6.8
Field
Type Reset
BUCK1_VID[6:0]
R/W
Description
0111000
(1.05 V)
This field sets the BUCK1 regulator output regulation voltage in normal mode.
Default = 1.05 V. Note that 0 V is a valid setting and all Power Goods stay high
when VID is set to 0x00 and (or) SLP_S0B goes low. See Table 6-3 for full
details.
BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 0000 0000]
Figure 6-26. BUCK2CTRL Register (offset = 21h) [reset = 0000 0000]
Bit
Bit Name
TPS65094x
Access
7
6
5
4
3
2
1
0
RESERVED
BUCK2_VID[6]
BUCK2_VID[5]
BUCK2_VID[4]
BUCK2_VID[3]
BUCK2_VID[2]
BUCK2_VID[1]
BUCK2_VID[0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-19. BUCK2CTRL Register Field Descriptions
Bit
Field
Type Reset
6–0
BUCK2_VID[6:0]
R/W
6.6.9
Description
0000000
(0 V)
This field sets the BUCK2 regulator output regulation voltage in normal mode.
Default = 0 V. Note that 0 V is a valid setting and all Power Goods must stay
high when VID is set to 0x00 and (or) SLP_S0B goes low. See Table 6-3 for full
details.
BUCK3CTRL: BUCK3 Control Register (offset = 23h) [reset = 0001 0001]
Figure 6-27. BUCK3CTRL Register (offset = 23h) [reset = 0001 0001]
Bit
Bit Name
TPS65094x
Access
7
6
5
4
3
2
1
0
RESERVED
BUCK3_VID[6]
BUCK3_VID[5]
BUCK3_VID[4]
BUCK3_VID[3]
BUCK3_VID[2]
BUCK3_VID[1]
BUCK3_VID[0]
0
0
0
1
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-20. BUCK3CTRL Register Field Descriptions
Bit
Field
Type Reset
6–0
BUCK3_VID[6:0]
R/W
0010001
(1.05 V)
Description
This field sets the BUCK3 regulator output regulation voltage in normal mode.
Default = 1.05 V. Note that 0 V is a valid setting and all Power Goods must stay
high when VID is set to 0x00 and (or) SLP_S0B goes low. See Table 6-4 for full
details.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
55
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
6.6.10 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP Dependent]
Figure 6-28. BUCK4CTRL Register (offset = 25h) [reset = OTP Dependent]
Bit
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BUCK4_MODE
RESERVED
TPS650940,
TPS650941,
TPS65942, and
TPS650944
0
0
1
1
1
1
0
1
TPS650945, and
TPS650947
0
0
1
1
1
1
1
1
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-21. BUCK4CTRL Register Field Descriptions
Bit
Field
1
Type Reset
BUCK4_MODE
R/W
Description
TPS65094
0,
TPS65094
1,
TPS65942
, and
TPS65094
4: 0
TPS65094
5, and
TPS65094
7: 1
This field sets the BUCK4 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
6.6.11 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP Dependent]
Figure 6-29. BUCK5CTRL Register (offset = 26h) [reset = OTP Dependent]
Bit
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BUCK5_MODE
RESERVED
TPS650940,
TPS650941,
TPS65942, and
TPS650944
0
0
1
1
1
1
0
1
TPS650945, and
TPS650947
0
0
1
1
1
1
1
1
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-22. BUCK5CTRL Register Field Descriptions
Bit
1
56
Field
BUCK5_MODE
Type Reset
R/W
TPS65094
0,
TPS65094
1,
TPS65942
, and
TPS65094
4: 0
TPS65094
5, and
TPS65094
7: 1
Description
This field sets the BUCK5 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.6.12 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = 0011 1101]
Figure 6-30. BUCK6CTRL Register (offset = 27h) [reset = 0011 1101]
Bit
Bit Name
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BUCK6_MODE
RESERVED
TPS65094x
0
0
1
1
1
1
0
1
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-23. BUCK6CTRL Register Field Descriptions
Bit
1
Field
Type Reset
Description
BUCK6_MODE
R/W
This field sets the BUCK6 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
0
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
57
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
6.6.13 DISCHCNT1: Discharge Control1 Register (offset = 40h) [reset = 0101 0101]
All xx_DIS[1:0] bits automatically set to 00 when the corresponding VR is enabled. Discharge resistance
values listed here are approximate.
Figure 6-31. DISCHCNT1 Register (offset = 40h) [reset = 0101 0101]
Bit
Bit Name
TPS65094x
Access
7
6
5
4
3
2
1
0
BUCK4_DIS[1]
BUCK4_DIS[0]
BUCK3_DIS[1]
BUCK3_DIS[0]
BUCK2_DIS[1]
BUCK2_DIS[0]
BUCK1_DIS[1]
BUCK1_DIS[0]
0
1
0
1
0
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-24. DISCHCNT1 Register Field Descriptions
Bit
7–6
5–4
3–2
1–0
58
Field
BUCK4_DIS[1:0]
BUCK3_DIS[1:0]
BUCK2_DIS[1:0]
BUCK1_DIS[1:0]
Type Reset
Description
R/W
01
BUCK4 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
01
BUCK3 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
01
BUCK2 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
01
BUCK1 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
R/W
R/W
R/W
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.6.14 DISCHCNT2: Discharge Control2 Register (offset = 41h) [reset = 0101 0101]
All xx_DIS[1:0] bits automatically set to 00 when the corresponding VR is enabled. Discharge resistance
values listed here are approximate.
Figure 6-32. DISCHCNT2 Register (offset = 41h) [reset = 0101 0101]
Bit
Bit Name
TPS65094x
Access
7
6
5
4
3
2
1
0
LDOA2_DIS[1]
LDOA2_DIS[0]
SWA1_DIS[1]
SWA1_DIS[0]
BUCK6_DIS[1]
BUCK6_DIS[0]
BUCK5_DIS[1]
BUCK5_DIS[0]
0
1
0
1
0
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-25. DISCHCNT2 Register Field Descriptions
Bit
Field
7–6
LDOA2_DIS[1:0]
5–4
SWA1_DIS[1:0]
3–2
Description
R/W
01
LDOA2 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
01
SWA1 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
01
BUCK6 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
01
BUCK5 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
R/W
BUCK6_DIS[1:0]
1–0
Type Reset
R/W
BUCK5_DIS[1:0]
R/W
6.6.15 DISCHCNT3: Discharge Control3 Register (offset = 42h) [reset = 0000 0101]
All xx_DIS[1:0] bits automatically set to 00 when the corresponding VR is enabled. Discharge resistance
values listed here are approximate.
Figure 6-33. DISCHCNT3 Register (offset = 42h) [reset = 0000 0101]
Bit
Bit Name
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
SWB1_DIS[1]
SWB1_DIS[0]
LDOA3_DIS[1]
LDOA3_DIS[0]
TPS65094x
0
0
0
0
0
1
0
1
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-26. DISCHCNT3 Register Field Descriptions
Bit
3–2
1–0
Field
SWB1_DIS[1:0]
LDOA3_DIS[1:0]
Type Reset
Description
R/W
01
SWB1 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
01
LDOA3 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
R/W
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
59
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
6.6.16 POK_DELAY: PCH_PWROK Delay Register (offset = 43h) [reset = 0000 0111]
Programmable Power Good delay for PCH_PWROK pin, measured from the moment when all VRs reach
the regulation range to Power Good assertion.
Figure 6-34. POK_DELAY Register (Offset = 43h) [reset = 0000 0111]
Bit
7
Bit Name
6
5
4
3
2
RESERVED
1
0
PWROKDELAY PWROKDELAY PWROKDELAY
[2]
[1]
[0]
RESERVED
RESERVED
RESERVED
RESERVED
TPS65094x
0
0
0
0
0
1
1
1
Access
R
R
R
R
R
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-27. POK_DELAY Register Field Descriptions
Bit
Field
2–0
PWROKDELAY[2:0]
Type Reset
Description
R/W
Programmable delay measured from the moment all rails have reached
regulation voltage to assertion of PCH_PWROK. All values have ±10%
variation.
000 = 2.5 ms
001 = 5.0 ms
010 = 10 ms
011 = 15 ms
100 = 20 ms
101 = 50 ms
110 = 75 ms
111 = 100 ms (default)
111
6.6.17 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset
= 0000 0000]
Figure 6-35. FORCESHUTDN Register (offset = 91h) [reset = 0000 0000]
Bit
Bit Name
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SDWN
TPS65094x
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-28. FORCESHUTDN Register Field Descriptions
Bit
0
Field
Type Reset
Description
SDWN
R/W
Forces reset of the PMIC. The bit is self-clearing.
0 = No action
1 = PMIC is forced to shut down.
0
6.6.18 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 0010 1111]
Figure 6-36. BUCK4VID Register (offset = 94h) [reset = 0010 1111]
Bit
Bit Name
TPS65094x
Access
7
6
5
4
3
2
1
0
RESERVED
BUCK4_VID[6]
BUCK4_VID[5]
BUCK4_VID[4]
BUCK4_VID[3]
BUCK4_VID[2]
BUCK4_VID[1]
BUCK4_VID[0]
0
0
1
0
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-29. BUCK4VID Register Field Descriptions
Bit
Field
Type Reset
6–0
BUCK4_VID[6:0]
R/W
60
0101111
(1.80 V)
Description
This field sets the BUCK4 regulator output regulation voltage in normal mode.
Default = 1.80 V. Note that 0 V is a valid setting and all Power Goods must stay
high when VID is set to 0x00. See Table 6-4 for full details.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.6.19 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 0100 1011]
Figure 6-37. BUCK5VID Register (Offset = 96h) [reset = 0100 1011]
Bit
Bit Name
TPS65094x
Access
7
6
5
4
3
2
1
0
RESERVED
BUCK5_VID[6]
BUCK5_VID[5]
BUCK5_VID[4]
BUCK5_VID[3]
BUCK5_VID[2]
BUCK5_VID[1]
BUCK5_VID[0]
0
1
0
0
1
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-30. BUCK5VID Register Field Descriptions
Bit
Field
Type Reset
6–0
BUCK5_VID[6:0]
R/W
Description
1001011
(1.24 V)
This field sets the BUCK5 regulator output regulation voltage in normal mode.
Default = 1.24 V. Note that 0 V is a valid setting and all Power Goods stay high
when VID is set to 0x00. See Table 6-3 for full details.
6.6.20 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP Dependent]
Figure 6-38. BUCK6VID Register (Offset = 98h) [reset = OTP Dependent]
Bit
7
6
5
4
3
2
1
0
RESERVED
BUCK6_VID[6]
BUCK6_VID[5]
BUCK6_VID[4]
BUCK6_VID[3]
BUCK6_VID[2]
BUCK6_VID[1]
BUCK6_VID[0]
TPS650940,
TPS650944 and
TPS650945
0
0
1
1
1
1
0
1
TPS650941
0
1
0
0
0
1
1
1
TPS650942 and
TPS650947
0
1
0
1
0
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
Access
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-31. BUCK6VID Register Field Descriptions
Bit
6–0
Field
BUCK6_VID[6:0]
Type
Reset
R/W
TPS650940,
TPS650944,
TPS650945:
(1.1 V)
TPS650941:
(1.20 V)
TPS650942,
TPS650947:
(1.35 V)
Description
and
0111101
1000111
and
1010110
This field sets the BUCK6 regulator output regulation voltage in
normal mode. Default = OTP Dependent. Note that 0 V is a valid
setting and all Power Goods stay high when VID is set to 0x00.
See Table 6-3 for full details.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
61
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
6.6.21 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP Dependent]
LDOA2_SLPVID is used when SLP_S0B is low. Keep LDOA2_SLPVID equal to LDOA2_VID if sleep
functionality is not desired.
Figure 6-39. LDOA2VID Register (offset = 9Ah) [reset = OTP Dependent]
Bit
Bit Name
TPS650940,
TPS650941,
TPS650942,
TPS650945, and
TPS650947
TPS650944
Access
7
6
5
4
3
2
1
0
LDOA2_
SLPVID[1]
LDOA2_
SLPVID[2]
LDOA2_
SLPVID[1]
LDOA2_
SLPVID[0]
LDOA2_VID[3]
LDOA2_VID[2]
LDOA2_VID[1]
LDOA2_VID[0]
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-32. LDOA2VID Register Field Descriptions
Bit
Field
7–4
Type Reset
LDOA2_SLPVID[3:0]
3–0
LDOA2_VID[3:0]
Description
R/W
TPS650940,
TPS650941,
TPS650942,
TPS650945, and This field sets the LDOA2 regulator output regulation voltage in sleep
TPS650947: 1010 mode. Default = OTP Dependent. See Table 6-6 for full details.
(1.2 V)
TPS650944: 0000
(0.7 V)
R/W
TPS650940,
TPS650941,
TPS650942,
TPS650945, and This field sets the LDOA2 regulator output regulation voltage in normal
TPS650947: 1010 mode. Default = OTP Dependent. See Table 6-6 for full details.
(1.2 V)
TPS650944: 0000
(0.7 V)
6.6.22 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP Dependent]
LDOA3_SLPVID is used when SLP_S0B is low. Keep LDOA3_SLPVID equal to LDOA3_VID if sleep
functionality is not desired.
Figure 6-40. LDOA3VID Register (offset = 9Bh) [reset = OTP Dependent]
Bit
Bit Name
TPS650940,
TPS650941,
TPS650942,
TPS650945, and
TPS650947
TPS650944
Access
7
6
5
4
3
2
1
0
LDOA3_
SLPVID[3]
LDOA3_
SLPVID[2]
LDOA3_
SLPVID[1]
LDOA3_
SLPVID[0]
LDOA3_VID[3]
LDOA3_VID[2]
LDOA3_VID[1]
LDOA3_VID[0]
1
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-33. LDOA3VID Register Field Descriptions
Bit
7–4
62
Field
LDOA3_SLPVID[3:0]
Type
Reset
Description
R/W
TPS650940, TPS650941,
TPS650942, TPS650945,
and TPS650947: 1011
(1.25 V)
TPS650944: 0000 (0.7 V)
This field sets the LDOA3 regulator output regulation voltage
in sleep mode. Default = OTP Dependent. See Table 6-6 for
full details.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Table 6-33. LDOA3VID Register Field Descriptions (continued)
Bit
3–0
Field
LDOA3_VID[3:0]
Type
Reset
Description
R/W
TPS650940, TPS650941,
TPS650942, TPS650945,
and TPS650947: 1011
(1.25 V)
TPS650944: 0000 (0.7 V)
This field sets the LDOA3 regulator output regulation voltage
in normal mode. Default = OTP Dependent. See Table 6-6 for
full details.
6.6.23 VR_CTRL1: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP Dependent]
Figure 6-41. VR_CTRL1 Register (offset = 9Ch) [reset = OTP Dependent]
Bit
7
6
5
4
3
2
1
0
BUCK2_
DISABLEB
BUCK1_
DISABLEB
1
RESERVED
RESERVED
BUCK3_MODE
BUCK2_MODE
BUCK1_MODE
BUCK3_
DISABLEB
TPS650940,
TPS650941,
TPS650942, and
TPS650944
0
0
0
0
0
1
1
TPS650945, and
TPS650947
0
0
1
0
0
1
1
Access
R
R
R/W
R/W
R/W
R/W
R/W
Bit Name
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-34. VR_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
5
BUCK3_MODE
R/W
TPS6509
40,
TPS6509
41,
TPS6509
This field sets the BUCK3 regulator operating mode.
42, and
0 = Automatic mode
TPS6509
1 = Forced PWM mode
44: 0
TPS6509
45, and
TPS6509
47: 1
4
BUCK2_MODE
R/W
0
This field sets the BUCK2 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
3
BUCK1_MODE
R/W
0
This field sets the BUCK1 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
1
BUCK3 Active Low Disable bit. Writing 0 to this bit forces BUCK3 to turn off
regardless of status of enable pins (PMICEN, SLP_Sx). Has priority over
BUCK3_EN.
0: Disabled
1: BUCK3 operates normally.
1
BUCK2 Active Low Disable bit. Writing 0 to this bit forces BUCK2 to turn off
regardless of status of enable pins (PMICEN, SLP_Sx). Has priority over
BUCK2_EN.
0: Disabled
1: BUCK2 operates normally.
1
BUCK1 Active Low DISABLE bit. Writing 0 to this bit forces BUCK1 to turn off
regardless of status of enable pins (PMICEN, SLP_Sx). Has priority over
BUCK1_EN.
0: Disabled
1: BUCK1 operates normally.
2
1
0
BUCK3_DISABLEB
BUCK2_DISABLEB
BUCK1_DISABLEB
R/W
R/W
R/W
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
63
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
6.6.24 VR_CTRL2: VR Enable Register (offset = 9Eh) [reset = 0000 0000]
Figure 6-42. VR_CTRL2 Register (offset = 9Eh) [reset = 0000 0000]
Bit
Bit Name
7
6
5
4
3
2
1
0
LDOA2_EN
SWA1_EN
BUCK6_EN
BUCK5_EN
BUCK4_EN
BUCK3_EN
BUCK2_EN
BUCK1_EN
TPS65094x
Access
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-35. VR_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LDOA2_EN
R/W
0
LDOA2 Enable bit.
0: Enabled if LDOLS_EN = 1
1: Enabled regardless of LDOLS_EN state
6
SWA1_EN
R/W
0
SWA1 Enable bit.
0: Enabled if LDOLS_EN pin or SWA1_EN pin = 1
1: Enabled regardless of LDOLS_EN or SWA1_EN state
5
BUCK6_EN
R/W
0
BUCK6 Enable bit.
0: BUCK6 operates normally.
1: Enabled regardless of power sequencing
4
BUCK5_EN
R/W
0
BUCK5 Enable bit.
0: BUCK5 operates normally.
1: Enabled regardless of power sequencing
3
BUCK4_EN
R/W
0
BUCK4 Enable bit.
0: BUCK4 operates normally.
1: Enabled regardless of power sequencing
2
BUCK3_EN
R/W
0
BUCK3 Enable bit. BUCK3_DISABLEB has priority over BUCK3_EN.
0: BUCK3 operates normally.
1: Enabled regardless of power sequencing, unless BUCK3_DISABLEB = 0
1
BUCK2_EN
R/W
0
BUCK2 Enable bit. BUCK2_DISABLEB has priority over BUCK2_EN.
0: BUCK2 operates normally.
1: Enabled regardless of power sequencing, unless BUCK2_DISABLEB = 0
0
BUCK1_EN
R/W
0
BUCK1 Enable bit. BUCK1_DISABLEB has priority over BUCK1_EN.
0: BUCK1 operates normally.
1: Enabled regardless of power sequencing, unless BUCK1_DISABLEB = 0
6.6.25 VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = OTP Dependent]
Figure 6-43. VR_CTRL3 Register (Offset = 9Fh) [reset = OTP Dependent]
Bit
7
6
5
4
3
2
1
0
SWA1_
DISABLEB
VTT_
DISABLEB
VTT_EN
RESERVED
SWB1_2_EN
LDOA3_EN
RESERVED
SWB1_2_
DISABLEB
TPS650940,
TPS650944, and
TPS650945
0
1
1
0
1
0
0
0
TPS650941,
TPS650942 and
TPS650947
0
1
1
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
Access
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
64
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Table 6-36. VR_CTRL3 Register Field Descriptions
Bit
6
5
4
3
Field
Type
SWB1_2_DISABLEB
Reset
Description
1
SWB1_2 Active Low Disable Bit. Writing 0 to this bit forces
SWB1_2 to turn off regardless of status of enable pins (PMICEN,
SLP_Sx). Has priority over SWB1_2_EN.
0: Disabled
1: SWB1_2 operates normally.
R/W
1
SWA1 Active Low Disable Bit. Writing 0 to this bit forces SWA1 to
turn off regardless of status of enable pins (PMICEN, SLP_Sx).
Has priority over SWA1_EN.
0: Disabled
1: SWA1 operates normally.
R/W
TPS650940,
TPS650944, and
TPS650945: 0
TPS650941,
TPS650942 and
TPS650947: 1
VTT_LDO Active Low Disable Bit. Writing 0 to this bit forces
VTT_LDO to turn off regardless of status of enable pins
(PMICEN, SLP_Sx). Has priority over VTT_EN.
0: Disabled
1: VTT_LDO operates normally.
R/W
TPS650940,
TPS650944 and
TPS650945: 1
TPS650941,
TPS650942 and
TPS650947: 0
VTT_LDO Enable bit. VTT_DISABLEB has priority over VTT_EN.
0: VTT_LDO operates normally.
1: Enabled regardless of power sequencing, unless
VTT_DISABLEB = 0
R/W
SWA1_DISABLEB
VTT_DISABLEB
VTT_EN
1
SWB1_2_EN
R/W
0
SWB1_2_Enable bit. SWB1_2_DISABLEB has priority over
SWB1_2_EN.
0: SWB1_2 operates normally.
1: Enabled regardless of power sequencing, unless
SWB1_2_DISABLEB = 0
0
LDOA3_EN
R/W
0
LDOA3 Enable bit.
0: Enabled if LDOLS_EN = 1
1: Enabled regardless of LDOLS_EN state
6.6.26 GPO_CTRL: GPO Control Register (offset = A1h) [reset = 0010 0000]
Figure 6-44. GPO_CTRL Register (offset = A1h) [reset = 0010 0000]
Bit
Bit Name
7
6
5
4
3
2
1
0
RESERVED
RESERVED
GPO_LVL
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TPS65094x
Access
0
0
1
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-37. GPO_CTRL Register Field Descriptions
Bit
5
Field
Type Reset
Description
GPO_LVL
R/W
Open-drain GPO output level bit.
0: The pin is driven to logic low.
1: The pin is high impedance.
1
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
65
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
6.6.27 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = 1100 0000]
Figure 6-45. PWR_FAULT_MASK1 Register (offset = A2h) [reset = 1100 0000]
Bit
Bit Name
TPS65094x
Access
7
6
5
4
3
2
1
0
LDOA2_
FLTMSK
SWA1_
FLTMSK
BUCK6_
FLTMSK
BUCK5_
FLTMSK
BUCK4_
FLTMSK
BUCK3_
FLTMSK
BUCK2_
FLTMSK
BUCK1_
FLTMSK
1
1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-38. PWR_FAULT_MASK1 Register Field Descriptions
Bit
7
6
5
4
66
Field
LDOA2_FLTMSK
SWA1_FLTMSK
BUCK6_FLTMSK
BUCK5_FLTMSK
Type
R/W
R/W
R/W
R/W
Reset
Description
1
LDOA2 Power Fault Mask. When masked, power fault from LDOA2 does not
cause PMIC shutdown.
0: Not masked
1: Masked
1
SWA1 Power Fault Mask. When masked, power fault from SWA1 does not
cause PMIC shutdown.
0: Not masked
1: Masked
0
BUCK6 Power Fault Mask. When masked, power fault from BUCK6 does not
cause PMIC shutdown.
0: Not masked
1: Masked
0
BUCK5 Power Fault Mask. When masked, power fault from BUCK5 does not
cause PMIC shutdown.
0: Not masked
1: Masked
3
BUCK4_FLTMSK
R/W
0
BUCK4 Power Fault Mask. When masked, power fault from BUCK4 does not
cause PMIC shutdown.
0: Not masked
1: Masked
2
BUCK3_FLTMSK
R/W
0
BUCK3 Power Fault Mask. When masked, power fault from BUCK3 does not
cause PMIC shutdown.
0: Not masked
1: Masked
1
BUCK2_FLTMSK
R/W
0
BUCK2 Power Fault Mask. When masked, power fault from BUCK2 does not
cause PMIC shutdown.
0: Not masked
1: Masked
0
BUCK1_FLTMSK
R/W
0
BUCK1 Power Fault Mask. When masked, power fault from BUCK1 does not
cause PMIC shutdown.
0: Not masked
1: Masked
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.6.28 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 0011 0111]
Figure 6-46. PWR_FAULT_MASK2 Register (offset = A3h) [reset = 0011 0111]
Bit
7
Bit Name
RESERVED
6
5
4
3
2
1
0
RESERVED
V5ANA_
FLTMSK
LDOA1_
FLTMSK
VTT_
FLTMSK
SWB1_2_
FLTMSK[1]
SWB1_2_
FLTMSK[0]
LDOA3_
FLTMSK
TPS65094x
0
0
1
1
0
1
1
1
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-39. PWR_FAULT_MASK2 Register Field Descriptions
Bit
5
4
3
2–1
0
Field
V5ANA_FLTMSK
LDOA1_FLTMSK
Type Reset
Description
R/W
1
V5ANA Power Fault Mask. When masked, power fault from V5ANA does not
cause PMIC shutdown.
0: Not masked
1: Masked
1
LDOA1 Power Fault Mask. When masked, power fault from LDOA1 does not
cause PMIC shutdown.
0: Not masked
1: Masked
0
VTT LDO Power Fault Mask. When masked, power fault from VTT LDO does
not cause PMIC shutdown.
0: Not Masked
1: Masked
R/W
VTT_FLTMSK
R/W
SWB1_2_FLTMSK
R/W
11
SWB1_2 Power Fault Mask. When masked, power fault from SWB1_2 does not
cause PMIC shutdown.
00: Not masked
11: Masked
01-10 = RESERVED
LDOA3_FLTMSK
R/W
1
LDOA3 Power Fault Mask. When masked, power fault from LDOA3 does not
cause PMIC shutdown.
0: Not masked
1: Masked
6.6.29 DISCHCNT4: Discharge Control4 Register (offset = ADh) [reset = 0110 0001]
Figure 6-47. DISCHCNT4 Register (offset = ADh) [reset = 0110 0001]
Bit
Bit Name
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
VTT_DIS
RESERVED
RESERVED
RESERVED
RESERVED
TPS65094x
Access
0
1
1
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-40. DISCHNT4 Register Field Descriptions
Bit
4
Field
Type Reset
Description
VTT_DIS
R/W
VTT_LDO discharge resistance
0 = No discharge
1 = 100 Ω
0
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
67
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
6.6.30 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP Dependent]
Figure 6-48. LDOA1CTRL Register (offset = AEh) [reset = OTP Dependent]
Bit
7
Bit Name
6
LDOA1_DIS[1]
TPS650940,
TPS650941,
TPS650942,
TPS650945 and
TPS650947
0
TPS650944
Access
5
4
LDOA1_SDWN_
LDOA1_DIS[0]
LDOA1_VID[3]
CONFIG
1
1
3
2
1
0
LDOA1_VID[2]
LDOA1_VID[1]
LDOA1_VID[0]
LDOA1_EN
1
1
0
0
1
0
1
1
0
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-41. LDOA1CTRL Register Field Descriptions
Bit
Field
7–6
Type
LDOA1_DIS[1:0]
5
LDOA1_VID[3:0]
0
LDOA1_EN
Description
01
LDOA1 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
R/W
1
Control for Disabling LDOA1 during Emergency Shutdown
0: LDOA1 will turn off during Emergency Shutdown.
1: LDOA1 will not turn off during Emergency Shutdown as long as
LDOA1_EN = 1.
R/W
TPS650940,
TPS650941,
TPS650942,
TPS650945
and
TPS650947:
1110 (3.3 V)
TPS650944:
0100 (1.8V)
This field sets the LDOA3 regulator output regulation voltage in normal
mode. Default = OTP Dependent. See Table 6-5 for full details.
R/W
TPS650940,
TPS650941,
TPS650942,
TPS650945
and
TPS650947: 0
TPS650944: 1
LDOA1 Enable Bit.
0: Disable
1: Enable
R/W
LDOA1_SDWN_CONFIG
4–1
Reset
6.6.31 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
Figure 6-49. PG_STATUS1 Register (offset = B0h) [reset = 0000 0000]
Bit
7
LDOA2_
PGOOD
Bit Name
6
5
4
3
2
1
0
RESERVED
BUCK6_
PGOOD
BUCK5_
PGOOD
BUCK4_
PGOOD
BUCK3_
PGOOD
BUCK2
_PGOOD
BUCK1_
PGOOD
TPS65094x
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-42. PG_STATUS1 Register Field Descriptions
Bit
68
Field
Type
Reset
Description
7
LDOA2_PGOOD
R
0
LDOA2 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
5
BUCK6_PGOOD
R
0
BUCK6 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Table 6-42. PG_STATUS1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
BUCK5_PGOOD
R
0
BUCK5 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
3
BUCK4_PGOOD
R
0
BUCK4 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
2
BUCK3_PGOOD
R
0
BUCK3 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
1
BUCK2_PGOOD
R
0
BUCK2 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
0
BUCK1_PGOOD
R
0
BUCK1 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
6.6.32 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
Figure 6-50. PG_STATUS2 Register (offset = B1h) [reset = 0000 0000]
Bit
7
6
5
4
3
LDOA1_
PGOOD
VTT_
PGOOD
2
RESERVED
1
0
RESERVED
LDOA3_
PGOOD
RESERVED
RESERVED
LDO5_
PGOOD
TPS65094x
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Name
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-43. PG_STATUS2 Register Field Descriptions
Bit
Field
Type Reset
Description
5
LDO5_PGOOD
R
0
LDO5 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
4
LDOA1_PGOOD
R
0
LDOA1 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
3
VTT_PGOOD
R
0
VTT LDO Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
0
LDOA3_PGOOD
R
0
LDOA3 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
6.6.32.1 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
Figure 6-51. PWR_FAULT_STATUS1 Register (offset = B2h) [reset = 0000 0000]
Bit
Bit Name
TPS65094x
Access
7
LDOA2_
PWRFLT
6
5
4
3
2
1
0
RESERVED
BUCK6_
PWRFLT
BUCK5_
PWRFLT
BUCK4_
PWRFLT
BUCK3_
PWRFLT
BUCK2_
PWRFLT
BUCK1_
PWRFLT
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
69
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
Table 6-44. PWR_FAULT_STATUS1 Register Field Descriptions
Bit
Field
Type Reset
Description
7
LDOA2_PWRFLT
R
0
This fields indicates that LDOA2 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
5
BUCK6_PWRFLT
R
0
This fields indicates that BUCK6 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
4
BUCK5_PWRFLT
R
0
This fields indicates that BUCK5 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
3
BUCK4_PWRFLT
R
0
This fields indicates that BUCK4 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
2
BUCK3_PWRFLT
R
0
This fields indicates that BUCK3 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
1
BUCK2_PWRFLT
R
0
This fields indicates that BUCK2 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
0
BUCK1_PWRFLT
R
0
This fields indicates that BUCK1 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
6.6.32.2 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
Figure 6-52. PWR_FAULT_STATUS2 Register (offset = B3h) [reset = 0000 0000]
Bit
7
6
5
4
3
VTT_
PWRFLT
2
RESERVED
1
0
RESERVED
LDOA3_
PWRFLT
RESERVED
RESERVED
RESERVED
LDOA1_
PWRFLT
TPS65094x
0
0
0
0
0
0
0
0
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-45. PWR_FAULT_STATUS2 Register Field Descriptions
Bit
70
Field
Type Reset
Description
4
LDOA1_PWRFLT
R/W
0
This fields indicates that LDOA1 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
3
VTT_PWRFLT
R/W
0
This fields indicates that VTT LDO has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
0
LDOA3_PWRFLT
R/W
0
This fields indicates that LDOA3 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
6.6.33 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
Asserted when an internal temperature sensor detects rise of die temperature above the HOT temperature
threshold (THOT). There are five temperature sensors across the die.
Figure 6-53. TEMPHOT Register (offset = B5h) [reset = 0000 0000]
Bit
7
Bit Name
6
5
4
3
2
1
0
VTT_HOT
TOP-RIGHT
_HOT
TOP-LEFT
_HOT
BOTTOMRIGHT_HOT
RESERVED
RESERVED
RESERVED
DIE_HOT
TPS65094x
0
0
0
0
0
0
0
0
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-46. TEMPHOT Register Field Descriptions
Bit
Field
Type Reset
Description
4
DIE_HOT
R/W
0
Temperature of rest of die has exceeded THOT.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
3
VTT_HOT
R/W
0
Temperature of VTT LDO has exceeded THOT.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
2
TOP-RIGHT_HOT
R/W
0
Temperature of die top-right has exceeded THOT. Top-right corner of die from
top view given pin 1 is in top-left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
1
TOP-LEFT_HOT
R/W
0
Temperature of die top-left has exceeded THOT. Top-left corner of die from top
view given pin 1 is in top-left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
0
BOTTOM-RIGHT_HOT
R/W
0
Temperature of die bottom-right has exceeded THOT. Bottom-right corner of die
from top view given pin 1 is in top-left corner.
0: Not asserted.
1: Asserted. The host to write 1 to clear.
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
71
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
7 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1
Application Information
7.2
Typical Application
For a detailed description about application usage, refer to the TPS65094x Design Guide and to the
TPS65094x Schematic Checklist, Layout Checklist, and ILIM Calculator Tool. The TPS65094x can be
used in several different applications from computing, industrial interfacing, and much more. This section
describes the general application information and provides a more detailed description on the TPS65094x
device that powers the Intel Apollo Lake system. The functional block diagram for the device is shown in
Figure 7-1, which outlines the typical external components necessary for proper device functionality.
72
Application and Implementation
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
PMICEN
SLP_S3B
LDOA1
1.35 V to 3.3 V
1.8 V(b)
200 mA
LDOLS_EN(a)
SWA1_EN(b)
BOOT1
DRVH1
BUCK1
Default: 1V
VSET
SLP_S4B
SLP_S0B
VSYS
DRV5V_1_6
EC
LDO5V
DRV5V_2_A1
LDOA1
Optional(a)
Required(b)
EN
EN
Control
Inputs
SW1
Typical
Application
Usage:
0.5 V to 1.45 V
(DVS)
5A
VNN
DRVL1
FBVOUT1
PGNDSNS1
ILIM1
THERMTRIPB
VSYS
V1P8A
BOOT2
DRVH2
CLK
SoC
DATA
I2C CTRL
BUCK2
Default: 0V
SW2
VSET
V1P8A
EN
Control
Outputs
PCH_PWROK
RSMRSTB
PROCHOT
Internal
Interrupt
Events
GPO
INTERRUPT_CNTL
IRQB
VCCGI
DRVL2
Typical
Application
Usage:
0.5 V to 1.45 V
(DVS)
21 A
FBVOUT2
PGNDSNS2
FBGND2
ILIM2
BUCK5V
PVIN3
TEST CTRL
VSET
OTP
EN
REGISTERS
LX3
BUCK3
Default: 1.05 V
3A
VCCRAM
FB3
BUCK5V
PVIN4
VSYS
VSYS
BUCK5V
Digital Core
V5ANA
VSET
EN
BUCK4
Default: 1.8 V
2A
LDO5
V1P8A
LDO5V
LDO3P3
LX4
FB4
REFSYS
nPUC
BUCK5V
PVIN5
VREF
VSET
EN
LX5
BUCK5
Default: 1.24 V
2A
V1P24A
FB5
AGND
VSYS
Thermal
monitoring
BOOT6
Thermal shutdown
DRVH6
VSET
EN
SW6
BUCK6
Default: OTP
Dependent
7A
VDDQ
DRVL6
FBVOUT6
PGNDSNS6
ILIM6
PVINVTT
EN
(a) LDOA1 1RW ³$OZD\V 2Q´
(b) LDOA1 ³$OZD\V 2Q´
V1P8U(1)
SWA1
SWB1_2(2)
V1P8A(1)
0.5 V to 3.3 V(2)
0.5 V to 3.3 V
(1) LPDDR3 and LPDDR4
(2) DDR3L
VTT
VTTFB
LOAD SWB2
400 mA
0.5 V to 3.3 V
Dashed connections optional.
Refer to Pin Attributes for
connection if unused.
VTT
VTT_LDO
½ × VDDQ
ILIM set by OTP
SWB2
SWB1
LOAD SWB1
400 mA
SWA1
PVINSWA1
LOAD SWA1
300 mA
PVINSWB1_B2
LDOA3
0.7 V to 1.5 V
600 mA
EN
EN
EN
VSET
PVINLDOA2_A3
LDOA2
LDOA2
0.7 V to 1.5 V
600 mA
LDOA3
EN
VSET
EN
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. Functional Block Diagram
Application and Implementation
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
73
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
7.2.1
www.ti.com
Design Requirements
The TPS65094x device requires decoupling capacitors on the supply pins. Follow the values for
recommended capacitance on these supplies given in the Specifications section. The controllers,
converter, LDOs, and some other features can be adjusted to meet specific application requirements.
Section 7.2.2, Detailed Design Procedure, describes how to design and adjust the external components to
achieve desired performance.
7.2.2
Detailed Design Procedure
7.2.2.1
Controller Design Procedure
Designing the controller can be divided into the following steps:
1. Design the output filter.
2. Select the FETs.
3. Select the bootstrap capacitor.
4. Select the input capacitors.
5. Set the current limits.
Figure 7-2 shows a diagram of the controller. Controllers BUCK1, BUCK2, and BUCK6 require a 5-V
supply and capacitors at their corresponding DRV5V_x_x pins. For most applications, the DRV5V_x_x
input must come from the LDO5P0 pin to ensure uninterrupted supply voltage; a 2.2-µF, X5R, 20%, 10-V,
or similar capacitor must be used for decoupling.
VSYS
DRVHx
BOOT1
LDO5V
DRV5V_x_x
VOUT
LOUT
SWx
COUT
Controller
DRVLx
Control
from SOC
PGNDSNSx
FBVOUTx
RILIM
ILIMx
(1)
PowerPADTM
Copyright © 2017, Texas Instruments Incorporated
Figure 7-2. Controller Diagram
74
Application and Implementation
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
7.2.2.1.1 Selecting the Output Capacitors
TI recommends using ceramic capacitors with low ESR values to provide the lowest output voltage ripple.
The output capacitor requires either an X7R or an X5R dielectric. Capacitors with Y5V or Z5U dielectrics
display a wide variation in capacitance over temperature and become resistive at high frequencies.
At light load currents, the controller operates in PFM mode, and the output voltage ripple is dependent on
the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize
the voltage ripple in PFM mode. To achieve specified regulation performance and low output voltage
ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of
ceramic capacitors drops with increasing DC bias voltage.
For the output capacitors of the BUCK controllers, TI recommends placing small ceramic capacitors
between the inductor and load with many vias to the PGND plane. This solution typically provides the
smallest and lowest cost solution available for DCAP2 controllers.
To meet the transient specifications, the output capacitance must equal or exceed the minimum
capacitance listed in the electrical characteristics table for BUCK1, BUCK2, and BUCK6 (assuming quality
layout techniques are followed). See Section 5.7, Electrical Characteristics: Buck Controllers.
7.2.2.1.2 Selecting the Inductor
An inductor must be placed between the external FETs and the output capacitors. Together, the inductor
and output capacitors make the double-pole that contributes to stability. In addition, the inductor is
responsible for the output ripple, efficiency, and transient performance. When the inductance increases,
the ripple current decreases, which typically results in an increased efficiency. However, with an increase
in inductance, the transient performance decreases. Finally, the inductor selected must be rated for
appropriate saturation current, core losses, and DC resistance (DCR).
Equation 3 shows the calculation for the recommended inductance for the controller.
VOUT u (VIN VOUT )
L
VIN u fsw u IOUT(MAX) u KIND
where
•
•
•
•
•
VOUT is the typical output voltage.
VIN is the typical input voltage.
fSW is the typical switching frequency.
IOUT(MAX) is the maximum load current.
KIND is the ratio of ILripple to the IOUT(MAX). For this application, TI recommends that KIND is set to a value
from 0.2 to 0.4.
(3)
With the chosen inductance value and the peak current for the inductor in steady state operation, IL(max)
can be calculated using Equation 4. The rated saturation current of the inductor must be higher than the
IL(MAX) current.
(VIN VOUT ) u VOUT
IL(MAX) IOUT(MAX)
2 u VIN u fsw u L
(4)
Following the previous equations, Table 7-1 lists the preferred inductor selected for the controllers..
Table 7-1. Recommended Inductors
MANUFACTURER
PART NUMBER
VALUE
SIZE
HEIGHT
Cyntec
PIMB061H
0.47 µH
6.8 mm × 7.3 mm
1.8 mm
Cyntec
PIMB062D
0.22 µH
6.8 mm × 7.3 mm
2.4 mm
Application and Implementation
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
75
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
7.2.2.1.3 Selecting the FETs
This controller is designed to drive two NMOS FETs. Typically, lower RDSON values are better for
improving the overall efficiency of the controller. However, higher gate-charge thresholds result in lower
efficiency, so the two must be balanced for optimal performance. As the RDSON for the low-side FET
decreases, the minimum current limit increases; therefore, ensure selection of the appropriate values for
the FETs, inductor, output capacitors, and current-limit resistor. TI's CSD87331Q3D, CSD87381P, and
CSD87588N devices are recommended for the controllers, depending on the required maximum current.
7.2.2.1.4 Bootstrap Capacitor
To ensure the internal high-side gate drivers are supplied with a stable low-noise supply voltage, a
capacitor must be connected between the SWx pins and the respective BOOTx pins. TI recommends
placing ceramic capacitors with the value of 0.1 µF for the controllers. During testing, a 0.1-µF, size 0402,
10-V capacitor is used for the controllers.
TI recommends reserving a small resistor in series with the bootstrap capacitor in case the turnon and
turnoff of the FETs must be slowed to reduce voltage ringing on the switch node, which is a common
practice for controller design.
7.2.2.1.5 Selecting the Input Capacitors
Due to the nature of the switching controller with a pulsating input current, a low-ESR input capacitor is
required for best input-voltage filtering and also for minimizing the interference with other circuits caused
by high input-voltage spikes. For the controller, a typical 2.2-µF capacitor can be used for the DRV5V_x_x
pin to handle the transients on the driver. For the FET input, 10 µF of input capacitance (after derating) is
recommended for most applications. To achieve the low-ESR requirement, a ceramic capacitor is
recommended. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be
considered. For better input-voltage filtering, the input capacitor can be increased without any limit.
7.2.2.1.5.1 Setting the Current Limit
The current-limiting resistor value must be chosen based on Equation 1.
NOTE
Use the correct value for the ceramic capacitor capacitance after derating to achieve the
recommended input capacitance.
TI recommends placing a ceramic capacitor as close as possible to the FET across the respective VSYS
and PGND pins of the FETs. The preferred capacitors for the controllers are two Murata
GRM21BR61E226ME44: 22 µF, 0805, 25 V, ±20%, or similar capacitors.
76
Application and Implementation
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
7.2.2.2
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Converter Design Procedure
Designing the converter has only the following two steps:
1. Design the output filter.
2. Select the input capacitors.
The converter must be supplied by a 5-V source. Figure 7-3 shows a diagram of the converter.
VIN_BUCK345_ANA
PVINx
LXx
CIN
LOUT
VOUT
FBx
Converter
PowerPADTM
Control from SOC
Copyright © 2017, Texas Instruments Incorporated
Figure 7-3. Converter Diagram
Application and Implementation
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
77
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
7.2.2.2.1 Selecting the Inductor
An inductor must be placed between the external FETs and the output capacitors. Together, the inductor
and output capacitors form a double-pole in the control loop that contributes to stability. In addition, the
inductor is responsible for the output ripple, efficiency, and transient performance. When the inductance
increases, the ripple current decreases, which typically results in an increase in efficiency. However, with
an increase in inductance, the transient performance decreases. Finally, the inductor selected must be
rated for appropriate saturation current, core losses, and DCR.
NOTE
Internal parameters for the converters are optimized for a 0.47-µH inductor; however, it is
possible to use other inductor values as long as they are chosen carefully and thoroughly
tested.
Equation 5 shows the calculation for the recommended inductance for the converter.
VOUT u (VIN VOUT )
L
VIN u fsw u IOUT(MAX) u KIND
where
•
•
•
•
•
VOUT is the typical output voltage.
VIN is the typical input voltage.
fSW is the typical switching frequency.
IOUT(MAX) is the maximum load current.
KIND is the ratio of ILripple to the IOUT(MAX). For this application, TI recommends that KIND is set to a value
from 0.2 to 0.4.
(5)
With the chosen inductance value and the peak current for the inductor in steady state operation, IL(MAX)
can be calculated using Equation 6. The rated saturation current of the inductor must be higher than the
IL(MAX) current.
(VIN VOUT ) u VOUT
IL(MAX) IOUT(MAX)
2 u VIN u fsw u L
(6)
Following these equations, Table 7-2 lists the preferred inductor selected for the converters.
Table 7-2. Recommended Inductors
MANUFACTURER
PART NUMBER
VALUE
SIZE
HEIGHT
Cyntec
PIFE32251B-R47MS
0.47 µH
3.2 mm × 2.5 mm
1.2 mm
78
Application and Implementation
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
7.2.2.2.2 Selecting the Output Capacitors
TI recommends using ceramic capacitors with low-ESR values are recommended to provide the lowest
output voltage ripple. The output capacitor requires either an X7R or an X5R rating. Y5V and Z5U
capacitors, aside from the wide variation in capacitance overtemperature, become resistive at high
frequencies.
At light load currents, the converter operates in PFM mode and the output voltage ripple is dependent on
the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize
the voltage ripple in PFM mode. To achieve specified regulation performance and low output voltage
ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of
ceramic capacitors drops with increasing DC-bias voltage.
For the output capacitors of the BUCK converters, TI recommends placing small ceramic capacitors
between the inductor and load with many vias to the PGND plane. This solution typically provides the
smallest and lowest-cost solution available for DCAP2 controllers.
To meet the transient specifications, the output capacitance must equal or exceed the minimum
capacitance listed for BUCK3, BUCK4, and BUCK5 (assuming quality layout techniques are followed).
7.2.2.2.3 Selecting the Input Capacitors
Due to the nature of the switching converter with a pulsating input current, a low-ESR input capacitor is
required for best input-voltage filtering and for minimizing the interference with other circuits caused by
high input-voltage spikes. For the PVINx pin, 2.5 µF of input capacitance (after derating) is required for
most applications. A ceramic capacitor is recommended to achieve the low-ESR requirement. However,
the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. For better inputvoltage filtering, the input capacitor can be increased without any limit.
NOTE
Use the correct value for the ceramic capacitor capacitance after derating to achieve the
recommended input capacitance.
The preferred capacitor for the converters is one Samsung CL05A106MP5NUNC: 10 µF, 0402, 10 V,
±20%, or similar capacitor.
7.2.2.3
LDO Design Procedure
The VTT LDO must handle the fast load transients from the DDR memory for termination. Therefore, TI
recommends using ceramic capacitors to maintain a high amount of capacitance with low ESR on the VTT
LDO outputs and inputs. The preferred output capacitors for the VTT LDO are the GRM188R60J226MEA0
from Murata (22 µF, 0603, 6.3 V, ±20%, or similar capacitors). The preferred input capacitor for the VTT
LDO is the CL05A106MP5NUNC from Samsung (10 µF, 0402, 10 V, ±20%, or similar capacitor).
The remaining LDOs must have input and output capacitors chosen based on the values in Section 5.9,
Electrical Characteristics: LDOs.
Application and Implementation
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
79
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
7.2.3
80
www.ti.com
Application Curves
Figure 7-4. BUCK2 Controller Load Transient
Figure 7-5. BUCK3 Converter Load Transient
Figure 7-6. BUCK2 Controller Start-Up
Figure 7-7. BUCK3 Converter Start-Up
Application and Implementation
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
7.3
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
Specific Application for TPS650944
For the TPS650944 device, if register reset is desired when the PMICEN pin is pulled low, an alternate
reset condition can be used. There are two simple options. The first option is to write 1 to the SDWN bit in
the FORCESHUTDN register (see Section 6.6.17, FORCESHUTDN: Force Emergency Shutdown Control
Register) to force power rails to turn off and reset all registers. The second option is to use the falling
edge detection of the THERMTRIPB pin to trigger the device reset. In this case, when the PMICEN pin is
pulled low, the THERMTRIPB pin on PMIC should be pulled low simultaneously, which can be done in
several ways. One approach is to connect a low-voltage Schottky diode between the PMICEN and
THERMTRIPB pins. Because the THERMTRIPB SoC pin is push-pull configured, a second diode is
needed to prevent shorting the SoC pin to GND. An example can be seen in Figure 7-8. Both diodes must
have a forward voltage below PMIC VIL (0.4 V) at the appropriate current. Another approach is to route the
THERMTRIPB signal from SoC through the EC and tie PMICEN and THERMTRIPB together at the PMIC.
EC
PMICEN
LDOA1
10 k
SoC
PMIC
THERMTRIPB
NOTE: Not applicable if LDOA1 is not configured to "Always On"
Figure 7-8. PMICEN and THERMTRIPB Connection Option for LDOA1 "Always On" Spins
For the TPS650944 device, if both the PVINSWA1 and PVINSWB1_B2 pins are tied to 2.5 V, LDOA2 and
LDOA3 will turn on if all VRs and load switches are enabled and have released their Power Good signals.
To avoid LDOA2 and LDOA3 turning on unexpectedly, TI recommends using voltages other than 2.5 V on
both SWA1 and SWB1_2.
Application and Implementation
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
81
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
7.4
www.ti.com
Do's and Don'ts
•
•
•
•
•
Connect the LDO5V output to the DRV5V_x_x inputs for situations where an external 5-V supply is not
initially available or is not available the entire time PMIC is on. If the external 5-V supply is always
present, then DRV5V_x_x can be directly connected to remove the V5ANA-to-LDO5P0 load switch
RDSON.
Ensure that none of the control pins are potentially floating.
Include 0-Ω resistors on the DRVH and BOOT pins of controllers on prototype boards, which allows for
slowing the controllers if the system is unable to handle the noise generated by the large switching or if
switching voltage is too large due to layout.
Do not connect the V5ANA power input to a different source other than PVINx. A mismatch here
causes reference circuits to regulate incorrectly.
Do not supply the V5ANA power input before the VSYS. Reference biasing of the internal FETs may
turn on the HS FET and pass the input to the output until VSYS is biased.
8 Power Supply Recommendations
This device is designed to work with several different input voltages. The minimum voltage on the VSYS
pin is 5.6 V for the device to start up; however, this is a low-power rail. The input to the FETs must be
from 5.4 V to 21 V as long as the proper BOM choices are made. Input to the converters must be
5 V. For the device to output maximum power, the input power must be sufficient. For the controllers, VIN
must be able to supply up to 5 A (typically), though less is acceptable with higher voltages or less usage.
For the converters, PVINx must be able to supply 2 A (typically).
A best practice here is to determine power usage by the system and back-calculate the necessary power
input based on expected efficiency values.
82
Power Supply Recommendations
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
9 Layout
9.1
Layout Guidelines
For a detailed description regarding layout recommendations, refer to the TPS65094x Design Guide and
to the TPS65094x Schematic Checklist, Layout Checklist, and ILIM Calculator Tool. For all switching
power supplies, the layout is an important step in the design, especially at high peak currents and high
switching frequencies. If the layout is not carefully done, the regulator can have stability problems and EMI
issues. Therefore, use wide and short traces for the main current path and for the power ground tracks.
The input capacitors, output capacitors, and inductors must be placed as close as possible to the device.
Use a common-ground node for power ground and use a different, isolated node for control ground to
minimize the effects of ground noise. Connect these ground nodes close to the AGND pin by one or two
vias. Use of the design guide is highly encouraged in addition to the following list of other basic
requirements:
• Do not allow the AGND, PGNDSNSx, or FBGND2 to connect to the thermal pad on the top layer.
• To ensure proper sensing based on FET RDSON, PGNDSNSx must not connect to PGND until very
close to the PGND pin of the FET.
• All inductors, input/output capacitors, and FETs for the converters and controller must be on the same
board layer as the device.
• To achieve the best regulation performance, place feedback connection points near the output
capacitors and minimize the control feedback loop as much as possible.
• Bootstrap capacitors must be placed close to the device.
• The input and output capacitors of the internal reference regulators must be placed close to the device
pins.
• Route DRVHx and SWx as a differential pair. Ensure that there is a PGND path routed in parallel with
DRVLx, which provides optimal driver loops.
9.2
Layout Example
VREF Capacitor
BUCK2
BUCK3
BUCK5
BUCK4
VTT
BUCK6
BUCK1
Figure 9-1. EVM Layout Example With All Components on the Top Layer
Layout
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
83
TPS65094
SWCS133D – SEPTEMBER 2015 – REVISED MAY 2019
www.ti.com
10 Device and Documentation Support
10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES
NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR
SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR
SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.1.2 Development Support
See the following for development support:
TPS65094x Schematic Checklist, Layout Checklist, and ILIM Calculator Tool
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• TPS65094x Design Guide
• TPS65094x Evaluation Module
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
10.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools
and contact information for technical support.
10.5 Trademarks
D-CAP2, D-CAP, E2E are trademarks of Texas Instruments.
Ultrabook, Intel are trademarks of Intel Corporation.
NXP is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
84
Device and Documentation Support
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS650940A0RSKR
ACTIVE
VQFN
RSK
64
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650940A0
PG1.0
TPS650940A0RSKT
ACTIVE
VQFN
RSK
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650940A0
PG1.0
TPS650941A0RSKR
ACTIVE
VQFN
RSK
64
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650941A0
PG1.0
TPS650941A0RSKT
ACTIVE
VQFN
RSK
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650941A0
PG1.0
TPS650942A0RSKR
ACTIVE
VQFN
RSK
64
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650942A0
PG1.0
TPS650942A0RSKT
ACTIVE
VQFN
RSK
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650942A0
PG1.0
TPS650944A0RSKR
ACTIVE
VQFN
RSK
64
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650944A0
PG1.0
TPS650944A0RSKT
ACTIVE
VQFN
RSK
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650944A0
PG1.0
TPS650945A0RSKR
ACTIVE
VQFN
RSK
64
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650945A0
PG1.0
TPS650945A0RSKT
ACTIVE
VQFN
RSK
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650945A0
PG1.0
TPS650947A0RSKR
ACTIVE
VQFN
RSK
64
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650947A0
PG1.0
TPS650947A0RSKT
ACTIVE
VQFN
RSK
64
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T650947A0
PG1.0
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
