Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
TPS6510x Triple Output LCD Supply With Linear Regulator and VCOM Buffer
1 Features
3 Description
•
•
•
•
The TPS6510x series offers a compact and small
power supply solution that provides all three voltages
required by thin film transistor (TFT) LCD displays.
The auxiliary linear regulator controller can be used
to generate a 3.3-V logic power rail for systems
powered by a 5-V supply rail only.
1
•
•
•
•
•
•
•
•
•
•
•
2.7-V to 5.8-V Input Voltage Range
1.6-MHz Fixed Switching Frequency
3 Independent Adjustable Outputs
Boost Converter Output Voltage VO1 of up to 15 V
With < 1% Output Voltage Accuracy
Negative Regulated Charge Pump VO2
Positive Charge Pump VO3
Integrated VCOM Buffer
Virtual Synchronous Converter Technology in
Boost Converter
Auxiliary 3.3-V Linear Regulator Controller
Internal Soft Start
Internal Power-On Sequencing
Fault Detection of all Outputs (TPS65100/05)
No Fault Detection (TPS65101)
Thermal Shutdown
Available in TSSOP-24 and VQFN-24
PowerPAD™ Packages
2 Applications
•
•
•
•
•
•
TFT LCD Displays for Notebooks
TFT LCD Displays for Monitors
Portable DVD Players
Tablet PCs
Car Navigation Systems
Industrial Displays
The main output VO1, is a 1.6-MHz, fixed-frequency
PWM boost converter providing the source drive
voltage for the LCD display. The device is available in
two versions with different internal switch current
limits to allow the use of a smaller external inductor
when lower output power is required. The
TPS65100/01 has a typical switch current limit of 2.3
A, and the TPS65105 has a typical switch current
limit of 1.37 A. A fully integrated adjustable charge
pump doubler/tripler provides the positive LCD gate
drive voltage. An externally adjustable negative
charge pump provides the negative gate drive
voltage. Due to the high 1.6-MHz switching frequency
of the charge pumps, inexpensive and small 220-nF
capacitors can be used.
The TPS6510x series has an integrated VCOM buffer
to power the LCD backplane. For LCD panels
powered by 5 V only, the TPS6510x series has a
linear regulator controller using an external transistor
to provide a regulated 3.3-V output for the digital
circuits. For maximum safety, the TPS65100/05 goes
into shutdown as soon as one of the outputs is out of
regulation. The device can be enabled again by
toggling the input or the enable (EN) pin to GND. The
TPS65101 does not enter shutdown when one of the
outputs is below its power good threshold.
Block Diagram
Device Information(1)
TPS651 0x
VI
2.7 V to 5.8 V
Boo st
Converter
PART NUMBER
VO1
Up to 15 V / 350 mA
Negative
Charge Pu mp
VO2
Down to ±12 V / 20 mA
Positive
Charge Pu mp
VO3
Up to 30 V / 20 mA
Inte grated
VCOM Buffer
VCOM
Line ar Reg ulator
Controller
TPS6510x
PACKAGE
BODY SIZE (NOM)
HTSSOP (24)
7.80 mm × 4.40 mm
VQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VO4
3.3 V
Copyright © 201 6, Texas Instrumen ts Incorpor ate d
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
6
6
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
13
14
16
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Applications ................................................ 17
9.3 System Examples ................................................... 24
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
11.3 Thermal Performance ........................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
29
29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2006) to Revision D
Page
•
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
•
Deleted Ordering Information table, see POA at the end of the datasheet. .......................................................................... 1
2
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
5 Device Options
LINEAR REGULATOR OUTPUT
VOLTAGE
MINIMUM SWITCH CURRENT LIMIT
PACKAGE MARKING
3.3 V
1.6 A
TPS65100
3.3 V
1.6 A
TPS65101
3.3 V
0.96 A
TPS65105
6 Pin Configuration and Functions
PWP Package
24-Pin HTSSOP
(Top View)
8
17
C1-
SUP
9
16
C1+
VCOM
10
15
C2-/MODE
VCOMIN
11
14
C2+
FB3
12
13
OUT3
C1+
PGND
19
DRV
C2-/MODE
ENR
2
17
C2+
EN
3
16
OUT3
FB1
4
15
FB3
FB4
5
14
VCOMIN
BASE
6
13
VCOM
Exposed_Thermal_Die
Not to scale
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
12
18
Thermal PAD
18
SUP
7
C1-
PGND
20
GND
1
11
19
COMP
PGND
6
DRV
SW
21
REF
10
FB2
20
PGND
21
5
GND
4
SW
22
VIN
9
COMP
SW
22
REF
3
23
BASE
8
ENR
SW
EN
23
FB2
24
2
7
1
FB4
VIN
FB1
24
RGE Package
24-Pin VQFN
(Top View)
Not to scale
Submit Documentation Feedback
3
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
Pin Functions
PIN
I/O
DESCRIPTION
NAME
HTSSOP
VQFN
BASE
3
6
O
Base drive output for the external transistor. If Linear Regulator is not needed pull this
pin against VIN.
C1+
16
19
—
Positive terminal of the charge pump flying capacitor
C1-
17
20
—
Negative terminal of the charge pump flying capacitor
C2+
14
17
—
Positive terminal for the charge pump flying capacitor. If the device runs in voltage
doubler mode, this pin should be left open.
C2-/MODE
15
18
—
Negative terminal of the charge pump flying capacitor and charge pump MODE pin. If
the flying capacitor is connected to this pin, the converter operates in a voltage tripler
mode. If the charge pump needs to operate in a voltage doubler mode, the flying
capacitor is removed and the C2-/MODE pin should be connected to GND.
COMP
22
1
—
Compensation pin for the main boost converter. A small capacitor is connected to this
pin.
DRV
18
21
O
External charge pump driver
EN
24
3
I
Enable pin of the device. This pin should be terminated and not be left floating. A logic
high enables the device and a logic low shuts down the device.
ENR
23
2
I
Enable pin of the linear regulator controller. This pin should be terminated and not be
left floating. Logic high enables the regulator and a logic low puts the regulator in
shutdown.
FB1
1
4
I
Feedback pin of the boost converter
FB2
21
24
I
Feedback pin of negative charge pump
FB3
12
15
I
Feedback pin of positive charge pump
FB4
2
5
I
Feedback pin of the linear regulator controller. The linear regulator controller is set to a
fixed output voltage of 3.3 V or 3 V depending on the version.
GND
19
22
—
Ground
OUT3
13
16
O
Positive charge pump output
PGND
7, 8
10, 11
—
Power ground
REF
20
23
O
Internal reference output typically 1.23 V
Supply pin of the positive, negative charge pump, boost converter gate drive circuit,
and VCOM buffer. This pin should be connected to the output of the main boost
converter and cannot be connected to any other voltage source. For performance
reasons, it is not recommended for a bypass capacitor to be connected directly to this
pin.
SUP
9
12
I
SW
5, 6
8, 9
—
Switch pin of the boost converter
VCOM
10
13
O
VCOM buffer output
VCOMIN
11
14
I
Positive input terminal of the VCOM buffer. When the VCOM buffer is not used, this
terminal can be connected to GND to reduce the overall quiescent current of the IC.
VIN
4
7
I
Input voltage pin of the device
PowerPAD™/
Thermal Die
—
—
—
4
Submit Documentation Feedback
The PowerPAD or exposed thermal die needs to be connected to the power ground
pins (PGND)
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
Voltages on pin VIN (2)
Voltages on pin SUP, PG
(2)
MIN
MAX
UNIT
–0.3
6
V
–0.3
15.5
V
Voltage on pin FB1, FB2, FB3, FB4
–0.3
5.5
V
Voltages on pin EN, MODE, ENR (2)
–0.3
VI + 0.3
V
Voltage on VCOMIN
–0.3
14
V
Voltage on pin SW (2)
–0.3
20
V
Voltage on pin DRV
–0.3
15
V
Voltage on pin REF
–0.3
4
V
Voltage on pin BASE
–0.3
5.5
V
Voltage on pin VOUT3
–0.3
30
V
Voltage on pin VCOM
–0.3
15
V
Voltage on pin C1+, C2+
–0.3
30
V
Voltage on pin C1–, C2–
–0.3
15
V
Continuous power dissipation
See Dissipation Ratings
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VI
Input voltage
NOM
2.7
(1)
MAX
5.8
V
L
Inductor
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
4.7
UNIT
µH
See the Detailed Design Procedure for further information.
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
5
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
7.4 Thermal Information
TPS6510x
THERMAL METRIC (1)
PWP (HTSSOP)
RGE (VQFN)
24 PINS
24 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
37.2
33
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
18.9
35.3
°C/W
RθJB
Junction-to-board thermal resistance
16.4
10.7
°C/W
ψJT
Junction-to-top characterization parameter
0.4
0.4
°C/W
ψJB
Junction-to-board characterization parameter
16.2
10.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.1
1.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
VI = 3.3 V, EN = VI, VO1 = 10 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VI
Input voltage range
2.7
5.8
V
0.7
0.9
mA
VO1 = SUP = 10 V, VO3 = 2 × VO1
1.7
2.7
VO1 = SUP = 10 V, VO3 = 3 × VO1
3.9
6
ENR = VCOMIN = GND, VO3 = 2 × VO1
Boost converter not switching
II(VIN)
Quiescent current (VIN)
II(QCharge)
Charge pump quiescent
current (SUP)
II(QVCOM)
VCOM quiescent current
(SUP)
ENR = GND, VO1 = SUP = 10 V
750
1300
µA
II(QEN)
LDO controller quiescent
current (VIN)
ENR = VI, EN = GND
300
800
µA
II(sd)
Shutdown current (VIN)
EN = ENR = GND
1
10
µA
VIT–
Undervoltage lockout
threshold
VI falling
2.2
2.4
V
Thermal shutdown
temperature threshold
TJ rising
160
mA
°C
LOGIC SIGNALS
VIH
High-level input voltage (EN,
ENR)
VIL
Low-level input voltage (EN,
ENR)
IIH , IIL
Input leakage current
1.5
EN = ENR = GND or VI
V
0.01
0.4
V
0.1
µA
15
V
MAIN BOOST CONVERTER VO1
VO1
Output voltage range
5
VO1 – VI
Minimum input to output
voltage difference
1
V(REF)
Reference output voltage
(REF)
1.205
1.213
1.219
V
Vref
Feedback regulation voltage
(FB1)
1.136
1.146
1.154
V
IIB
Feedback input bias current
10
100
nA
rDS(on)
N-MOSFET on-resistance
(Q1)
VO1 = 10 V, I(sw) = 500 mA
195
290
VO1 = 5 V, I(sw) = 500 mA
285
420
ILIM
N-MOSFET switch current
limit (Q1)
TPS65100, TPS65101
1.6
2.3
2.6
A
0.96
1.37
1.56
A
P-MOSFET on-resistance
(Q2)
VO1 = 10 V, I(sw) = 100 mA
9
15
VO1 = 5 V, I(sw) = 100 mA
14
22
rDS(on)
6
Submit Documentation Feedback
TPS65105
V
mΩ
Ω
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
Electrical Characteristics (continued)
VI = 3.3 V, EN = VI, VO1 = 10 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Maximum P-MOSFET peak
switch current
I(SW)(off)
Off-state current (SW)
V(sw) = 15 V
MAX
1
A
µA
1
10
0°C ≤ TA ≤ 85°C
1.295
1.6
2.1
–40°C ≤ TA ≤ 85°C
1.191
1.6
2.1
fOSC
Oscillator frequency
ΔVO(ΔVI)
Line regulation
2.7 V ≤ VI ≤ 5.7 V, Iload = 100 mA
ΔVO(ΔIO)
Load regulation
0 mA ≤ IO ≤ 300 mA
UNIT
MHz
0.012
%/V
0.2
%/A
NEGATIVE CHARGE PUMP VO2
VO2
Output voltage range
V(REF)
Reference output voltage
(REF)
Vref
Feedback regulation voltage
(FB2)
IIB
Feedback input bias current
rDS(on)
–2
Q8 P-Channel switch rDS(ON)
Q9 N-Channel switch rDS(ON)
1.205
1.213
1.219
–36
0
36
mV
10
100
nA
IO = 20 mA
IOM
Maximum output current
ΔVO(ΔVI)
Line regulation
7 V ≤ VO1 ≤ 15 V, IO = 10 mA, VO2 = –5 V
ΔVO(ΔIO)
Load regulation
1 mA ≤ IO ≤ 20 mA, VO2 = –5 V
V
4.3
8
2.9
4.4
V
Ω
20
mA
0.09
%/V
0.126
%/mA
POSITIVE CHARGE PUMP VO3
VO3
Output voltage range
V(REF)
Reference output voltage
1.205
Vref
Feedback regulation voltage
(FB3)
1.187
IIB
Feedback input bias current
Q3 P-Channel switch rDS(on)
1.1
1.8
4.6
8.5
1.2
2.2
610
720
rDS(on)
Q4 N-Channel switch rDS(on)
Q5 P-Channel switch rDS(on)
IO = 20 mA
Q6 N-Channel switch rDS(on)
30
V
1.213
1.219
V
1.214
1.238
V
10
100
nA
9.9
15.5
Ω
Vd
D1 – D4 Shottky diode
forward voltage
IOM
Maximum output current
ΔVO(ΔVI)
Line regulation
10 V ≤ VO1 ≤ 15 V, IO = 10 mA, VO3 = 27 V
0.56
%/V
ΔVO(ΔIO)
Load regulation
1 mA ≤ IO ≤ 20 mA, VO3 = 27 V
0.05
%/mA
I(D1-D4) = 40 mA
mV
20
mA
LINEAR REGULATOR CONTROLLER VO4
VO4
Output voltage range (FB4)
4.5 V ≤ VI ≤ 5.5 V, 10 mA ≤ IO ≤ 500 mA
VI – VO4 – VBE ≥ 0.5 V
(1)
3.2
3.3
13.5
19
20
27
I(BASE)
Maximum base drive current
ΔVO(ΔVI)
Line regulation
4.75 V ≤ VI ≤ 5.5 V, IO = 500 mA
0.186
ΔVO(ΔIO)
Load regulation
1 mA ≤ IO ≤ 500 mA, VI = 5 V
0.064
Start-up current
VO4 ≤ 0.8 V
VI – VO4 – VBE ≥ 0.75 V
(1)
11
20
3.4
V
mA
%/V
%/A
25
mA
VCOM BUFFER
Vcm
Common mode input range
VIo
Input offset voltage (IN)
(1)
IO = 0 mA
2.25
VO1-2
–25
25
V
mV
With VI = supply voltage of the TPS6510x, VO4 = output voltage of the regulator, VBE = basis emitter voltage of external transistor
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
7
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
Electrical Characteristics (continued)
VI = 3.3 V, EN = VI, VO1 = 10 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
ΔVO(ΔIO)
DC Load regulation
IIB
Input bias current (IN)
TEST CONDITIONS
MIN
–30
37
IO = ±50 mA
–45
55
IO = ±100 mA
–72
85
–97
UNIT
mV
110
–300
Peak output current
MAX
IO = ±25 mA
IO = ±150 mA
IOM
TYP
–30
300
nA
VO1 = 15 V
1.2
A
VO1 = 10 V
0.65
A
VO1 = 5 V
0.15
A
FAULT PROTECTION THRESHOLDS
VO1 Rising
–12%
VO1
–8.75%
VO1
–6 VO1
V
VO2)
VO2 Rising
–13 VO2
–9% VO2
–5 VO2
V
VO3)
VO3 Rising
–11 VO3
–8% VO3
–5 VO3
V
V(th,
VO1)
V(th,
V(th,
Shutdown threshold
7.6 Dissipation Ratings
8
PACKAGE
RΘJA
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
24-Pin TSSOP
30.13 C°/W (PWP soldered)
3.3 W
1.83 W
1.32 W
24-Pin VQFN
30 C°/W
3.3 W
1.8 W
1.3 W
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
7.7 Typical Characteristics
350
r
− N−Channel Main Switch − mΩ
DS(on)
1.9
Switching Frequency − MHz
1.8
VI = 2.7 V
1.7
VI = 3.3 V
1.6
VI = 5.8 V
1.5
1.4
1.3
−40
−20
0
20
40
60
80
100
300
Vo1 = 5 V
250
200
Vo1 = 10 V
150
Vo1 = 15 V
100
−40
Figure 1. Switching Frequency vs Free-Air Temperature
0
20
40
60
80
100
Figure 2. rDS(on) N-Channel Main Switch vs Free-Air
Temperature
100
100
90
90
Vo1 = 6 V
80
80
Vo1 = 10 V
70
Efficiency − %
Efficiency − %
−20
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
60
50
Vo1 = 15 V
40
70
Vo1 = 10 V
60
50
Vo1 = 15 V
40
30
30
VI = 3.3 V
Vo2, Vo3 = No Load, Switching
20
10
1
10
100
VI = 5 V
Vo2, Vo3 = No Load, Switching
20
10
1k
1
10
100
1k
IL − Load Current − mA
IL − Load Current − mA
Figure 3. Efficiency vs Load Current
Figure 4. Efficiency vs Load Current
100
ILoad at Vo1 = 100 mA
Vo2, Vo3 = No Load, Switching
Efficiency - %
95
VSW
10 V/div
Vo1 = 6 V
90
Vo1 = 10 V
85
VO
50 mV/div
Vo1 = 15 V
80
75
70
2.5
IL
1 A/div
3
3.5
4
4.5
5
5.5
VI = 3.3 V
VO = 10 V/300 mA
6
VI - Input V oltage - V
Figure 5. Efficiency vs Input Voltage
250 ns/div
Figure 6. PWM Operation Continuous Mode
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
9
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
Typical Characteristics (continued)
VSW
10 V/div
Vo1
200 mV/div
VO
50 mV/div
VI = 3.3 V
VO = 10 V/10 mA
IO
50 mA to 250 mA
IL
500 mA/div
VI = 3.3 V
Vo1 = 10 V, CO= 22 µF
100 µs/div
250 ns/div
Figure 7. PWM Operation at Light Load
Figure 8. Load Transient Response
VI = 3.3 V
Vo1 = 10 V, CO= 2×22 mF
Vo1
100 mV/div
Vo1
5 V/div
Vo2
5 V/div
Vo3
10 V/div
IO
50 mA to 250 mA
VI = 3.3 V
VO = 10 V,
VCOM CI = 1 nF
VCOM
2 V/div
100 µs/div
500 µs/div
Figure 9. Load Transient Response
Figure 10. Power-Up Sequencing
0.20
VI = 3.3 V
VO = 10 V,
IO = 300 mA
Vo2 = −8 V
0.18
TA = −40°C
I O − Output Current − A
0.16
Vo1
5 V/div
II
500
mA/div
0.14
TA = 85°C
0.12
0.10
TA = 25°C
0.08
0.06
0.04
0.02
0
8.8
9.8
500 µs/div
Figure 11. Soft Start VO1
10
Submit Documentation Feedback
10.8
11.8
12.8
13.8
14.8
Vo1 − Output Voltage − V
Figure 12. VO2 Maximum Load Current
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
Typical Characteristics (continued)
0.12
0.14
TA = −40°C
Vo3 = 18 V (Doubler Mode)
0.10
TA = −40°C
I O − Output Current − A
I O − Output Current − A
0.12
TA = 85°C
0.10
TA = 25°C
0.08
0.06
0.04
TA = 25°C
0.08
TA = 85°C
0.06
0.04
0.02
0.02
Vo3 = 28 V (Tripler Mode)
0
9
10
11
12
13
14
15
0
9
10
11
12
13
14
15
Vo1 − Output Voltage − V
Vo1 − Output Voltage − V
Figure 13. VO3 Maximum Load Current
Figure 14. VO3 Maximum Load Current
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
11
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
8 Detailed Description
8.1 Overview
The TPS6510x series consists of a main boost converter operating with a fixed switching frequency of 1.6 MHz
to allow for small external components. The boost converter output voltage VO1 is also the input voltage,
connected through the pin SUP, for the positive and negative charge pumps and the bias supply for the VCOM
buffer. The linear regulator controller is independent from this system with its own enable pin. This allows the
linear regulator controller to continue to operate while the other supply rails are disabled or in shutdown due to a
fault condition on one of their outputs. See Functional Block Diagram for more information.
12
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
8.2 Functional Block Diagram
VIN
SW
SW
Q2
FB1
FB2
Bias Vref = 1.213 V
Thermal Shutdown
Start-Up Sequencing
Undervoltage Detection
Short-Circuit Protection
S
D
Main boost
converter
EN
Current Limit
and
Soft Start
1.6-MHz
Oscillator
FB3
Control Logic
Gate Drive Circuit
SUP
D
COMP
S
Q1
GM Amplifier
Comparator
Sawtooth
Generator
FB1
VFB
1.146 V
SUP
SUP
(VO)
FB3
Positive
Charge Pump
GM Amplifier
Low Gain
D
Q3
S
Current
Control
VFB
1.146 V
Vref
1.214 V
Negative
Charge Pump
SUP
Q8
SUP
C1-
Gain Select
(Doubler or
Tripple Mode)
D
Q4
S
SUP
Soft Start
D
C1+
Current
Control
Soft Start
S
D
Q7
S
DRV
D
Q9
SUP
S
Vo3
D
S
D4
Q5
C2+
FB2
D
Vref
0V
S
D3
Q6
C2-
Reference
Output
REF
D1
D2
Vref
1.213 V
Soft Start
Iref = 20 mA
Short Circuit
Detect
SUP
Vin
Soft Start
D
Q11
S
~1 V
FB4
D
Linear
Regulator
Controller
S
Vref
1.213 V
VCOM
D
Q12
S
Q10
Disable
VCOM
Buffer
ENR
BASE
VCOMIN
GND
PGND
PGND
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
13
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
8.3 Feature Description
8.3.1 Main Boost Converter
The main boost converter operates with PWM and a fixed switching frequency of 1.6 MHz. The converter uses a
unique fast response, voltage mode controller scheme with input voltage feedforward. This achieves excellent
line and load regulation (typical is 0.2% A) and allows the use of small external components. To add higher
flexibility to the selection of external component values the device uses external loop compensation. Although the
boost converter looks like a nonsynchronous boost converter topology operating in discontinuous mode at light
load, the TPS6510x series maintains continuous conduction even at light load currents. This is accomplished
using the Virtual Synchronous Converter Technology for improved load transient response. This architecture
uses an external Schottky diode and an integrated MOSFET in parallel connected between SW and SUP (see
the functional block diagram). The integrated MOSFET Q2 allows the inductor current to become negative at light
load conditions. For this purpose, a small integrated P-channel MOSFET with typical rDS(on) of around10 Ω is
sufficient. When the inductor current is positive, the external Schottky diode with the lower forward voltage
conducts the current. This causes the converter to operate with a fixed frequency in continuous conduction mode
over the entire load current range. This avoids the ringing on the switch pin as seen with a standard
nonsynchronous boost converter and allows a simpler compensation for the boost converter.
8.3.2 VCOM Buffer
VCOMIN is the input of the VCOM buffer. If the VCOM buffer is not required for certain applications, it is possible
to shut down the VCOM buffer by statically connecting VCOMIN to ground, reducing the overall quiescent
current. The VCOM pin can be left open in this case. The VCOM buffer features soft start avoiding a large
voltage drop at VO1 during start-up. During operation the VCOMIN cannot be pulled dynamically to ground.
8.3.3 Enable and Power-On Sequencing
The device has two enable pins. These pins should be terminated and not left floating to prevent unpredictable
operation. Pulling the enable pin (EN) high enables the device and starts the power on sequencing with the main
boost converter VO1 coming up first then the negative and positive charge pump and the VCOM buffer. If the
VCOMIN pin is low, the VCOM buffer remains disabled. The linear regulator has an independent enable pin
(ENR). Pulling this pin low disables the regulator, and pulling this pin high enables this regulator.
If the enable pin EN is pulled high, the device starts its power on sequencing. The main boost converter starts up
first with its soft start. If the output voltage has reached 91.25% of its output voltage, the negative charge pump
comes up next. The negative charge pump starts with a soft start and when the output voltage has reached 91%
of the nominal value, the positive charge pump comes up with a soft start. The VCOM buffer is enabled as soon
as the positive charge pump has reached its nominal value and VCOMIN is greater than typically 1.0 V. Pulling
the enable pin low shuts down the device. Depended on load current and output capacitance, each of the
outputs goes down.
8.3.4 Positive Charge Pump
The TPS6510x series has a fully regulated integrated positive charge pump generating VO3. The input voltage for
the charge pump is applied to the SUP pin that is equal to the output of the main boost converter VO1. The
charge pump is capable of supplying a minimum load current of 20 mA. Depending on the voltage difference
between VO1 and VO3 higher load currents are possible.
8.3.5 Negative Charge Pump
The TPS6510x series has a regulated negative charge pump using two external Schottky diodes. The input
voltage for the charge pump is applied to the SUP pin that is connected to the output of the main boost converter
VO1. The charge pump inverts the main boost converter output voltage and is capable of supplying a minimum
load current of 20 mA. Depending on the voltage difference between VO1 and VO1, higher load currents are
possible. See Figure 12.
14
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
Feature Description (continued)
8.3.6 Linear Regulator Controller
The TPS6510x series includes a linear regulator controller to generate a 3.3-V rail which is useful when the
system is powered from a 5-V supply. The regulator is independent from the other voltage rails of the device and
has its own enable (ENR). Since most of the systems require this voltage rail to come up first it is recommended
to use a R-C delay on EN. This delays the start-up of the main boost converter which will reduce the inrush
current as well. If the linear regulator is not used then it is recommended to pull ENR pin to GND and to pull
BASE and FB4 pin to VIN.
8.3.7 Soft Start
The main boost converter as well as the charge pumps, linear regulator, and VCOM buffer have an internal soft
start. This avoids heavy voltage drops at the input voltage rail or at the output of the main boost converter VO1
during start-up caused by high inrush currents. See Figure 10 and Figure 11. During soft start of the main boost
converter VO1 the internal current limit threshold is increased in three steps. The device starts with the first step
where the current limit is set to 2/5 of the typical current limit (2/5 of 2.3A) for 1024 clock cycles then increased to
3/5 of the current limit for 1024 clock cycles and the 3rd step is the full current limit. The TPS65101 has an
extended soft-start time where each step is 2048 clock cycles.
8.3.8 Fault Protection
All the outputs of the TPS65100 and TPS65105 have short-circuit detection where the device enters shutdown.
The TPS65101, as an exception, does not enter shutdown in case one of the outputs falls below its power good
threshold. The main boost converter has overvoltage and undervoltage protection. If the output voltage VO1 rises
above the overvoltage protection threshold of typically 5% of VO1, then the device stops switching but remains
operational. When the output voltage falls below this threshold again, then the converter continues operation.
When the output voltage falls below power good threshold of typically 8.75% of VO1, in case of a short-circuit
condition, then the TPS65100 and TPS65105 goes into shutdown. Because there is a direct pass from the input
to the output through the diode, the short-circuit condition remains. If this condition needs to be avoided, a fuse
at the input or an output disconnect using a single transistor and resistor is required. The negative and positive
charge pumps have an undervoltage lockout to protect the LCD panel of possible latch-up conditions in case of a
short-circuit condition or faulty operation. When the negative output voltage is typically above 9.5% of its output
voltage (closer to ground), then the device enters shutdown. When the positive charge pump output voltage VO3
is below 8% typical of its output voltage, then the device goes into shutdown as well.
See the fault protection thresholds section in the Electrical Characteristics table. The device can be enabled
again by toggling the enable pin EN below 0.4 V or by cycling the input voltage below the undervoltage threshold
of 2.2 V. The linear regulator reduces the output current to typical 20 mA under a short-circuit condition when the
output voltage is typically < 1 V. See the Functional Block Diagram. The linear regulator does not go into
shutdown under a short-circuit condition.
8.3.9 Thermal Shutdown
A thermal shutdown is implemented to prevent damage due to excessive heat and power dissipation. Typically,
the thermal shutdown threshold is 160°C. If this temperature is reached, the device goes into shutdown. The
device can be enabled by toggling the enable pin to low and back to high or by cycling the input voltage to GND
and back to VI again.
8.3.10 Linear Regulator Controller
The TPS6510x series includes a linear regulator controller to generate a 3.3-V rail when the system is powered
from a 5-V supply. Because an external NPN transistor is required, the input voltage of the TPS6510x series
applied to VI needs to be higher than the output voltage of the regulator. To provide a minimum base drive
current of 13.5 mA, a minimum internal voltage drop of 500 mV from VI to V(BASE) is required.
This can be translated into a minimum input voltage on VI for a certain output voltage as Equation 1 shows:
VI(min)= VO4 + VBE + 0.5 V
(1)
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
15
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
Feature Description (continued)
The base drive current together with the hFE of the external transistor determines the possible output current.
Using a standard NPN transistor like the BCP68 allows an output current of 1 A and using the BCP54 allows a
load current of 337 mA for an input voltage of 5 V. Other transistors can be used as well depending on the
required output current, power dissipation, and PCB space. The device is stable with a 4.7-µF ceramic output
capacitor. Larger output capacitor values can be used to improve the load transient response when higher load
currents are required.
8.4 Device Functional Modes
8.4.1 Enable and Disable
VI ≥ VIT+: When the input voltage is above the undervoltage lockout threshold, the device is turned on and the
power-on sequencing starts.
VI ≤ VIT-: When the input voltage is below the undervoltage lockout threshold, the device turns off and all
functions are disabled.
8.4.2 Fault Mode
8.4.2.1 Overvoltage Protection
VO1 > 105% of VO1 (typical): device stops switching but remains operational. When the output falls below this
threshold, the converter continues operation.
8.4.2.2 Short-Circuit Protection
VO1 < 91.25% of VO1 (typical): device goes into shutdown. Because there is a direct pass from input to output
through the diode, the short-circuit condition remains. A fuse at the input or an output disconnect can avoid this
condition.
VO2 < 91% of VO2 (typical): device goes into shutdown. The device can be enabled by toggling the enable pin
(EN) below 0.4 V or by cycling the input voltage below VIT-.
VO3 < 92% of VO3 (typical): device goes into shutdown. The device can be enabled by toggling the enable pin
(EN) below 0.4 V or by cycling the input voltage below VIT-.
VO4 < 1 V (typical): linear regulator reduces output current to typical 20 mA. It does not go into shutdown.
16
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS6510x series provides all three voltages that are required for (TFT) LCD displays. The auxiliary linear
regulator controller can be used to generate a 3.3-V logic power rail for systems powered by a 5-V supply rail
only. Additionally it has an integrated VCOM buffer to power the LCD backplane.
9.2 Typical Applications
Figure 15 shows a typical application circuit for a display panel power by a 5-V supply rail. It generates up to 350
mA at 15 V to drive the source driver and 20 mA at 30 V and –12 V to drive the gate drivers.
L1
4.7 PH
D1
VI
V O1
2.7 to 5.8 V
Up to 15 V/350 mA
C3
22 PF
TPS651 00
C5
C4
22 PF
R1
C11
10 nF
VO1
VIN
COMP
VCOMIN
R7
1nF
C1
VO2
Up to 12 V/20 mA
0.22 P F
C2
D3
R3
0.22 PF
R2
C2+
C2-/MODE
ENR
C1+
C1-
OUT3
DRV
FB3
FB2
VCOM
REF
FB4
PGND
C12
D2
C6
0.22 PF
0.22 PF
FB1
SUP
EN
R8
SW
SW
Vo3
up to 30 V/20 mA
R5
PGND
BAS E
C7
0.22 PF
GND
R4
R6
C11
0.22 PF
Q1
BCP68
VI
C9
1 PF
VO 4
3.3 V
C10
4.7 PF
VCOM
C8
1 PF
Copyright © 201 6, Texas Instruments Incorpor ate d
Figure 15. Typical Application Circuit
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
17
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
Typical Applications (continued)
9.2.1 Design Requirements
Table 1 shows the design parameters for this example.
Table 1. Design Parameters
PARAMETER
VALUE
VI
Input supply voltage
VO1
Boost converter output voltage and current
3.3 V
VO1(PP)
Boost converter peak-to-peak output voltage ripple
V(SW)
Switch voltage drop
VF
Schottky diode forward voltage drop
VO2
Positive charge pump output voltage and current
VO2(PP)
Positive charge pump peak-to-peak output voltage ripple
VO3
Negative charge pump output voltage and current
VO3(PP)
Negative charge pump peak-to-peak output voltage ripple
10 V at 300 mA
1% = 10 mV
0.5 V
0.8 V
23 V at 20 mA
100 mV
–5 V at 20 mA
100 mV
9.2.2 Detailed Design Procedure
9.2.2.1 Boost Converter Design Procedure
The first step in the design procedure is to calculate the maximum possible output current of the main boost
converter = 10 V.
1. Duty cycle:
VO1 + VF - VI
10 V + 0.8 V - 3.3 V
D=
=
= 0.73
VO1 + VF - VSW 10 V + 0.8 V - 0.5 V
(2)
2. Average inductor current:
I
300 mA
IL = O1 =
= 1.1 A
1 - D 1 - 0.73
3. Inductor peak-to-peak ripple current:
DiL =
(VI - VSW )´ D (3.3 V - 0.5 V )´ 0.73
fosc ´ L
=
1.6 MHz ´ 4.7 mH
(3)
= 271 mA
(4)
4. Peak switch current:
Di
271 mA
I(SW )M = IL + L = 1.1 A +
= 1.24 A
2
2
(5)
The integrated switch, the inductor and the external Schottky diode must be able to handle the peak switch
current. The calculated peak switch current has to be equal or lower than the minimum N-MOSFET switch
current limit (Q1) as specified in the electrical characteristics table (1.6 A for the TPS65100/01 and 0.96 A for the
TPS65105).
If the peak switch current is higher, then the converter cannot support the required load current. This calculation
must be done for the minimum input voltage where the peak switch current is highest. The calculation includes
conduction losses like switch rDS(on) and diode forward drop voltage losses. Additional switching losses, inductor
core and winding losses, etc., require a slightly higher peak switch current in the actual application. The above
calculation still allows an estimate for a good design and component selection.
18
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
9.2.2.1.1 Inductor Selection
Several inductors work with the TPS6510x series. Especially with the external compensation, the performance
can be adjusted to the specific application requirements. The main parameter for inductor selection is the
saturation current of the inductor which should be higher than the peak switch current as calculated above with
additional margin to cover for heavy load transients and extreme start-up conditions. Another method is to
choose the inductor with a saturation current at least as high as the minimum switch current limit of 1.6 A for the
TPS65100/01 and 0.96 A for the TPS65105. The different switch current limits allow selection of a physically
smaller inductor when less output current is required. The second important parameter is inductor DC resistance.
Usually, the lower the DC resistance, the higher the efficiency. However, inductor DC resistance, is not the only
parameter determining the efficiency. Especially for a boost converter where the inductor is the energy storage
element the type and material of the inductor influences the efficiency as well. Especially at the high switching
frequency of 1.6 MHz, inductor core losses, proximity effects, and skin effects become more important. Usually,
an inductor with a larger form factor yields higher efficiency. The efficiency difference between different inductors
can vary between 2% to 10%.
For the TPS6510x series, inductor values between 3.3 μH and 6.8 μH are a good choice but other values can be
used as well. Possible inductors are shown in Table 2.
Table 2. Inductor Selection
DEVICE
INDUCTOR VALUE
TPS65100
TPS65105
COMPONENT SUPPLIER
DIMENSIONS / mm
ISAT / DCR
4.7 μH
Coilcraft DO1813P-472HC
8,89 x 6,1 x 5
2.6 A/54 mΩ
4.2 μH
Sumida CDRH5D28 4R2
5,7 x 5,7 x 3
2.2 A/23 mΩ
4.7 μH
Sumida CDC5D23 4R7
6 x 6 x 2,5
1.6 A/48 mΩ
3.3 μH
Wuerth Elektronik 744042003
4,8 x 4,8 x 2
1.8 A/65 mΩ
4.2 μH
Sumida CDRH6D12 4R2
6,5 x 6,5 x 1,5
1.8 A/60 mΩ
3.3 μH
Sumida CDRH6D12 3R3
6,5 x 6,5 x 1,5
1.9 A/50 mΩ
3.3 μH
Sumida CDPH4D19 3R3
5,1 x 5,1 x 2
1.5 A/26 mΩ
3.3 μH
Coilcraft DO1606T-332
6,5 x 5,2 x 2
1.4 A/120 mΩ
3.3 μH
Sumida CDRH2D18/HP 3R3
3,2 x 3,2 x 2
1.45 A/69 mΩ
4.7 μH
Wuerth Elektronik 744010004
5,5 x 3,5 x 1
1.0 A/260 mΩ
3.3 μH
Coilcraft LPO6610-332M
6,6 x 5,5 x 1
1.3 A/160 mΩ
9.2.2.1.2 Output Capacitor Selection
For the best output voltage filtering, a low ESR output capacitor is recommended. Ceramic capacitors have a low
ESR value, but depending on the application, tantalum capacitors can be used as well. A 22-μF ceramic output
capacitor works for most of the applications. Higher capacitor values can be used to improve the load transient
regulation. See Table 3 for selection of the output capacitor. The output voltage ripple can be calculated as:
I(SW)M ´ L ö
æ 1
I
DVO1 = O1 ´ ç
÷ + I(SW)M ´ ESR
CO è fOSC VO1 + VF - VI ø
where
•
•
•
•
•
•
•
I(SW)M = Peak switch current as calculated in the previous section with I(SW)M
L = Selected inductor value
IO = Normal load current
fosc = Switching frequency
VF = Rectifier diode forward voltage (typical 0.3 V)
CO = Selected output capacitor
ESR = Output capacitor ESR value
(6)
9.2.2.1.3 Input Capacitor Selection
For good input voltage filtering, low ESR ceramic capacitors are recommended. A 22-μF ceramic input capacitor
is sufficient for most of the applications. For better input voltage filtering, this value can be increased. See
Table 3 for input capacitor recommendations.
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
19
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
Table 3. Input and Output Capacitors Selection
CAPACITOR
VOLTAGE RATING
COMPONENT SUPPLIER
COMMENTS
22 μF/1210
16 V
Taiyo Yuden EMK325BY226MM
output capacitor CO
22 μF/1206
6.3 V
Taiyo Yuden JMK316BJ226
input capacitor CI
9.2.2.1.4 Rectifier Diode Selection
A Schottky diode is recommended to achieve good efficiency as the forward voltage drop is lower than of silicon
diodes. The following table shows criteria which should be considered when choosing the rectifier diode:
Table 4. Rectifier Diode Selection Requirements
PARAMETER
VALUE
≥ VO1(M)
Voltage Rating
Higher than maximum output voltage of boost
converter
≥ IO
Higher than the output current
> IL(PP)
Higher than the inductor peak current
Low as possible
For good efficiency
Average Forward Current
Peak Current
Forward voltage drop, reverse
leakage current
Comment
Possible diodes are: On Semiconductor MBRM120L, Microsemi UPS120E, and Fairchild Semiconductor
MBRS130L.
9.2.2.1.5 Converter Loop Design and Stability
The TPS6510x series converter loop can be externally compensated and allows access to the internal
transconductance error amplifier output at the COMP pin. A small feedforward capacitor across the upper
feedback resistor divider speeds up the circuit as well. To test the converter stability and load transient
performance of the converter, a load step from 50 mA to 250 mA is applied, and the output voltage of the
converter is monitored. Applying load steps to the converter output is a good tool to judge the stability of such a
boost converter. Please refer to SLVA381 to understand the relationship between the phase margin in an AC
loop response and the ringing in a load-step
9.2.2.1.6 Design Procedure Quick Steps
1.
2.
3.
4.
Select the feedback resistor divider to set the output voltage.
Select the feedforward capacitor to place a zero at 50 kHz.
Select the compensation capacitor on pin COMP. The smaller the value, the higher the low frequency gain.
Use a 50-kΩ potentiometer in series to Cc and monitor VO1 during load transients. Fine tune the load
transient by adjusting the potentiometer. Select a resistor value that comes closest to the potentiometer
resistor value. This needs to be done at the highest VI and highest load current since the stability is most
critical at these conditions.
9.2.2.1.7 Setting the Output Voltage and Selecting the Feedforward Capacitor
The output voltage is set by the external resistor divider and is calculated as:
æ
R ö
VO1 = Vref ´ ç 1 + 1 ÷
è R2 ø
(7)
Across the upper resistor a bypass capacitor is required to speed up the circuit during load transients as shown
in Figure 16.
20
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
VO1
Up to 10 V/150 mA
D1
C8
6.8 pF
R1
430 kW
C4
22 mF
SW
SW
FB1
SUP
C2
0.22 mF
R2
56 kW
C2+
C2-/MODE
Copyright © 2016, Texas Instruments Incorporated
Figure 16. Feedforward Capacitor
Together with R1 the bypass capacitor C8 sets a zero in the control loop at approximately 50 kHz:
1
fZ =
20 ´ p ´ C8 ´ R1
(8)
A value closest to the calculated value should be used. Larger feedforward capacitor values reduce the load
regulation of the converter and cause DC voltage changes as shown in Figure 17.
Load Step
Figure 17. Load Regulation Caused by a Too Large Feedforward Capacitor Value
9.2.2.2 Negative Charge Pump
The negative charge pump provides a regulated output voltage by inverting the main output voltage VO1. The
negative charge pump output voltage is set with external feedback resistors.
The maximum load current of the negative charge pump depends on the voltage drop across the external
Schottky diodes, the internal on resistance of the charge pump MOSFETS Q8 and Q9, and the impedance of the
flying capacitor C12. When the voltage drop across these components is larger than the voltage difference from
VO1 to VO2, the charge pump is in dropout, providing the maximum possible output current.
Therefore, the higher the voltage difference between VO1 and VO2, the higher the possible load current. See
Figure 12 for the possible output current versus boost converter voltage VO1.
VO2(max) = -(VO1 - 2VF - IO (2 ´ rDS(on)Q8 + 2 ´ rDS(on)Q9) )
(9)
Setting the output voltage:
æR ö
VO2 = -1.213 V ´ ç 3 ÷
è R4 ø
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
21
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
æ VO2 ö
R3 = R4 ´ ç
ç 1.213 V ÷÷
è
ø
The lower feedback resistor value R4 should be in a range between 40 kΩ to 120 kΩ or the overall feedback
resistance should be within 500 kΩ to 1 MΩ. Smaller values load the reference too heavily and larger values may
cause stability problems. The negative charge pump requires two external Schottky diodes. The peak current
rating of the Schottky diode has to be twice the load current of the output. For a 20-mA output current, the dual
Schottky diode BAT54 or similar is a good choice.
9.2.2.3 Positive Charge Pump
The positive charge pump can be operated in a voltage doubler mode or a voltage tripler mode depending on the
configuration of the C2+ and C2-/MODE pins. To operate in a voltage doubler leave the C2+ pin open and
connect C2-/MODE to GND. To operate the charge pump in the voltage tripler mode, a flying capacitor needs to
be connected between C2+ and C2-/MODE.
Positive Charge Pump Output Voltage VO3 (V)
The maximum load current of the positive charge pump depends on the voltage drop across the internal Schottky
diodes, the internal on resistance of the charge pump MOSFETS, and the impedance of the flying capacitor.
When the voltage drop across these components is larger than the voltage difference VO1 x 2 to VO3 (doubler
mode) or VO1 x 3 to VO3 (tripler mode), then the charge pump is in dropout, providing the maximum possible
output current. Therefore, the higher the voltage difference between 2 x VO1 or 3 x VO1 to VO3, the higher the
possible load current. See Figure 13 and Figure 14 for the output current versus boost converter voltage VO1 and
the following calculations. The following graph shows voltage ranges of a doubler and tripler depending of the
boost converter voltage VO1.
45
Doubler Mode
40
Tripler Mode
35
30
25
20
15
10
5
0
6
7
8
9
10
11
12
13
14
Boost Converter Output Voltage VO1 (V)
15
C001
Figure 18. Positive Charge Pump – Output Ranges for IO = 20 mA
Table 5 gives first order formulas to calculate the minimum and maximum output voltages of the positive charge
pump.
Table 5. Voltage Limitation Positive Charge Pump
MODE
EQUATION
Doubler
Tripler
22
Minimum output voltage
VO3(min_d) = VO1
Maximum output voltage
VO3(max_d) = 2 × VO1 – (2 × VF + 2 × IO·(2 × rDS(on)Q5 + rDS(on)Q3 + rDS(on)Q4 ))
Minimum output voltage
VO3(min_t) = VO3(max_d)
Maximum output voltage
VO3(max_t) = 3 × VO1 – (4 × VF + 2 × IO (3 × rDS(on)Q5 + rDS(on)Q3 + rDS(on)Q4 ))
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
The output voltage is set by the external resistor divider and is calculated as:
æ R5 ö
VO3 = 1.214 V ´ ç 1 +
÷
è R6 ø
(10)
æ VO3
ö
R5 = R6 ´ ç
- 1÷
ç 1.214 V
÷
è
ø
(11)
9.2.2.4 VCOM Buffer
The VCOM buffer is typically used to drive the backplane of a TFT panel. The VCOM output voltage is typically
set to half of the main output voltage VO1 plus a small shift to implement the specific compensation voltage. The
TFT video signal gets coupled through the TFT storage capacitor plus the LCD cell capacitance to the output of
the VCOM buffer. Because of these, short current pulses in the positive and negative direction appear at the
output of the VCOM buffer. To minimize the output voltage ripple caused by the current pulses, a
transconductance amplifier having a current source output and an output capacitor is used. The output capacitor
supports the high frequency part of the current pulses drawn from the LCD panel. The VCOM buffer only needs
to handle the low frequency portion of the current pulses. A 1-μF ceramic output capacitor is sufficient for most of
the applications.
The VCOM buffer has an integrated soft start to avoid voltage drops on VO1 during start-up. The soft start is
implemented as such that the VCOMIN is held low until the VCOM buffer is fully biased and the common mode
range is reached. Then the positive input is released and the VCOM buffer output slowly comes up. Usually a 1nF capacitor on VCOMIN to GND is used to filter high frequency noise coupled in from VO1. The size of this
capacitor together with the upper feedback resistor value determines the start-up time. The larger the capacitor
from VCOMIN to GND, the slower the start-up time.
9.2.3 Application Curves
Table 6 lists the application curves.
Table 6. Table of Graphs
FIGURE
MAIN BOOST CONVERTER (VOUT1)
PWM operation at light load
Figure 7
Load transient response, CO = 22 μF
Figure 8
Load transient response, CO = 2 x 22 μF
Figure 9
Power-up sequencing
Figure 10
Soft start VO1
Figure 11
NEGATIVE CHARGE PUMP
IOM
VO2 Maximum load current
vs Output voltage VO1
Figure 12
POSITIVE CHARGE PUMP
IOM
VO3 Maximum load current
vs Output voltage VO1 (doubler mode)
Figure 13
IOM
VO3 Maximum load current
vs Output voltage VO1 (tripler mode)
Figure 14
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
23
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
9.3 System Examples
9.3.1 Notebook Supply
Figure 19 shows a typical application circuit suitable to supply (TFT) LCD displays in notebook applications. The
circuit is designed to operate from a single-cell Li-Ion battery and generates output voltages for the source driver
VO1 of 10 V, for the gate driver VO2 of –5 V and VO3 of 23 V and a VCOM voltage of VO1/2.
L1
3.3 mH
VI
3.3 V
C3
22 mF
R9
15 kW
R7
500 kW
VIN
Vo1
C14
1 nF
R8
500 kW
C1
0.22 mF
C5
0.22 mF
R3
620 kW
SW
VCOMIN
FB1
C12
0.22 mF
D3
ENR
SUP
C1+
C2+
C2-/MODE
C1-
OUT3
DRV
FB3
FB2
VCOM
REF
FB4
PGND
BASE
R1
430 kW
C4
22 mF
SW
COMP
EN
D2
VO2
-5 V/20 mA
C8
6.8 pF
TPS65100
C9
1 nF
VO1
10 V/300 mA
D1
C2
0.22 mF
R2
56 kW
VO3
23 V/20 mA
R5
1M
C6
0.22 mF
PGND
GND
R3
150 kW
R6
56 kW
C11
220 nF
Vcom
5V
C7
1 mF
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Typical Application, Notebook Supply Diagram
24
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
System Examples (continued)
9.3.2 Monitor Supply
Figure 20 shows a typical application circuit suitable to supply (TFT) LCD displays in monitor applications. The
circuit is designed to operate by a 5-V power rail and generates output voltages for the source driver VO1 of 13.5
V, for the gate driver VO2 of –7 V and VO3 of 23 V and a VCOM voltage of VO1/2. Additionally monitor
applications also require a supply voltage for the digital part that is provided from VO4 of 3.3 V.
L1
4.7 mH
CDRH5D18-4R1
Vin
5V
C3
22 mF
VO1
VO1
13.5 V/400 mA
D1
R7
500 kW
C14
1 nF
C9
2.2 nF
VIN
0.22 mF
C1
C12
0.22 mF
SW
VCOMIN
FB1
R3
750 kW
D3
C2+
C1+
C1-
C2-/MODE
VO3
23 V/20 mA
OUT3
DRV
FB3
FB2
VCOM
REF
FB4
PGND
BASE
R2
75 kW
SUP
ENR
D2
C7
0.22 mF
R5
1 MW
PGND
GND
R4
130 kW
C11
220 nF
C4
22 mF
R1
820 kW
SW
COMP
EN
R8
500 kW
VO2
-7 V/20 mA
C6
0.22 mF
C5
3.3 pF
TPS65100
R9
4.3 kW
R6
56 kW
Q1
BCP68
Vin
C12
1 mF
Vcom
7V
VO4
3.3 V/500 mA
C10
4.7 mF
C8
1 mF
Copyright © 2016, Texas Instruments Incorporated
Figure 20. Typical Application, Monitor Supply Diagram
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
25
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
10 Power Supply Recommendations
The TPS6510x devices are designed to operate from an input voltage supply range from 2.7 V to 5.8 V. This
input supply must be well regulated.
11 Layout
11.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high-peak currents
and switching frequencies. If the layout is not carefully designed, the regulator might show stability and EMI
problems. Therefore, the traces carrying high-switching currents should be routed first using wide and short
traces. The input filter capacitor should be placed as close as possible to the input pin VIN of the IC. TI
recommends the following PCB layout guidelines for the TPS6510x devices:
1.
2.
3.
4.
5.
6.
7.
8.
Connect PGND and AGND together on the same ground plane
Connect all capacitor grounds and PGND together on a common ground plane.
Place the input capacitor as close as possible to the input pin of the IC.
Place the rectifier diode as close as possible to the IC
Route first the traces carrying high-switching current with wide and short traces
Isolate analog signal paths from power paths.
If vias are necessary, try to use more than one in parallel to decrease parasitics, especially for power traces.
Solder the thermal pad to the PCB for good thermal performance.
11.2 Layout Example
VOUT4
GND
EN
ENR
VI
GND
FB 1
GND
V OUT4
B AS E
SW
VI
FB 2
SW
SW
REF
GND
P WR GND
P WR GND
V OUT1
VOUT1
EN
E NR
COMP
DRV
C1C1+
V CO MIN
V CO M
C2C2+
FB3
V OUT3
VOUT2
MODE
VCOM
GND
GND
VOUT3
Figure 21. TPS6510x Layout Example
26
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
11.3 Thermal Performance
An influential component of thermal performance of a package is board design. To take full advantage of the
heat dissipation abilities of the PowerPAD or VQFN package with exposed thermal die, a board that acts similar
to a heat sink and allows the use of an exposed (and solderable) deep downset pad should be used. For further
information, see the Texas Instruments application notes PowerPAD Thermally Enhanced Package and
PowerPAD Made Easy. For the VQFN package, see the QFN/SON PCB Attachement application report.
Especially for the VQFN package it is required to solder down the Thermal Pad to achieve the required thermal
resistance.
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
27
TPS65100, TPS65101, TPS65105
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• PowerPAD Thermally Enhanced Package (SLMA002)
• QFN/SON PCB Attachement (SLUA271)
• PowerPAD Made Easy (SLMA004)
• How to Compensate the TPS6510x (SLVA813)
• Simplifying Stability Checks (SLVA381)
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS65100
Click here
Click here
Click here
Click here
Click here
TPS65101
Click here
Click here
Click here
Click here
Click here
TPS65105
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
28
Submit Documentation Feedback
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
TPS65100, TPS65101, TPS65105
www.ti.com
SLVS496D – SEPTEMBER 2003 – REVISED AUGUST 2016
12.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2003–2016, Texas Instruments Incorporated
Product Folder Links: TPS65100 TPS65101 TPS65105
Submit Documentation Feedback
29
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65100PWP
ACTIVE
HTSSOP
PWP
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS65100
TPS65100PWPR
ACTIVE
HTSSOP
PWP
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS65100
TPS65100RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65100
TPS65101PWP
ACTIVE
HTSSOP
PWP
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS65101
TPS65101PWPR
ACTIVE
HTSSOP
PWP
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS65101
TPS65101RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65101
TPS65105PWP
ACTIVE
HTSSOP
PWP
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS65105
TPS65105PWPR
ACTIVE
HTSSOP
PWP
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS65105
TPS65105RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65105
TPS65105RGERG4
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65105
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
