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TPS65133
SLVSC01A – JUNE 2013 – REVISED APRIL 2015
TPS65133 ±5-V, 250-mA Dual-Output Power Supply
1 Features
3 Description
•
•
•
•
•
•
•
The TPS65133 is designed to supply any system
requiring ±5.0-V supply rails. Each output can supply
up to 250 mA of output current. The input supply
voltage range is suitable for use with lithium ion
batteries or from a fixed 3.3-V supply.
1
•
•
•
•
•
2.9-V to 5.0-V Input Voltage Range
Fixed 5.0-V Positive Output Voltage (VPOS)
Fixed –5.0-V Negative Output Voltage (VNEG)
±1% Output Voltage Accuracy
High Efficiency
250-mA Output Current Capability
Independent Converter Operation Allows 100%
Output Current Mismatch
Excellent Line and Load Transient Response
Operates in CCM to Minimize Output Noise
Boost Converter able to Operate with Input Supply
Voltages close to 5.0 V
Short-Circuit Protection
Thermal Shutdown
Efficiency is typically over 90% for most applications
(operating from a lithium ion battery, output currents
in the range 50 mA to 200 mA). The two converters in
the TPS65133 device operate independently,
allowing 100% mismatch between positive and
negative output currents.
Device Information(1)
PART NUMBER
TPS65133
PACKAGE
WSON (12)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
•
•
•
LCD Bias
AMOLED Supplies
Operational Amplifier Supplies
Headphone Amplifier Supplies
Sensor Front-End Supplies
Data Acquisition Supplies
General ±5-V Power Supplies
4 Typical Application
L2
4.7 µH
PVIN
Efficiency
100
SWP
C1
10 µF
90
PGND
VPOS
C2
10 µF
VPOS
5 V, 250 mA
AVIN
C4
100 nF
AGND VNEG
C3
10 µF
ENABLE
EN
GND
GND
GND
VNEG
±5 V, 250 mA
80
Efficiency (%)
VI
2.9 V to 5.0 V
70
60
50
40
30
20
SWN
10
L1
4.7 µH
0
0.00
VI = 3.7 V
0.05
0.10
0.15
Output Current (A)
0.20
0.25
G000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65133
SLVSC01A – JUNE 2013 – REVISED APRIL 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application ................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application .................................................. 11
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
12.5
Device Support ....................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2013) to Revision A
Page
•
Added Device Information table, ESD Ratings table, Switching Characteristics table, Feature Description section,
Device Functional Modes, Application and Implementation section, Power Supply Recommendations section,
Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................. 1
•
Changed Layout Example ................................................................................................................................................... 17
2
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6 Pin Configuration and Functions
DPD Package
12-Pin WSON
(Top View)
SWP
1
12
PVIN
PGND
2
11
AVIN
VPOS
3
10
SWN
GND
4
9
VNEG
AGND
5
8
GND
GND
6
7
EN
Exposed
Thermal
Pad
Pin Functions
PIN
NAME
DESCRIPTION
NO.
AGND
5
Analog ground
AVIN
11
Internal logic supply pin
EN
7
Enable of boost and buck-boost converter
GND
4, 6, 8
SWP
1
Switch pin of the boost converter
PGND
2
Power ground of the boost converter
PVIN
12
Supply pin for the negative buck-boost converter. Place a capacitor close to this pin.
SWN
10
Switch pin of the negative buck-boost converter
VNEG
9
Output of the negative buck-boost converter (VNEG), place a capacitor close to this pin.
VPOS
3
Output of the boost converter (VPOS), place a capacitor close to this pin.
Exposed thermal pad
Ground
Exposed thermal pad. Connect this pad to all GND pins.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
PVIN, AVIN, EN, SWP, VPOS
–0.3
6
V
VNEG
–6.5
0.3
V
SWN
–6.5
5.5
V
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Input voltage
(1)
(2)
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
With respect to GND pin.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions (1)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
3.7
MAX
UNIT
VI
Input voltage
2.9
5
V
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
Refer to the Application Information section for additional information.
7.4 Thermal Information
TPS65133
THERMAL METRIC
(1)
DPD (WSON)
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
51.5
RθJC(top)
Junction-to-case (top) thermal resistance
41.7
RθJB
Junction-to-board thermal resistance
25
ψJT
Junction-to-top characterization parameter
0.5
ψJB
Junction-to-board characterization parameter
25.2
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.4
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
VI = 3.7 V, EN = VI, VPOS = 5.0 V, VNEG = –5.0 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT AND THERMAL PROTECTION
VI
Input voltage
2.9
Shut down supply current
EN = GND
I(IN) = I(AVIN) + I(PVIN) + I(SWP)
Undervoltage lockout threshold
VI falling
Undervoltage lockout threshold
VI rising
0.1
5
V
15
μA
2.1
V
2.5
Thermal shutdown temperature
V
135
°C
LOGIC SIGNALS (EN)
High-level input voltage
1.2
V
Low-level input voltage
0.4
V
5.05
V
BOOST CONVERTER (VPOS)
VPOS
V(SCP)(P)
Output voltage
4.95
5
Low-side MOSFET on-state
resistance
I(SWP) = 200 mA
250
High-side MOSFET on-state
resistance
I(SWP) = –200 mA
350
High-side MOSFET current limit
Inductor valley current
Short-circuit threshold in operation
VPOS falling
Active discharge resistance
EN = GND; I(VPOS) = 1 mA
Line regulation
IPOS = 100 mA
mΩ
0.8
15
Load regulation
1.1
A
4.1
V
30
Ω
60
0.02
%/V
0.24
%/A
BUCK-BOOST CONVERTER (VNEG)
VNEG
V(SCP)(N)
Negative output voltage default
–5.05
–5
High-side MOSFET on-state
resistance
I(SWN) = –200 mA
250
Low-side MOSFET on-state
resistance
I(SWN) = 200 mA
350
Low-side MOSFET current limit
Inductor valley current
–4.95
V
mΩ
1.5
Short-circuit threshold in operation
Active discharge resistance
EN = GND; I(VNEG) = –1 mA
Line regulation
INEG = –100 mA
100
Load regulation
2.2
A
–4.5
V
150
Ω
200
0.01
%/V
0.16
%/A
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.2
1.7
2.2
MHz
BOOST CONVERTER (VPOS)
Switching frequency
IPOS = 200 mA
Short-circuit detection time
The delay from when VPOS < V(SCP)(P) to when
the boost converter turns off
1
3
5
Switching frequency
INEG = –200 mA
1
1.7
2.4
Short-circuit detection time
The delay from when VNEG > V(SCP)(N) to when
the inverting buck-boost converter turns off
1
3
5
Start-up delay
The delay from when VPOS has reached its target
value to when VNEG starts ramping
ms
BUCK-BOOST CONVERTER (VNEG)
MHz
2
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ms
ms
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4.0
0.50
3.5
0.45
3.0
0.40
2.5
0.35
Resistance (Ω)
Current (µA)
7.7 Typical Characteristics
2.0
1.5
1.0
0.5
0.30
0.25
0.20
0.15
0.0
0.10
−0.5
0.05
−1.0
−50
−25
0
25
50
75
Junction Temperature (°C)
100
0.00
−50
125
1.0
0.50
0.9
0.45
0.8
0.40
0.7
0.35
0.6
0.5
0.4
0.3
0.15
0.05
125
0.00
−50
−25
G003
Figure 3. Boost Converter Rectifier rDS(on)
G002
0.20
0.10
100
125
0.25
0.1
0
25
50
75
Junction Temperature (°C)
100
0.30
0.2
−25
0
25
50
75
Junction Temperature (°C)
Figure 2. Boost Converter Switch rDS(on)
Resistance (Ω)
Resistance (Ω)
Figure 1. Shutdown Current into AVIN and PVIN
0.0
−50
−25
G001
0
25
50
75
Junction Temperature (°C)
100
125
G004
Figure 4. Inverting Buck-Boost Converter Switch rDS(on)
0.50
0.45
Resistance (Ω)
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
−50
−25
0
25
50
75
Junction Temperature (°C)
100
125
G005
Figure 5. Inverting Buck-Boost Converter Rectifier rDS(on)
6
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8 Detailed Description
8.1 Overview
The TPS65133 device comprises a boost converter and an inverting buck-boost converter. The boost converter
generates a positive output voltage of 5.0 V and the inverting buck-boost converter generates a negative output
voltage of –5.0 V. Both converters have an output voltage accuracy of ±1%.
8.2 Functional Block Diagram
AVIN
Thermal
Shutdown
Bandgap
Reference
Undervoltage
Lockout
VREF
AGND
Start VPOS
Converter
EN
Power Good
Start Timer
(2 ms)
Start VNEG
Converter
SWP
PGND
VPOS
Current
Limit
Discharge
±
Oscillator
Short-Circuit
Protection
Boost Converter
Control Logic
VREF
+
VREF
+
Inverting Buck-Boost Converter
Control Logic
±
Constant
Off-Time
Control
Current
Limit
Short-Circuit
Protection
Discharge
PVIN
VNEG
GND
GND
GND
SWN
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8.3 Feature Description
8.3.1 Boost Converter (VPOS)
The boost converter uses a current-mode topology with synchronous rectification (see Figure 6). The
synchronous rectifier improves efficiency and provides input-output isolation when the converter is disabled.
When the input supply voltage is close 5.0 V, preventing normal boost operation, the synchronous rectifier is
disabled, allowing the output voltage regulation to be maintained (see Operation with VI ≈ VPOS (Diode Mode)).
SPACER
2.9 V to 5.0 V
10 µF
4.7 µH
SWP
PGND
VPOS
5.0 V, 250 mA
10 µF
Oscillator
Boost Converter
Control Logic
Short-Circuit
Protection
Discharge
±
Current
Limit
VREF
+
Figure 6. VPOS Boost Converter Internal Block Diagram
8.3.1.1 Switching Frequency (VPOS)
The boost converter switching frequency may vary slightly as the operating conditions change, but is typically
around 1.7 MHz for most operating conditions.
8.3.1.2 Output Voltage (VPOS)
The boost converter's output voltage is factory-programmed to 5.0 V ±1.0% and cannot be changed by the user.
8.3.1.3 Startup (VPOS)
The boost converter starts up as soon as EN=HIGH and the input supply voltage is above the UVLO threshold.
The converter features an integrated soft-start function to control the ramp of its output voltage.
8.3.1.4 Shutdown (VPOS)
The boost converter shuts down when EN=LOW or the input supply voltage falls below the UVLO threshold.
8.3.1.5 Active Discharge (VPOS)
The boost converter output is actively discharged to ground when the converter is disabled (see Figure 8). During
startup, active discharge begins as soon as the input supply voltage is above the UVLO threshold. During
shutdown, active discharge persists until the input supply voltage is too low to support its operation (VI ≈ 1.5 V).
8.3.1.6 Short-Circuit Protection (VPOS)
The boost converter is protected against short-circuits on its output. If a short-circuit condition is detected during
start-up, the converter limits its output current until the short-circuit condition is removed. Note that if a boost
converter short-circuit condition is detected during start-up, the inverting buck-boost converter will not start until
the condition is removed (because the sequencing logic requires VPOS to be in regulation before the inverting
buck-boost converter is started).
8
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Feature Description (continued)
During normal operation the boost converter detects a short-circuit on its output if VPOS < 4.1 V for longer than
3 ms. When a short-circuit condition is detected both VPOS and VNEG are disabled and the device shuts down.
Normal operation is resumed by pulling EN low and then high again, or by cycling the input supply voltage.
8.3.2 Inverting Buck-Boost Converter (VNEG)
The inverting buck-boost converter uses a current-mode topology with synchronous rectification (see Figure 7).
SPACER
VREF
+
Inverting Buck-Boost Converter
Control Logic
Current
Limit
2.9 V to 5.0 V
±
Constant
Off-Time
Control
Short-Circuit
Protection
Discharge
PVIN
VNEG
±5.0 V, 250 mA
10 µF
SWN
4.7 µH
Figure 7. VNEG Buck-Boost Converter Internal Block Diagram
8.3.2.1 Switching Frequency (VNEG)
The inverting buck-boost converter's switching frequency varies slightly with operating conditions, but is
approximately 1.7 MHz for most operating conditions.
8.3.2.2 Output Voltage (VNEG)
The inverting buck-boost converter's output voltage is factory-programmed to –5.0 V ±1.0% and cannot be
changed by the user.
8.3.2.3 Startup (VNEG)
The inverting buck-boost converter starts up approximately 2 ms after the boost converter output has reached
5.0 V. The converter's switch current is limited during startup and the output voltage ramps in a controlled
manner.
8.3.2.4 Shutdown
The inverting buck-boost converter shuts down when EN=LOW or the input supply voltage falls below the UVLO
threshold.
8.3.2.5 Active Discharge (VNEG)
The inverting buck-boost converter output is actively discharged to ground when the converter is disabled (see
Figure 8). During startup, active discharge begins as soon as the input supply voltage is above the UVLO
threshold. During shutdown, active discharge persists until the input supply voltage is too low to support its
operation (VI ≈ 1.5 V).
8.3.2.6 Short-Circuit Protection (VNEG)
The inverting buck-boost converter is protected against short-circuits on its output. If a short-circuit condition is
detected during startup, the device converter limits its output current until the short-circuit condition is removed.
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Feature Description (continued)
During normal operation the inverting buck-boost converter detects a short-circuit on its output if VNEG > –4.5 V
for longer than 3 ms. When a short-circuit condition is detected both VPOS and VNEG are disabled and the device
shuts down. Normal operation is resumed by pulling EN low and then high again, or by cycling the input supply
voltage.
8.3.3 Startup and Shutdown Sequencing
Figure 8 illustrates the startup and shutdown sequencing of the TPS65133 device.
SPACER
VI
VUVLO
VUVLO
EN
0.5 ms
0.5 ms
VPOS
2 ms
2 ms
VNEG
0.5 ms
0.5 ms
Output actively discharged.
Figure 8. Startup and Shutdown Sequencing
8.3.4 Thermal Shutdown
The TPS65133 device features a thermal shutdown function to prevent damage because of excessive
temperature. Once a junction temperature of 135°C (typical) is exceeded the device goes into shuts down.
Normal operation is resumed (assuming that the device junction temperature has fallen below the thermal shutdown threshold) by pulling EN low and then high again, or by cycling the input supply voltage.
8.4 Device Functional Modes
8.4.1 Operation with VI < 2.9 V
The recommended minimum input supply voltage is 2.9 V. The device continues to operate with input supply
voltages below 2.9 V, however, full performance is not guaranteed. The device does not operate with input
supply voltages below the UVLO threshold.
8.4.2 Operation with VI ≈ VPOS (Diode Mode)
The TPS65133 device features a "diode" mode that enables it to regulate its positive output even when the input
supply voltage is close to 5.0 V (i.e. too high for normal boost operation). When operating in diode mode the
converter's synchronous rectifier stops switching and instead its body diode is used to rectify the output current.
Boost converter efficiency is reduced in diode mode. At low output currents (≈2 mA and below), the boost
converter automatically transitions from pulse-width modulation to pulse-skip operation. This ensures that the
boost converter's output stays in regulation, but increases the voltage ripple on VPOS.
8.4.3 Operation with EN
When EN=LOW the TPS65133 device is disabled and switching is inhibited. When the input supply voltage is
above the undervoltage lockout threshold and EN=HIGH the device is enabled and its start-up sequence begins.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS65133 device can be used to generate ±5-V supply rails from input supply voltages in the range 2.9 V to
5 V, and has been optimized for use with regulated 3.3-V rails and single-cell Li-Ion batteries. Its output voltages
are fixed at ±5 V and cannot be changed by the user. Both output voltages are controlled by the EN pin: a high
logic level on the EN pin enables both outputs, and a low logic level disables them. Note that when the input
supply voltage is above the UVLO threshold and the EN pin is low, both outputs are disabled and actively
discharged to ground. When the input supply voltage is below the UVLO threshold, both outputs are disabled,
but they are not actively discharged.
9.2 Typical Application
Figure 9 shows a typical application schematic suitable for supplying up to 250 mA at ±5 V from e.g. a single-cell
Li-Ion battery.
L2
4.7 µH
VI
2.9 V to 5.0 V
PVIN
SWP
PGND
VPOS
C1
10 µF
C2
10 µF
VPOS
5 V, 250 mA
AVIN
C4
100 nF
AGND VNEG
C3
10 µF
VNEG
±5 V, 250 mA
EN
ENABLE
GND
GND
GND
SWN
L1
4.7 µH
Figure 9. Typical Application Circuit
9.2.1 Design Requirements
The design parameters for the application circuit in Figure 9 are listed in Table 1.
Table 1. Design Parameters
PARAMETERS
EXAMPLE VALUES
Input voltage range
2.9 V to 5.0 V
Output voltage
±5.0 V
Switching frequency
1.7 MHz
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9.2.2 Detailed Design Procedure
In order to maximize performance, the TPS65133 device has been optimized for use with a relatively narrow
range of external components, and customers are recommended to use the application circuit shown in Figure 9
and the components listed in Table 2 and Table 3.
9.2.2.1 Inductor Selection
The two dc-dc converters in the TPS65133 device have been optimized for use with 4.7 µH inductors, and it is
recommended to use this value in all applications. Customers using different values of inductors should
characterize performance thoroughly before going to mass production.
Table 2. Inductor Selection
PARAMETER
VALUE
L1, L2
4.7 µH
MANUFACTURER
PART NUMBER
Coilmaster
MMPP252012-4R7N
Toko
1239AS-H-4R7M
ABCO
LPP252012-4R7N
Coilcraft
XFL4020-4R7ML
9.2.2.2 Capacitor Selection
The recommended capacitor values are shown in Table 3. Applications using less than the recommended
capacitance (e.g. to save PCB area) may experience increased voltage ripple. In general, the lower the output
power required by the application, the lower the capacitance needed for proper performance. C4 improves
immunity to noise on the input supply voltage, but it is not necessary in many applications.
Table 3. Capacitor Selection
PARAMETER
VALUE
C1, C2, C3
10 µF
C4
100 nF
MANUFACTURER
PART NUMBER
GRM21BR71A106KE51
Murata
GRM21BR71E104KA01
9.2.3 Application Performance Graphs
100
5.05
90
5.04
80
5.03
Output Voltage (V)
Efficiency (%)
The performance shown in the following graphs was obtained using the circuit shown in Figure 9 and the
external components listed in Table 2 and Table 3. (1)
70
60
50
40
30
20
5.01
5.00
4.99
4.98
IO = 50 mA
IO = 100 mA
IO = 250 mA
4.97
VI = 3.3 V
VI = 3.7 V
10
0
0.00
5.02
0.05
0.10
0.15
Output Current (A)
0.20
4.96
0.25
4.95
3.00
3.25
G000
3.50
3.75 4.00 4.25
Input Voltage (V)
4.50
4.75
5.00
G000
VI = 3.7 V
Figure 10. Efficiency vs Output Current
(1)
12
Figure 11. VPOS Line Regulation
The Toko inductor was used to obtain the application graphs.
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−4.97
5.05
−4.98
5.04
−4.99
5.03
Output Voltage (V)
Output Voltage (V)
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−5.00
−5.01
−5.02
−5.03
−5.04
IO = 50 mA
IO = 100 mA
IO = 250 mA
−5.05
−5.06
−5.07
3.00
3.25
3.50
3.75 4.00 4.25
Input Voltage (V)
4.50
4.75
5.02
5.01
5.00
4.99
4.98
4.97
VI = 3.3 V
VI = 3.7 V
4.96
5.00
4.95
0.00
G000
0.05
0.10
0.15
Output Current (A)
0.20
0.25
G000
VI = 3.7 V
Figure 12. VNEG Line Regulation
Figure 13. VPOS Load Regulation
−4.97
−4.98
Output Voltage (V)
−4.99
−5.00
−5.01
−5.02
−5.03
−5.04
−5.05
VI = 3.3 V
VI = 3.7 V
−5.06
−5.07
0.00
0.05
0.10
0.15
Output Current (A)
0.20
0.25
G000
Figure 14. VNEG Load Regulation
VI = 3.7 V, IPOS = INEG = 100 mA
VI = 3.7 V, IPOS = INEG = 0 mA
Figure 15. VPOS and VNEG Startup Behavior (0 mA)
VI = 3.7 V, IPOS = INEG = 0 mA
Figure 16. VPOS and VNEG Startup Behavior (100 mA)
Figure 17. VPOS and VNEG Shutdown Behavior (0 mA)
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VI = 3.7 V, IPOS = INEG = 100 mA
VI = 3.7 V, IPOS = 10 mA
Figure 18. VPOS and VNEG Shutdown Behavior (100 mA)
VI = 3.7 V, IPOS = 100 mA
Figure 19. VPOS Switching Waveforms (10 mA)
VI = 3.7 V, IPOS = 50 mA to 200 mA
Figure 20. VPOS Switching Waveforms (100 mA)
VI = 3.7 V to 4.2 V, IPOS = 50 mA
VI = 3.7 V, INEG = 10 mA
Figure 22. VPOS Line Transient
14
Figure 21. VPOS Load Transient
Figure 23. VNEG Switching Waveforms (10 mA)
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VI = 3.7 V, INEG = 100 mA
VI = 3.7 V, INEG = 50 mA to 200 mA
Figure 24. VNEG Switching Waveforms (100 mA)
Figure 25. VNEG Load Transient
Switching Frequency (MHz)
2.5
2.0
1.5
1.0
0.5
VPOS
VNEG
0.0
2.5
VI = 3.7 V to 4.2 V, INEG = 50 mA
3.0
3.5
4.0
Input Voltage (V)
4.5
5.0
G000
IPOS = INEG = 100 mA
Figure 26. VNEG Line Transient
Figure 27. Switching Frequency
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10 Power Supply Recommendations
The TPS65133 device is designed to operate from an input supply voltage in the range 2.9 V to 5.0 V. If the
input supply is located more than a few centimeters from the device additional bulk capacitance may be required.
The 10-µF shown in the schematics in this data sheet are typical for this function.
16
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11 Layout
11.1 Layout Guidelines
No PCB layout is perfect, and compromises are always necessary. However, the basic principles listed below (in
order of importance) go a long way to achieving the full performance of the TPS65133 device.
• Route discontinuous switching currents on the top layer using short, wide traces. Avoid routing these signals
through vias, which have relatively high parasitic inductance and resistance.
• Place C1 as close as possible to pin 12.
• Place C2 as close as possible to pin 3. Place C3 as close as possible to pin 9.
• Use the exposed thermal pad to connect GND, AGND and PGND.
• Use a copper pour (preferably on layer 2) as a thermal spreader and connect it to the exposed thermal pad
using a number of thermal vias.
Figure 28 illustrates how a PCB layout following the above principles may be realized in practice.
11.2 Layout Example
Connections to VI on inner or bottom layer.
GND
C1
C4
L2
L1
SWP
1
12
PVIN
PGND
2
11
AVIN
VPOS
3
10
SWN
GND
4
9
VNEG
AGND
5
8
GND
GND
6
7
EN
C2
C3
VPOS
VNEG
Thermal vias to conduct heat energy away from the
device as well as providing a good connection to the
ground plane.
Via to signal layer on internal or bottom layer.
Via to copper pour ground plane on internal or bottom layer.
Figure 28. PCB Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided AS IS by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OUTLINE
DPD0012A
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
0.8 MAX
0.08
SEATING PLANE
(0.2) TYP
EXPOSED
THERMAL PAD
0.05
0.00
1.21±0.1
6
7
2X
2.25
2.02±0.1
1
12
10X 0.45
PIN 1 ID
(OPTIONAL)
12X
0.5
0.3
12X
0.25
0.15
0.1
0.05
C A
C
B
4215265/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DPD0012A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.21)
12X (0.6)
SYMM
1
12
12X (0.2)
SYMM
(2.02)
(0.75)
10X (0.45)
7
6
(0.35)
( 0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215265/A 09/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
DPD0012A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.13)
12X (0.6)
1
SYMM
METAL
TYP
12
12X (0.2)
2X
(0.9)
SYMM
(0.55)
10X (0.45)
7
6
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
83% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4215265/A 09/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65133DPDR
ACTIVE
WSON
DPD
12
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SHY
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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