TPS65177ARHAR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 TPS65177/A Fully I2C Programmable 6-CH LCD Bias IC for all Size TV Including Gate Pulse Modulation 1 Features 2 Applications • • • 1 • • • • • • • • • • • • • Enable / Disable – TPS65177: AVI power cycle – TPS65177A: VI power cycle or EN-pin 8.6-V to 14.7-V Input Voltage Range Non-Synchronous Boost Converter (V(AVDD)) – Integrated Isolation Switch – 13.5-V to 19.8-V Output Voltage (I2C) – 15-V Default Output Voltage – 4.25-A Switch Current Limit (I2C) – High Voltage Stress Mode (I2C) Synchronous Buck Converter (V(HAVDD)) – 4.8-V to 11.1-V Output Voltage (I2C) – 7.5-V Default Output Voltage – 1.7-A Switch Current Limit – High Voltage Stress Mode (I2C) Non-Synchronous Buck Converter (V(IO)) – 2.2-V to 3.7-V Output Voltage (I2C) – 2.5-V Default Output Voltage – 3-A Switch Current Limit Synchronous Buck Converter (V(CORE)) – 0.8-V to 3.3-V Output Voltage (I2C) – 1-V Default Output Voltage – 2.5-A Switch Current Limit Positive Charge-Pump Controller (V(GH)) – 20-V to 40-V Output Voltage (I2C) – 28-V Default Output Voltage – Temp. Compensation Offset 0-V to 15-V (I2C) – 4-V Default Offset (28 V to 32 V) Negative Charge-Pump Controller (V(GL)) – –14.5-V to –5.5-V Output Voltage (I2C) – –7.9-V Default Output Voltage Gate Pulse Modulation (GPM) – Down to 0-V, 5-V, 10-V or 15-V (I2C) – 0-V Default Discharge Voltage Temperature Compensation for V(GH) Thermal Shutdown I2C Compatible Interface EEPROM Memory 6-mm × 6-mm × 1-mm 40-Pin VQFN Package GIP (Gate-in-Panel) LCD TVs Non-GIP LCD TVs 3 Description The TPS65177/A provides all supply rails needed by a GIP (Gate-in-Panel) or non-GIP TFT-LCD panel. All output voltages are I2C programmable. V(IO) and V(CORE) for the T-CON, V(AVDD) and V(HAVDD) for the Source Driver and the Gamma Buffer, V(GH) and V(GL) for the Gate Driver or the Level Shifter. For use with non-GIP technology Gate Pulse Modulation (GPM) is implemented, for use with GIP technology the V(GH) rail can be temperature compensated. Furthermore a High Voltage Stress Mode (HVS) for V(AVDD) and V(HAVDD) and an integrated V(AVDD) Isolation Switch is implemented. V(CORE), V(HAVDD), V(GH), V(GL), GPM and the V(GH) temperature compensation can be enabled and disabled by I2C programming. A single BOM (Bill of Materials) can cover several panel types and sizes whose desired output voltage levels can be programmed in production and stored in a non-volatile integrated memory. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS65177 VQFN (40 Pin) 6.00 mm x 6.00 mm TPS65177A VQFN (40 Pin) 6.00 mm x 6.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Block Diagram VI 8.6 V to 14.7 V I2 C compatible Boost Converter Isolation Switch V(AVDD) 13.5 V to 19 V, 2.2 A @ 18 V Buck Converter 1 V(IO) 2.2 V to 3.7 V, 2.7 A @ 3.3 V Buck Converter 2 (Synchronous) V(CORE) 0.8 V to 3.3 V, 2.4 A @ 1.2 V Buck Converter 3 (Synchronous) V(HAVDD) 4.8 V to 11.1 V, 1 A @ 9 V Positive Charge Pump Controller (Temp. Compensated) V(GH) 20 V to 40 V, 200 mA Negative Charge Pump Controller V(GL) ±5.5 V to ±14.5 V, 200 mA Gate Pulse Modulation 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7 1 1 1 2 3 5 Absolute Maximum Ratings ..................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions...................... 6 Thermal Information .................................................. 6 Electrical Characteristics.......................................... 7 I2C Interface Timing Characteristics ....................... 9 I2C Timing Diagram................................................... 9 Typical Characteristics ............................................ 10 Detailed Description ............................................ 12 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 13 14 17 7.5 Gate Pulse Modulation (V(GHM)).............................. 31 7.6 Programming .......................................................... 33 7.7 Register Map........................................................... 42 8 Application and Implementation ........................ 46 8.1 Application Information............................................ 46 8.2 Typical Applications ................................................ 46 8.3 System Examples ................................................... 53 9 Power Supply Recommendations...................... 55 10 Layout................................................................... 56 10.1 Layout Guideline ................................................... 56 10.2 Layout Example .................................................... 56 11 Device and Documentation Support ................. 58 11.1 11.2 11.3 11.4 11.5 11.6 Related Links ........................................................ Third-Party Products Disclaimer ........................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 58 58 58 58 58 58 12 Mechanical, Packaging, and Orderable Information ........................................................... 58 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2016) to Revision C • Page Added TPS65177A device and changed Features description, color of several graphics ................................................... 1 Changes from Revision A (July 2012) to Revision B Page • Added the ESD Ratings table, Features Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendation section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sections. ............................................................ 1 • Added text to the Power-Up section, " If the EN pin is not connected to VIN...".................................................................. 14 Changes from Original (March 2012) to Revision A Page • Changed PR equation ........................................................................................................................................................... 28 • Deleted Inverting Doubler: VGL_max equation ........................................................................................................................ 29 • Deleted Inverting Doubler: VGL_max equation ........................................................................................................................ 29 • Deleted Inverting Doubler: PDIS equation.............................................................................................................................. 30 • Deleted Inverting Doubler: PDIS equation.............................................................................................................................. 30 • Changed PR equation ........................................................................................................................................................... 31 • Changed Figure 46, Figure 47, ........................................................................................................................................... 53 • Changed Figure 48............................................................................................................................................................... 56 2 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 5 Pin Configuration and Functions NC SWBK1 SWBK1 VIO INBK2 CTRL VCORE SWBK2 PGND2 EN RHA Package 40 Pin (VQFN) Top View 40 39 38 37 36 35 34 33 32 31 INBK1 1 30 VHAVDD INBK1 2 29 PGND3 NC 3 28 SWBK3 SDA 4 27 NC SCL 5 26 INBK3 Exposed Thermal PAD 8 23 VGH AGND 9 22 DRV P COMP 10 21 DRV N 12 13 14 15 16 17 18 19 20 VGL 11 NC INV L SWO VGHM SWI 24 SW 7 SW HVS PGND1 RE PGND1 25 NTC 6 VL A0 Pin Functions PIN NAME NO. INBK1 1, 2 TYPE DESCRIPTION — Buck 1 converter (V(IO)) supply pin. This pin is internally connected to INBK3. Place a buffer capacitor close to this pin. Not connected. NC 3 — SDA 4 I/O I2C data pin. SCL 5 I I2C clock pin. A0 6 I I2C address select pin. HVS 7 I Boost and Buck 3 converter High Voltage Stress Mode enable pin. INVL 8 — Internal logic supply pin. Place a buffer capacitor close to this pin. Analog Ground pin. Internal circuitry uses this ground. AGND 9 — COMP 10 I/O Boost converter (V(AVDD)) compensation pin. VL 11 I/O Internal 5 V regulator output pin. Connect a buffer capacitor to this pin. NTC 12 I Thermal Resistor sense pin. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A Submit Documentation Feedback 3 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com Pin Functions (continued) PIN TYPE DESCRIPTION NAME NO. PGND1 13, 14 — Boost converter (V(AVDD)) Power Ground pin. SW 15, 16 O Boost converter (V(AVDD)) switch pin. Avoid long traces to the diode and inductor because this trace carries switching waveforms that generate noise. SWI 17 I Isolation Switch input pin. SWO 18 O Isolation Switch output pin. NC 19 — Not connected. VGL 20 I Negative Charge Pump (V(GL)) voltage sense pin. DRVN 21 O Negative Charge Pump (V(GL)) base drive pin. DRVP 22 I Positive charge pump (V(GH)) base drive pin. VGH 23 I Positive charge pump (V(GH)) output voltage sense and Gate Pulse Modulation supply pin. VGHM 24 I/O RE 25 O Slope adjustment of Gate Pulse Modulation. INBK3 26 — Buck 3 converter (V(HAVDD)) supply pin. This pin is internally connected to INBK1. Place a buffer capacitor close to this pin. NC 27 — Not connected. SWBK3 28 O Buck 3 Converter (V(HAVDD)) switch pin. Avoid long traces to the inductor because this trace carries switching waveforms that generate noise. PGND3 29 — Buck 3 Converter (V(HAVDD)) Power Ground pin. VHAVDD 30 I Buck 3 Converter (V(HAVDD)) voltage sense pin. EN 31 I Enable of Isolation Switch, Boost converter and Buck 3 converter. PGND2 32 — Buck 2 converter (V(CORE)) Power Ground pin. SWBK2 33 O Buck 2 converter (V(CORE)) switch pin. Avoid long traces to the inductor because this trace carries switching waveforms that generate noise. VCORE 34 I Buck 2 converter (V(CORE)) output voltage sense pin. CTRL 35 I Gate Pulse Modulation control pin. INBK2 36 — VIO 37 I Buck 1 converter (V(IO)) output voltage sense pin. 38, 39 O Buck 1 converter (V(IO)) switch pin. Avoid long traces to the diode and inductor because this trace carries switching waveforms that generate noise. 40 — Not connected. Exposed thermal pad — The Exposed thermal pad is connected to AGND. SWBK1 NC 4 Gate Pulse Modulation output pin. Buck 2 converter (V(CORE)) supply pin. Place a buffer capacitor close to this pin. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT MIN MAX –0.3 20 V –2 18 V COMP, EN, A0, SDA, SCL, CTRL, SWBK2, VCORE, INBK2, DRVN, NTC –0.3 7 V VL –0.3 5.5 V DRVP, VGH, VGHM, RE –0.3 40 V VGL –15 0.3 V Operating junction temperature range –40 150 °C Storage temperature range, Tstg –65 150 °C VIO, INBK1, HVS, INVL, INBK3, SWBK3, VHAVDD, SW, SWI, SWO SWBK1 Pin Voltage (1) (2) (2) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. With respect to the GND pin. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±700 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A Submit Documentation Feedback 5 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 6.3 www.ti.com Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TYP MAX VI Supply input voltage range 8.6 12 14.7 UNIT V C(VL) Internal 5 V regulator (VL) buffer capacitance (after DC-Bias derating) 0.1 1 4.7 µF BOOST CONVERTER V(AVDD) Boost output voltage range L Boost inductor (inductor value that can be used) 13.5 4.7 6.8 19.8 V 10 µH CI Input capacitor placed at the inductor (ceramic capacitor value) 4.7 10 C(SWI) Isolation Switch input capacitor (ceramic capacitor value) 4.7 10 100 µF C(SWO) Isolation Switch output capacitor (ceramic capacitor value) 20 40 200 µF 3.7 V 10 µH µF BUCK 1 CONVERTER V(IO) Buck 1 output voltage range 2.2 L Buck 1 inductor (inductor value that can be used) 4.7 6.8 CI Buck 1 input capacitor (ceramic capacitor value) 4.7 10 COUT Buck 1 output capacitor (ceramic capacitor value) 20 30 µF 100 µF BUCK 2 CONVERTER V(CORE) Buck 2 output voltage range 0.8 L Buck 2 inductor (inductor value that can be used) 4.7 6.8 CI Buck 2 input capacitor (ceramic capacitor value) 4.7 10 COUT Buck 2 output capacitor (ceramic capacitor value) 10 20 3.3 V 10 µH µF 50 µF BUCK 3 CONVERTER V(HAVDD) Buck 3 output voltage range 4.8 L Buck 3 inductor (inductor value that can be used) 4.7 6.8 CIN Buck 3 input capacitor (ceramic capacitor value) 4.7 10 COUT Buck 3 output capacitor (ceramic capacitor value) 4.7 10 11.1 V 10 µH µF 50 µF NEGATIVE CHARGE PUMP CONTROLLER V(GL) Controller output voltage range C(FLY) Flying capacitor (ceramic capacitor value) –5.5 –14.5 V 0.1 0.47 4.7 µF R(switch) COUT Resistance to the switch pin 0 2.2 20 Ω Output capacitor (ceramic capacitor value) 1 4.7 50 µF 40 V POSITIVE CHARGE PUMP CONTROLLER V(GH) Controller output voltage range 20 V(GH_offset) Temperature compensation V(GH) positive offset C(FLY) Flying capacitor (ceramic capacitor value) R(switch) COUT 15 V 0.1 0 0.47 4.7 µF Resistance to the switch pin 0 2.2 20 Ω Output capacitor (ceramic capacitor value) 1 4.7 50 µF TEMPERATURE TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C 6.4 Thermal Information RHA (VQFN) THERMAL METRIC (1) 40 PINS UNIT RθJA Junction-to-ambient thermal resistance 32.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 20.3 °C/W RθJB Junction-to-board thermal resistance 7.9 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 7.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.6 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com 6.5 SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 Electrical Characteristics VI = 12 V, EN = 3.3 V, V(AVDD) = 18 V, V(HAVDD) = 9 V, V(IO) = 3.3 V, V(CORE) = 1.2 V, V(GH) = 28 V, V(GL) = –10.3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 14.7 V 8.6 V SUPPLY CURRENT VI VIT+ VIT– Operating input voltage 8.6 Undervoltage lockout threshold (UVLO) Thermal shutdown VI rising 8 8.3 Hysteresis VI falling 0.75 V Junction temperature rising 150 ºC LOGIC SIGNALS VIH High-level input voltage EN, HVS, SDA, SCL, A0, CTRL VIL Low-level input voltage EN, HVS, A0, CTRL 2 V SDA, SCL 1 V 0.9 V 5.1 V INTERNAL REGULATOR V(VL) Internal supply 4.9 5 ISOLATION SWITCH rDS(ON) MOSFET on-resistance I(SWI) = 1 A 100 mΩ BOOST CONVERTER (V(AVDD)) V(AVDD) Switching frequency 600 750 900 kHz Output voltage range 13.5 18 19 V 19.8 V 0 3 V 20.5 22.5 V Output voltage range for max. 500h High Voltage Stress Mode V(AVDD) positive offset Switch overvoltage protection At SW pin, V(AVDD) rising Output voltage tolerance At TJ = 0 ºC to 85 ºC 1% Feedback input bias current rDS(on) MOSFET on-resistance I(SW) = current limit MOSFET current limit At TJ = 0 ºC to 85 ºC MOSFET current limit negative offset 4.25 350 600 µA 100 200 mΩ 5 5.75 A 0 Line Regulation 8.6 V ≤ VI ≤ 14.7 V, IOUT = 500 mA Load Regulation 1 mA ≤ IOUT ≤ 2 A 2.8 A 0.001 %/V 0.08 %/A BUCK1 CONERTER (V(IO)) V(IO) Switching frequency 600 750 900 kHz Output voltage range 2.2 3.3 3.7 V Output voltage tolerance At TJ = 0 ºC to 85ºC I Feedback input bias current rDS(on) MOSFET on-resistance I(SWBK1) = current limit MOSFET current limit At TJ = 0 ºC to 85 ºC Line Regulation 8.6 V ≤ VI ≤ 14.7 V, IOUT = 500 mA Load Regulation 1 mA ≤ IOUT ≤ 2 A 2% 2.8 10 200 µA 200 300 mΩ 3.5 4.2 A 0.002 %/V 0.07 %/A BUCK2 CONVERTER (V(CORE)) V(CORE) Switching frequency 0.5 1 2 Output voltage range 0.8 1.2 3.3 Output voltage tolerance At TJ = 0 ºC to 85 ºC MOSFET on-resistance I(SWBK2) = current limit MOSFET current limit At TJ = 0 ºC to 85 ºC Line Regulation 2.2 V ≤ VI ≤ 3.7 V, IOUT = 500 mA Load Regulation 1 mA ≤ IOUT ≤ 1.5 A Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A V 2% Feedback input bias current rDS(on) MHz 2.5 20 200 µA 175 300 mΩ 3 3.5 A 0.001 %/V 0.2 %/A Submit Documentation Feedback 7 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com Electrical Characteristics (continued) VI = 12 V, EN = 3.3 V, V(AVDD) = 18 V, V(HAVDD) = 9 V, V(IO) = 3.3 V, V(CORE) = 1.2 V, V(GH) = 28 V, V(GL) = –10.3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Switching frequency 0.5 Output voltage range 4.8 1 2 MHz 9 11.1 V 1.5 V BUCK3 CONVERTER (V(HAVDD)) V(HAVDD) Output Voltage Stress Mode V(HAVDD) positive offset Output voltage tolerance 0 At TJ = 0 ºC to 85 ºC 1.5% Feedback input bias current rDS(on) MOSFET on-resistance I(SWBK3) = current limit MOSFET current limit At TJ = 0 ºC to 85 ºC Line Regulation 8.6 V ≤ VI ≤ 14.7 V, IOUT = 500 mA Load Regulation 1 mA ≤ IOUT ≤ 1 A 1.2 90 200 µA 300 500 mΩ 1.5 1.8 A 0.002 %/V 0.05 %/A NEGATIVE CHARGE PUMP CONTROLLER (V(GL)) V(GL) Output voltage range –5.5 Output voltage tolerance 50 Max. DRVN drive current –14.5 V 2.5% Feedback input bias current I(DRVN) –10.3 At TJ = 0 ºC to 85 ºC V(DRVN) = 0.6 V 5 Resistor DRVN to GND 50 100 200 µA 10 mA 200 kΩ Line Regulation 8.6 V ≤ VI ≤ 14.7 V, IOUT = 50 mA 0.015 %/V Load Regulation 1 mA ≤ IOUT ≤ 100 mA 0.002 %/mA POSITIVE CHARGE PUMP CONTROLLER (V(GH)) V(GH) Output voltage range V(GH_offset) Temp. compensation V(GH) positive offset V(GH_offset) = 8 V 20 28 35 V 0 8 15 V 40 V Max. output voltage including V(GH_offset) Output voltage tolerance At TJ = 0 ºC to 85 ºC 2.5% Feedback input bias current I(DRVP) 120 5 200 µA 10 mA Max. DRVP drive current V(DRVP) = 17 V Line Regulation 8.6 V ≤ VI ≤ 14.7 V, IOUT = 50 mA 0.001 %/V Load Regulation 1 mA ≤ IOUT ≤ 100 mA 0.001 %/mA GATE PULSE MODULATION (V(GHM)) Gate Pulse Modulation falling limit V(GHM) = 15 V 5 15 V rDS(ON)M1 VGH to VGHM on-resistance CTRL = 3.3 V, I(VGHM) = 20 mA, V(GH) = 28 V 3 5 Ω rDS(ON)M2 VGHM to RE on-resistance CTRL = GND, I(RE) = 20 mA, V(GHM) = 15 V 3 5 Ω CTRL to VGHM propagation delay CTRL rising 250 360 ns 8 Submit Documentation Feedback 0 150 Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 I2C Interface Timing Characteristics 6.6 (1) PARAMETER fSCL TEST CONDITIONS SCL clock frequency MAX UNIT Standard mode MIN TYP 100 kHz Fast mode 400 kHz 1 MHz Fast mode plus tLOW LOW period of the SCL clock tHIGH HIGH period of the SCL clock tBUF Bus free time between a STOP and START condition thd:STA Hold time for a repeated START condition tsu:STA Setup time for a repeated START condition tsu:STO Setup time for STOP condition thd:DAT Data hold time tsu:DAT Data setup time CB Capacitive load for SDA and SCL tRCL1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit tRCL Rise time of SCL signal tFCL Fall time of SCL signal tRDA Rise time of SDA signal tFDA (1) Fall time of SDA signal Standard mode 4.7 µs Fast mode 1.3 µs Standard mode 4.0 µs Fast mode 600 ns Standard mode 4.7 µs Fast mode 1.3 µs Standard mode 4.0 µs Fast mode 600 ns Standard mode 4.7 µs Fast mode 600 ns Standard mode 4.0 µs Fast mode 600 ns Standard mode 0 3.45 µs Fast mode 0 0.9 µs Standard mode 250 Fast mode 100 ns ns 400 pF Standard mode 20 + 0.1CB 1000 ns Fast mode 20 + 0.1CB 1000 ns Standard mode 20 + 0.1CB 1000 ns Fast mode 20 + 0.1CB 300 ns Standard mode 20 + 0.1CB 300 ns Fast mode 20 + 0.1CB 300 ns Standard mode 20 + 0.1CB 1000 ns Fast mode 20 + 0.1CB 300 ns Standard mode 20 + 0.1CB 300 ns Fast mode 20 + 0.1CB 300 ns Industry standard I2C timing characteristics. Not tested in production. 6.7 I2C Timing Diagram SDA tf tLOW tr tsu;DAT tf tBUF tr thd;STA SCL S thd;STA thd;DAT tsu;STA HIGH tsu;STO Sr Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A P S Submit Documentation Feedback 9 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com 6.8 Typical Characteristics VI = 12 V unless otherwise noted. 0.25 10 9 0.2 8 rDS(on) (:) rDS(on) (:) 7 0.15 0.1 6 5 4 3 0.05 2 1 0 -50 -25 0 25 50 75 Junction Temperature (qC) 100 0 -50 125 -25 0.25 0.2 0.2 0.15 0.15 0.1 0.05 125 D002 0.1 0.05 0 -50 -25 0 25 50 75 Junction Temperature (qC) 100 0 -50 125 -25 0 25 50 75 Junction Temperature (qC) D003 Figure 3. V(IO) Buck 1 Converter NMOS rDS(on) 100 125 D004 Figure 4. V(CORE) Buck 2 Converter NMOS rDS(on) 0.25 0.5 0.2 0.4 0.15 0.3 rDS(on) (:) rDS(on) (:) 100 Figure 2. V(AVDD) Boost Converter PMOS rDS(on) 0.25 rDS(on) (:) rDS(on) (:) Figure 1. V(AVDD) Boost Converter NMOS rDS(on) 0.1 0.05 0.2 0.1 0 -50 -25 0 25 50 75 Junction Temperature (qC) 100 125 Submit Documentation Feedback 0 -50 -25 0 25 50 75 Junction Temperature (qC) D005 Figure 5. V(CORE) Buck 2 Converter PMOS rDS(on) 10 0 25 50 75 Junction Temperature (qC) D001 100 125 D006 Figure 6. V(HAVDD) Buck 3 Converter NMOS rDS(on) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 Typical Characteristics (continued) VI = 12 V unless otherwise noted. 0.5 10 9 0.4 8 IDRVP (mA) rDS(on) (:) 7 0.3 0.2 6 5 4 3 0.1 2 1 0 -50 -25 0 25 50 75 Junction Temperature (qC) 100 125 0 -50 -25 D007 Figure 7. V(HAVDD) Buck 3 Converter PMOS rDS(on) 0 25 50 75 Junction Temperature (qC) 100 125 D008 Figure 8. V(GH) charge-pump DRVP drive current 10 9 8 IDRVP (mA) 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 Junction Temperature (qC) 100 125 D009 Figure 9. V(GL) charge-pump DRVN drive current Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A Submit Documentation Feedback 11 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com 7 Detailed Description 7.1 Overview The TPS65177/A provides all supply rails needed by a GIP (Gate-in-Panel) or non-GIP TFT-LCD panel. All output voltages are I2C programmable. V(IO) and V(CORE) for the T-CON, V(AVDD) and V(HAVDD) for the Source Driver and the Gamma Buffer, V(GH) and V(GL) for the Gate Driver or the Level Shifter. For use with non-GIP technology Gate Pulse Modulation (GPM) is implemented, for use with GIP technology the V(GH) rail can be temperature compensated. Furthermore a High Voltage Stress Mode (HVS) for V(AVDD) and V(HAVDD) and an integrated V(AVDD) Isolation Switch is implemented. V(CORE), V(HAVDD), V(GH), V(GL), GPM and the V(GH) temperature compensation can be enabled and disabled by I2C programming. A single BOM (Bill of Materials) can cover several panel types and sizes whose desired output voltage levels can be programmed in production and stored in a non-volatile integrated memory. 12 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 7.2 Functional Block Diagram INVL VREF Undervoltage Lockout typ. 8.3V Bandgap AGND SW Soft-Star t completed Star t Boost SDA 2.5V I2C Address select N-MOS INBK2 D S N-MOS D S PGND2 DRVP 5mA 100µA CTRL Limit 1V Error VREF VGH VGHM Sh ort Limit voltage 0V, 5V, 10V, 15V RE Short Sh ort Short PGND1 INBK3 S D Buck 3 Control Logic Error SWBK3 D TOFF Control S PGND3 Boost Soft-Star t completed 40% 80% (50ms) GPM Control Logic PGND1 S 6V 1.25V Sh ort Soft-Star t typ. 1.5ms Pos. CP Control Logic D SWO Soft-Star t 3ms 1V clamp VGH_LOW 2V clamp VGH_HIGH SW Soft-Star t 10/20ms Buck 2 Control Logic SWBK2 NTC 750kHz Oscillator Sh ort Error SW D Boost Control Logic VREF VSWO (Boost) VHAVDD Sh ort Error VGL Limit 300µA Neg. CP Control Logic Soft-Star t typ. 1.5ms Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A 100k VREF VCORE S N-MOS Soft-Star t 3ms OVP P-MOS S INBK1 Sh ort 40% 80% (50ms) D SWI Soft-Star t 10ms Error Buck 1 Control Logic Power Good SWBK1 P-MOS 40% 80% (50ms) SWBK1 Sh ort SWO Logic N-MOS Error Star t Buck2 200mA VREF VREF VIO 6V 40% 80% (50ms) HVS 40% 80% (50ms) COMP Soft-Star t completed Power Good Enable Star t pos. Charge Pump GPM Soft-Star t completed VREF I2C Interface SCL Star t neg. Charge Pump Limit Star t Buck 3 and ISO SW A0 Power Good OR 40% 80% (50ms) AND Soft-Star t completed P-MOS Star t Timer 2.5ms EN Star t Buck1 21.5V Thermal Shutdown typ. 150ºC -1V Regulator VL = 5V for logic VL DRVN 5mA INVL Submit Documentation Feedback 13 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com 7.3 Feature Description 7.3.1 Power-Up When VI rises above the UVLO (undervoltage lockout) the device loads the stored values in the non-volatile Initial Value register into the volatile DAC register. When all data is written the power-up sequencing starts with enabling the buck 1 converter (V(IO)), which ramps up its output voltage in 3 ms. When the output is in regulation the buck 2 converter (V(CORE)) starts and ramps up its output voltage in 3 ms, when its output voltage is in regulation the negative charge pump controller starts and V(GL) is declining in typ. 1.5 ms until the output voltage is in regulation. In case V(GL) is driven by the boost switch pin (SW) V(GL) starts declining when the boost starts switching. When the enable pin (EN) is pulled “high” the isolation switch closes smoothly so that after typ. 10 ms its output (V(AVDD)) is at VI level, then the boost converter (V(AVDD)) starts and its output voltage (V(AVDD)) ramps linearly in 10 ms or 20 ms (programmable by I2C) until it is in regulation. Then the positive charge pump controller starts and V(GH) is rising in typ. 1.5 ms until the output voltage is in regulation. To ensure proper sequencing even if EN is pulled “high” already at the beginning (e.g. connected to VI) the start of the boost converter V(AVDD) is blocked until V(GL) is Power Good or 2.5 ms have passed since V(GL) was enabled. If the EN pin is not connected to VI, the device detects a collapsed V(AVDD) voltage about 40 ms after EN is pulled low. This function prevents the panel to restart without a proper power supply reset. The device partially shuts down as described in the Short-Circuit and Overload Protection section. The device is in a latched state and only a power cycle can restart the V(AVDD), V(HAVDD), V(GH) and V(GL) rail. When V(GL) is driven by the boost switch pin (SW) the EN-pin should be connected to VI, otherwise V(GL) detects a short when EN is pulled low as the V(GL) voltage collapses. V(GL) collapses because the supporting switch node (SW) stops switching and the device partially shuts down as described in the Short-Circuit and Overload Protection section. The device is in a latched state and only a power cycle can restart the V(AVDD), V(HAVDD), V(GH) and V(GL) rail. The buck 2 and buck 3 converter as the negative and positive charge pump controller can be disabled by I2C. If disabled they are skipped in the sequencing (e.g. disabled buck 2 → buck 1 is in regulation → start neg. CP). The Gate Pulse Modulation block is disabled when VI is below UVLO or EN is “low” and enabled when V(GH) is in regulation. When the block is disabled by UVLO the high side switch of the Gate Pulse Modulation is turned on and the output VGHM is connected to the VGH pin, when the block is disabled by pulling the EN pin “low” the low side switch is turned on and the output VGHM is connected to the RE pin. 7.3.1.1 TPS65177 If the EN pin is not connected to VI, the device detects a collapsed V(AVDD) voltage about 40 ms after EN is pulled low. This function prevents the panel to restart without a proper power supply reset. The device partially shuts down as described in the Short-Circuit and Overload Protection section. The device is in a latched state and only a power cycle can restart the V(AVDD), V(HAVDD), V(GH) and V(GL) rail. 7.3.1.2 TPS65177A The device can be restarted without a power cycle, however note that when V(GL) is driven by the boost switch pin (SW) the EN-pin should be connected to VI. If the EN-pin is not connected to VI the V(GL) protection detects a short when EN is pulled low as the V(GL) voltage collapses. V(GL) collapses because the supporting switch node (SW) stops switching and the device partially shuts down as described in the Short-Circuit and Overload Protection section. The device is in a latched state and only a power cycle can restart the V(AVDD), V(HAVDD), V(GH) and V(GL) rail. 14 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 Feature Description (continued) VI UVLO UVLO 3ms V(IO) 3ms V(CORE) Using SWBK1 switch node Using SW switch node V(GL) Power-Good ~1.5ms Timer 2.5ms EN V(AVDD) Enable Signal blocked until V(GL) Power-Good or Timer expired 10ms 10ms, 20ms ~1.5ms V(HAVDD) V(GH) CTRL VGHM Figure 10. TPS65177 Power-up Sequencing VI UVLO UVLO 3ms V(IO) 3ms V(CORE) Using SWBK1 switch node Using SW switch node V(GL) Power-Good ~1.5ms Timer 2.5ms EN V(AVDD) Enable Signal blocked until V(GL) Power-Good or Timer expired 10ms 10ms 10ms, 20ms 10ms, 20ms ~1.5ms V(HAVDD) Using SW switch node ~1.5ms Using SW switch node V(GH) CTRL Using SW switch node VGHM Figure 11. TPS65177A Power-up Sequencing Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A Submit Documentation Feedback 15 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com Feature Description (continued) 7.3.2 Power-Down When VI falls below the UVLO threshold all blocks are disabled and the discharge rate is given by the output load and the output capacitors. The Gate Pulse Modulation output V(GHM) follows V(GH). 7.3.3 Thermal Shutdown A thermal shutdown is implemented to prevent damage because of excessive heat and power dissipation. Once a temperature of typically 150 ºC is exceeded the device shuts down and stays off. VI must fall below Undervoltage lockout threshold (UVLO) to reset the thermal shutdown. 7.3.4 Undervoltage Lockout To avoid mis-operation of the device at low input voltages an undervoltage lockout is included, which shuts down the device at voltages lower than typically 8.3 V. 7.3.5 Short-Circuit and Overload Protection 7.3.5.1 Boost Converter (V(AVDD)): When V(SWO) < 40% of its nominal value → Shut down Boost, Isolation Switch, Buck3, neg. and pos. Charge Pump controller (Buck 1 and Buck 2 keep working) → latched condition, only triggering UVLO enables the device again. When V(SWO) < 80% of its nominal value for longer than 50 ms (overload) → Shut down Boost, Isolation Switch, Buck3, neg. and pos. Charge Pump controller (Buck 1 and Buck 2 keep working) → latched condition, only triggering UVLO enables the device again. 7.3.5.2 Buck 1 Converter (V(IO)): When V(IO) < 40% of its nominal value → Shut down the whole device → latched condition, only triggering UVLO enables the device again. When V(IO) < 80% of its nominal value for longer than 50 ms (overload) → Shut down the whole device → latched condition, only triggering UVLO enables the device again. 7.3.5.3 Buck 2 Converter (V(CORE)): When V(CORE) < 40% of its nominal value → Shut down the whole device → latched condition, only triggering UVLO enables the device again. When V(CORE) < 80% of its nominal value for longer than 50 ms (overload) → Shut down the whole device → latched condition, only triggering UVLO enables the device again. 7.3.5.4 Buck 3 Converter (V(HAVDD)): When V(HAVDD) < 40% of its nominal value 16 Submit Documentation Feedback → Shut down Buck3, Isolation Switch, Boost, neg. and pos. Charge Pump controller (Buck 1 and Buck 2 keep working) → latched condition, only triggering UVLO enables the device again. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 Feature Description (continued) When V(HAVDD) < 80% of its nominal value for longer than 50 ms (overload) → Shut down Buck3, Isolation Switch, Boost, neg. and pos. Charge Pump controller (Buck 1 and Buck 2 keep working) → latched condition, only triggering UVLO enables the device again. 7.3.5.5 Positive Charge-Pump Controller (V(GH)): When V(GH) < 40% of its nominal value → Shut down pos. Charge Pump, Isolation Switch, Boost, Buck3, neg. Charge Pump controller (Buck1 and Buck2 keep working) → latched condition, only triggering UVLO enables the device again. When V(GH) < 80% of its nominal value for longer than 50 ms (overload) → Shut down pos. Charge Pump, Isolation Switch, Boost, Buck3, neg. Charge Pump controller (Buck1 and Buck2 keep working) → latched condition, only triggering UVLO enables the device again. 7.3.5.6 Negative Charge-Pump Controller (V(GL)): When V(GL) < 40% of its nominal value → Shut down neg. Charge Pump, Isolation Switch, Boost, Buck3, pos. Charge Pump controller (Buck1 and Buck2 keep working) → latched condition, only triggering UVLO enables the device again. When V(GL) < 80% of its nominal value for longer than 50 ms (overload) → Shut down neg. Charge Pump, Isolation Switch, Boost, Buck3, pos. Charge Pump controller (Buck1 and Buck2 keep working) → latched condition, only triggering UVLO enables the device again. Programmed voltage 80% of Programmed voltage Overload detection 40% of Programmed voltage Short-Circuit detection GND Figure 12. Short-Circuit Levels Overview 7.4 Device Functional Modes 7.4.1 Boost Converter (V(AVDD)) The quasi-synchronous current mode boost converter operates with Pulse Width Modulation (PWM) with a fixed frequency of 750 kHz. For maximum design flexibility and stability with different external components, the converter uses external loop compensation by a simple RC circuit. The converter has an input-to-output switch at the output rail to disconnect its output. 7.4.1.1 Soft-Start The boost converter is enabled by the EN-pin, the startup is done in two steps: 1. Input-to-output isolation switch soft-start The isolation switch is turned on slowly in 10 ms 2. Boost converter soft-start When the isolation switch is fully turned on (after 10 ms) the boost converter starts switching and ramps up Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A Submit Documentation Feedback 17 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com Device Functional Modes (continued) its output voltage V(AVDD) from VI to the programmed voltage value in 10 or 20 ms (programmable by I2C). 7.4.1.2 Compensation The regulator loop can be compensated by adjusting the external RC circuit connected to the COMP pin. The COMP-pin is the output of the transconductance error amplifier. The compensation capacitor adjusts the low frequency gain and the resistor the high frequency gain. Lower output voltages require a higher gain and therefore a smaller compensation capacitor. A good start working for most applications is C(COMP) = 470 pF and R(COMP) = 75 kΩ. In case of a high noise level an additional 22-pF capacitor can be put between the COMP-pin and GND to filter the high frequency noise. The cut-off frequency can be calculated as follows: 1 fZ = 2 ´ p ´ R COMP ´ CCOMP (1) 7.4.1.3 Setting the Output Voltage V(AVDD) The output voltage is programmable by I2C between 13.5 V and 19.8 V in 100 mV steps. 7.4.1.4 High Voltage Stress Mode (HVS) By pulling the HVS-pin “high” an I2C programmable offset voltage is added to the set boost and buck 3 converters output voltage V(AVDD) and V(HAVDD). The offset voltages are programmable independently. 7.4.1.5 Programmable Current Limit The current limit of typ. 5 A can be reduced by I2C programming in 400 mA steps down to 2.2 A to support smaller inductors with lower saturation current. 7.4.1.6 Design Procedure The first step in the design procedure is to verify whether the maximum possible output current of the boost converter supports the specific application requirements. 1. Converter Duty Cycle: D = 1 - VIN ´ h VAVDD VIN ´ D 2. Inductor ripple current: DIL = fs ´ L æ DI L ç 3. Maximum output current: IOUT _ m ax = ç ILIM _ m in - 2 è I DIL 4. Peak switch current: ISWPEAK = OUT + 1 - D 2 SPACER ö ÷ ´ (1 - D) ÷ ø η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.9 as an estimation) ƒs = Switching frequency (typ. 750 kHz) L = Selected inductor value (typ. 6.8 µH) ILIM_min: Minimum current limit ISWPEAK = Peak switch current for the used output current (must be < ILIM_min = 4.25 A) ΔIL = Inductor peak-to-peak ripple current The peak switch current ISWPEAK is the current that the integrated switch, the inductor and the external Schottky diode have to be able to handle. The calculation must be done for the minimum input voltage where the peak switch current is the highest. 18 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 Device Functional Modes (continued) 7.4.1.7 Inductor Selection Inductor value: 4.7 µH ≤ L ≤ 10 µH The higher the inductor value the lower the inductor current ripple and the output voltage ripple but the slower the transient response. Saturation current: ISAT ≥ ISWPEAK or ISAT ≥ ILIM_max The inductor saturation current must be higher than the switch peak current for the max. peak output current or as a more conservative approach higher than the max. switch current limit. DC resistance: The lower the inductors resistance the lower the losses and the higher the efficiency. (1) INDUCTANCE SUPPLIER (1) COMPONENT CODE SIZE (L x W x H mm) DCR Typ. (mΩ) ISAT (A) 6.8 µH Sumida CDRH105R 10.5 x 10.3 x 5.1 14 5.4 6.8 µH Sumida CDRH10D43R 10.8 x 10.5 x 4.5 20 7 10 µH Sumida CDRH10D43R 10.8 x 10.5 x 4.5 26 5.2 6.8 µH Chilisin SCDS105R 10.5 x 10.3 x 5.1 14 5.4 6.8 µH Chilisin SCDS104R 10.5 x 10.3 x 4 21 5 10 µH Chilisin SCDS105R 10.5 x 10.3 x 5.1 22 4.45 See Third-Party Products disclaimer 7.4.1.8 Rectifier Diode Selection 7.4.1.8.1 Diode Type Schottky or Super Barrier Rectifier (SBR) for better efficiency 7.4.1.8.2 Forward Voltage The lower the forward voltage VF the higher the efficiency and the lower the diode temperature. 7.4.1.8.3 Reverse Voltage VR must be higher than the output voltage and should be higher than the OVP voltage 22.5 V 7.4.1.8.4 Thermal Characteristics The diode must be able to handle the dissipated power of: PD = VF x IOUT (2) Table 1. Diodes (1) VR / IAVG VF Typ. at 25°C 30 V / 3 A 0.39 V at 3 A 30 V / 3 A 0.39 V at 3 A 40 V / 3 A 0.38 V at 3 A 40 V / 2 A 0.5 V at 2 A COMPONENT CODE SUPPLIER (1) RθJL SIZE SBR3U30P1 5 °C/W PowerDI® 123 Diodes SSM33LSPT 18 °C/W SMA-S Chenmko SSM34LAS 18 °C/W SMA-S Chenmko SSM24APT 20 °C/W SMA-S Chenmko See Third-Party Products disclaimer 7.4.1.9 Output Capacitor Selection For best output voltage filtering, low ESR ceramic capacitors are recommended. Four 10 µF (or two 22 µF) ceramic capacitors work for most applications. To improve the load transient response more capacitance can be added. Between the rectifier diode and the SWI-pin one 10 µF capacitor is required. To calculate the output voltage ripple the following equations can be used: Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A Submit Documentation Feedback 19 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com I V V DVC_ RIPPLE = AVDD - IN ´ OUT + D VC _ ESR VAVDD ´ fS C OUT (1) DVC _ESR = ISWPEAK ´ R C_ ESR (3) CAPACITOR VOLTAGE RATING TEMPERATURE CHARACTERISTICS SUPPLIER (1) COMPONENT CODE 10 µF / 1206 25 V X5R Murata GRM31CR61E106KA12 10 µF / 1206 25 V X7R Taiyo Yuden TMK316AB7106KL See Third-Party Products disclaimer. 7.4.2 Buck 1 Converter (V(IO)) The non-synchronous current mode buck 1 converter operates with Pulse Width Modulation (PWM) with a fixed frequency of 750 kHz. The converter features integrated soft-start, bootstrap and compensation to minimize external component and pin count. The buck 1 converter operates in Discontinuous Conduction Mode (DCM) or Continuous Conduction Mode (CCM) depending on the load current. For low load currents the converter operates in DCM. In this mode the inductor current reaches 0 A when the switch is turned off. With increasing load current the inductor current finally does not reach 0 A anymore but is always positive and then the converter operates in CCM. The switch node waveforms for DCM and CCM operation are shown in Figure 23 and Figure 24. The ringing during DCM (at light load) is normal for this operating mode, it occurs because of parasitic capacitance in the PCB layout. Because there is very little energy contained in the ringing waveform it does not significantly affect EMI performance. Minimum output current for DCM: MIDCM = VI N - VI O V ´ IO 2 ´ L ´ fS VIN For low load currents when the minimum on time is not sufficient, the buck 1 converter uses a skip mode to be able to regulate its output voltage V(IO). During the skip mode the converter switches for a few cycles to raise the output voltage then it stops switching until the output voltage falls below a given threshold and the converter starts switching again. Due to this behavior the output voltage ripple can be slightly higher during skip mode. 7.4.2.1 Soft-Start The buck 1 converter is enabled with the undervoltage lockout (UVLO). It starts switching and ramps up its output voltage V(IO) linearly in 3 ms to the programmed voltage value. 7.4.2.2 Setting the Output Voltage V(IO) The output voltage is programmable by I2C between 2.2 V and 3.7 V in 100 mV steps. 7.4.2.3 Design Procedure The first step in the design procedure is to verify whether the maximum possible output current of the buck 1 converter supports the specific application requirements. Because the buck 2 converter is supplied by the buck 1 converter and the negative charge pump is driven from the buck 1 converter’s switch node the effective output current I(IO) is higher than the buck 1 output current alone. 1. Converter Duty Cycle: D = VIO VIN ´ η 2. Inductor ripple current: DIL = (VIN - VIO )´ D fS ´ L 3. Maximum output current: IOUT_max = ILIM_min - DIL 2 ΔIL 4. Peak switch current: I SWPEAK = IOUT + 2 5. Effective output current: IBUCK1_EFFECTIVE = IOUT_BUCK1 + IIN_BUCK2 + VIN ´ IGL VIO spacer 20 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.8 as an estimation) ƒs = Switching frequency (typ. 750 kHz) L = Selected inductor value (typ. 6.8 µH) ILIM_min: Minimum current limit (3 A) ISWPEAK = Peak switch current for the used output current (must be < ILIM_min = 3 A) ΔIL = Inductor peak-to-peak ripple current The peak switch current ISWPEAK is the current that the integrated switch, the inductor and the external Schottky diode have to be able to handle. The calculation must be done for the maximum input voltage where the peak switch current is the highest. 7.4.2.4 Inductor Selection Inductor value: 4.7 µH ≤ L ≤ 10 µH The higher the inductor value the lower the inductor current ripple and the output voltage ripple but the slower the transient response. Saturation current: ISAT ≥ ISWPEAK or ISAT ≥ ILIM_max The inductor saturation current must be higher than the switch peak current for the max. peak output current or as a more conservative approach higher than the max. switch current limit. DC resistance: The lower the inductors resistance the lower the losses and the higher the efficiency. (1) INDUCTANCE SUPPLIER (1) COMPONENT CODE SIZE (L x W x H mm) DCR Typ. (mΩ) ISAT (A) 6.8 µH Sumida CDRH8D43 8.3 x 8.3 x 4.5 20 4.4 10 µH Sumida CDRH8D43 8.3 x 8.3 x 4.5 29 4 6.8 µH Chilisin SCPS0740T 7.5 x 7.8 x 4 28 3.9 See Third-Party Products disclaimer 7.4.2.5 Rectifier Diode Selection 7.4.2.5.1 Diode Type Schottky or Super Barrier Rectifier (SBR) for better efficiency 7.4.2.5.2 Forward Voltage The lower the forward voltage VF the higher the efficiency and the lower the diode temperature. 7.4.2.5.3 Reverse Voltage VR must be higher than the output voltage 7.4.2.5.4 Forward Current The average rectified forward current IAVG must be higher than IOUT × (1 – D) 7.4.2.5.5 Thermal Characteristics The diode must be able to handle the dissipated power of: PD = VF x IOUT × (1 – D) (4) Table 2. Diodes (1) VR / IAVG VF typ. at 25°C COMPONENT CODE RθJL SIZE SUPPLIER (1) 30 V / 3 A 0.39 V at 3 A SBR3U30P1 5 °C/W PowerDI® 123 Diodes 30 V / 3 A 0.39 V at 3 A SSM33LSPT 18 °C/W SMA-S Chenmko 40 V / 3 A 0.38 V at 3 A SSM34LAS 18 °C/W SMA-S Chenmko 40 V / 2 A 0.5 V at 2 A SSM24APT 20 °C/W SMA-S Chenmko See Third-Party Products disclaimer Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A Submit Documentation Feedback 21 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com 7.4.2.6 Output Capacitor Selection For best output voltage filtering low ESR ceramic capacitors are recommended. Three 10 µF (or two 22 µF) ceramic capacitors work for most applications. To improve the load transient response more capacitance can be added. To calculate the output voltage ripple the following equations can be used: ΔVC_RIPPLE = (1) VIO I ´ OUT + Δ VC_ESR VIN ´ fS COUT Δ VC_ESR = ISW PEAK ´ RC_ESR (5) CAPACITOR VOLTAGE RATING TEMPERATURE CHARACTERISTICS SUPPLIER (1) COMPONENT CODE 10 µF / 1206 6.3 V X5R Murata GRM219R60J106KE19 10 µF / 1206 6.3 V X7R Taiyo Yuden JMK212AB7106KG See Third-Party Products disclaimer 7.4.3 BUCK 2 CONVERTER (V(CORE)) The synchronous current mode buck 2 converter operates with Pulse Frequency Modulation (PFM) with a fixed off-time and a typ. frequency of 1 MHz. The converter features integrated soft-start, bootstrap and compensation to minimize external component and pin count. It is supplied by the buck 1 converter’s output. If not needed the buck 2 converter can be disabled by I2C. 7.4.3.1 Soft-Start The buck 2 converter is enabled when the buck 1 converter is in regulation. It starts switching and ramps up its output voltage V(CORE) linearly in 3ms to the programmed voltage value. 7.4.3.2 Setting the Output Voltage V(CORE) The output voltage is programmable by I2C between 0.8 V and 3.3 V in 100 mV steps. 7.4.3.3 Design Procedure The first step in the design procedure is to verify whether the maximum possible output current of the buck 2 converter supports the specific application requirements. 1. Switching frequency: MfS = 2. Converter Duty Cycle: MD = 3. Inductor ripple current: MΔIL = ( VIO - VCORE ) ´ (1.17VCORE + 0.22 ) VIO MHz VCORE VIO ´ η (VIO - VCOR E ) ´ D fS ´ L 4. Maximum output current: MIOUT_ m ax = IL IM _m in - ΔIL 2 ΔIL 5. Peak switch current: MI SWPEAK = IOUT + 2 spacer η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.8 as an estimation) L = Selected inductor value (typ. 6.8 µH) ILIM_min: Minimum current limit (2.5A) ISWPEAK = Peak switch current for the used output current (must be < ILIM_min = 2.5 A) ΔIL = Inductor peak-to-peak ripple current The peak switch current ISWPEAK is the current that the switch and the inductor have to be able to handle. 22 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 7.4.3.4 Inductor Selection Inductor value: 4.7µH ≤ L ≤ 10µH The higher the inductor value the lower the inductor current ripple and the output voltage ripple but the slower the transient response. Saturation current: ISAT ≥ ISWPEAK or ISAT ≥ ILIM_max The inductor saturation current must be higher than the switch peak current for the max. peak output current or as a more conservative approach higher than the max. switch current limit. DC resistance: The lower the inductors resistance the lower the losses and the higher the efficiency. (1) INDUCTANCE SUPPLIER (1) COMPONENT CODE SIZE (L x W x H mm) DCR typ. (mΩ) ISAT (A) 4.7 µH Sumida CDRH5D28R/HP 6.2 x 6.2 x 3 35 3.7 6.8 µH Sumida CDRH5D28R/HP 6.2 x 6.2 x 3 49 3.1 4.7 µH Chilisin SCPS0725T 7.8 x 7.7 x 2.5 40 4 6.8 µH Chilisin SCPS0725T 7.8 x 7.7 x 2.5 66 3.5 4.7 µH Chilisin LVS606028 6.2 x 6.2 x 2.2 38 3.7 6.8 µH Chilisin LVS606028 6.2 x 6.2 x 2.2 50 3.1 4.7 µH Mag Layers MSCDRI-7025AL 8 x 8 x 2.5 45 3.5 6.8 µH Mag Layers MSCDRI-7025AL 8 x 8 x 2.5 63 3.1 See Third-Party Products disclaimer 7.4.3.5 Output Capacitor Selection For best output voltage filtering low ESR ceramic capacitors are recommended. Three 10 µF (or one 22 µF) ceramic capacitors work for most applications. To improve the load transient response more capacitance can be added. To calculate the output voltage ripple the following equations can be used: ΔVC_RIPPLE = (1) VC ORE I ´ OUT + ΔVC_ESR VIO ´ fS C OU T ΔVC_ESR = ISWPEAK ´ R C_ESR (6) SUPPLIER (1) COMPONENT CODE X5R Murata GRM219R60J106KE19 X7R Taiyo Yuden JMK212AB7106KG CAPACITOR VOLTAGE RATING TEMPERATURE CHARACTERISTICS 10 µF / 1206 6.3 V 10 µF / 1206 6.3 V See Third-Party Products disclaimer 7.4.4 Buck 3 Converter (V(HAVDD)) The synchronous current mode buck 3 converter operates with Pulse Frequency Modulation (PFM) with a fixed off-time and a typ. frequency of 1 MHz. The converter features integrated soft-start, bootstrap and compensation to minimize external component and pin count. If not needed the buck 3 converter can be disabled by I2C. 7.4.4.1 Soft-Start The buck 3 converter is enabled together with the boost converter. It starts switching and ramps up its output voltage V(HAVDD) to the programmed voltage value tracking the boost converters output voltage V(AVDD). 7.4.4.2 Setting the Output Voltage V(HAVDD) The output voltage is programmable by I2C between 4.8 V and 11.1 V in 100 mV steps. 7.4.4.3 High Voltage Stress Mode (HVS) By pulling the HVS-pin “high” an I2C programmable offset voltage is added to the set boost and buck 3 converters output voltage V(AVDD) and V(HAVDD). The offset voltages are programmable independently. Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A Submit Documentation Feedback 23 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com 7.4.4.4 Design Procedure The first step in the design procedure is to verify whether the maximum possible output current of the buck 3 converter supports the specific application requirements. 1. Switching frequency: MfS = 0.76 ´ VHAVDD ´ VIN - VHAVDD 2. Converter Duty Cycle: M D = MHz VIN VHAVDD VIN ´ η 3. Inductor ripple current: M ΔIL = ( VIN - VHAVDD) ´ D fS ´ L 4. Maximum output current: MIOUT_max = ILIM_min - ΔIL 2 DI 5. Peak switch current: M ISWPEAK = IOUT + L 2 spacer η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.8 as an estimation) fS: Switching frequency (typ. 1 MHz) L = Selected inductor value (typ. 6.8 µH) ILIM_min: Minimum current limit (1.7 A) ISWPEAK = Peak switch current for the used output current (must be < ILIM_min = 1.7 A) ΔIL = Inductor peak-to-peak ripple current The peak switch current ISWPEAK is the current that the switch and the inductor have to be able to handle. 7.4.4.5 Inductor Selection Inductor value: 4.7 µH ≤ L ≤ 10 µH The higher the inductor value the lower the inductor current ripple and the output voltage ripple but the slower the transient response. Saturation current: ISAT ≥ ISWPEAK or ISAT ≥ ILIM_max The inductor saturation current must be higher than the switch peak current for the max. peak output current or as a more conservative approach higher than the max. switch current limit. DC resistance: The lower the inductors resistance the lower the losses and the higher the efficiency. (1) INDUCTANCE SUPPLIER (1) COMPONENT CODE SIZE (L x W x H mm) DCR typ. (mΩ) ISAT (A) 4.7 µH Chilisin SCDS6D28T 7x7x3 25 2.5 6.8 µH Chilisin SCDS6D28T 7x7x3 40 2.1 4.7 µH Chilisin SCPS0725T 7.8 x 7.7 x 2.5 40 4 6.8 µH Chilisin SCPS0725T 7.8 x 7.7 x 2.5 66 3.5 4.7 µH Chilisin LVS404018 4.2 x 4.2 x 2 90 2 6.8 µH Chilisin LVS404018 4.2 x 4.2 x 2 110 1.6 4.7 µH Mag Layers MSCDRI-7025AL 8 x 8 x 2.5 45 3.5 6.8 µH Mag Layers MSCDRI-7025AL 8 x 8 x 2.5 63 3.1 See Third-Party Products disclaimer 7.4.4.6 Output Capacitor Selection For best output voltage filtering low ESR ceramic capacitors are recommended. One 10 µF ceramic capacitor works for most applications. To improve the load transient response more capacitance can be added. To calculate the output voltage ripple the following equations can be used: 24 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com ΔVC_RIPPLE = (1) SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 VHAVDD I ´ OUT + Δ VC_ESR VIN ´ fS COUT Δ VC_ESR = ISW PEAK ´ RC_ESR (7) CAPACITOR VOLTAGE RATING TEMPERATURE CHARACTERISTICS SUPPLIER (1) COMPONENT CODE 10 µF / 1206 16 V X5R Murata GRM31CR61C106KA88 10 µF / 1206 16 V X7R Taiyo Yuden EMK316AB7106KL See Third-Party Products disclaimer 7.4.5 Positive Charge Pump Controller (V(GH)) with Temperature Compensation The positive charge pump is driven from the boost converter’s switch node and regulated by controlling the current through an external PNP transistor. The controller is optimized for transistors with a DC gain (hFE) between 100 and 300, a base drive current up to 5 mA is supported. A temperature compensation for its output voltage V(GH) is implemented and the levels of the output voltages are programmed by I2C. The positive charge pump and the temperature compensation function can be disabled by I2C separately. 7.4.5.1 Soft-Start The positive charge pump controller is enabled when the boost converter is in regulation. The output voltage V(GH) ramps up to the programmed voltage in typ. 1.5 ms. 7.4.5.2 Setting the Output Voltage V(GH) The low voltage V(GH_LOW) at high temperature is programmed directly by I2C from 20 V to 35 V in 1 V steps, the high voltage V(GH_HIGH) at low temperature is programmed with a positive offset voltage of 1 V steps relative to V(GH_LOW). An external NTC thermistor with a resistor network (RP and RL) sets the temperatures when V(GH_LOW) (VNTC ≤ 1 V, hot) and V(GH_HIGH) (VNTC ≥ 2 V, cold) are reached. To achieve a linear curve between V(GH_LOW) and V(GH_HIGH) a suitable linearalization resistor parallel to the NTC must be used. NTC VL RL RP NTC RT0 is the resistance at an absolute temperature T0 in Kelvin (normally 25°C) T is the temperature in Kelvin (°C + 273.15 K/°C) B is a material constant provided by the NTC supplier VL: Internal supply voltage VL = 5 V RNTC(T) = RT ´ e 1 1ö - ÷÷ T Tø è 0 0 RP = VL ´ RNTC (THOT ) ´ RNTC(TCOLD ) VL ´ R NTC(TCOLD ) - 2VL ´ R NTC(THOT ) + 2RNTC(THOT ) - 2RNTC(TCOLD) RL = RP ´ RNTC (THOT ) ´ (VL - 1V) RP + RNTC (THOT ) RNTC(THOT): NTC resistance hot RNTC(TCOLD): NTC resistance cold æ -B ´çç Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A Submit Documentation Feedback 25 TPS65177, TPS65177A SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 www.ti.com NTC VL 121kW 402 kW NTC 10 kW NCP18XH103F03RB NTC VL 35.7 kW 80.6kW NTC 10 kW NCP18XH103F03RB NTC VL 14 kW 137kW NTC 10 kW NCP18XH103F03RB 7.4.5.3 Design Procedure 1. Supported max. output voltage The maximum possible output voltage is calculated as follows: IGH 1 ö æ1 Doubler Mode: VGH _ max = VINPU T + VAVDD – 2VF - VQ - R ´ IGH ´ ç + ÷ - C´f D 1 D è ø S 1 ö 2IGH æ1 Tripler Mode: VGH _ max = VIN PUT + 2VAVDD – 4VF - VQ - 2R ´ IGH ´ ç + ÷è D 1 - D ø C ´ fS 26 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS65177 TPS65177A TPS65177, TPS65177A www.ti.com SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016 VF: Diode forward voltage R: Switch node resistor VINPUT: Transistor emitter voltage D: Boost duty cycle C: Flying capacitor value fS: Boost switching frequency (750kHz) VQ: Collector-emitter saturation voltage 2. Diode selection Diode type: No specific type required Forward voltage: The lower the forward voltage VF the higher the maximum output voltage Reverse voltage: VR must be higher than the switching voltage applied at the flying capacitor Forward current: The average forward current IAVG must be higher than the output current IOUT Thermal characteristics: The diode must be able to handle the dissipated power of PD = VF × IOUT Peak currents of up to some amps through the diodes can occur during start-up for a few cycles. This condition lasts for