Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
TPS65182x PMIC For E Ink® Vizplex™-Enabled Electronic Paper Display
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
•
Single Chip Power Management Solution for
E Ink® Vizplex™ Electronic Paper Displays
Generates Positive and Negative Gate and
Source Driver Voltages and Back-Plane Bias from
a Single, Low-Voltage Input Supply
3-V to 6-V Input Voltage Range
Boost Converter for Positive Rail Base
Inverting Buck-Boost Converter for Negative Rail
Base
Two Adjustable LDOs for Source Driver Supply
– LDO1: 15 V, 120 mA (VPOS)
– LDO2: –15 V, 120 mA (VNEG)
Accurate Output Voltage Tracking
– VPOS - VNEG = ±50 mV
Two Charge Pumps for Gate Driver Supply
– CP1: 22 V, 10 mA (VDDH)
– CP2: –20 V, 12 mA, (VEE)
Adjustable VCOM Driver for Accurate PanelBackplane Biasing
– –0.3 V to –2.5 V
– Adjustable Through External Potentiometer
– 15-mA Max Integrated Switch
Thermistor Monitoring
– –10°C to 85°C Temperature Range
– ±1°C Accuracy from 0°C to 50°C
I2C Serial Interface
– Slave Address 0x48h (1001000)
Flexible Power-Up Sequencing
•
•
Sleep Mode Support
Thermally Enhanced Package for Efficient Heat
Management
(48-Pin 7 mm × 7 mm × 0.9 mm VQFN)
2 Applications
•
•
•
•
•
Power Supply for Active Matrix E Ink Vizplex
Panels
E-Book Readers
EPSON® S1D13522 (ISIS) Timing Controller
EPSON S1D13521 (Broadsheet) Timing
Controller
Application Processors With Integrated or
Software Timing Controller (OMAP™)
3 Description
The TPS65182x device is a single-chip power
supplies designed to for E Ink Vizplex displays used
in portable e-reader applications and support panel
sizes up to 9.7 inches. Two high efficiency DC/DC
boost converters generate ±17-V rails which are
boosted to 22 V and –20 V by two change pumps to
provide the gate driver supply for the Vizplex panel.
Device Information(1)
PART NUMBER
TPS65182
PACKAGE
BODY SIZE (NOM)
(2)
VQFN (48)
TPS65182B
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Not recommended for new design.
Typical Application Schematic
VDDH_D
VIN
From Input
Supply
(3 V to 6 V)
TS
Positive
Charge
Pump
Temperature
Sensor
VDDH_DRV
VDDH_FB
VPOS
VIN_SW
LDO1
VCOM
VN
DCDC2
VCOM
From Input
Supply
(3 V to 6 V)
VB_SW
VB
DCDC2
VCOM_Panel
VNEG
LDO2
VEE_D
I/O Control
VCOM
Positive
Charge
Pump
VEE_DRV
VEE_FB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
4
6
Absolute Maximum Ratings ..................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions...................... 6
Thermal Information .................................................. 7
Electrical Characteristics.......................................... 7
Data Transmission Timing ...................................... 10
Typical Characteristics ............................................ 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 17
8.5 Register Maps ......................................................... 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2010) to Revision D
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
5 Description (continued)
Two tracking LDOs create the ±15-V source driver supplies which support up to 120-mA of output current. All
rails are adjustable through the I2C interface to accommodate specific panel requirements.
Accurate back-plane biasing is provided by a linear amplifier and can be adjusted either by an external resistor or
the I2C interface. The VCOM driver can source or sink current depending on panel condition.
The TPS65182x provides precise temperature measurement function to monitor the panel temperature during
operation. The temperature reading is updated every 60 s and can be accessed through the I2C interface.
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
Submit Documentation Feedback
3
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
6 Pin Configuration and Functions
25 - VN_SW
27 - VIN_P
26 - N/C
29 - VEE_IN
28 - VN
31 - VEE_D
30 - VEE_DRV
33 - PGND2
32 - VEE_FB
34 - VDDH_FB
36 - VDDH_DRV
35 - VDDH_D
RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
R G Z
P A C K A G E
24 - PWR_GOOD
23 - PBKG
VDDH_IN - 37
N/C - 38
22 - PWR0
N/C - 39
VB_SW - 40
21 - PWR1
20 - PWR2
PGND3 - 41
VB - 42
VPOS_IN - 43
19 - PWR3
18 - SDA
17 - SCL
16 - VCOM_PWR
15 - VCOM
VPOS - 44
N/C - 45
N/C - 46
TS - 47
14 - VCOM_PANEL
13 - N/C
VCOM_CTRL - 12
AGND1 - 8
INT_LDO1 -9
VIN – 10
VCOM_XADJ - 11
DGND - 6
INT_LDO2 - 7
VNEG_IN - 4
WAKEUP - 5
N/C - 2
VNEG - 3
VREF - 1
AGND2 - 48
Pin Functions
PIN
DESCRIPTION (1)
I/O
NO.
NAME
1
VREF
O
Filter pin for 2.25-V internal reference to ADC
2
N/C
—
Not connected
3
VNEG
O
Negative supply output pin for panel source drivers
4
VNEG_IN
I
Input pin for LDO2 (VNEG)
5
WAKEUP
I
Wake up pin (active high). Pull this pin high to wake up from sleep mode.
6
DGND
—
Digital ground
7
INT_LDO2
O
Internal supply (digital circuitry) filter pin
8
AGND1
—
Analog ground for general analog circuitry
9
INT_LDO1
O
Internal supply (analog circuitry) filter pin
10
VIN
I
Input power supply to general circuitry
11
VCOM_XADJ
I
Analog input for conventional VCOM setup method. Tie this pin to ground if VCOM is set
through I2C interface.
(1)
4
There will be 0-ns, 93.75-µs, 62.52-µs of deglitch for PWRx, WAKEUP, and VCOM_CTRL, respectively.
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
Pin Functions (continued)
PIN
NO.
NAME
DESCRIPTION (1)
I/O
12
VCOM_CTRL
I
13
N/C
—
VCOM_PANEL gate driver enable (active high)
Not connected
14
VCOM_PANEL
O
Panel common-voltage output pin
15
VCOM
O
Filter pin for panel common-voltage driver
16
VCOM_PWR
I
Internal supply input pin to VCOM buffer. Connect to the output of DCDC2.
17
SCL
I
Serial interface (I2C) clock input
18
SDA
I/O
19
PWR3
I
Enable pin for CP1 (VDDH) (active high)
20
PWR2
I
Enable pin for LDO1 (VPOS) (active high)
21
PWR1
I
Enable pin for CP2 (VEE) (active high)
Serial interface (I2C) data input/output
22
PWR0
I
Enable pin for LDO2 (VNEG) and VCOM (active high)
24
PWR_GOOD
O
Open drain power good output pin (active low)
25
VN_SW
O
Inverting buck-boost converter switch out (DCDC2)
26
N/C
—
Not connected
27
VIN_P
I
Input power supply to inverting buck-boost converter (DCDC2)
28
VN
I
Feedback pin for inverting buck-boost converter (DCDC2)
29
VEE_IN
I
Input supply pin for CP1 (VEE)
30
VEE_DRV
O
Driver output pin for negative charge pump (CP2)
31
VEE_D
O
Base voltage output pin for negative charge pump (CP2)
32
VEE_FB
I
Feedback pin for negative charge pump (CP2)
33
PGND2
—
34
VDDH_FB
I
Feedback pin for positive charge pump (CP1)
35
VDDH_D
O
Base voltage output pin for positive charge pump (CP1)
36
VDDH_DRV
O
Driver output pin for positive charge pump (CP1)
37
VDDH_IN
I
Input supply pin for positive charge pump (CP1)
38
N/C
—
Not connected
39
N/C
—
Not connected
40
VB_SW
O
Boost converter switch out (DCDC1)
41
PGND3
—
Power ground for DCDC1
42
VB
I
Feedback pin for boost converter (DCDC1)
43
VPOS_IN
I
Input pin for LDO1 (VPOS)
44
VPOS
O
Positive supply output pin for panel source drivers
45
N/C
—
Not connected
46
N/C
—
Not connected
47
TS
I
48
AGND2
—
Reference point to external thermistor and linearization resistor
23
PowerPad (PBKG)
—
Die substrate/thermal pad. Connect to VN with short, wide trace. Wide copper trace will
improve heat dissipation. PowerPad must not be connected to ground.
Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps
Thermistor input pin. Connect a 10k NTC thermistor and a 43k linearization resistor
between this pin and AGND2.
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
Submit Documentation Feedback
5
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
7 Specifications
7.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
Input voltage range at VIN, VINP
–0.3
7
V
Ground pins to system ground
–0.3
0.3
V
Voltage range at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0,
VCOM_CTRL, VDDH_FB, VEE_FB, PWR_GOOD
–0.3
3.6
V
VCOM_XADJ
–3.6
0.3
V
Voltage on VB, VB_SW, VPOS_IN, VDDH_IN
–0.3
20
V
Voltage on VN, VNEG_IN, VEE_IN, VCOM_PWR
–20
0.3
V
Voltage from VINP to VN_SW
–0.3
Peak output current
30
V
Internally limited
mA
Continuous total power dissipation
2
W
125
°C
–10
85
°C
–65
150
°C
TJ
Operating junction temperature
–10
TA
Operating ambient temperature (3)
Tstg Storage temperature
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
It is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad
is electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the
buck-boost output will help heat dissipated efficiently.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
7.3
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Input voltage range at VIN, VINP
3
3.7
6
UNIT
V
Voltage range at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0,
VCOM_CTRL, VDDH_FB, VEE_FB, VCOM_XADJ, PWR_GOOD
0
3.6
V
TA
Operating ambient temperature
–10
85
°C
TJ
Operating junction temperature
–10
125
°C
6
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
7.4 Thermal Information
TPS65182x
THERMAL METRIC (1)
RGZ (VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
(2)
30.5
°C/W
Junction-to-case (top) thermal resistance
16.2
°C/W
Junction-to-board thermal resistance
7.1
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm X 114.3 mm, and
2 oz. copper for top and bottom plane. Actual thermal impedance will depend on PCB used in the application.
7.5
Electrical Characteristics
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
3.7
6
UNIT
INPUT VOLTAGE
VIN
Input voltage range
VUVLO
Undervoltage lockout threshold
VIN falling
2.9
V
V
VHYS
Undervoltage lockout hysteresis
VIN rising
400
mV
mA
INPUT CURRENT
IQ
Operating quiescent current into VIN
Device switching, no load
5.5
ISTD
Operating quiescent current into VIN
Device in standby mode
130
ISLEEP
Shutdown current
Device in sleep mode
2.8
µA
10
µA
INTERNAL SUPPLIES
VINT_LDO1
Internal supply
2.7
V
VINT_LDO2
Internal supply
2.7
V
VREF
Internal supply
2.25
V
DCDC1 (POSITIVE BOOST REGULATOR)
VIN
VOUT
Input voltage range
Output current
RDS(ON)
MOSFET on resistance
–5%
Switch current accuracy
Switching frequency
L
Inductor
C
Capacitor
ESR
Capacitor ESR
6
V
V
5%
160
VIN = 3.7 V
Switch current limit
fSW
3.7
17
DC set tolerance
IOUT
ILIMIT
3
Output voltage range
mA
350
mΩ
1.5
A
–30%
30%
1
MHz
2.2
µH
2x4.7
µF
20
mΩ
DCDC2 (INVERTING BUCK-BOOST REGULATOR)
VIN
VOUT
Input voltage range
Output voltage range
Output current
RDS(ON)
MOSFET on resistance
3.7
6
–17
DC set tolerance
IOUT
ILIMIT
3
–5%
V
5%
160
VIN = 3.7 V
350
Switch current limit
–30%
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
mA
mΩ
1.5
Switch current accuracy
V
A
30%
Submit Documentation Feedback
7
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
Electrical Characteristics (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
L
Inductor
C
Capacitor
ESR
Capacitor ESR
TEST CONDITIONS
MIN
TYP
MAX
4.7
UNIT
µH
2x4.7
µF
20
mΩ
LDO1 (VPOS)
VPOS_IN
Input voltage range
VSET
Output voltage set value
VIN = 17 V
16.15
17
17.85
14.25
15
15.75
VINTERVAL
Output voltage set resolution
VIN = 17 V
VPOS_OUT
Output voltage range
VSET = 15 V, ILOAD = 20 mA
14.85
VOUTTOL
Output tolerance
VSET = 15 V, ILOAD = 20 mA
–1%
VDROPOUT
Dropout voltage
ILOAD = 120 mA
VLOADREG
Load regulation – DC
ILOAD = 10% to 90%
ILOAD
Load current range
ILIMIT
Output current limit
TSS
Soft start time
C
Recommended output capacitor
250
15
V
V
mV
15.15
V
1%
250
mV
1%
120
mA
200
mA
1
ms
4.7
µF
LDO2 (VNEG)
VNEG_IN
Input voltage range
–17.85
–17
–16.15
VSET
Output voltage set value
VIN = –17 V
VINTERVAL
Output voltage set resolution
VIN = –17 V
–15.75
–15
–14.25
VNEG_OUT
Output voltage range
VSET = –15 V, ILOAD = –20 mA
–15.15
VOUTTOL
Output tolerance
VSET = –15 V, ILOAD = –20 mA
–1%
VDROPOUT
Dropout voltage
ILOAD = 120 mA
250
VLOADREG
Load regulation – DC
ILOAD = 10% to 90%
1%
ILOAD
Load current range
ILIMIT
Output current limit
TSS
Soft start time
C
Recommended output capacitor
250
–15
V
V
mV
–14.85
V
1%
120
mV
mA
200
mA
1
ms
4.7
µF
LD01 (POS) AND LDO2 (VNEG) TRACKING
VDIFF
Difference between VPOS and VNEG
VSET = ±15 V,
ILOAD = ±20 mA, 0°C to 60°C
–50
50
mV
VCOM DRIVER
VCOM
Output voltage range
G
VCOM gain (VCOM_XADJ/VCOM)
–2.5
VCOM_ADJ = 0 V
–0.3
1
V
V/V
VCOM SWITCH
TON
Switch ON time
VCOM = –1.25 V, VCOM_PANEL = 0 V
CVCOM = 4.7 µF, CVCOM_PANEL = 4.7 µF
RDS(ON)
MOSFET ON resistance
VCOM = –1.25 V, ICOM = 30 mA
ILIMIT
MOSFET current limit
Not tested in production
Switch leakage current
VCOM = 0 V,
VCOM_PANEL = –2.5 V
ISWLEAK
20
1
ms
35
Ω
200
mA
8.3
nA
17.85
V
CP1 (VDDH) CHARGE PUMP
VDDH_IN
Input voltage range
VFB
Output voltage range
ILOAD
Load current range
fSW
Switching frequency
Submit Documentation Feedback
17
1
Accuracy
VDDH_OUT
8
16.15
Feedback voltage
–3%
VSET = 22 V, ILOAD = 2 mA
21
V
3%
22
560
23
V
10
mA
KHz
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
Electrical Characteristics (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CD
Recommended driver capacitor
10
nF
CO
Recommended output capacitor
4.7
µF
CP2 (VEE) NEGATIVE CHARGE PUMP
VEE_IN
Input voltage range
–17.75
Feedback voltage
VFB
Output voltage range
ILOAD
Load current range
fSW
Switching frequency
CD
CO
–16.15
V
–1
Accuracy
VEE_OUT
–17
–3%
VSET = –20 V, ILOAD = 3 mA
–21
V
3%
–20
–19
12
V
mA
560
KHz
Recommended driver capacitor
10
nF
Recommended output capacitor
4.7
µF
THERMISTOR MONITOR (1)
ATMS
Temperature to voltage ratio
Not tested in production
OffsetTMS
Offset
Temperature = 0°C
1.575
V
VTMS_HOT
Temp hot trip voltage (T = 50°C)
TEMP_HOT_SET = 0x8C
0.768
V
TEMP_COOL_SET = 0x82
0.845
V
2.25
V
7.307
KΩ
VTMS_COOL Temp hot escape voltage (T = 45°C)
VTMS_MAX
Maximum input level
RNTC_PU
Internal pull up resistor
RLINEAR
External linearization resistor
ADCRES
ADC resolution
Not tested in production, 1 bit
ADCDEL
ADC conversion time
Not tested in production
TMSTTOL
Accuracy
Not tested in production
–0.0158
V/°C
43
KΩ
16.1
mV
19
–1
µs
1
LSB
LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, PWR_GOOD, PWRx, WAKEUP)
VOL
Output low threshold level
VIL
Input low threshold level
VIH
Input high threshold level
I(bias)
Input bias current
IO = 3 mA, sink current
(SDA, PWR_GOOD)
V
0.4
V
1.2
V
VIO = 1.8 V
tlow,WAKEUP WAKEUP low time
fSCL
0.4
minimum low time for WAKEUP pin
1
150
µA
ms
SCL clock frequency
400
KHz
OSCILLATOR
fOSC
Oscillator frequency
9
Frequency accuracy
TA = –40°C to 85°C
–10%
MHz
10%
THERMAL SHUTDOWN
TSHTDWN
Thermal trip point
Thermal hysteresis
(1)
150
°C
20
°C
10-KΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43 KΩ, 1%) are used at TS pin for panel
temperature measurement.
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
Submit Documentation Feedback
9
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
7.6 Data Transmission Timing
VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted)
MIN
f(SCL)
Serial clock frequency
tHD;STA
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
MAX
100
tLOW
LOW period of the SCL clock
tHIGH
HIGH period of the SCL clock
tSU;STA
Set-up time for a repeated START condition
tHD;DAT
NOM
Data hold time
tSU;DAT
Data set-up time
tr
Rise time of both SDA and SCL signals
tf
Fall time of both SDA and SCL signals
tSU;STO
Set-up time for STOP condition
tBUF
Bus Free Time Between Stop and Start Condition
tSP
Pulse width of spikes which mst be suppressed
by the input filter
Cb
Capacitive load for each bus line
400
UNIT
KHz
SCL = 100 KHz
4
µs
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
SCL = 400 KHz
1.3
µs
SCL = 100 KHz
4
µs
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
µs
SCL = 400 KHz
600
SCL = 100 KHz
0
3.45
µs
SCL = 400 KHz
0
900
ns
SCL = 100 KHz
250
SCL = 400 KHz
100
ns
ns
SCL = 100 KHz
1000
SCL = 400 KHz
300
SCL = 100 KHz
300
SCL = 400 KHz
300
ns
ns
SCL = 100 KHz
4
µs
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
SCL = 400 KHz
1.3
SCL = 100 KHz
n/a
n/a
SCL = 400 KHz
0
50
µs
SCL = 100 KHz
400
SCL = 400 KHz
400
ns
pF
7.7 Typical Characteristics
100
0.78
90
0.76
80
0.74
Efficiency (%)
Efficiency (%)
70
60
50
40
30
0.72
0.70
0.68
20
0
0.00
Boost
0.05
0.10
0.15
0.20
Load Current (A)
Submit Documentation Feedback
0.25
0.64
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
Load Current (mA)
C002
Figure 1. Efficiency vs Load Current
10
0.66
Buck-Boost
10
0.16
0.18
C007
Figure 2. Load Current vs Efficiency
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
8 Detailed Description
8.1 Overview
The TPS65182x family of devices provides two adjustable LDOs, inverting buck-boost converter, boost
converter, thermistor monitoring, and flexible power-up and power-down sequencing. The system can be
supplied by a regulated input voltage ranging from 3 V to 6 V. The device is characterized across a –10°C to
85°C temperature range, best suited for personal electronic applications.
The I2C interface provides comprehensive features for using the TPS65182x family of devices. All rails can be
enabled or disabled. Power-up and power-down sequences can also be programmed through the I2C interface,
as well as thermistor and interrupt configurations. Voltage adjustment can also be controlled through the I2C
interface.
The adjustable LDOs can supply up to 120 mA of current. The default output voltages for each LDO can be
adjusted through the I2C interface. LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of
opposite sign, but same magnitude. The sum of VLDO1 and VLOD2 is guaranteed to be less than 50 mv.
There are two charge pumps: VDDH and VEE 10 mA and 12 mA respectively. These charge pumps boost the
DC-DC boost converters ±16-V rails to provide a gate channel supply. The power good functionality is open-drain
output, if any of the four power rails (CP1, CP2, LDO1, LDO2) are not in regulation, encounters a fault, or is
disabled, the pin is pulled low. PWR_GOOD remains low if one of the rails is not enabled by the host, and only
after all rails are in regulation, PWR_GOOD is released to HiZ state (pulled up by external resistor).
The TPS65182x family of devices provides circuitry to bias and measure an external NTC to monitor the display
panel temperature in a range from –10°C to 85°C with an accuracy of ±1°C from 0°C to 50°C. Temperature
measurements are triggered by the controlling host and the last temperature reading is always stored in the
TMST_VALUE register. Interrupts are issued when the temperature exceeds the programmable HOT, or drops
below the programmable COLD threshold, or when the temperature has changed by more than a user-defined
threshold from the baseline value.
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
Submit Documentation Feedback
11
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
8.2 Functional Block Diagram
10uF
10uF
VIN_P
2.2uH
VB_SW
From Input Supply
(3.0V-6.0V)
From Input Supply
(3.0V-6.0V)
4.7uH
4.7uF
PGND3
DCDC1
VN_SW
DCDC2
VB
VN
10uF
PBKG
4.7uF
VDDH_IN
VDDH_D
Gate driver Supply
(22V, 10mA)
VDDH_DRV
1M
4.7uF
10nF
VDDH_FB
4.7uF
VEE_IN
POSITIVE
CHARGE
PUMP
VEE_D
NEGATIVE
CHARGE
PUMP
Gate driver Supply
(-20V, 12mA)
VEE_DRV
VEE_FB
1M
10nF
47.5k
4.7uF
53.6k
PGND2
VPOS_IN
VNEG_IN
4.7uF
Source Driver Supply
(15V, 120mA)
4.7uF
4.7uF
VPOS
LDO1
VNEG
LDO2
4.7uF
Source Driver Supply
(-15V, 120mA)
10k NTC
TS
TEMP
SENSOR
INT_LDO1
ADC
INT_LDO2
INT_LDO1
4.7uF
43k
INT_LDO2
4.7uF
10uF
VIN
From Input Supply
(3.0V-6.0V)
VREF
VREF
4.7uF
VCOM
VCOM_XADJ
4.7uF
AGND1
VNEG
AGND2
VCOM_PWR
DGND
4.7uF
4.7uF
GATE DRIVER
To panel back -plane
(-0.3 to -2.5V, 15mA)
From uC or DSP
VCOM_PANEL
VCOM_CTRL
PWR[1]
From uC or DSP
From uC or DSP
10k VIO
To uC or DSP
PWR[2]
From uC or DSP
From uC or DSP
PWR_GOOD
PWR[3]
From uC or DSP
PWR[0]
WAKEUP
DIGITAL
CORE
SDA
I2C
SCL
10k VIO
From uC or DSP
From /to uC or DSP
8.3 Feature Description
8.3.1 Modes of Operation
The TPS65182x has three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the lowestpower mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the device
is ready to accept commands through PWR[3:0] pins and/or I2C interface. In ACTIVE mode one or more power
rails are enabled.
SLEEP
This is the lowest power mode of operation. All internal circuitry is turned off and the device does
not respond to I2C communications. TPS65182x enters SLEEP mode whenever WAKEUP pin is
pulled low.
STANDBY
In STANDBY all internal support circuitry is powered up and the device is ready to accept
commands either through GPIO or I2C control but none of the power rails are enabled. To enter
STANDBY mode the WAKEUP pin must be pulled high and all PWRx pins must be pulled low. The
device also enters STANDBY mode if input under voltage lock out (UVLO), positive boost under
voltage (VB_UV), or inverting buck-boost under voltage (VN_UV) is detected, or thermal shutdown
occurs.
ACTIVE
The device is in ACTIVE mode when any of the output rails are enabled and no fault condition is
present. This is the normal mode of operation while the device is powered up. In ACTIVE mode, a
falling edge on any PWRx pin shuts down and a rising edge powers up the corresponding rail.
12
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
Feature Description (continued)
8.3.2 Mode Transistions
SLEEP → ACTIVE WAKEUP pin is pulled high (rising edge) with any PWRx pin high. Rails come up in a predefined power-up sequence.
SLEEP → STANDBY WAKEUP pin is pulled high (rising edge) with all PWRx pins low. Rails will remain down
until one or more PWRx pin is pulled high.
ACTIVE → SLEEP WAKEUP pin is pulled low (falling edge). Rails are shut down following the pre-defined
power-down sequence.
ACTIVE → STANDBY WAKEUP pin is high. All PWRx pins are pulled low (falling edge). Rails shut down in the
order in which PWRx pins are pulled low. In the event of thermal shut down (TSD), under voltage
lock out (UVLO), positive boost or inverting buck-boost under voltage (UV), the device shuts down
all rails in a pre-defined power-down sequence.
STANDBY → ACTIVE WAKEUP pin is high and any PWRx pin is pulled high (rising edge). Rails come up in the
same order as PWRx pins are pulled high.
STANDBY → SLEEP WAKEUP pin is pulled low (falling edge) while none of the output rails are enabled.
POWER DOWN
Battery removed
All rails
I2 C
WAKEUP (¯)
(* )
WAKEUP () & any P WRx pin = high
(*)
SLEEP
WAKEUP
WAKEUP
( ) &
All PWRx pins
= low
(¯ )
All rails
I2 C
STANDBY
WAKEUP
all PWRx pins
= high &
(**)
= ( ¯)
||
(**)
FAULT
)
(*)
(**)
=
=
=
=
=
= OFF
= YES
WAKEUP
= high &
(**)
any PWRx pin
( ) )
Rails
I2 C
ACTIVE
NOTES :
||, &
( ), ( ¯ )
FAULT
= OFF
= NO
logic OR , logic AND .
rising edge
, falling edge
.
UVLO || TSD ( thermal shutdown
)|| BOOST UV
Device follows default power
- up /down sequence
Power sequencing is GPIO controlled
.
= ON
= YES
.
.
Figure 3. Global State Diagram
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
Submit Documentation Feedback
13
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
Feature Description (continued)
8.3.3 Wake-Up and Power Up Sequencing
The TPS65182x supports a default power-up sequence supporting E Ink Vizplex displays. It also offers full user
control of the power-up sequence through GPIO control using the PWR3, 2, 1, 0 pins. Using GPIO control, the
output rails are enabled/disabled in the order in which the PWRx pins are asserted/de-asserted, respectively, and
the power-up timing is controlled by the host only. Rails are in regulation 2 ms after their respective PWRx pin
has been asserted with the exception of the first rail, which takes 6 ms to power up. The additional time is
needed to power up the positive and inverting buck-boost regulator which need to be turned on before any other
rail can be enabled. Once all rails are enabled and in regulation the PWR_GOOD pin is released (pin status =
HiZ and power good line is pulled high by external pull-up resistor). The PWRx pins are assigned to the rails as
follows:
• PWR0: LDO2 (VNEG) and VCOM
• PWR1: CP2 (VEE)
• PWR3: LDO2 (VPOS)
• PWR4: CP1 (VDDH)
Rails are powered down whenever the host de-asserts the respective PWRx pin, and once all rails are disabled
the device enters STANDBY mode. The next step is then to de-assert the WAKEUP pin to enter SLEEP mode
which is the lowest-power mode of operation.
It is possible for the host to force the TPS65182x directly into SLEEP mode from ACTIVE mode by de-asserting
the WAKEUP pin in which case the device follows the pre-defined power-down sequence before entering SLEEP
mode.
8.3.4 Dependencies Between Rails
Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and
several dependencies exist that affect the power-up sequencing. These dependencies are listed below.
1. Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled.
Internally, DCDC1 enable is gated by DCDC2 power good.
2. Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable
is gated DCDC1 power-good.
3. Positive boost (DCDC1) must be in regulation before VCOM can be enabled; Internally VCOM enable is
gated by DCDC1 power good.
4. Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally
CP2 enable is gated by DCDC1 power good.
5. Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally
CP1 enable is gated by DCDC1 power good.
6. LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power
good.
7. The minimum delay time between any two PWRx pins must be > 62.5 µs in order to follow the power up
sequence defined by GPIO control. If any two PWRx pins are pulled up together (< 62.5 µs apart) rails will
be staggered in a manner that a subsequent rail’s enable is gated by PG of a preceding rail. In this case, the
default order of power-up is LDO2 (VNEG), CP2 (VEE), LDO1 (VPOS), and CP1(VDDH). If any two PWRx
pins are pulled low then all rails will go down at the same time.
14
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
Feature Description (continued)
VIN
PWR0
D0
1.8ms (1)
PWR1
D1
PWR2
D2
PWR3
D3
WAKEUP
SLEEP
STANDBY
ACTIVE
ACTIVE
VN
VB
VNEG
DLY 1
VCOM
6ms (2,5)
DLY 2
DLY 0 + 4ms (2)
VEE
1ms (5)
DLY 1
DLY 3
VPOS
2ms (5)
DLY 2
DLY 0
VDDH
1ms (5)
DLY 3
PWR_GOOD
300 us (max)
11 .8ms (min)
(1) Minimum delay time between WAKEUP rising edge and IC rady to accept I 2C transaction .
(2) It takes 2ms minimum for each internal boost regulator to start up before VNEG can be enabled .
(5) It takes up to 2ms for LDOs (VPOS,VNEG) and 1ms for charge pumps (VDDH,VEE), to reach their steady state after being enabled.
DLY 0-DLY 3 are power up /down delays are factory -set to 2ms.
Figure 4. Power-Up and Power-Down Timing Diagram
8.3.5 Soft-Start
Softstart for DCDC1, DCDC2, LDO1, and LDO2 is accomplished by lowering the current limits during start-up. If
DCDC1 or DCDC2 are unable to reach power-good status within 10 ms, the device enters STANDBY mode.
8.3.6 VCOM Adjustment
VCOM can be adjusted by an external potentiometer by connecting a potentiometer to the VCOM_XADJ pin. The
potentiometer must be connected between ground and a negative supply. The gain from VCOM_XADJ to VCOM
is 1 and therefore the voltage applied to VCOM_XADJ pin should range from -0.3 to -2.5V.
8.3.7 VPOS and VNEG Supply Tracking
LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude.
The sum of VLDO1 and VLOD2 is guaranteed to be < 50 mV.
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
Submit Documentation Feedback
15
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
Feature Description (continued)
8.3.8 Fault Handling and Recovery
The TPS65182x monitors input and output voltages and die temperature and will take action if operating
conditions are outside normal limits. Whenever the TPS65182x encounters:
• Thermal Shutdown (TSD)
• Positive Boost Under Voltage (VB_UV)
• Inverting Buck-Boost Under Voltage (VN_UV)
• Input Under Voltage Lock Out (UVLO)
it will shut down all power rails and enter STANDBY mode. Shut down follows the pre-defined power-down
sequence and once a fault is detected, the PWR_GOOD pin is pulled low.
Whenver the TPS65182x encounters under voltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV)
or VDDH (VDDH_UV) it will shut down the corresponding rail (plus any dependent rail) only and remain in
ACTIVE mode, allowing the DCDC converters to remain up. Again, the PWR_GOOD pin will be pulled low.
As the PWRx inputs are edge sensitive, the host must toggle the PWRx pins to re-enable the rails through GPIO
control, i.e. it must bring the PWRx pins low before asserting them again.
8.3.9 Power Good Pin
The power good pin (PWR_GOOD) is an open drain output that is pulled high when all four power rails (CP1,
CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails encounters a fault. PWR_GOOD remains
low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released
to HiZ state (pulled up by external resistor).
8.3.10 Panel Temperature Monitoring
The TPS65182x provides circuitry to bias and measure an external negative temperature coefficient resistor
(NTC) to monitor device temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C to
50°C. Temperature reading is automatically updated every 60 s.
8.3.11 NTC Bias Circuit
Figure 5 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an
internally generated 2.25-V reference voltage through an integrated 7.307-KΩ bias resistor. A 43-KΩ resistor is
connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a
nominal 10-KΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is
digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1.
16
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
Feature Description (continued)
Table 1. ADC Output Value vs Termperature
TEMPERATURE
TMST_VALUE[7:0]
< -10°C
1111 0110
-10°C
1111 0110
-9°C
1111 0111
...
...
-2°C
1111 1110
-1°C
1111 1111
0°C
0000 0000
1°C
0000 0001
2°C
0000 0010
...
...
25°C
0001 1001
...
85°C
0101 0101
> 85°C
0101 0101
2.25V
7.307 kW
10
Digital
10 bit ADC
43 kW
10 kW NTC
TPS6518x
Figure 5. NTC Bias and Measurement Circuit
8.4 Device Functional Modes
8.4.1 I2C Bus Operation
The TPS65182x supports a special I2C mode making it compatible with the EPSON® Broadsheet S1D13521
timing controller. Standard I2C protocol requires the following steps to read data from a register:
1. Send device slave address, R/nW bit set low (write command)
2. Send register address
3. Send device slave address, R/nW set high (read command)
4. The slave will respond with data from the specified register address.end device slave address, R/nW set high
(read command).
The EPSON® Broadsheet S1D13521 controller does not support I2C writes nor I2C reads from addressed
registers, therefore the TPS65182x I2C interface has been modified and the reading the temperature data is
reduced to two steps:
1. Send device address, R/nW set high (read command)
2. Read the data from the slave. The slave will respond with data from TMST_VALUE register address.
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
Submit Documentation Feedback
17
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
Device Functional Modes (continued)
S
SLAVE ADDRESS
R A
DATA 0
A P
From master to slave
R Read
S Start
From slave to master
A Acknowlege
P Stop
Figure 6. Subaddress in I2C Transmission
The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open Drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 7. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate group and address bits are set for the device, then the device will issue an
acknowledge pulse and prepare the receive subaddress data. Subaddress data is decoded and responded to as
per the Register Map section of this document. Data transmission is completed by either the reception of a stop
condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high
transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must
occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address,
sub-address and data words. Reference Figure 7.
SDA
SCL
1-7
8
9
ADDRESS
R/W
ACK
1-7
8
9
1-7
8
9
S
START
P
DATA
ACK
DATA
ACK/
nACK
STOP
Figure 7. I2C Start/Stop/Acknowledge Protocol
SDA
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL
tHD;STA
S
tHD;DAT tHIGH
tSU;STA
tSU;STO
Sr
tf
P
S
Figure 8. I2C Data Transmission Timing
18
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
8.5 Register Maps
Table 2. Register Address Map
REGISTER
ADDRESS (HEX)
NAME
DEFAULT
VALUE
DESCRIPTION
0
0x00
TMST_VALUE
N/A
Thermistor value read by ADC
8.5.1 Thermistor Readout (TMST_VALUE) Register (offset = 0x00h)
DATA BIT
D7
D6
D5
FIELD NAME
D4
D3
D2
D1
D0
TMST_VALUE[7:0]
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FIELD NAME
BIT DEFINITION
Temperature read-out
1111 0110 – < -10°C
1111 0110 – -10°C
1111 0111 – -9°C
...
1111 1110 – -2°C
1111 1111 – -1 °C
TMST_VALUE[7:0]
0000 0000 – 0 °C
0000 0001 – 1°C
0000 0010 – 2°C
...
0001 1001 – 25°C
...
0101 0101 – 85°C
0101 0101 – > 85°C
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
Submit Documentation Feedback
19
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS65185 device is used to power display screens in E-book applications, specifically E-Ink Vizplex
display, by connecting the screen to the positive and negative charge pump, LDOs 1 and 2, and VCOM rails.
The display screens size that can be supported up to 9.7 inches.
9.2 Typical Application
VIN
From Input Supply
(3.0 V-6.0 V)
VDDH_D
TS
POSITIVE
CHARGE
PUMP
TEMP
SENSOR
VN_SW
LDO1
VDDH_DRV
VDDH_FB
VPOS
DCDC2
VN
VCOM
VCOM
VB_SW
From Input Supply
(3.0 V-6.0 V)
VCOM_PANEL
DCDC1
VB
LDO2
I/O Control
NEGATIVE
CHARGE
PUMP
VCOM
VNEG
VEE_D
VEE_DRV
VEE_FB
Figure 9. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
VOLTAGE
SEQUENCE (STROBE)
VNEG (LDO2)
–15 V
1
VEE (Charge pump 2)
–20 V
2
VPOS (LDO1)
15 V
3
VDDH (Charge pump 1)
22 V
4
9.2.2 Detailed Design Procedure
For the positive boost regulator (DCDC1) a 10-µF capacitor can be used as the input capacitor value; two 4.7-µF
capacitor are used as output capacitors to reduce ESR along with a 2.2-µH inductor. For the inverting buck-boost
regulator (DCDC2), an 10-µF capacitor can be used at the input capacitor value; A 10-µF and 4.7-µF capacitor
are used as output capacitors to reduce ESR, with a 4.7-µH inductor. Capacitor ESR for all capacitors should be
around 20 mΩ, and ceramic X5R material. These are the typical the values used, additional inductor and
capacitor values can be used for improved functionality, but the parts should be rated the same as the
recommended external components listed in Table 4.
20
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
Table 4. Recommended External Components
PART NUMBER
VALUE
SIZE
MANUFACTURER
LQH44PN4R7MP0
4.7 µH
4 mm × 4 mm × 1.65 mm
Murata
NR4018T4R7M
4.7 µH
4 mm × 4 mm × 1.8 mm
Taiyo Yuden
VLS252015ET-2R2M
2.2 µH
2 mm × 2.5 mm × 1.5 mm
TDK
NR4012T2R2M
2.2 µH
4 mm × 4 mm × 1.2 mm
Taiyo Yuden
INDUCTORS
CAPACITORS
GRM21BC81E475KA12L
4.7 µF, 25 V, X6S
805
Murata
GRM32ER71H475KA88L
4.7 µF, 50 V, X7R
1210
Murata
X5R or better
—
—
BAS3010
—
SOD-323
Infineon
MBR130T1
—
SOD-123
ON-Semi
BAV99
—
SOT-23
Fairchild
10 kΩ
603
Murata
All other capacitors
DIODES
THERMISTOR
NCP18XH103F03RB
9.2.3 Application Curves
0.1
±14.94
0.0
Load Regulation (%)
±14.92
VNEG (V)
±14.96
±14.98
±15.00
±15.02
±0.1
±0.2
±0.3
±0.4
±0.5
±15.04
±0.6
±15.06
±20
0
20
40
60
80
100
120
140
Load Current (mA)
±20
160
0
20
40
60
80
100
120
140
Load Current (mA)
C003
160
C004
Figure 11. Load Current vs Load Regulation
Figure 10. Load Current vs VNEG
0.05
15.03
15.02
Load Regulation (%)
VPOS (V)
15.01
15.00
14.99
14.98
14.97
±0.05
±0.15
±0.25
14.96
14.95
±0.35
±20
0
20
40
60
80
100
120
Load Current (mA)
140
160
±20
0
Figure 12. Load Current vs VPOS
20
40
60
80
100
120
140
Load Current (mA)
C005
160
C006
Figure 13. Load Current vs Load Regulation
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
Submit Documentation Feedback
21
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
10 Power Supply Recommendations
The device is designed to operate with an input voltage supply range from 3 V to 6 V. This input supply can be
from a externally regulated supply. If the input supply is located more than a few inches from the TPS65185,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 10 µF is a typical choice.
11 Layout
11.1 Layout Guidelines
The layout guidelines for TPS65182x are as follows:
• PBKG (Die substrate must connect to VN (–16 V) with short, wide trace. Wide copper trace will improve heat
dissipation.
• Power pad is internally connected to PBKG and must be connected to ground, but connected to VN with a
short wide copper trace.
• Inductor traces must be kept on the PCB top layer free of any vias.
• Feedback traces must be routed away from any potential noise source to avoid coupling.
• Output caps must be placed immediately at output pin.
• VIN pins must be bypassed to ground with low ESR ceramic bypass capacitors.
22
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
TPS65182, TPS65182B
www.ti.com
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
11.2 Layout Example
TPS6518x
Thermal Pad
Bottom Layer
VN connection
Figure 14. Typical Layout of TPS6518x
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
Submit Documentation Feedback
23
TPS65182, TPS65182B
SLVSAA2D – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS65182
Click here
Click here
Click here
Click here
Click here
TPS65182B
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
OMAP, E2E are trademarks of Texas Instruments.
Vizplex is a trademark of E Ink Corporation.
E Ink is a registered trademark of E Ink Corporation.
EPSON is a registered trademark of Seiko Epson Corporation.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65182 TPS65182B
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65182BRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-10 to 85
E INK
TPS65182B
TPS65182BRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-10 to 85
E INK
TPS65182B
TPS65182RGZR
NRND
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-10 to 85
E INK
TPS65182
TPS65182RGZT
NRND
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-10 to 85
E INK
TPS65182
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
