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TPS65197, TPS65197B
SLVSBB0D – APRIL 2012 – REVISED FEBRUARY 2018
TPS65197x: 8-Channel Level-Shifter Supporting No, 2-Channel and 3-Channel
Charge-Sharing with Panel Discharge to VGH during Shut-Down
1 Features
3 Description
•
•
•
•
The TPS65197/B is an 8-channel level-shifter with
discharge function intended for use in LCD display
applications such as Notebooks, Monitors and TVs.
1
•
•
•
•
•
8-Channel Level-Shifter (STV, RESET, 6 × CLK)
High Output-Voltage Level 16.5 V to 45 V (VGH)
Low Output-Voltage Level Down to –20 V (VGL)
Selectable Charge-Sharing
– No Charge-Sharing
– 2-Channel Charge-Sharing
– 3-Channel Charge-Sharing
2-Channel Panel Discharge
T-CON Failure Detection
– TPS65197: Logic Resets by STV Pulse
– TPS65197B: No Reset of the Logic
Latched Shut-Down Detection (Clocks to VGH)
Supports 100-kHz Clock Operating Frequency
28-Pin 4-mm × 4-mm QFN Package
The device converts the timing-controller (T-CON)
logic-level signals to the high-level signals needed by
the gate-in-panel (GIP) display.
The clock outputs, CLKOUTx, support normal level
shifting operation and 2-channel or 3-channel chargesharing, which can be used to improve picture quality
and power consumption. At power down, all outputs
follow their input signals as long as possible; when
the discharge function is used, the outputs are pulled
high (VGH).
The TPS65197 implements a logic reset to ignore
wrong T-CON signals after the rising STV edge which
forces all 6 output clocks to VGL1. The next CLKIN1
rising edge unlocks the logic and enables normal
operation. The TPS65197B does not have the logic
reset and always follows its input signals.
2 Applications
•
Gate-in-Panel (GIP) LCD
– Notebook
– Monitor
– TV
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS65197
WQFN (28)
4.00 mm x 4.00 mm
TPS65197B
WQFN (28)
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
CLKOUT1
SEL_CS
V(CLK1)
CLKIN1
V(CLK2)
CLKIN2
V(CLK3)
CLKIN3
V(CLK4)
CLKIN4
V(CLK5)
CLKIN5
V(CLK6)
CLKIN6
V(STV)
V(RESET)
CLKOUT2
Level
Shifter
VGH
V(GL1)
VGL1
V(GL2)
VGL2
V(CLKOUT3)
CS_3
CLKOUT4
V(CLKOUT4)
CS_4
CLKOUT5
V(CLKOUT5)
CLKOUT6
V(CLKOUT6)
STVOUT
V(STVOUT)
RESETOUT
RESETIN
V(GH)
V(CLKOUT2)
CS_2
CLKOUT3
STVIN
DIS_SENSE
V(CLKOUT1)
CS_1
Discharge
V(RESETOUT)
DISCH1
DISCH2
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65197, TPS65197B
SLVSBB0D – APRIL 2012 – REVISED FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
5 Revision History
Changes from Revision C (May 2017) to Revision D
•
Page
First public release of data sheet. ......................................................................................................................................... 1
Changes from Revision B (July 2015) to Revision C
•
Page
Changed VIH MIN value from 2 to 1.65 in the INPUT SIGNALS section of the Electrical Characteristics table .................... 5
Changes from Revision A (June 2015) to Revision B
•
Page
Added TPS65197B device and changed the Simplified Schematic ...................................................................................... 1
Changes from Original (April 2012) to Revision A
Page
•
Added ESD Ratings table, Timing Requirements table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Supportt section, and Mechanical, Packaging, and Orderable Information sections.................................... 1
•
Added TPS65197B ................................................................................................................................................................ 1
•
Changed the text in the first paragraph of Output Clock Behavior ...................................................................................... 10
•
Added Device and Documentation Support and Mechanical, Packaging, and Orderable Information sections ................. 20
2
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Product Folder Links: TPS65197 TPS65197B
TPS65197, TPS65197B
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SLVSBB0D – APRIL 2012 – REVISED FEBRUARY 2018
6 Pin Configuration and Functions
CLKOUT4
CS_3
CLKOUT3
CS_2
CLKOUT2
CS_1
CLKOUT1
28
27
26
25
24
23
22
RUY Package
28-Pin WQFN With Thermal Pad
Top View
CS_4
1
21
STVIN
CLKOUT5
2
20
CLKIN1
CLKOUT6
3
19
CLKIN2
18
CLKIN3
Exposed
Thermal
Pad
DISCH2
6
16
CLKIN5
DISCH1
7
15
CLKIN6
10
11
12
13
14
VGH
9
8
RESETIN
CLKIN4
DIS_SENSE
17
SEL_CS
5
VGL2
RESETOUT
VGL1
4
GND
STVOUT
Pin Functions
PIN
NAME
NUMBER
I/O/P
DESCRIPTION
CLKIN1
20
I
Clock 1 input
CLKIN2
19
I
Clock 2 input
CLKIN3
18
I
Clock 3 input
CLKIN4
17
I
Clock 4 input
CLKIN5
16
I
Clock 5 input
CLKIN6
15
I
Clock 6 input
CLKOUT1
22
I/O
Clock 1 output
CLKOUT2
24
I/O
Clock 2 output
CLKOUT3
26
I/O
Clock 3 output
CLKOUT4
28
I/O
Clock 4 output
CLKOUT5
2
I/O
Clock 5 output
CLKOUT6
3
I/O
Clock 6 output
CS_1
23
I/O
Clock 1 charge-sharing input
CS_2
25
I/O
Clock 2 charge-sharing input
CS_3
27
I/O
Clock 3 charge-sharing input
CS_4
1
I/O
Clock 4 charge-sharing input
DISCH1
7
I/O
Discharge 1 output. Internally connected to VGL1 and VGH
DISCH2
6
I/O
Discharge 2 output. Internally connected to VGL2 and VGH
DIS_SENSE
13
I
Discharge sense terminal
GND
9
–
Ground
RESETIN
14
I
RESET input
RESETOUT
5
I/O
RESET output
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SLVSBB0D – APRIL 2012 – REVISED FEBRUARY 2018
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Pin Functions (continued)
PIN
NAME
I/O/P
NUMBER
DESCRIPTION
SEL_CS
12
I
Charge-sharing method-selection terminal. When left floating or pulled to GND,
charge-sharing is disabled.
STVIN
21
I
STV input
STVOUT
4
I/O
VGH
8
P
Positive supply voltage. Place a buffer capacitor close to this terminal.
VGL1
10
P
Negative supply voltage for all outputs except discharge 2. Place a buffer capacitor
close to this terminal.
VGL2
11
P
Negative supply voltage for discharge 2
Thermal pad
–
–
The thermal pad is connected to VGL1.
STV output
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Terminal voltage (1)
MIN
MAX
SEL_CS, DIS_SENSE, CLKIN1, CLKIN2,
CLKIN3, CLKIN4, CLKIN5, CLKIN6, STVIN,
RESETIN
–0.3
7
VGH
–0.3
50
VGL1, VGL2
–25
0.3
V
CLKOUT1, CLKOUT2, CLKOUT3,
CLKOUT4, CLKOUT5, CLKOUT6, CS_1,
CS_2, CS_3, CS_4, STVOUT, RESETOUT,
DISCH1, DISCH2
–25
50
VGH – VGLx
62
–20
0
Operating junction temperature, TJ
VGL1 – VGL2
–40
150
Storage temperature, Tstg
–65
150
(1)
UNIT
ºC
With respect to the GND terminal
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±700
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
V(GH)
Voltage range of positive supply
16.5
45
V(GL_x)
Voltage range of negative supply
–20
–3
V(GH) – V(GL_x)
Voltage difference between V(GH) and V(GL_x)
0
60
VGL1 – VGL2
Voltage difference between V(GL1) and V(GL2) (V(GL1)
must be more negative than V(GL2))
–20
0
TA
Operating free-air temperature
–40
85
TJ
Operating junction temperature
–40
125
4
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UNIT
V
°C
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Product Folder Links: TPS65197 TPS65197B
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SLVSBB0D – APRIL 2012 – REVISED FEBRUARY 2018
7.4 Thermal Information
TPS65197/B
THERMAL METRIC (1)
RUY
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
34.5
RθJCtop
Junction-to-case (top) thermal resistance
25.5
RθJB
Junction-to-board thermal resistance
7.5
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
7.5
RθJCbot
Junction-to-case (bottom) thermal resistance
2.5
(1)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
V(GH) = 30 V, V(GL1) = –10 V, V(GL2) = –8 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
V(GH)
Input voltage range V(GH)
16.5
45
V(GL1)
Input voltage range V(GL1)
–20
–3
V(GL2)
Input voltage range V(GL2)
–20
–3
I(GH)
Positive supply current
I(GL1)
Negative supply current
I(GL2)
Negative supply current
V(UVLO)
Undervoltage lockout threshold
T(SD)
Thermal shutdown temperature
0.3
CLKINx = STVIN = RESETIN =
SEL_CS = 0 V, DIS_SENSE = 5 V
–0.5
–0.05
–0.5
–0.05
V
1
mA
V(GH) rising, TJ = –40ºC to 85ºC
13.5
15
16.5
V(GH) falling, TJ = –40ºC to 85ºC
2
3.5
5
130
150
170
TJ rising
UNIT
V
°C
INPUT SIGNALS (CLKINx, STVIN, RESETIN, SEL_CS, DIS_SENSE)
VIH
High-level input voltage CLKINx,
STVIN, RESETIN
Input rising
VIL
Low-level input voltage CLKINx,
STVIN, RESETIN
Input falling
1.65
0.8
Charge-sharing-disabled voltage
V(SEL_CS)
V(DIS_SENS
0.5
3-Channel Charge-Sharing voltage
1
2
2-Channel Charge-Sharing voltage
2.8
6.5
Discharge detection threshold
V(DIS_SENSE) falling, TJ = 0ºC to 85ºC
Input current CLKINx, STVIN,
RESETIN, DIS_SENSE
CLKINx = STVIN = RESETIN =
DIS_SENSE = 5 V
Input current SEL_CS
SEL_CS = 5 V
E)
IIN
R(SEL_CS)
SEL_CS pin, internal pulldown
resistance
1.17
50
V
1.26
1.36
2
100
nA
50
100
µA
100
150
kΩ
11
25
LEVEL SHIFTERS (CLKOUT1 to CLKOUT6)
rDS(on)
R(CS)
High-side on-resistance, CLKOUTx
I(OUT) = 10 mA, sourcing (high side)
Low-side on-resistance, CLKOUTx
I(OUT) = 10 mA, sinking (low side)
Internal charge-sharing resistance
I(CS) = 10 mA, TJ = –40ºC to 85ºC
30
7
15
60
100
Ω
LEVEL SHIFTERS (STVOUT, RESETOUT)
rDS(on)
High-side on-resistance STVOUT,
RESETOUT
I(OUT) = 10 mA, sourcing (high side)
30
60
Low-side on-resistance STVOUT,
RESETOUT
I(OUT) = 10 mA, sinking (low side)
15
30
Ω
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Electrical Characteristics (continued)
V(GH) = 30 V, V(GL1) = –10 V, V(GL2) = –8 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
14
60
3
10
UNIT
DISCHARGE OUTPUTS (DISCH1, DISCH2)
rDS(on)
High-side on-resistance, DISCH1
I(OUT) = 10 mA, sourcing (high side)
Low-side on-resistance DISCH1
I(OUT) = 10 mA, sinking (low side)
High-side on-resistance, DISCH2
I(OUT) = 10 mA, sourcing (high side)
14
60
Low-side on-resistance DISCH2
I(OUT) = 10 mA, sinking (low side)
10
20
Ω
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
50
140
50
150
MAX
UNIT
LEVEL SHIFTERS (CLKOUT1 to CLKOUT6)
Slew+
Slew rate, rising
Slew–
Slew rate, falling
C(OUT) = 4.7 nF, V(OUT) = 20% to 80%
V/µs
tdr
V(OUT) rising, C(OUT) = 150 pF
40
100
tdf
V(OUT) falling, C(OUT) = 150 pF
50
100
tdr(CS)
V(OUT) rising, C(OUT) = 150 pF, R(CS) =
50 Ω
50
150
V(OUT) falling, C(OUT) = 150 pF, R(CS) =
50 Ω
70
150
Propagation delay
tdf(CS)
ns
LEVEL SHIFTERS (STVOUT, RESETOUT)
Slew+
Slew rate, rising
Slew–
Slew rate, falling
tdr
tdf
C(OUT) = 4.7 nF, V(OUT) = 20% to 80%
Propagation delay
STVOUT
RESETOUT
CLKOUTx
20
50
30
60
V/µs
V(OUT) rising, C(OUT) = 150 pF
40
100
V(OUT) falling, C(OUT) = 150 pF
50
100
VGH
80%
ns
3.3 V
50%
20%
VGL1
Slew+
GND
CLKIN1
Slew-
3.3 V
50%
GND
CLKIN4
STVIN
RESETIN
CLKINx
3.3 V
GND
VGH
90%
50%
CLKOUT1
10%
VGL1
Tdf(CS)
STVOUT
RESETOUT
CLKOUTx
90%
10%
tdr
6
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VGH
VGL1
tdf
Tdr(CS)
VGH
90%
CLKOUT4
10%
VGL1
Tdr(CS)
Tdf(CS)
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SLVSBB0D – APRIL 2012 – REVISED FEBRUARY 2018
7.7 Typical Characteristics
A012
A011
Figure 1. Propagation Delay, Charge Sharing Disabled
Figure 2. Propagation Delay, Charge Sharing Enabled
A013
Figure 3. Slew Rate
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8 Detailed Description
8.1 Overview
The TPS65197/B is a 8-channel level-shifter with optional discharge function during shut-down. It supports no
charge-sharing as well as 2-channel and 3-channel charge-sharing. Two channels are used to generate the STV
and RESET signal, the remaining 6 channels generate the clocks. The two discharge outputs (DISCH1 and
DISCH2) are connected to VGL1 and VGL2 during operation, at shutdown both discharge outputs are connected
to VGH.
8.2 Functional Block Diagram
SEL_CS
VGH
CLKOUT1
CLKIN1
VGH
CS_1
VGL1
CLKIN2
CLKOUT2
VGH
CS_2
VGL1
CLKOUT3
CLKIN3
VGH
CS_3
Charge-Sharing
logic
VGL1
CLKIN4
CLKOUT4
VGH
CS_4
VGL1
CLKOUT5
CLKIN5
VGH
VGL1
CLKIN6
CLKOUT6
VGH
VGL1
STVIN
STVOUT
VGH
VGL1
RESETIN
RESETOUT
VGH
VGL1
DIS_SENSE
DISCH1
VGH
VGH
VREF
VGL1
VGL1
DISCH2
VGL2
GND
8
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Logic all outputs = VGH
when DIS_SENSE < VREF
VGL2
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8.3 Feature Description
8.3.1 Sequencing
UVLO typ. 15 V
VGH
UVLO typ. 3.5 V
VGL1
VGL2
STVIN
RESETIN
CLKINx
STVOUT
RESETOUT
CLKOUTx
Outputs
follow VGL1
Outputs
follow VGL1
Outputs
follow VGH
typ. 1.2 V
DIS_SENSE
Outputs
follow
VGL1, VGL2
DISCH1
VGL1
DISCH2
VGL2
Outputs
follow VGH
8.3.2 Power Up
At power up VGL1 and VGL2 must be present before VGH is rising. VGL1 must be always more negative or equal to
VGL2, VGH should not rise faster than in 100 us. All clock output channels and DISCH1 follow VGL1, DISCH2
follows VGL2 until VGH rises above its rising UVLO threshold voltage of 15 V, then all clock output channels of the
TPS65197B follow their input signals. The TPS65197 has a different startup behavior as CLKOUT1 to CLKOUT6
are forced to VGL1 until the 1st rising edge of CLKIN1 releases all clocks. The discharge-sense (DIS_SENSE)
voltage must be higher than its maximum threshold voltage of 1.36 V before VGH reaches the rising UVLO
threshold of 15 V, otherwise all outputs are forced to VGH and the state is latched. The selected Charge-Sharing
method is latched when VGH reaches the rising UVLO according to the SEL_CS voltage, it is reset with the falling
UVLO.
8.3.3 Power Down
When the discharge-sense (DIS_SENSE) voltage falls below its typical threshold voltage of 1.26 V, all clock
output channels follow VGH until VGH falls below its typical falling UVLO threshold voltage of 3.5 V; then all clock
output channels and DISCH1 follow VGL1, DISCH2 follows VGL2. Once discharge-sense is triggered the state is
latched, to reset and continue normal operation VGH has to fall below the falling UVLO threshold of 3.5 V.
In case the discharge-sense (DIS_SENSE) voltage stays high during power down, all clock output channels
follow their input signals until VGH falls below its typical falling UVLO threshold voltage of 3.5 V; then all clock
output channels follow VGL1. The discharge channels follow VGL1 and VGL2 all the time.
8.3.4 Disabling the Discharge Function
When the discharge function is not used, the DIS_SENSE pin must be pulled above its maximum threshold
voltage of 1.36 V all the time (for example to 3.3 V).
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Feature Description (continued)
8.3.5 Undervoltage Lockout
To avoid improper operation of the device at low input voltages, an undervoltage lockout function is implemented.
When VGH is below the UVLO threshold each output channel is clamped to its respective negative supply, VGL1
or VGL2.
8.3.6 Thermal Shutdown
A thermal shutdown is implemented to prevent damage because of excessive heat or power dissipation. Once
the junction temperature exceeds a typical value of 150 ºC, all outputs are set to high-impedance. This state is
latched. VGH must fall below the falling UVLO (3.5 V) to reset the thermal shutdown.
8.4 Device Functional Modes
8.4.1 Output Clock Behavior
The STV and RESET channels always follow their inputs while the clocks 1 to 6 behave different for TPS65197
and TPS65197B.
TPS65197:
At startup the output signals CLKOUT1 to CLKOUT6 are forced low (VGL1) until the first rising edge of CLKOUT1
releases all clocks. Every rising edge of STVIN stops the Charge-Sharing and resets the output signals
CLKOUT1 to CLKOUT6 (that is, forced low) until the next rising edge of CLKIN1 after which the clock outputs
follow their inputs again. The rising edge of CLKIN1 should occur not sooner than 50 ns after the rising edge of
STVIN. This logic ensures a proper reset and a clean start every frame.
TPS65197B:
The TPS65197B does not have the reset logic as TPS65197 and all outputs always follow their input signals
(also at startup). If Charge-Sharing is activated every rising edge of STVIN stops the Charge-Sharing and the
output signals CLKOUT1 to CLKOUT6 follow their input signals. The next Charge-Sharing event should not
occur sooner than 50 ns after the rising edge of STVIN.
10
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Device Functional Modes (continued)
8.4.2 Charge-Sharing Methods TPS65197
STVIN
STVIN rising forces
CLKOUT1 to 6 to VGL1
STVIN rising forces
CLKOUT1 to 6 to VGL1
CLKIN1 rising releases the
clocks CLKOUT1 to 6
CLKIN1
CLKIN1 rising releases the
clocks CLKOUT1 to 6
CLKIN2
CLKIN3
CLKIN4
CLKIN5
CLKIN6
CLKOUT1 / CLKOUT2
CLKOUT3 / CLKOUT4
CLKOUT5 / CLKOUT6
Figure 4. TPS65197: Charge-Sharing Disabled (CS_SEL < 0.5 V)
STVIN
STVIN rising forces
CLKOUT1 to 6 to VGL1
STVIN rising forces
CLKOUT1 to 6 to VGL1
CLKIN1 rising releases the
clocks CLKOUT1 to 6
CLKIN1
CLKIN1 rising releases the
clocks CLKOUT1 to 6
CLKIN2
CLKIN3
CLKIN4
CLKIN5
CLKIN6
CLKOUT1 / CLKOUT3 / CLKOUT5
CLKOUT2 / CLKOUT4 / CLKOUT6
Charge-sharing
Charge-sharing
Charge-sharing
Charge-sharing
Charge-sharing
Charge-sharing
of CLKOUT1 ↔
of CLKOUT3 ↔
of CLKOUT5 ↔
of CLKOUT2 ↔
of CLKOUT4 ↔
of CLKOUT6 ↔
CLKOUT3 between CLKIN1↓
CLKOUT5 between CLKIN3↓
CLKOUT1 between CLKIN5↓
CLKOUT4 between CLKIN2↓
CLKOUT6 between CLKIN4↓
CLKOUT2 between CLKIN6↓
CLKIN3↑.
CLKIN5↑.
CLKIN1↑.
CLKIN4↑.
CLKIN6↑.
CLKIN2↑.
Figure 5. TPS65197: 3-Channel Charge-Sharing (CS_SEL = 1 V…2 V)
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Device Functional Modes (continued)
STVIN
STVIN rising forces
CLKOUT1 to 6 to VGL1
STVIN rising forces
CLKOUT1 to 6 to VGL1
CLKIN1 rising releases the
clocks CLKOUT1 to 6
CLKIN1
CLKIN1 rising releases the
clocks CLKOUT1 to 6
CLKIN2
CLKIN3
CLKIN4
CLKIN5
CLKIN6
CLKOUT1 / CLKOUT4
CLKOUT2 / CLKOUT5
CLKOUT3 / CLKOUT6
Charge-sharing of CLKOUT1 ↔ CLKOUT4 between CLKIN1↓ CLKIN4↑ and CLKIN4↓ CLKIN1↑.
Charge-Sharing of CLKOUT2 ↔ CLKOUT5 between CLKIN2↓ CLKIN5↑ and CLKIN5↓ CLKIN2↑.
Charge-Sharing of CLKOUT3 ↔ CLKOUT6 between CLKIN3↓ CLKIN6↑ and CLKIN6↓ CLKIN3↑.
Figure 6. TPS65197: 2-Channel Charge-Sharing (CS_SEL = 2.8 V…6.5 V)
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Device Functional Modes (continued)
8.4.3 Charge-Sharing Methods TPS65197B
TPS65197B:
STVIN
CLKIN1
CLKIN2
CLKIN3
CLKIN4
CLKIN5
CLKIN6
CLKOUT1 / CLKOUT2
CLKOUT3 / CLKOUT4
CLKOUT5 / CLKOUT6
Figure 7. TPS65197B: Charge-Sharing Disabled (CS_SEL < 0.5 V)
Rising edge of STVIN stops Charge-Sharing
Ÿ Outputs follow their Inputs.
STVIN
CLKIN1
CLKIN2
CLKIN3
CLKIN4
CLKIN5
CLKIN6
CLKOUT1 / CLKOUT3 / CLKOUT5
CLKOUT2 / CLKOUT4 / CLKOUT6
Charge-sharing
Charge-sharing
Charge-sharing
Charge-sharing
Charge-sharing
Charge-sharing
of CLKOUT1 ↔
of CLKOUT3 ↔
of CLKOUT5 ↔
of CLKOUT2 ↔
of CLKOUT4 ↔
of CLKOUT6 ↔
CLKOUT3 between CLKIN1↓
CLKOUT5 between CLKIN3↓
CLKOUT1 between CLKIN5↓
CLKOUT4 between CLKIN2↓
CLKOUT6 between CLKIN4↓
CLKOUT2 between CLKIN6↓
CLKIN3↑.
CLKIN5↑.
CLKIN1↑.
CLKIN4↑.
CLKIN6↑.
CLKIN2↑.
Figure 8. TPS65197B: 3-Channel Charge-Sharing (CS_SEL = 1 V…2 V)
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Device Functional Modes (continued)
Rising edge of STVIN stops Charge-Sharing
Ÿ Outputs follow their Inputs.
STVIN
CLKIN1
CLKIN2
CLKIN3
CLKIN4
CLKIN5
CLKIN6
CLKOUT1 / CLKOUT4
CLKOUT2 / CLKOUT5
CLKOUT3 / CLKOUT6
Charge-sharing of CLKOUT1 ↔ CLKOUT4 between CLKIN1↓ CLKIN4↑ and CLKIN4↓ CLKIN1↑.
Charge-Sharing of CLKOUT2 ↔ CLKOUT5 between CLKIN2↓ CLKIN5↑ and CLKIN5↓ CLKIN2↑.
Charge-Sharing of CLKOUT3 ↔ CLKOUT6 between CLKIN3↓ CLKIN6↑ and CLKIN6↓ CLKIN3↑.
Figure 9. TPS65197B: 2-Channel Charge-Sharing (CS_SEL = 2.8 V…6.5 V)
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS65197/B is a 8-channel level-shifter with discharge function. It supports no charge-sharing as well as 2channel and 3-channel charge-sharing.
9.2 Typical Application
CLKOUT4
CS_3
CLKOUT3
CS_2
CLKOUT2
CS_1
CLKOUT1
Charge-Sharing resistors can be left open when CS is disabled
28
27
26
25
24
23
22
CS_4
1
21
STVIN
CLKOUT5
2
20
CLKIN1
CLKOUT6
3
19
CLKIN2
18
CLKIN3
Exposed
Thermal
Pad
STVOUT
4
RESETOUT
5
17
CLKIN4
DISCH2
6
16
CLKIN5
DISCH1
7
15
CLKIN6
12
GND
VGL1
VGL2
SEL_CS
V(GL2)
V(GH)
V(GL1)
2u 1 µF
50 V / 0603
13
14
RESETIN
11
DIS_SENSE
10
100
0402
VIO or VI
9
VIO, VCORE or GND
8
VGH
Connected to VGL1
Figure 10. Typical Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the input parameters shown in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE
16.5 V to 45 V
Input voltage range
–20 V to –3 V
Input signals
83 kHz
low level < 0.8 V
Logic levels
high level > 2 V
Output load
150 pF and 50 Ω in series with 4.7 nF
Charge-sharing resistance
100 Ω
9.2.2 Detailed Design Procedure
Level Shifters for LCD panels generate fast signals, therefore special care must be taken to the input and output
trace length and layout symmetry. Signal delays can be caused by unsymmetric trace length. Placing the
components around the device is not critical, as mostly resistors are used. Care must be taken for the supply
capacitors which should be close to the device and have a good connection to ensure clean output signals.
9.2.3 Application Curves
A001
Figure 11. Power Up, Power Down
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A002
Figure 12. No Charge Sharing Input Signals
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A003
Load: 150 pF
A004
Load: 50 Ω, 4.7 nF
Figure 13. No Charge Sharing Outputs
Figure 14. No Charge Sharing Outputs
A009
A008
Load: 150 pF
Figure 15. 2-Channel Charge Sharing Input Signals
RCS = 100 Ω
Figure 16. 2-Channel Charge Sharing Outputs
A005
A010
Load: 50 Ω, 4.7 nF
RCS = 100 Ω
Figure 17. 2-Channel Charge Sharing Outputs
Figure 18. 3-Channel Charge Sharing Input Signals
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A006
Load: 150 pF
RCS = 100 Ω
A007
Load: 50 Ω, 4.7 nF
Figure 19. 3-Channel Charge Sharing Outputs
RCS = 100 Ω
Figure 20. 3-Channel Charge Sharing Outputs
10 Power Supply Recommendations
The TPS65197/B is designed to operate from an input voltage supply range between 16.5 V and 45 V on the
positive supply rail (VGH) and between –20 V and –3 V on the negative supply rails (VGL1, VGL2). A 1-µF
capacitor on VGH and VGL1 should be used to ensure clean output signals.
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11 Layout
11.1 Layout Guidelines
Proper PCB layout is essential for achieving the expected performance and a low device temperature. The
following points should be considered.
• Place the supply decoupling capacitors as close as possible to device terminals VGH and VGL1.
• Use wide traces to route power from the bias IC to the device to avoid voltage drops. The device is able to
sink and source high peak currents up to 1 A. If wide traces are not possible, place additional 1-µF capacitors
of at least 0805 size close to the supply decoupling capacitors.
• The output channel traces should be kept as short as possible to reduce EMI emissions, and not too thin to
minimize stray inductances producing voltage overshoots at the panel, because high peak currents up to 1 A
can flow.
• The thermal pad must be connected by many vias to a large copper area on a VGL1 potential, to be used as
a heat sink. Use a copper area of at least 10 cm2. The bigger the copper area, the cooler the device
temperature. On a multilayer board, use the copper areas of as many layers as possible to maximize the heat
sink.
• Output resistors for clock channels 1 to 6 can be used to reduce EMI emissions and device temperature if
necessary. They generate heat and should therefore not be placed close to the device.
11.2 Layout Example
CLKOUT4
CS_3
CLKOUT3
CS_2
CLKOUT2
CS_1
CLKOUT1
28
27
26
25
24
23
22
VIA to VGL1 Plane
CLKIN1
CLKOUT6
3
19
CLKIN2
STVOUT
4
18
CLKIN3
RESETOUT
5
17
CLKIN4
DISCH2
6
16
CLKIN5
DISCH1
7
15
CLKIN6
8
9
10
11
12
13
14
RESETIN
20
DIS_SENSE
2
SEL_CS
CLKOUT5
VGL2
STVIN
VGL1
21
GND
1
VGH
CS_4
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
PowerPAD™ Thermally Enhanced Package application report (SLMA002)
PowerPAD™ Made Easy application report (SLMA004)
QFN Layout Guidelines application report (SLOA122)
QFN/SON PCB Attachment application report (SLUA271)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS65197
Click here
Click here
Click here
Click here
Click here
TPS65197B
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS65197BRUYR
ACTIVE
WQFN
RUY
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65197B
Samples
TPS65197BRUYT
ACTIVE
WQFN
RUY
28
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS
65197B
Samples
TPS65197RUYR
ACTIVE
WQFN
RUY
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65197A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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