TPS65198
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SLVSAT4B – JUNE 2011 – REVISED JULY 2013
13-Channel Level Shifter With Op-Amp for LCD TVs and Monitors
Check for Samples: TPS65198
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
The TPS65198 provides an integrated level shifter
solution, primarily intended for TV and monitor
applications using GIP technology. The device
features a built-in state machine that generates
twelve output signals from the five input signals
provided by the timing controller (T-CON). In addition,
the TPS65198 generates a signal to discharge the
display panel during power-down and a high-speed
operational amplifier for buffering the system's VCOM
voltage.
1
Six CLK Outputs
VST and RESET Outputs
ODD and EVEN Outputs
VGH_F and VGH_R Outputs
Panel DISCHARGE Output
Supports Forward and Reverse Operation
Abnormal Operation Detection
Supports all Display Resolutions
High-Speed Operational Amplifier
28-Pin 4×4 mm QFN Package
Level shifter outputs are forced to a safe state (VGL)
during abnormal panel operation, which is indicated
by the T-CON using the EO and GST signals.
APPLICATIONS
•
LCD TVs and Monitors Using GIP Technology
Level Shifters
with
Gate Shaping
GCLK
MCLK
GST
EO
BI-SCAN
State
Machine
CLK1-CLK6
Level Shifters
without
Gate Shaping
VST
RESET
VGH_F
VGH_R
Level Shifters
without
Gate Shaping
ODD
EVEN
Panel Discharge
VSENSE
POS
NEG
DISCHARGE
Operational Amplifier
OUT
ORDERING INFORMATION (1)
(1)
TA
ORDERING
PACKAGE
PACKAGE MARKING
–40°C to 85°C
TPS65198RUYR
28-Pin 4×4 QFN
TPS65198
The device is supplied taped and reeled, with 3000 devices per reel.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
TPS65198
SLVSAT4B – JUNE 2011 – REVISED JULY 2013
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
Voltage (2)
GCLK, MCLK, GST, EO, BI-SCAN, VSENSE
7
VGH1, VGH2, RE
40
VGL
–25
VGH1 with respect to VGL, VGH2 with respect to VGL
60
POS, NEG, OUT, AVDD
20
CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, VST, RESET, VGH-F, VGH_R, EVEN, ODD,
DISCHARGE
–25
Human Body Model
ESD Rating
(1)
(2)
MAX
UNIT
V
40
2
kV
Machine Model
200
V
Charged Device Model
700
V
Ambient temperature, TA
–40
85
°C
Junction temperature, TJ
–40
150
°C
Storage temperature, TSTG
–65
150
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
With respect to the GND pin.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS65198
QFN (28) PIN
θJA
Junction-to-ambient thermal resistance
33.8
θJCtop
Junction-to-case (top) thermal resistance
23.6
θJB
Junction-to-board thermal resistance
6.7
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
6.7
θJCbot
Junction-to-case (bottom) thermal resistance
2.1
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
VGH1
Level shifter positive supply voltage range
VGH2
VGL
Level shifter negative supply voltage range
VGH1-VGL
TYP
MAX
UNIT
15
38
V
15
38
V
–3
–23
V
18
56
V
18
56
V
8
20
V
VGH2-VGL
Level shifter differential supply voltage range
AVDD
Op-amp positive supply voltage range
TA
Operating ambient temperature
–40
25
85
°C
TJ
Operating junction temperature
–40
85
125
°C
ELECTRICAL CHARACTERISTICS
VGH1= 28V, VGH2= 28V, VGL= –10V, AVDD = 15V, TA = –40°C to 85°C; Typical values are at 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL SHIFTER
POWER SUPPLY
IGH1
Positive supply current
GST, GCLK, MCLK, EO, BI-SCAN = 0 V
0.4
mA
IGH2
Positive supply current
GST, GCLK, MCLK, EO, BI-SCAN = 0 V
0.06
mA
IGL
Negative supply current
GST, GCLK, MCLK, EO, BI-SCAN = 0V
0.13
mA
UVLO
UVLO threshold
VGH1 rising
9.2
VGH1 falling
3.4
V
INPUT SIGNALS (GCLK, MCLK, GST, EO, BI-SCAN)
VIH
High input voltage threshold
Input rising
VIL
Low input voltage threshold
Input falling
Input current
GST, GCLK, MCLK, EO = 3.3 V
BI-SCAN = 3.3 V
RPULL-DOWN
V
±100
nA
V
GST, GCLK, MCLK, EO = 0 V
IIN
1.4
0.8
24
BI-SCAN pin internal pull-down resistor
33
±100
nA
44
µA
100
kΩ
LEVEL SHIFTERS (CLK1 to CLK8)
High side ON resistance
IOUT = 10 mA, sourcing (high side)
Low side ON resistance
IOUT = 10 mA, sinking (low side)
tPLH
GCLK rising edge propagation delay
GCLK rising edge to CLK rising edge, COUT = 150 pF
50
100
ns
tPHL
MCLK falling edge propagation delay
MCLK falling edge to CLK falling edge, COUT = 150 pF
50
100
ns
High side ON resistance
IOUT = 10 mA, sourcing (high side)
35
Low side ON resistance
IOUT = 10 mA, sinking (low side)
16
GST rising edge to VST rising edge, COUT = 150 pF
50
100
GST rising edge to RESET rising edge, COUT = 150 pF
50
100
GST falling edge to VST falling edge, COUT = 150 pF
50
100
GST falling edge to RESET falling edge, COUT = 150 pF
50
100
EO rising edge to ODD falling edge, COUT = 150 pF
50
100
EO rising edge to EVEN falling edge, COUT = 150 pF
50
100
EO falling edge to ODD rising edge, COUT = 150 pF
50
100
EO falling edge to EVEN rising edge, COUT = 150 pF
50
100
EO to GST rising edge
50
100
BI-SCAN rising edge to VGH_R rising edge, COUT = 150 pF
50
100
BI-SCAN rising edge of VGH_F falling edge, COUT = 150 pF
50
100
BI-SCAN falling edge to VGH_F rising edge, COUT = 150 pF
50
100
BI-SCAN falling edge of VGH_F falling edge, COUT = 150 pF
50
100
rDS(ON)
12
Ω
7
LEVEL SHIFTERS (VST, RESET, ODD, EVEN, VGH_F, VGH_R)
rDS(ON)
tPLH
GCLK rising edge propagation delay
tPHL
GCLK falling edge propagation delay
tPLH
EO rising edge propagation delay
tPHL
EO falling edge propagation delay
tSU
EO set-up time during abnormal operation
tPLH
BI-SCAN rising edge propagation delay
tPHL
BI-SCAN falling edge propagation delay
t12
Bi-SCAN dead time
t13
Ω
ns
ns
ns
ns
ns
ns
ns
VGH_F falling edge to VGH_R rising edge, COUT = 150 pF
20
500
1000
VGH_R falling edge to VGH_F rising edge, COUT = 150 pF
20
500
1000
ns
GATE SHAPING (RE)
rDS(ON)
Gate shaping resistance
Measured between active CLK channel and RE at 10 mA
70
tPHL
MCLK rising edge propagation delay
MCLK rising edge to CLK falling edge, COUT = 150 pF
65
Ω
100
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ELECTRICAL CHARACTERISTICS (continued)
VGH1= 28V, VGH2= 28V, VGL= –10V, AVDD = 15V, TA = –40°C to 85°C; Typical values are at 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.5
1.725
UNIT
PANEL DISCHARGE (DISCHG)
VSENSEL
Discharge threshold voltage
VSENSE falling
VHYS
Discharge threshold voltage hysteresis
VSENSE rising
ISENSE
VSENSE input current
VSENSE = 2 V
High side ON resistance
IOUT = 10 mA, sourcing (high side)
35
Low side ON resistance
IOUT = 10 mA, sinking (low side)
16
rDS(ON)
1.275
100
V
mV
±1
µA
Ω
OPERATIONAL AMPLIFIER
IAVDD
Supply current
VCM = 7.5 V, unity gain, no load
6
mA
VIO
Input offset voltage
VCM = 7.5 V
–25
25
mV
IIB
Input bias current
VCM = 7.5 V
–100
100
BW
Unity gain 3 dB bandwidth
VCM = 7.5 V, VIN = 63 mVPP, no load
70
MHz
AVOL
Open loop gain
VCM = 7.5 V, no load
80
dB
CMRR
Common-mode rejection ratio
CMRR = ΔVCM / ΔVOS, VCM = 5.5 V to 9.5 V
90
dB
PSRR
Power supply rejection ratio
PSRR = ΔAVDD / ΔVOS, AVDD = 8V to 20 V
80
dB
High-side output resistance
VPOS = 9.5 V, VNEG = 7.5 V, IOUT = 10 mA
15
Low-side output resistance
VPOS = 7.5 V, VNEG = 9.5 V, IOUT = 10 mA
35
rDS(ON)
IPK
4
Peak output current
4
Unity gain, VPOS = 7.25V, VOUT = 7.5V
200
414
Unity gain, VPOS = 7.75V, VOUT = 7.5V
200
344
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nA
Ω
mA
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BI-SCAN
GCLK
MCLK
GST
EO
VSENSE
GND
28
27
26
25
24
23
22
PIN ASSIGNMENT
TOP VIEW
CLK1
1
21
AVDD
CLK2
2
20
POS
CLK3
3
19
NEG
CLK4
4
18
OUT
CLK5
5
17
VGH2
CLK6
6
16
VGH1
RE
7
15
VGL
8
9
10
11
12
13
14
VGH_R
VGH_F
ODD
EVEN
VST
RESET
DISCHG
Exposed
Thermal Die
(VGL)
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
CLK1
1
O
CLK1 output
CLK2
2
O
CLK2 output
CLK3
3
O
CLK3 output
CLK4
4
O
CLK4 output
CLK5
5
O
CLK5 output
CLK6
6
O
CLK6 output
RE
7
O
Gate shaping resistor connection
VGH_R
8
O
VGH_R output
VGH_F
9
O
VGH_F output
ODD
10
O
ODD output
EVEN
11
O
EVEN output
VST
12
O
VST output
RESET
13
O
RESET output
DISCHG
14
O
DISCHG output
VGL
15
P
Negative supply voltage
VGH1
16
P
Positive supply voltage for all outputs except ODD and EVEN
VGH2
17
P
Positive supply voltage for ODD and EVEN outputs
OUT
18
O
Operational amplifier output
NEG
19
I
Operational amplifier inverting input
POS
20
I
Operational amplifier non-inverting input
AVDD
21
P
Operational amplifier positive supply
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PIN FUNCTIONS (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
GND
22
P
Ground
VSENSE
23
I
Voltage sense input for discharge function
EO
24
I
EO input
GST
25
I
GST input
MCLK
26
I
MCLK input
GCLK
27
I
GCLK input
BI-SCAN
28
I
BI-SCAN input
Exposed
Thermal Die
N/A
P
Connect to VGL
6
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
TITLE
TEST CONDITIONS
CLKx
Peak Output Current vs
Figure 1
VST, RESET, ODD, EVEN, VGH_F, VGH_R
10nF load
Figure 2
DISCHARGE
Figure 3
CLKx
Figure 4
VST, RESET, ODD, EVEN, VGH_F, VGH_R
47Ω + 10nF load
DISCHARGE
Rise Time vs
Figure 5
Figure 6
CLKx
Figure 7
VST, RESET, ODD, EVEN, VGH_F, VGH_R
150 pF load
Figure 8
DISCHARGE
Figure 8
CLKx
Figure 10
VST, RESET, ODD, EVEN, VGH_F, VGH_R
Fall Time vs
FIGURE
47Ω + 10nF load
Figure 11
DISCHARGE
Figure 12
CLKx
Figure 13
VST, RESET, ODD, EVEN, VGH_F, VGH_R
150 pF load
Figure 14
DISCHARGE
Figure 15
VSENSE Threshold vs
VSENSE, DISCH
Figure 16
Power-Up Sequence vs
CLKs, VGH, VGL
Figure 17
Power-Down Sequence vs
CLKs, VGH, VGL, DISCH
Figure 18
Small-Signal 3dB Bandwidth
AVDD = 15 V, VCM = 7.5 V, VIN = 63 mVPP,
Unity gain, RFEEDBACK = 0 Ω
No load
Figure 19
Peak Output Current
AVDD = 15 V, VCM = 7.5 V, VIN = 2 VPP, Openloop
10 nF load
Figure 20
Slew Rate
VOUT falling
COUT = 150pF, No Load
Figure 21
Figure 1. Peak Output Current - CLKs
Figure 2. Peak Output Current - VST, RESET, etc.
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Figure 3. Peak Output Current - DISCHARGE
Figure 4. Rise Time - CLKs
Figure 5. Rise Time – VST, RESET, etc.
Figure 6. Rise Time – DISCHARGE
Figure 7. Rise Time - CLKs
Figure 8. Rise Time - VST, RESET, etc.
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Figure 9. Rise Time - DISCHARGE
Figure 10. Fall Time – CLKs
Figure 11. Fall Time – VST, RESET, etc.
Figure 12. Fall Time – DISCHARGE
Figure 13. Fall Time – CLKs
Figure 14. Fall Time – VST, RESET, etc.
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Figure 15. Fall Time – DISCHARGE
Figure 16. VSENSE Threshold – VSENSE, DISCHARGE
Figure 17. Power Up Sequence
Figure 18. Power Down Sequence
Figure 19. Small-Signal 3dB Bandwidth
Figure 20. Peak Output Current
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Figure 21. Slew Rate
DETAILED DESCRIPTION
Level Shifter
An internal block diagram of the level shifter block is shown in Figure 22.
VGH1
6
Gate
Shaping
CLK1-CLK6
VGL
RE
GCLK
MCLK
GST
EO
BI-SCAN
VGH1
5
4
State
Machine
VST
RESET
VGH_F
VGH_R
VGL
VGH2
2
ODD
EVEN
VGL
VGH1
DISCHG
VREF
VGL
Figure 22. Internal Block Diagram
State Machine
The state machine generates 12 output signals (all outputs except DISCHG) from the five input signals, as
described below.
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GCLK
The rising edge of GCLK defines the rising edge of the active CLK channel. The phase difference between
adjacent CLK signals is 60°, which means that the frequency of the output clocks is exactly one sixth the
frequency of the GCLK signal (see Figure 23 to Figure 26).
The falling edge of GCLK has no effect.
MCLK
The rising edge of MCLK defines the start of gate-shaping for the active CLK channel. The phase difference
between adjacent CLK signals is 60°, which means that the frequency of the output clocks is exactly one sixth
the frequency of the MCLK signal (see Figure 23 to Figure 26).
The falling edge of MCLK defines the falling edge of the active CLK channel (and, by definition, the end of gateshaping).
GST
The function of the GST signal depends on the state of GCLK when the GST pulse occurs. When GCLK is low
(see Figure 23 and Figure 29, and section describing VST behavior):
• the rising edge of GST defines the rising edge of VST
• the falling edge of GST defines the falling edge of VST
• the GST signal indicates the start of a new frame, and resets all internal counters in the state machine
When GCLK is high (see Figure 24 and Figure 26 and section describing RESET behavior):
• the rising edge of GST defines the rising edge of RESET
• the falling edge of GST defines the falling edge of RESET
EO
During normal operation a pulse applied to EO toggles the ODD and EVEN outputs (see section below
describing the ODD and EVEN outputs).
See also section describing Abnormal Operation.
BI-SCAN
The BI-SCAN signal is used to select forward or reverse operation.
During forward operation (BI-SCAN=low), VGH_F=high, VGH_R=low and the clock signals are output in the
following order:
(start of frame) 4 – 5 – 6 – 1 – 2 – 3 – 4 – 5 – 6 – 1 – 2 – 3 . . . . . 4 – 5 – 6 – 1 – 2 – 3 (end of frame)
During reverse operation (BI-SCAN=high), VGH_F=low, VGH_R=high and the clock signals are output in the
following order:
(start of frame) 3 – 2 – 1 – 6 – 5 – 4 – 3 – 2 – 1 – 6 – 5 – 4 . . . . . 3 – 2 – 1 – 6 – 5 – 4 (end of frame)
The BI-SCAN pin is internally pulled down by a 100kΩ (typical) resistor.
12
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RESET
CLK6
CLK5
CLK4
CLK3
CLK2
CLK1
VST
GCLK
MCLK
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GST
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Figure 23. Timing Diagram: Normal Operation, Start of Frame
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TPS65198
RESET
CLK6
CLK5
CLK4
CLK3
CLK2
CLK1
VST
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GCLK
MCLK
GST
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Figure 24. Timing Diagram: Normal Operation, End of Frame
14
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RESET
CLK6
CLK5
CLK4
CLK3
CLK2
CLK1
VST
GCLK
MCLK
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Figure 25. Timing Diagram: Reverse Operation, Start of Frame
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RESET
CLK6
CLK5
CLK4
CLK3
CLK2
CLK1
VST
GCLK
MCLK
GST
t9
t8
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Figure 26. Timing Diagram: Reverse Operation, End of Frame
16
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VGH_F and VGH_R
The VGH_F and VGH_R signals follow the BI-SCAN and GST inputs in accordance with Table 1.
Table 1. Truth Table
INPUTS
Normal
OUTPUTS
NORMAL OCCURRENCE
BI-SCAN
GST
Q
VGH_F
VGH_R
1
X
X
0
1
0
X
0
1
0
Forward, power-up
0
↑
1
1
0
Reverse to forward
0
0
0
1
0
Forward, power-down
0
0
1
0
1
Reverse, power-down
Abnormal
Reverse, power-up
Forward to reverse
Same as Normal mode
The VGH_F and VGH_R outputs feature a dead time (t12 and t13) such that when BI-SCAN changes state
VGH_F and VGH_R are temporarily both low before the active channel goes high (see Figure 27).
GST
BI-SCAN
VGH_F
VGH_R
t13
t12
Dead Time
Dead Time
Figure 27. VGH_F and VGH_R Operation, Showing Dead Time
To ensure the VGH_F and VGH_R outputs remain valid during power-down (when the BI-SCAN signal may not
be valid), the BI-SCAN signal is latched on every rising edge of GST (see Figure 28).
BI-SCAN
Latched signal used by
rest of internal circuitry
≥1
D
Q
GST
Figure 28. BI-SCAN Latching Scheme
The VGH_F and VGH_R channels follow a well defined characteristic during power-up and power-down (see
Power Supply Sequencing).
VST
The VST signal follows the GST and GCLK input signals in accordance with the truth table below (see also
Figure 23 to Figure 26).
INPUTS
OUTPUT
OPERATION
GST
GCLK
VST
Normal
1
0
1
1
1
0
0
X
0
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INPUTS
OUTPUT
OPERATION
GST
GCLK
VST
Abnormal
X
X
0
RESET
The RESET output is derived from the GST and GCLK signals in accordance with the truth table below (see also
Figure 23 to Figure 26).
INPUTS
OUTPUT
OPERATION
GST
GCLK
VST
Normal
0
X
0
1
0
0
1
1
1
X
X
0
Abnormal
ODD and EVEN
The ODD and EVEN outputs toggle on the rising edge of the EO input signal in accordance with the truth table
below. The pulse width of the EO signal defines a dead time during which both ODD and EVEN outputs are
temporarily low (see Figure 29).
INPUT
(1)
OUTPUTS
OPERATION
EO
EVEN
ODD
Power-Up
X
1
0
Normal
↑
Abnormal
X
toggle
1
(1)
toggle (1)
0
With dead time
EO
ODD
EVEN
Dead Time
Dead Time
Figure 29. ODD and EVEN Generation, Showing Dead Time
Abnormal Operation
The TPS65198 supports abnormal operation. Abnormal operation is detected when EO is high during the rising
edge of GST (see Figure 30), after which the level shifter outputs are forced to the following state:
1. CLK1-CLK6 low
2. VST, RESET low
3. ODD and EVEN in power-up state (EVEN high, ODD low) (2)
4. VGH_F and VGH_R not changed (outputs follow BI-SCAN input as in normal operation)
Normal operation is resumed the next time EO is low during the rising edge of GST. Upon exiting abnormal
operation the state machine adopts its normal start-of-frame initial state.
(2)
18
Note that because of the dead time introduced by the EO signal during normal operation, a short low pulse may appear on the EVEN
output when abnormal operation is detected (see Figure 30).
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Abnormal operation
indicated
Normal operation
indicated
GST
EO
ODD
EVEN
Figure 30. EO During Abnormal Operation, EVEN Initially High
Abnormal operation
indicated
Normal operation
indicated
GST
EO
ODD
EVEN
Figure 31. EO During Abnormal Operation, EVEN Initially Low
CLK1 to CLK6
The CLK outputs go high on the rising edge of GCLK and go low on the falling edge of MCLK. The CLK outputs'
frequency is exactly one sixth of the GCLK and MCLK frequencies and adjacent CLK channels are separated by
60° phase difference.
The CLK outputs are generated in a specific order that depends on whether the device is operating in forward or
reverse mode (see Figure 23 to Figure 26 and the section describing BI-SCAN operation).
Gate Voltage Shaping
The clock outputs CLK1 to CLK6 support gate voltage shaping, which can help reduce image flickering in certain
applications. A simplified block diagram of one of the clock channels is shown in Figure 32.
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VGH1
Q1
GCLK
MCLK
State
Machine
CLK
Q2
Q3
VGL
RE
Figure 32. CLK Output Stage
•
•
•
On the rising edge of the GCLK, the active channel's Q1 is enabled and its Q2 disabled; the output goes to
VGH1.
Gate voltage shaping starts on the rising edge of MCLK, which disables Q1 and enables Q3. The LCD panel's
pixel and storage capacitor now discharge through Q3 at a rate determined by the external resistor RE (see
Figure 33).
On the falling edge of MCLK, Q3 is disabled and Q2 enabled; the output goes to VGL.
GCLK÷6
MLK
CLKOUTx
Figure 33. Gate Shaping Timing Diagram
Panel Discharge
In addition to the 12 level shifter channels described above, the TPS65198 contains one output specifically
intended for discharging the LCD panel during power-down (see Figure 34). The discharge channel uses the
input signal connected to the VSENSE pin, which features a Schmitt trigger input stage. Figure 34 and Figure 35
show the discharge behavior during power-up and power-down.
20
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SLVSAT4B – JUNE 2011 – REVISED JULY 2013
VLOGIC
VGH1
VSENSE
-
VREF
+
VGH1
Level
Shifter
DSCHG
VGL
Note: Comparator is NOT disabled by UVLO.
Figure 34. Discharge Internal Block Diagram
When the discharge function is active, the level shifter outputs enter Abnormal Mode, as defined below.
Power Supply Sequencing (CLK1-CLK6, VST, RESET)
These outputs track VGL when VGH1VREF (see Figure 35 and Figure 36).
Power Supply Sequencing (ODD, EVEN)
EVEN tracks VGL when VGH1VUVLO and VSENSE>VREF (see Figure 35
and Figure 36). EVEN tracks VGH when VSENSEVREF (see Figure 35
and Figure 36). ODD tracks VGL when VSENSEVUVLO
VGH2
VGL
Min. operating voltage
BI-SCAN
VGH_F
VGH_R
EVEN
ODD
CLKs
DISCHRG
Figure 36. Power Supply Sequencing During Reverse Operation
Operational Amplifier
The operational amplifier included in the TPS65198 has been optimized for buffering the VCOM voltage used in
LCD panels. Its high slew rate, high output current and wide bandwidth enable it to drive the dynamic loads
present on VCOM. Like most operational amplifiers, this amplifier may become unstable if a highly capacitive load
is connected to its output. It is therefore recommended not to connect additional capacitance between VCOM and
GND in an attempt to decouple it. Not only could this create stability problems, the high performance of the
operational amplifier mean that such measures are unnecessary in typical applications.
AVDD
POS
+
NEG
-
OUT
GND
Figure 37. Operational Amplifier Block Diagram
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APPLICATION INFORMATION
VGH1
VGH2
10 µF
From T-CON
1 µF
16
17
VGH1
VGH2
27
)
1
GCLK
CLK1
MCLK
CLK2
2
26
3
25
GST
CLK3
EO
CLK4
BI-SCAN
CLK5
24
4
5
28
6
CLK6
12
VLOGIC
TPS65198
VST
13
RESET
10
ODD
100 Ω
11
23
VSENSE
EVEN
9
3 kΩ
VGH_F
8
VGH_R
14
21
AVDD
DISCHARGE
AVDD
10 µF
18
10 kΩ
OUT
19
20
POS
)
To LCD Panel
NEG
10 kΩ
GND
22
VGL
15
RE
7
2 kΩ
10µF
VGL
Figure 38. Typical Application Circuit
24
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SLVSAT4B – JUNE 2011 – REVISED JULY 2013
REVISION HISTORY
Changes from Original (June 2011) to Revision A
Page
•
Changed Condition statement of the Electrical Characaterisics table from TJ to TA ............................................................ 3
•
Changed Condition statement of the Electrical Characaterisics table from TJ to TA ............................................................ 4
•
Added IPK spec to Elec Characteristics table. ....................................................................................................................... 4
Changes from Revision A (November 2011) to Revision B
•
Page
Changed VIH spec from 2.0 MAX to 1.4 MAX in Typical Characteristics ............................................................................. 3
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25
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS65198RUYR
ACTIVE
WQFN
RUY
28
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65198
TPS65198RUYT
ACTIVE
WQFN
RUY
28
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65198
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jan-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jan-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS65198RUYR
WQFN
RUY
28
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
TPS65198RUYT
WQFN
RUY
28
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
TPS65198RUYT
WQFN
RUY
28
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jan-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65198RUYR
WQFN
RUY
28
3000
367.0
367.0
35.0
TPS65198RUYT
WQFN
RUY
28
250
210.0
185.0
35.0
TPS65198RUYT
WQFN
RUY
28
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65198RUYR
ACTIVE
WQFN
RUY
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65198
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of