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TPS65200
SLVSA48A – APRIL 2010 – REVISED SEPTEMBER 2015
TPS65200 Li+ Battery Charger With WLED Driver and Current Shunt Monitor
1 Features
•
1
•
•
2 Applications
•
•
•
•
Mobile Phones and Smart Phones
MP3 Players
Portable Navigation Devices
Handheld Devices
3 Description
The TPS65200 device integrates a high-efficiency,
USB-friendly switched-mode charger with OTG
support for single-cell Li-ion and Li-polymer batteries,
D+D- detection, a 50-mA fixed-voltage LDO, a highefficiency WLED boost converter, and high-accuracy
current-shunt monitor into a single chip.
The TPS65200 comes in a tiny, 2.8-mm × 2.6-mm,
36-pin, 0.4-mm pitch die size ball grid array
(DSBGA).
Device Information(1)
PART NUMBER
TPS65200
PACKAGE
BODY SIZE (NOM)
DSBGA (36)
2.60 mm × 2.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Charging Curve
1000
4.30
900
4.25
Charging Current
800
4.20
700
4.15
600
4.10
500
4.05
400
4.00
300
B a tte ry V o l ta g e [V ]
•
Battery Switching Charger, WLED Driver, and
Current Shunt Monitor in a Single Package
Battery Charger
– Charges Faster Than Linear Chargers
– High-Accuracy Voltage and Current Regulation
– Input Current Regulation Accuracy: ±5%
(100 mA, 500 mA)
– Charge Voltage Regulation Accuracy:
±0.5% (25°C)
±1% (0 - 125°C)
– Charge Current Regulation Accuracy: ±5%
– Bad Adaptor Detection and Rejection
– Safety Limit Register for Maximum Charge
Voltage and Current Limiting
– High-Efficiency Mini-USB/AC Battery Charger
for Single-Cell Li-Ion and Li-Polymer Battery
Packs
– Built-In Input Current Sensing and Limiting
– Integrated Power FETs for Up to 1.25-A
Charge Rate
– Programmable Charge Parameters through I2C
Interface (Up to 400 Kbps):
– Input Current
– Fast-Charge/Termination Current
– Charge Voltage (3.5 V - 4.44 V)
– Safety Timer
– Termination Enable
– Synchronous Fixed-Frequency PWM
Controller Operating at 3 MHz With 0% to
99.5% Duty Cycle
– Safety Timer With Reset Control
– Reverse Leakage Protection Prevents Battery
Drainage
– Thermal Regulation and Protection
– Input/Output Overvoltage Protection
– Automatic Charging
– Boost Mode Operation for USB OTG
– Input Voltage Range (VSYS): 2.5 V to
4.5 V
– Output Voltage for VBUS: 5 V
WLED Driver
– 35-V Open LED Protection for Up to 8 LEDs
– 200-mV Reference Voltage With ±2%
Accuracy
– Built-In Soft Start for WLED Boost
C h a r g in g C u rr e n t [m A ]
•
1
– Up to 90% Efficiency
Current Shunt Monitor
– Fixed Gain of 25 V/V
– Input Referred Offset Voltage Less Than
±40 µV Typical Enables Use of Shunt
Resistors as Low as 20 mΩ
– Buffered Reference Voltage
Package
– 36-Ball, 0.4-mm Pitch DSBGA Package
3.95
Battery Voltage
200
3.90
100
3.85
0
0
2000
4000
6000
8000
10000
3.80
12000
time [s]
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65200
SLVSA48A – APRIL 2010 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Data Transmission Timing ...................................... 10
Typical Characteristics ............................................ 11
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 24
7.5 Programming........................................................... 35
7.6 Register Maps ......................................................... 36
8
Application and Implementation ........................ 50
8.1 Application Information............................................ 50
8.2 Typical Application .................................................. 50
9 Power Supply Recommendations...................... 53
10 Layout................................................................... 53
10.1 Layout Guidelines ................................................. 53
10.2 Layout Example .................................................... 54
11 Device and Documentation Support ................. 55
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
55
55
55
55
55
12 Mechanical, Packaging, and Orderable
Information ........................................................... 55
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2010) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SLVSA48A – APRIL 2010 – REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
F
BOOT
SDA
SCL
DM
PGND
SWL
E
VBUS
VBUS
VIO
DP
FB
COMP
D
PMID
PMID
PMID
INT
CTRL
LDO
C
SWC
SWC
SWC
OTG
VSHNT
VSYS
B
PGND
PGND
PGND
STAT
SGND
VZERO
A
BAT
CSOUT
CSIN
VDD
VSHRT
DGND
1
2
3
4
5
6
TI YMLLLLS
TPS65200
YFF Package
36-Pin DSBGA
Bottom View, Top View
TI
YM
LLLL
S
= TI LETTERS
= YEAR / MONTH DATE CODE
= LOT TRACE CODE
= ASSEMBLY SITE CODE
O
= Pin A1 (Filled Solid)
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
A1
BAT
O
Output of the linear charger and battery voltage sense. Connect the battery from this pin to ground.
A2
CSOUT
I
Charge current-sense input. Battery current is sensed through the voltage drop across an external sense
resistor. A 0.1-μF ceramic capacitor to PGND is required.
A3
CSIN
I
Charge current-sense input. Battery current is sensed through the voltage drop across an external sense
resistor. A 0.1-μF ceramic capacitor to PGND is required.
A4
VDD
O
Internal supply for battery charger. Connect a 1-mF ceramic capacitor from this output to PGND. External load
on VDD is not recommended.
A5
VSHRT
I
The voltage on this pin defines the battery voltage for transitioning from linear charge (pre-charge) to fast
charge. A 10-µA current source is internally connected to this pin. Connect a resistor from this pin to ground to
setup VSHORT reference. If the pin is left floating or tied to VDD an internal VSHORT reference of 2.1 V is
used.
A6
DGND
Digital ground
PGND
Power ground
B1
B2
B3
O
Charge status pin. Pulled low when charge in progress. Open drain for other conditions. This pin can also be
controlled through I2C register. STAT can be used to drive a LED or communicate with a host processor.
B4
STAT
B5
SGND
B6
VZERO
I
This pin sets the zero-current output voltage level of the current shunt monitor.
SWC
O
Internal switch to inductor connection (charger)
C4
OTG
I
Boost control pin. Boost mode is turned on whenever this pin is active. Polarity is user defined through I2C
register. The pin is disabled by default and can be enabled through I2C register bit.
C5
VSHNT
O
Output of current shunt monitor. For positive currents (into battery) VSHNT > VZERO. For negative currents
(out of the battery) VSHNT < VZERO.
C6
VSYS
I
Input supply for WLED driver and current shunt monitor
PMID
O
Connection point between reverse blocking MOSFET and high-side switching MOSFET. Bypass it with a
minimum of 1-μF capacitor from PMID to PGND. No other circuits are recommended to connect at PMID pin.
INT
O
Interrupt pin (open-drain). This pin is pulled low to signal to the main processor that a fault has occurred.
Signal ground
C1
C2
C3
D1
D2
D3
D4
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
D5
CTRL
I
Control pin of the LED boost regulator. It is a multi-functional pin which can be used for enable control and
PWM dimming.
D6
LDO
O
LDO output. LDO is regulated to 4.9 V and drives 60-mA of current. Bypass LDO to GND with at least a 1-μF
ceramic capacitor. LDO is enabled when VBUS is above the VBUS UVLO threshold.
VBUS
I/O
Charger input voltage. Bypass it with a 1-μF ceramic capacitor from VBUS to PGND. It also provides power to
the load in boost mode.
E3
VIO
I
I/O reference voltage. A VIO level above 0.6 V disables automatic D+/D- detection.
E4
DP
I
USB port D+ input connection
E5
FB
I
Feedback pin for current. Connect the sense resistor from FB to GND.
E6
COMP
O
Output of the transconductance error amplifier. Connect an external capacitor to this pin to compensate the
regulator.
F1
BOOT
O
Boot-strapped capacitor for the high-side MOSFET gate driver. Connect a 10-nF ceramic capacitor (voltage
rating above 10 V) from BOOST pin to SWC pin.
F2
SDA
I/O
I2C interface data
F3
SCL
I
I2C interface clock
F4
DM
I
USB port D- input connection
F5
PGND
F6
SWL
E1
E2
Power ground
I
This is the switching node of the LED driver. Connect the inductor from the supply to the SWL pin. This pin is
also used to sense the output voltage for open LED protection.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage (with respect to PGND)
Input/Output voltage (with respect to
PGND)
(1) (2)
VBUS
MIN
MAX
UNIT
V
–2
20
SDA, SCL, DM, DP, SWL, VZERO, VSHRT, CSIN,
CSOUT, CSOT, LDO, INT, OTG, VSYS, VSHNT,
VDD, VIO, BAT, CTRL
–0.3
7
PMID, STAT
–0.3
VDD
20
6.5
SWC, BOOT
–0.7
FB,COMP
–0.3
3
SWL
–0.3
44
Voltage difference between CSIN and CSOUT inputs (VCSIN -VCSOUT)
V
20
±7
V
Output current (average)
SWC
1.5
A
Output current (continuous)
LDO
100
mA
85
°C
TA
Operating ambient temperature
–40
TJ
Max operating junction temperature
150
°C
TC
Max operating case temperature
150
°C
150
°C
Tstg Storage temperature
(1)
(2)
4
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
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SLVSA48A – APRIL 2010 – REVISED SEPTEMBER 2015
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VBUS
Supply voltage
4
6
V
SWL
Output voltage
VBAT
39
V
6.4 Thermal Information
TPS65200
THERMAL METRIC
(1)
YFF (DSBGA)
UNIT
36 PINS
RθJA
Junction-to-ambient thermal resistance
54.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.2
°C/W
RθJB
Junction-to-board thermal resistance
8.5
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
8.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2
10
UNIT
INPUT CURRENTS
Charger Hi-Z mode
WLED disabled
Shunt monitor
disabled
IDISCHARGE
Battery discharge current in high
Impedance mode (CSIN,
CSOUT,SWC, SWL, BAT, VSYS
pins)
0°C < TJ < 85°C,
VBAT = 4.2 V
Charger Hi-Z mode
WLED enabled, no
load
Shunt monitor
disabled
1800
Charger HiZ mode
WLED disabled Shunt
monitor enabled
IVBUS
VBUS supply current
VBUS > VBUS(min)
60
Charger PWM ON
10000
Charger PWM OFF
5000
0°C < TJ < 85°C, HZ_MODE = 1
IVBUS_LEAK
Leakage current from battery to
VBUS pin
µA
µA
15
0°C < TJ < 85°C, VBAT = 4.2 V HiZ mode
5
µA
3.5
4.44
V
–0.5%
0.5%
–1%
1%
VOLTAGE REGULATION
Output charge voltage
VOREG
Voltage regulation accuracy
Operating in voltage regulation,
programmable
TA = 25°C
Full temperature range
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Electrical Characteristics (continued)
VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VSHRT ≤ VCSOUT < VOREG
VBUS > 5 V, RSNS = 20 mΩ,
LOW_CHG = 0, Programmable
550
TYP
MAX
UNIT
CURRENT REGULATION -FAST CHARGE
IOCHARGE
Output charge current
1250
mA
VLOWV ≤ VCSOUT < VOREG,
VBUS > 5 V, RSNS = 20 mΩ,
LOW_CHG = 1
150
200
CHARGE TERMINATION DETECTION
ITERM
Termination charge current
VCSOUT > VOREG-VRCH, VBUS > 5 V,
RSNS = 20 mΩ, Programmable
Deglitch time for charge termination
Both rising and falling, 2-mV overdrive,
tRISE, tFALL = 100 ns
50
400
30
mA
ms
CHARGE CURRENT ACCURACY
VOS, CHRGR
Offset voltage, sense voltage
amplifier
Charge current accuracy =
VOS/(ISETxRSNS)
TA = 0°C to 85°C
–1
Input voltage lower limit
Bad adaptor detection, VBUS falling
3.6
Deglitch time for VBUS rising above
VIN(MIN)
Rising voltage, 2-mV over drive,
tRISE = 100 ns
Hysteresis for VIN(MIN)
VBUS rising
IADET
Current source to GND
During bad adaptor detection
TINT
Detection interval
Input power source detection
1
mV
4
V
BAD ADAPTOR DETECTION
VIN(MIN)
3.8
30
100
20
30
ms
200
mV
40
mA
2
s
INPUT BASED DYNAMIC POWER MANAGEMENT
VIN_LOW
The threshold when input based
DPM loop kicks in
Charge mode, programmable
DPM loop kick-in threshold
tolerance
4.2
4.76
–2%
2%
V
INPUT CURRENT LIMITING
IIN_LIMIT
Input current limiting threshold
IIN_LIMIT = 100 mA
88
93
98
IIN_LIMIT = 500 mA
450
475
500
IIN_LIMIT = 975 mA
875
925
975
mA
VDD REGULATOR
Internal bias regulator voltage
VDD
VBUS > VIN(min) or VSYS > VBATMIN,
IVDD = 1 mA, CVDD = 1 μF
2
VDD output short current limit
Voltage from BST pin to SWC pin
6.5
30
During charge or boost operation
V
mA
6.5
V
160
mV
BATTERY RECHARGE THRESHOLD
VRCH
Recharge threshold voltage
Below VOREG
Deglitch time
VCSOUT decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive
100
130
130
ms
STAT OUTPUT
VOL(STAT)
Low-level output saturation voltage
IO = 10 mA, sink current
High-level leakage current
Voltage on STAT pin is 5 V
0.4
V
1
µA
REVERSE PROTECTION COMPARATOR
Reverse protection threshold, VBUS-
VREV
VCSOUT
VREV-EXIT
6
2.3 V ≤ VCSOUT ≤ VOREG, VBUS falling
Reverse protection exit hysteresis
2.3 V ≤ VCSOUT ≤ VOREG
Deglitch time for VBUS rising above
VREV + VREV_EXIT
Rising voltage
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0
40
100
mV
140
200
260
mV
30
ms
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SLVSA48A – APRIL 2010 – REVISED SEPTEMBER 2015
Electrical Characteristics (continued)
VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.05
3.3
3.55
120
150
mV
3
MHz
VBUS UVLO
VUVLO
IC active threshold voltage
VBUS rising
VUVLO_HYS
IC active hysteresis
VBUS falling from above VUVLO
V
PWM
fPWM
RDSON
PWM frequency, charger
Internal top reverse blocking
MOSFET on-resistance
IIN_LIMIT = 500 mA,
Measured from VBUS to PMID
180
Internal top N-channel Switching
MOSFET on-resistance
Measured from PMID to SWC
120
Internal bottom N-channel
MOSFET on-resistance
Measured from SW to PGND
150
DMAX
Maximum duty cycle
DMIN
Minimum duty cycle
Synchronous mode to
nonsynchronous mode transition
current threshold (1)
mΩ
99.5%
0%
Low-side MOSFET
cycle-by-cycle current sensing
100
mA
BOOST MODE OPERATION FOR VBUS (OPA_MODE=1, HZ_MODE=0)
VBUS_B
Boost output voltage (to pin VBUS)
2.5 V < VBUS < 4.5 V; Including line and
load regulation over full temp range
4.75
IBO
Maximum output current for boost
VBUS_B = 5 V, 2.5 V < VBUS < 4.5 V
200
IBLIMIT
Cycle by cycle current limit for
boost
VBUS_B = 5 V, 2.5 V < VSYS < 4.5 V
VBUSOVP
Overvoltage protection threshold for Threshold over VBUS to turn off converter
boost (VBUS pin)
during boost
VBATMAX
VBATMIN
5
1
5.8
6
VBUS falling from above VBUSOVP
Maximum battery voltage for boost
VSYS rising edge during boost
VBATMAX hysteresis
VSYS falling from above VBATMAX
200
Minimum battery voltage for boost
(VSYS pin)
During boosting
2.5
Before boost starts
2.9
A
6.2
200
4.75
HZ_MODE = 1
500
Input VBUSOVP threshold voltage
Threshold over VBUS to turn off converter
during charge
6.3
VOVP_IN_USB hysteresis
VBUS falling from above VOVP_IN
Battery OVP threshold voltage
VCSOUT threshold over VOREG to turn off
charger during charge (% VOREG)
VOVP hysteresis
Lower limit for VCSOUT falling from > VOVP
(% VOREG)
Cycle-by-cycle current limit for
charge
Charge mode operation
V
mA
VBUSOVP hysteresis
Boost output resistance at high
impedance mode (From VBUS to
PGND)
5.25
4.9
V
mV
5.05
V
mV
3.05
V
kΩ
CHARGER PROTECTION
VOVP-IN_USB
VOVP
ILIMIT
VCSOUT rising, VSHRT connected to VDD
Trickle to fast charge threshold
VSHORT
(1)
Resistor connected from VSHRT to GND
Internal current source connected
to VSHRT pin
VCSOUT falling from above VSHORT
Enable threshold for internal
VSHORT reference
percentage of VDD
6.7
140
110%
117%
V
mV
121%
11%
1.8
2.4
2
2.1
1.8
9.4
VSHORT hysteresis
6.5
10
3
A
2.2
V
VBUS –
0.7
V
10.6
µA
100
mV
90%
Bottom N-channel MOSFET always turns on for approximately 60 ns and then turns off if current is too low.
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Electrical Characteristics (continued)
VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
30
40
UNIT
ISHORT
Trickle charge charging current
VCSOUT ≤ VSHORT
TCF
Thermal regulation threshold
Charge current begins to taper down
120
°C
T32S
Time constant for the 32-second
timer
32 second mode
32
s
20
mA
WLED VOLTAGE AND CURRENT CONTROL
VREF
Voltage feedback regulation voltage
VREF_PWM
Voltage feedback regulation voltage VFB[4:0] = 01110 (VFB = 25%)
under brightness control
VFB[4:0] = 01110 (VFB = 10%)
fCTRL
PWM dimming frequency
tCNTRL, MIN
Minimum on-time for PWM dimming
pulse
IFB
Voltage feedback input bias current
fPWM
PWM frequency, WLED boost
Dmax
Maximum duty cycle
tmin_on
Minimum 0N pulse width
L
Inductor
COUT
Output capacitor
198
203
208
47
50
53
17
20
23
1
100
2.2
1
600
90%
mV
kHz
µs
VFB = 200 mV
VFB = 100 mV
mV
µA
kHz
93%
40
ns
10
22
µH
0.47
10
µF
600
mΩ
1
µA
WLED POWER SWIITCH
RDS(on)
N-channel MOSFET on-resistance
VSYS = 3.6 V
ILN_NFET
N-channel leakage current
VSWL = 30 V, TA = 25°C
300
WLED PROTECTION
VUVLO
Under Voltage Lock Out (VSYS pin) VSYS falling
2.2
UVLO hysteresis
70
VOVP
Overvoltage Protection threshold
ILIM
N-Channel MOSFET current limit
D = Dmax
ILIM_Start
Startup current limit
D = Dmax
tHALF_LIM
Time step for half current limit
tREF
tstep
2.5
V
mV
35
37
39
V
560
700
840
mA
400
mA
5
ms
VREF filter time constant
180
µs
VREF ramp up time
213
µs
CURRENT SHUNT MONITOR
VCM
Common-mode input range
VCSIN = VCSOUT
–0.3
CMR
Common-mode rejection
VCSIN = 2.7 V to 5 V, VCSIN – VCSOUT = 0
mV
100
VOS, CSM
Offset-voltage, referred to input
TA = 0°C to 60°C
–75
75
TA = -20°C to 85°C
–85
85
G
Gain
–1%
VSYS - VSHNT
Swing to GND
VSHNT - VGND
GBW
Bandwidth
CLOAD = 10 pF
IVZERO
VZERO bias current
TA = -20°C to 85°C
VZERO
Swing to positive power supply rail
(VSYS)
VSYS – VZERO
Swing to GND
VZERO - VGND
Undervoltage lockout (VSYS pin)
VSYS falling
VUVLO
8
UVLO hysteresis
µV
V/V
1%
100
mV
100
9
kHz
10
1.5
nA
V
0.7
2.2
70
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V
dB
25
Gain error
Swing to positive power supply rail
(VSYS)
VSHNT
7
2.5
V
mV
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Electrical Characteristics (continued)
VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.8
4.9
5
UNIT
LDO
VLDO
LDO Output Voltage
VIN = 5.5V
PSRR
f = 100 Hz, CLDO = 1.0 μF
ILDO
Maximum LDO Output Current
VDO
Dropout Voltage
60
60
VIN = 4.5 V, ILDO = 50 mA
V
dB
mA
100
250
mV
0.6
0.7
V
100
150
DM pin, switch open
4.5
5
DP pin, switch open
4.5
5
D+/D- DETECTION
VDP_SCR
IDM_SINK
D+ voltage source
0.5
D+ voltage source output current
250
D- current sink
50
CI
Input capacitance
II
Input leakage
VDP_LOW
DP low comparator threshold
0.8
VDM_HIGH
DM high comparator threshold
0.8
VDM_LOW
DM low comparator threshold
µA
DM pin, switch open
–1
1
DP pin, switch open
–1
1
µA
pF
µA
V
V
475
mV
LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, CTRL, INT)
Output low threshold level
VOL
IO = 3 mA, sink current (SDA, INT)
0.4
Input low threshold level
0.4
Input high threshold level
I(bias)
Input bias current (SCL, SDA, INT)
fSCL
SCL clock frequency
RCTRL
CTRL pulldown resistor
tOFF
CTRL pulse width to shutdown
V
1.2
VIO = 1.8 V
400
CTRL high to low
800
1
µA
400
kHz
1600
kΩ
2.5
7-bit slave address
ms
1101 010
OSCILLATOR
fOSC
Oscillator frequency
Frequency accuracy
3
TA = –40°C to 85°C
–10%
MHz
10%
THERMAL SHUTDOWN
TSHTDWN
Thermal trip point
165
Thermal hysteresis
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6.6 Data Transmission Timing
VBAT = 3.6 ±5%, TA = 25 ºC, CL = 100 pF (unless otherwise noted)
MIN
NOM
MAX
Standard mode
100
Fast mode
400
f(SCL)
Serial clock frequency
t(BUF)
Bus free time between stop and start SCL = 100 kHz
condition
SCL = 400 kHz
t(SP)
Tolerable spike width on bus
tLOW
SCL low time
tHIGH
SCL high time
tS(DAT)
SDA → SCL setup time
tS(STA)
Start condition setup time
tS(STO)
Stop condition setup time
tH(DAT)
SDA → SCL hold time
tH(STA)
Start condition hold time
tr(SCL)
Rise time of SCL Signal
tf(SCL)
Fall time of SCL Signal
tr(SDA)
Rise time of SDA Signal
tf(SDA)
Fall time of SDA Signal
4.7
50
SCL = 400 kHz
t LOW
SCL = 100 kHz
4.7
SCL = 400 kHz
1.3
SCL = 100 kHz
4
SCL = 400 kHz
0.6
SCL = 100 kHz
250
SCL = 400 kHz
100
SCL = 100 kHz
4.7
SCL = 400 kHz
0.6
µs
ns
µs
4
SCL = 400 kHz
0.6
SCL = 100 kHz
0
3.45
SCL = 400 kHz
0
0.9
4
SCL = 400 kHz
0.6
µs
µs
µs
SCL = 100 kHz
1000
SCL = 400 kHz
300
SCL = 100 kHz
300
SCL = 400 kHz
300
SCL = 100 kHz
1000
SCL = 400 kHz
300
SCL = 100 KHz
300
SCL = 400 kHz
300
t r(
ns
µs
SCL = 100 kHz
SCL = 100 kHz
KHz
µs
1.3
SCL = 100 kHz
UNIT
ns
ns
ns
ns
t H( STA)
tF
SCL
t H(STA)
t H(DAT)
t HIGH
t S(DAT)
tS(STA)
t S(STO)
SDA
t (BUF)
P
S
S
P
Figure 1. I2C Data Transmission Timing
10
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6.7 Typical Characteristics
TA = 25°C, unless otherwise specified.
6.7.1 Switching Charger
VBUS = 5 V
ICHARGE = 150 mA
VBUS = 5 V
Figure 2. PWM Charge Operation
ICHARGE = 150 mA
Figure 3. PWM Charge Operation
1000
4.30
900
4.25
4.20
700
4.15
600
4.10
500
4.05
400
4.00
300
B a tte ry V o l ta g e [V ]
C h a r g in g C u rr e n t [m A ]
Charging Current
800
3.95
Battery Voltage
200
3.90
100
3.85
0
0
2000
4000
6000
8000
3.80
12000
10000
time [s]
1500 mAh Li-ion
RIN = 60 Ω
VBUS = 5.5 V
Figure 5. Charging Curve
1000
700
4.5
Charging Current
4.25
600
4
700
3.75
Battery Voltage
600
3.5
VSHORT set to 2.8V
500
3.25
400
3
300
2.75
200
2.5
LOW_ICHG bit set
(150mA)
100
2
100
200
300
IIN_limit = 975 mA
400
300
200
100
400
time [s]
ICHARGE = 950 mA
500
2.25
0
0
(V B U S -V B A T ) [m V ]
800
B a tte ry V o l ta g e [V ]
C h a r g i n g C u rr e n t [m A ]
ICHARGE = 950 mA
IIN_limit = 975 mA
VBAT = 3 V (#165)
Figure 4. Bad Adaptor Detection
900
5.55 Whr
0
VSHORT = 2.8 V
0
400
800
1200
1600
2000
Charge current [mA]
Figure 6. Precharge Curve
Figure 7. Effective Dropout Voltage
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Switching Charger (continued)
100%
98%
96%
VBAT=4.0V
E f fici en cy
94%
VBAT=3.6V
92%
90%
88%
VBAT=2.8V
86%
VBAT=2.5V
84%
82%
80%
0.4
0.6
0.8
1
1.2
1.4
1.6
Charging Current[A]
VBUS = 5.5 V
Figure 8. Charger Efficiency
6.7.2 OTG Boost
VBAT = 3.8 V
ILOAD = 200 mA
Figure 9. Start Up
12
VBAT = 3.8 V
ILOAD = 200 mA
Figure 10. Shutdown
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OTG Boost (continued)
VBAT = 3.8 V
ILOAD = 1 mA
Figure 11. PWM Boost Operation
VBAT = 3.8 V
ILOAD = 200 mA
Figure 13. PWM Boost Operation
VBAT = 3.8 V
ILOAD = 200 mA
Figure 15. I2C Controlled Voltage Step
VBAT = 3.8 V
ILOAD = 30 mA
Figure 12. PWM Boost Operation
VBAT = 3.8 V
ILOAD = 5 mA - 200 mA
Figure 14. Transient Response
VBAT = 3.8 V
ILOAD = 200 mA
Figure 16. I2C Controlled Voltage Step
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6.7.3 LDO
Figure 17. Turnon Delay
Charger = ON at 950 mA
Figure 18. Turnoff Delay
VBUS = 5.5 V
Charger = ON at 950 mA
Figure 19. Start-Up
50 mA Load, Charger = ON at 950 mA
Figure 20. Shutdown
VBUS = 5.5 V
50 mA Load, Charger = ON at 950 mA
Figure 21. Start-Up
14
VBUS = 5.5 V
VBUS = 5.5 V
Figure 22. Shutdown
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LDO (continued)
100%
VBAT=4.2V
95%
VBAT=3.6V
E f fici en cy
90%
85%
VBAT=2.9V
80%
75%
70%
65%
60%
0
0.05
0.1
0.15
0.2
0.25
0.3
Output Current [A]
VBUS = 5.5 V
Charger OFF
ILOAD = 5 mA to 50 mA
VBUS = 5.5 V
Figure 23. Transient Response
Figure 24. OTG Boost Efficiency
6.7.4 WLED Boost
VBAT = 3.8 V
VFB = 200 mV
7 LEDs
VBAT = 3.8 V
Figure 25. Start-Up
VFB = 200 mV
7 LEDs
Figure 26. Shutdown
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WLED Boost (continued)
VBAT = 4.2 V
VFB = 200 mV
7 LEDs
VBAT = 4.2 V
Figure 27. PWM Operation
VBAT = 3 V
VFB = 200 mV
VBAT = 3.8 V
7 LEDs
VBAT = 3 V
VFB = 20 mV
7 LEDs
Figure 30. PWM Operation
VFB = 200 mV
VBAT = 3.8 V
Figure 31. PWM Dimming
16
7 LEDs
Figure 28. PWM Operation
Figure 29. PWM Operation
50% Duty Cycle
7 LEDs
VFB = 20 mV
VFB = 200 mV
7 LEDs (#162)
Figure 32. Open LED Protection
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WLED Boost (continued)
90%
90%
6 LEDs
4 LEDs
VBAT=4.2V
85%
85%
80%
80%
VBAT=2.8V
10 LEDs
E f fici en cy
E f fici en cy
8 LEDs
75%
70%
70%
65%
65%
60%
60%
55%
55%
50%
VBAT=3.6V
75%
50%
0
5
10
15
20
0
5
10
WLED current [mA]
15
20
WLED current [mA]
VBAT = 3.3 V
6 LEDs
Figure 33. Efficiency
Figure 34. Efficiency
Pulse Duty Cycle [%]
0.1
1
10
100
1
V F B [V ]
0.1
0.01
0.001
VBAT = 3.8 V
FPWM = 5 kHz
7 LEDs
Figure 35. WLED Dimming Linearity
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7 Detailed Description
7.1 Overview
The TPS65200 charger features a synchronous 3-MHz PWM controller with integrated power MOSFETs, input
current sensing and regulation, input-voltage dynamic power management, high-accuracy charge current and
voltage regulation, and charge termination. The charger charges the battery in three phases: low-current
precharge, constant current fast-charge, and constant voltage trickle-charge. The input current is automatically
limited to the value set by the host. The charger can be configured to terminate charge based on user-selectable
minimum current level and to automatically restart the charge cycle if the battery voltage falls below the recharge
threshold. A safety timer with reset control provides a safety backup for I2C interface. The charger automatically
enters sleep mode or high impedance mode when the input supply is removed. The charge status is reported to
the host using the I2C interface and STAT pin. The D+D- detection circuit allows automatic detection of a USB
wall-charger. If a wall-charger is detected the input current limit is automatically increased from 500 mA to 975
mA.
In OTG mode the PWM controller boosts the battery voltage to 5 V and provides up to 200-mA of current to the
USB output. At very light loads the boost operates in burst mode to optimize efficiency. OTG mode can be
enabled either through I2C interface or GPIO control.
The TPS65200 also provides a WLED boost converter with integrated 40-V switch FET, that drives up to 10
WLEDs in series. The boost converter runs at 600-kHz fixed switching frequency to reduce output ripple, improve
conversion efficiency, and allows for the use of small external components. The default WLED current is set with
a sense resistor, and the feedback voltage is regulated to 200 mV, as shown in the typical application. For
brightness dimming, the feedback voltage can be changed through the I2C interface or by application of a PWM
signal to the CTRL pin. In the latter case the feedback voltage is regulated down proportional to the PWM duty
cycle (analog dimming) rather than pulsing the LED current to avoid audible noise on the output capacitor. For
maximum protection, the device features integrated open LED protection that disables the TPS65200 to prevent
the output from exceeding the absolute maximum ratings during open LED conditions.
A fixed-gain, high-accuracy current shunt monitor senses the voltage drop across an external, 20-mΩ sense
resistor and provides an analog output voltage that is proportional to the charge/discharge current of the battery.
The sense voltage is amplified by a factor of 25 and offset by VZERO, an externally provided reference voltage.
VZERO is internally buffered to avoid loading of the reference source.
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7.2 Functional Block Diagram
VSYS
CTRL
from uC
TSD
DGND
SGND
10mH
SWL
BG/BIAS
WLED
Driver
0.47 mF
LDO
to load
220nF
COMP
LDO
4.9V, 60mA
PGND
UVLO
FB
PMID
1mF
VBUS
from USB connector
R SET
10W
1mF
Q1
1mF
VSHRT
BOOT
10mA
10nF
System Load
1m H
R SNS
SWC
VIO
Single cell
Li+ Battery
Q2
VIO
20mW
10mF
0.6 V
Q3
10mF
PGND
DP
DM
from USB port
from USB port
VIO
D+/Ddetection
Switching
Charger
0.1mF
VIO
CSIN
SCL
SDA
from uC
from /to uC
0.1mF
CSOUT
VDD
I2C
1mF
BAT
VBAT
OSC
STAT
VIO
INT
DIGITAL
Current Shunt
Monitor
VZERO
from System
+
from USB transceiver
OTG
VSHNT
470kW
to ADC
0.1mF
7.3 Feature Description
7.3.1 Global State Diagram
During normal operation, TPS65200 is either in STANDBY mode or ACTIVE mode, depending on user inputs. In
STANDBY mode, most functions are turned off to conserve power, but the IC can still be accessed through I2C
bus and the current shunt monitor can be turned on and off. The bias system and main oscillator are turned off in
STANDBY mode.
The device enters ACTIVE mode whenever VBUS is asserted or the WLED driver is turned on. In ACTIVE mode,
the main oscillator and reference system are turned on. The device remains in ACTIVE mode as long as VBUS
remains high, the WLED driver is enabled or both conditions exist.
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Feature Description (continued)
|| = OR
& = AND
(?) = rising edge
(?) = falling edge
STARTUP
POWER DOWN
VBUSVUVLO, VBUS
WLED driver= Disabled
LDO = OFF
CHARGER= HiZ
STANDBY
LDO_EN = 1 ||
CH_EN_[1:0] != 00
Charger not HiZ||
WLED is ON||
Charger in HiZ mode&
WLED OFF
WLED driver= ON or
CHARGER= /HiZ
ACTIVE
Figure 36. Global State Diagram
7.3.2 LED Driver Operation
The TPS65200 offers a high-efficiency, high-output voltage boost converter designed for driving up to 10 white
LED in series. The serial LED connection provides even illumination by sourcing the same output current through
all LEDs, eliminating the need for expensive factory calibration. The device integrates 40-V/0.7-A switch FET and
operates in pulse width modulation (PWM) with 600-kHz fixed switching frequency. For operation, see Functional
Block Diagram.
The LED driver can be enabled either through the CTRL pin or the WLED_EN bit in the CONTROL register. The
CTRL input is edge sensitive and should be pulled low at power-up. The CTRL pin allows PWM dimming of the
LEDs whereas the WLED_EN bit offers simple ON/OFF control only. The WLED_EN bit has priority over the
CTRL pin and when set to 1, the CTRL pin is ignored. If WLED_EN is set to 0 and the CTRL pin is low for
> 2.5 ms, the WLED driver is shut down.
The feedback loop regulates the FB pin voltage to the reference set by the VFB[4:0] bits in the WLED register
with a default setting of 200 mV. If any fault occurs during normal operation the driver is disabled, WLED_EN bit
is reset to 0 and the driver is put into FAULT state until the CTRL pin has been low for > 2.5 ms. The state
diagram for the WLED driver is shown in Figure 37.
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Feature Description (continued)
CTRL = L means CTRL pin is low for>2.5ms
|| = OR
& = AND
(?) = rising edge
(?) = falling edge
POWER DOWN
CTRL = L &
WLED_EN=0
DISABLED
WLED_EN = 0 &
CTRL = L
FAULT
BOOST is turned off
FAULT
WLED_EN = 1 ||
CTRL = H
WLED BOOST
ON
Figure 37. State Diagram for WLED Driver
7.3.2.1 Undervoltage Lockout
An undervoltage lockout circuit prevents operation of the WLED driver at input voltages (CSOUT pin) below 2.2
V. When the input voltage is below the under voltage threshold, the driver is shutdown and the internal switch
FET is turned off. If the input voltage rises by 70 mV above the undervoltage lockout hysteresis, the WLED driver
restarts. An internal thermal shutdown turns off the device when the typical junction temperature of 165°C is
exceeded. The device is released from shutdown automatically when the junction temperature decreases by
10°C.
7.3.2.2 Shutdown
To minimize current consumption, the WLED driver is shutdown when the WLED_EN bit is low and the CTRL pin
is pulled low for more than 2.5 ms. Although the internal FET does not switch in shutdown, there is still a DC
current path between the input and the LEDs through the inductor and Schottky diode. The minimum forward
voltage of the LED array must exceed the maximum input voltage to ensure that the LEDs remain off in
shutdown. However, in the typical application with two or more LEDs, the forward voltage is large enough to
reverse bias the Schottky and keep leakage current low.
7.3.2.3 Soft-Start Circuit
Soft-start circuitry is integrated into the WLED driver to avoid a high inrush current during start-up. After the
device is enabled, the voltage at FB pin ramps up to the reference voltage in 32 steps, each step takes 213 µs.
This ensures that the output voltage rises slowly to reduce the input current. Additionally, for the first 5 ms after
the COMP voltage ramps, the current limit of the switch is set to half of the normal current limit specification.
During this period, the input current is kept below 400 mA (typical).
7.3.2.4 Open LED Protection
Open LED protection circuitry prevents IC damage as the result of white LED disconnection. The TPS65200
monitors the voltage at the SWL pin during each switching cycle. The circuitry turns off the switch FET and shuts
down the WLED driver as soon as the SWL voltage exceeds the VOVP threshold for eight clock cycles. As a
result, the output voltage falls to the level of the input supply. The WLED driver remains in shutdown mode until it
is enabled by toggling the CTRL pin or the WLED_EN bit of the CTRL register.
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Feature Description (continued)
7.3.2.5 Current Program
The FB voltage is regulated to a low 200-mV reference voltage. The LED current is programmed externally using
a current-sense resistor in series with the LED string. The value of the RSET is calculated using Equation 1.
VFB
ILED = ¾
RSET
where
•
•
•
ILED = output current of LEDs
VFB = regulated voltage of FB
RSET = current sense resistor
(1)
The output current tolerance depends on the FB accuracy and the current sensor resistor accuracy.
7.3.2.6 Brightness Dimming
The TPS65200 offers two methods of LED brightness dimming. When the CTRL pin is constantly high, the FB
voltage is regulated to the value set in the WLED register which ranges from 0 mV to 200 mV and is divided into
32 steps. For applications requiring higher dimming resolution, a PWM signal can be applied to the CTRL pin to
reduce this regulation voltage and dim LED brightness. The relationship between the duty cycle and FB voltage
is given by Equation 2.
VFB = duty cycle · VFB[4:0]
where
•
•
Duty = duty cycle of the PWM signal
VFB[4:0] = internal reference voltage, default = 200 mV
(2)
The IC chops up the internal reference voltage at the duty cycle of the PWM signal and filters it by an internal low
pass filter. The output of the filter is connected to the error amplifier as the reference voltage for the FB pin
regulation. Therefore, although a PWM signal is used for brightness dimming, only the WLED DC current is
modulated, which is often referred to as analog dimming. This eliminates the audible noise which often occurs
when the LED current is pulsed in replica of the frequency and duty cycle of PWM control. The regulation voltage
itself is independent of the PWM logic voltage level which often has large variations.
VFB [4 :0 ]
IDAC
CTRL
WLED _EN
FB
Figure 38. WLED Analog Dimming Circuit
7.3.2.7 Inductor Overcurrent Protection
The overcurrent limit in the boost converter limits the maximum input current and thus maximum input power for
a given input voltage. Maximum output power is less than maximum input power due to power conversion losses.
Therefore, the current limit setting, input voltage, output voltage and efficiency can all change maximum current
output. The current limit clamps the peak inductor current and the maximum DC output current equals the current
limit minus half of the peak-peak current ripple. The ripple current is a function of switching frequency, inductor
value and duty cycle. Equation 3 through Equation 5 are used to determine the maximum output current.
VIN
D=1- ¾
VOUT
22
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Feature Description (continued)
where
•
•
•
D = duty cycle of the boost converter
VIN = Input voltage
VOUT = Output voltage of the boost converter. It is equal to the sum of VFB and the voltage drop across LEDs.
(3)
VIN · D
IPP = ¾
L · fS
where
•
•
•
IPP = inductor peak to peak ripple
L = inductor value
fs = switching frequency
(
(4)
)
IPP
VIN · ILIM - ¾
·h
2
IOUT(MAX) = ¾
VOUT
where
•
•
•
IOUT(MAX) = maximum output current of the boost converter
ILIM = overcurrent limit
η = efficiency
(5)
For instance, for VIN = 3 V, 7 LEDs output equivalent to VOUT of 23 V, an inductor value of 22 µH, a current limit
of 700 mA, and an efficiency of 85%, the maximum output current is ~65 mA.
7.3.3 HV LDO
TPS65200 provides a 4.9-V LDO that is powered off the VBUS input. The LDO is enabled whenever VVBUS >
VUVLO (3.3 V) and disabled when VVBUS > VOVP-IN_USB (6.5 V). LDO output voltage follows VBUS for VVBUS < 4.9 V
and is regulated to 4.9 V when VVBUS > 4.9 V. In any case output current is limited to 100 mA. The LDO can also
be disabled by the host by setting the LDO_EN bit of the CONTROL register to 0. An operational flow chart of
the LDO enable is shown in Figure 39.
|| = OR
& = AND
(?) = rising edge
(?) = falling edge
POWER DOWN
LDO OFF
LDO_EN = 0
LDO_EN = 1
LDO ON
Figure 39. State Diagram for the HV LDO
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Feature Description (continued)
7.3.4 Interrupt Pin
The interrupt pin is used to signal any fault condition to the host processor. Whenever a fault occurs in the IC,
the corresponding fault bit is set in the INT1, INT2, or INT3 register, and the open-drain output is pulled low. The
INT pin is released (returns to HiZ state) if any of the INT1, INT2, INT3 registers is accessed by the host, but
fault bits are cleared only by reading the INTx register containing the bit. However, if a failure persists, the
corresponding interrupt bit remains set but no new interrupt is issued. The TSD bit (thermal shutdown) is auto
cleared which means that the bit is reset to 0 automatically after the chip has cooled down below the thermal
shutdown release threshold.
The MASK1, MASK2, and MASK3 registers are used to mask certain events or group of events from generating
interrupts. The MASKx settings affect the INT pin only and have no impact on protection and monitor circuits
themselves.
7.3.5 Current Shunt Monitor
TPS65230 offers an integrated high-precision current shunt monitor to measure battery charging and discharging
currents. The inputs of a low-offset amplifier are connected across an external low-value shunt resistor. This
shunt voltage is gained up by a factor of 25 and added to a reference voltage connected to the VZERO terminal.
VSHUNT > VZERO for currents flowing into the battery and VSHUNT < VZERO for currents flowing out of the battery.
The reference voltage is buffered by a low-offset, high impedance input buffer.
VSHUNT = 25 · (VCSIN - VCSOUT) + VZERO + VOFFSET
where
•
•
•
•
•
VSHUNT is the output voltage of the current shunt monitor
VCSIN is the charger side of the shunt resistor
VCSOUT is the battery side of the shunt resistor
VZERO is the 0-current reference voltage
VOFFSET is the offset of the differential amplifier
(6)
The offset of the differential amplifier introduces a measurement error of ±40 µV input referred, equivalent to ±2
mA assuming a 20-mΩ shunt resistor which can be calibrated out by the system.
The shunt monitor is disabled by default and can be enabled by the host by setting the SMON_EN bit in the
CONTROL register to 1.
7.4 Device Functional Modes
7.4.1 Charge Mode Operation
For current limited power source, such as a USB host or hub, the high efficiency converter is critical in fully
utilizing the input power capacity and quickly charging the battery. Due to the high efficiency in a wide range of
the input voltage and battery voltage, the switching mode charger is a good choice for high speed charging with
less power loss and better thermal management.
The TPS65200 is a highly-integrated synchronous switched-mode charger with reverse boost function for USB
OTG support, featuring integrated MOSFETs and small external components, targeted at extremely space-limited
portable applications powered by 1-cell Li-ion or Li-polymer battery pack.
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Device Functional Modes (continued)
ANY CHARGER
STATE
POWER DOWN
ANY CHARGER
STATE
OTG = Active || CH_EN[1:0] = 01
CHARGER FAULT ||
CH_EN[1:0] = 00 ||
VBUS < VUVLO, VBUS
CH_EN[1:0] = 00
BOOST
BOOST FAULT ||
CH_EN != 01 & OTG = not active
HiZ
(CH_EN[1:0] = 10 || CH_EN[1:0] = 11) &
D+/D- detection done
VVBUSVIN(MIN)
|| = OR
& = AND
(?) = rising edge
(?) = falling edge
VVBUS VOREG-VRCH
CHARGE DONE
CHRCHI= 1
VCSOUT > V OREG-VRCH
Figure 40. State Diagram of USB Charger Circuit
The TPS65200 has three operation modes: charge mode, boost mode, and high impedance mode. In charge
mode, the TPS65200 supports a precision Li-ion or Li-polymer charging system for single-cell applications. In
boost mode, TPS65200 will boost the battery voltage to VBUS for powering attached OTG devices. In high
impedance mode, the TPS65200 charger stops charging or boosting and operates in a mode with very low
current from VBUS or battery, to effectively reduce the power consumption when the portable device is in
standby mode. Through carefully designed internal control circuits, TPS65200 achieves smooth transition
between different operation modes.
The global state diagram of the charger is shown in Figure 40 and the detailed charging algorithm in Figure 41.
HiZ mode is the default state of the charger where Q1, charger PWM and boost operation is turned off. If any
fault occurs during charging, the CH_EN[1:0] bits in the CONTROL register are reset to 00b (OFF), fault bits are
set in the INT2 register, an interrupt is issued on the INT pin, and HiZ mode is entered. Charging is re-initiated by
either host control or automatically if VBUS is power cycled.
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Device Functional Modes (continued)
ADAPTOR
DETECTION
CHARGE DONE
NO
Regulate
Input Current ,
Change Current or
Voltage
----------------CHSTAT [2:0]=001
NO
V CSOUT < VSHORT ?
YES
Enable ISHORT
----------------CHSTAT [2:0]=100
V BUS < V IN(MIN )
NO
VCSOUT < V SHORT ?
YES
YES
NO
NO
VBUS < V IN(MIN) ?
YES
Turn off Charge
NO
DELAY T INT
TERM _EN = 1 &
V CSOUT > VOREG – V RCH &
ITERM detected
YES
Turn off Charge
----------------CHTERMI=1
CHARGE DONE
Figure 41. Detailed Charging Flow Chart
7.4.1.1 Input Current Limiting and D+/D- Detection
By default the VBUS input current limit is set to 500 mA. When VBUS is asserted the TPS65200 performs a
charger source identification to determine if it is connected to a USB port or dedicated charger. This detection is
performed 200 ms after VBUS is asserted to ensure the USB plug has been fully inserted before identification is
performed. If a dedicated charger is detected the input current limit is increased to 975 mA, otherwise the current
limit remains at 500 mA, unless changed by the user.
Automatic detection is performed only if VIO is below 0.6 V to avoid interfering with the USB transceiver which
may also perform D+/D- detection when the system is running normally. However, D+/D- can be initiated at any
time by the host by setting the DPDM_EN bit in the CONTROL register to 1. After detection is complete the
DPDM_EN bit is automatically reset to 0 and the detection circuitry is disconnected from the DP DM pins to avoid
interference with USB data transfer.
The input current limit can also be set through the I2C interface to 100 mA, 500 mA, 975 mA, or no limit by
writing to the CONFIG_B register. The effective current limit will be the higher of the D+D- detection result and
the IIN_LIMIT[1:0] setting in CONFIG_A register. Whenever VBUS drops below the UVLO threshold
IIN_LIMIT[1:0] is reset to 100-mA setting to avoid excessive current draw from an unknown USB port.
Once the input current reaches the input current limiting threshold, the charge current is reduced to keep the
input current from exceeding the programmed threshold. The host can choose to ignore the D+D- detection
result by setting the LMTSEL bit of the CONFIG_A register to 1.
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Device Functional Modes (continued)
DISABLED
VBUS > VUVLO ,VBUS
ILIMIT = 500mA
DPDM_D = 0
Delay 200ms
VIO < 0.6V?
NO
YES
D+ / D- Detection Circuit
Turn on VDP _SRC ,
IDM _SINK , DP_SW,
and DM_SW
VDP_ SRC
Delay 40ms
DPDM_EN=0
Delay 80ms
V BUS 3.8 V), it is possible that the input voltage drops below the battery voltage during
adaptor rejection test. In this case, the reverse protection will kick-in and disable the charger. Also note that the
30-mA current sink is turned on for 30 ms only. If the input capacitance is > 500 µF (not recommended), the
adaptor may be accepted although it is not capable of providing 30-mA of current. In these cases, the VDPPM
loop will limit the charging current to maintain the input voltage.
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VBUS
VIN(MIN)
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30ms
deglitch
HiZ
ISHORT
Adaptor detection
control
Delay 10ms
Enable Adaptor Detection
----------------Enable Input current sink
Start 30ms timer
Figure 43. Bad Adaptor Detection Circuit
NO
V BUS > VIN(MIN) ?
NO
YES
30ms timer
expired?
YES
Bad Adaptor Detected
----------------Disable Input current sink
CHBADI = 1
Good Adaptor Detected
----------------Disable Input current sink
Enable VIN based DPM
Delay TINT
CHARGE
Figure 44. Bad Adaptor Detection Flow-Chart
7.4.1.3 Input Current Limiting at Start-Up
The LOW_CHG bit is automatically set when VBUS is asserted to limit the charge current to 150 mA. This
ensures that a battery cannot be charged with high currents without host control.
7.4.1.4 Charge Profile
In charge mode, TPS65200 has five control loops to regulate input voltage, input current, charge current, charge
voltage, and device junction temperature. During the charging process, all five loops are enabled and the one
that is dominant will take over the control. The TPS65200 supports a precision Li-ion or Li-polymer charging
system for single-cell applications. Figure 46 indicates a typical charge profile without input current regulation
loop and it is similar to the traditional CC/CV charge curve, while Figure 47 shows a typical charge profile when
input current limiting loop is dominant during the constant current mode, and in this case the charge current is
higher than the input current so the charge process is faster than the linear chargers. For TPS65200, the input
current limits, the charge current, termination current, and charge voltage are all programmable using I2C
interface.
7.4.1.5 Precharge to Fast Charge Threshold (VSHORT)
A deeply discharged battery (VBAT < VSHORT) is charged with a constant current of ISHORT (typically 30 mA) until
the voltage recovers to > VSHORT at which point fast charging begins. The pre-charge to fast-charge threshold
has a default value of 2.1 V and can be adjusted by connecting a resistor from the VSHRT pin to ground. An
internal current source forces a 10-µA current into the resistor and the resulting voltage is compared to half the
battery voltage to determine if the battery is deeply discharged or shorted. Therefore the voltage on the VSHRT
pin equals half of VSHORT threshold. For example a 100-kΩ resistor connected from VSHRT to GND results in a
2-V precharge to fast charge transition point. If the VSHRT pin is left floating or is shorted to the VDD pin, an
internal reference voltage of 1.05 V is used resulting in a 2.1-V pre-charge to fast-charge threshold.
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VDD
VBAT
10mA
R
R
+
VSHRT
VBAT >VSHRT
+
90% VDD
1 .05 V
VSHORT can be adjusted by an external resistor. Note that the VSHRT pin voltage equals
half VSHORT threshold. When VSHRT pin is left floating or is tied to VDD, an internal
reference of 1.05 V is used resulting in a 2.1-V pre-charge to fast-charge transition threshold.
Figure 45. Precharge to Fast-Charge Transition Threshold (VSHORT)
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
voltage
Regulation
Current
Charge Voltage
V SHORT
Charge Current
Termination
I SHORT
Precharge
(Linear Charge)
Fast Charge
( PWM Charge)
The input current remains constant during current regulation phase.
Figure 46. Typical Charging Profile of TPS65200 Without Input Current Limit
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Precharge
Phase
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Current Regulation
Phase
Voltage Regulation
Phase
Regulation
voltage
Charge Voltage
V SHORT
Charge Current
Termination
ISHORT
Precharge
(Linear Charge)
Fast Charge
(PWM Charge)
The charging current during current regulation phase decreases as battery voltage
increases. This mode ensures fastest charging of the battery without exceeding the
adaptor current limit.
Figure 47. Typical Charging Profile of TPS65200 With Input Current Limit
7.4.1.6 PWM Controller in Charge Mode
The TPS65200 provides an integrated, fixed 3-MHz frequency voltage-mode controller with feed-forward function
to regulate charge current or voltage. This type of controller is used to help improve line transient response,
thereby simplifying the compensation network used for both continuous and discontinuous current conduction
operation. The voltage and current loops are internally compensated using a Type-III compensation scheme that
provides enough phase margin for stable operation, allowing the use of small ceramic capacitors with very low
ESR. There is a 0.5-V offset on the bottom of the PWM ramp to allow the device to operate between 0% to
99.5% duty cycles.
The TPS65200 has two back-to-back common-drain N-channel MOSFETs at the high side and one N-channel
MOSFET at the low side. An input N-MOSFET (Q1) prevents battery discharge when VBUS is lower than
VCSOUT. The second high-side N-MOSFET (Q2) behaves as the switching control switch. A charge pump circuit is
used to provide gate drive for Q1, while a boot strap circuit with external boot-strap capacitor is used to boost up
the gate drive voltage for Q2.
Cycle-by-cycle current limit is sensed through the internal sense MOSFETs for Q2 and Q3. The threshold for Q2
is set to a nominal 1.9-A peak current. The low-side MOSFET (Q3) also has a current limit that decides if the
PWM controller will operate in synchronous or non-synchronous mode. This threshold is set to 100mA and it
turns off the low-side N-channel MOSFET (Q3) before the current reverses, preventing the battery from
discharging. Synchronous operation is used when the current of the low-side MOSFET is greater than 100 mA to
minimize power losses.
7.4.1.7 Battery Charging Process
During precharge phase, while the battery voltage is below the VSHORT threshold, the TPS65200 applies a shortcircuit current, ISHORT, to the battery. When the battery voltage is above VSHORT and below VOREG, the charge
current ramps up to fast charge current, IOCHARGE, or a charge current that corresponds to the input current of
IIN_LIMIT. The slew rate for fast charge current is controlled to minimize the current and voltage over-shoot during
transient. Both the input current limit (default at 100 mA), IIN_LIMIT, and fast charge current, IOCHARGE, can be set
by the host. Once the battery voltage is close to the regulation voltage, VOREG, the charge current is tapered
down as shown in Figure 46. The voltage regulation feedback occurs by monitoring the battery-pack voltage
between the CSOUT and PGND pins. TPS65200 is a fixed single-cell voltage version, with adjustable regulation
voltage (3.5 V to 4.44 V) programmed through I2C interface.
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The TPS65200 monitors the charging current during the voltage regulation phase. When the termination
threshold, ITERM, is detected and the battery voltage is above the recharge threshold, the TPS65200 terminates
charge. The termination current level is programmable and charge termination is disabled by default. To enable
the charge current termination, the host can set the charge termination bit TERM_EN of CONFIG_C register to 1.
Refer to I2C section for details.
A
•
•
•
•
new charge cycle is initiated when one of the following events occur:
VBUS is power-cycled.
CH_EN[1:0] = 11b and the battery voltage drops below the recharge threshold (TERM_EN = 1).
The RESET bit is set (host controlled).
The device is in CHARGE DONE state (see Figure 40) and the TERM_EN bit is set from 1 to 0.
7.4.1.8 Thermal Regulation and Protection
During the charging process, to prevent overheating of the chip, TPS65200 monitors the junction temperature,
TJ, of the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TCF.
The charge current will be reduced to zero when the junction temperature increases about 10°C above TCF. At
any state, if TJ exceeds TSHTDWN, TPS65200 will suspend charging and enter HiZ state. Charging will resume
after TJ falls 10°C below TSHTDWN.
7.4.1.9 Safety Timer in Charge and Boost Mode (CH32MI, BST32SI)
The TPS65200 charger hosts a safety timer that stops any boost or charging action if host control is lost. The
timer is started when the CH_EN[1:0] bits are set to anything different from 00 and is continuously reset by any
valid I2C command. If the timer exceeds 32 s and boost mode is enabled (CH_EN[1:0] = 01b), the boost is
disabled, CH_EN[1:0] is set to 00b, boost time-out fault is indicated in the INT2 register, and an interrupt is
issued. Similarly, once the timer exceeds 32 minutes and the charger is enabled (CH_EN[1:0] = 10b or 11b), the
charger is disabled, CH_EN[1:0] is set to 00b, charger time-out fault is indicated in INT2 register and an interrupt
is issued. Time-out faults affect CH_EN[1:0] bits only and not charger parameters. The safety timer flow chart is
shown in Figure 48.
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Reset and start
32min timer
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CH_EN[1:0] != 00
DISABLED
CH_EN[1:0] = 00
Any state
32s timer
expired?
YES
NO
CH_EN [1:0]
= 10?
YES
Disable boost
----------------CH_EN[1:0] = 00
BST32SI =1
YES
Disable charger
----------------CH_EN[1:0] = 00
CH32MI = 1
NO
32m timer
expired?
NO
YES
CHSTAT[2:0] = 010?
(Charge done)
NO
YES
Any I2C
action?
NO
Figure 48. Timer Flow Chart for TPS65200 Charger
7.4.1.10 Input Voltage Protection in Charge Mode
7.4.1.10.1 Input Overvoltage Protection (VBUSOVPI)
The TPS65200 provides a built-in input overvoltage protection to protect the device and other components
against damage if the input voltage (voltage from VBUS to PGND) gets too high. When an input overvoltage
condition is detected, the TPS65200 turns off the PWM converter, sets the VBUSOVPI bit in the INT1 register
and issues an interrupt. Once VVBUS drops below the input overvoltage exit threshold, the fault is cleared and
charge process resumes.
7.4.1.10.2 Reverse Current Protection (CHRVPI)
The TPS65200 charger enters Hi-Z state if the voltage on VBUS pin falls below VCSOUT + VREV, and VBUS is still
higher than the poor source detection threshold, VIN(MIN). The CHRVPI bit is set in the INT2 register and an
interrupt is issued. This feature prevents draining the battery during the absence of VBUS. In Hi-Z mode, both the
reverse blocking switch Q1 and PWM are turned off.
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7.4.1.10.3 Input Voltage Based Dynamic Power Management (CHDPMI)
During normal charging process, if the input power source is not able to support the charging current, VBUS
voltage will decease. Once VVBUS drops to VIN_LOW (default 4.36 V), the charge current will taper down to prevent
further drop of VBUS. This feature makes the IC compatible with adaptors with different current capabilities.
Whenever the VDPM loop activates, the CHDPMI interrupt is set in the INT2 register and the INT pin is pulled
low. The CHDPMI interrupt is delayed by 32 ms to prevent the interrupt to occur when the charging source is
removed.
7.4.1.11 Battery Protection in Charge Mode
7.4.1.11.1 Battery Charge Current Limiting
Whenever a valid power source is connected to the charger, the LOW_CHG bit of the CONFIG_C register is set
to 1 which limits the charging current to 150 mA. Once the host detects that that charging source has been
inserted it needs to reset the LOW_CHG bit to 0 to achieve a higher charging current. This feature prevents
charging of a battery at high currents when system voltage is too low for the system to boot.
7.4.1.11.2 Output Overvoltage Protection (CHBATOVPI)
The TPS65200 provides a built-in overvoltage protection to protect the device and other components against
damage if the battery voltage gets too high, as when the battery is suddenly removed. When an overvoltage
condition is detected, TPS65200 turns off the PWM converter, sets the CHBATOVPI bit in the INT2 register,
issues an interrupt, and enters HiZ mode. Once VCSOUT drops to the battery overvoltage exit threshold, charging
resumes.
7.4.1.11.3 Battery Short Protection
During the normal charging process, if the battery voltage is lower than the short-circuit threshold, VSHORT, the
charger will operate in short circuit mode with a lower charge rate of ISHORT.
7.4.1.12 Charge Status Output, STAT Pin
The STAT pin is used to indicate charging status of the IC and its behavior can be controlled by setting the
STAT_EN bits of the CONTROL register. In AUTO mode, STAT is pulled low during charging and is highimpedance otherwise. STAT pin can also be forced low or to Hi-Z state by setting the STAT_EN bits accordingly.
The STAT pin has enough pulldown strength to drive a LED and can be used for visual charge status indication.
7.4.2 Boost Mode Operation
In 32 second mode, when CH_EN[1:0] = 01 in CONTROL register, TPS65200 operates in boost mode and
delivers power to VBUS from the battery. In normal boost mode, TPS65200 converts the battery voltage (2.5V to
4.5 V) to VBUS-B (5 V) and delivers a current as much as IBO (200 mA) to support other USB OTG devices
connected to the USB connector. Boost mode can also be enabled through the OTG pin. By default the OTG pin
is disabled and can be enabled by setting the OTG_EN bit to 1. The polarity of the OTG pin is user
programmable through the OTG_PL bit. Both bits are located in the CONFIG_C register. The OTG pin allows the
USB transceiver to take control of the boost function without involvement of the main processor.
7.4.2.1 PWM Controller in Boost Mode
Similar to charge mode operation, in boost mode, the TPS65200 provides an integrated, fixed 3-MHz frequency
voltage-mode controller to regulate output voltage at PMID pin (VPMID). The voltage control loop is internally
compensated using a Type-III compensation scheme that provides enough phase margin for stable operation
with a wide load range and battery voltage range.
In boost mode, the input N-MOSFET (Q1) prevents battery discharge when VBUS pin is over loaded. Cycle-bycycle current limit is sensed through the internal sense MOSFET for Q3. The threshold for Q3 is set to a nominal
1.0-A peak current. The upper-side MOSFET (Q2) also has a current limit that decides if the PWM controller will
operate in synchronous or non-synchronous mode. This threshold is set to 75 mA and it turns off the high-side Nchannel MOSFET (Q2) before the current reverses, preventing the battery from charging. Synchronous operation
is used when the current of the high-side MOSFET is greater than 75 mA to minimize power losses.
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7.4.2.2 Boost Start Up
To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start
up.
7.4.2.3 PFM Mode at Light Load
In boost mode, TPS65200 will operate in pulse skipping mode (PFM mode) to reduce the power loss and
improve the converter efficiency at light load condition. During boosting, the PWM converter is turned off once
the inductor current is less than 75 mA; and the PWM is turned back on only when the voltage at PMID pin drops
to about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition
between PWM and PFM mode.
7.4.2.4 Safety Timer in Boost Mode (BST32SI)
At the beginning of boost operation, the TPS65200 starts a 32-second timer that is reset by the host through any
valid I2C transaction to the IC. Once the 32-second timer expires, TPS65200 will turn off the boost converter,
issue an interrupt, set the BST32SI bit in the INT3 register, and return to Hi-Z mode. Fault condition is cleared by
POR or reading the INT3 register.
7.4.2.5 Protection in Boost Mode
7.4.2.5.1 Output Overvoltage Protection (BSTBUSOVI)
The TPS65200 provides a built-in overvoltage protection to protect the device and other components against
damage if the VBUS voltage gets too high. When an overvoltage condition is detected, TPS65200 turns off the
PWM converter, resets CH_EN[1:0] bits to 00b (OFF), sets the BSTBUSOVI bit in the INT3 register, issues an
interrupt, and enters HiZ mode. Once VVBUS drops to the normal level, the boost will start after host sets
CH_EN[1:0] = 01b.
7.4.2.5.2 Output Over-Load Protection (BSTOLI)
The TPS65200 provides a built-in over-load protection to prevent the device and battery from damage when
VBUS is over loaded. Once an over load condition is detected, Q1 will operate in linear mode to limit the output
current while VPMID is kept in voltage regulation. If the over load condition lasts for more than 30 ms, the overload fault is detected. When an over-load condition is detected, TPS65200 turns off the PWM converter, resets
CH_EN[1:0] bits to 00b (OFF), sets the BSTOLI bit in the INT3 register, and issues an interrupt. The boost will
not start until the host sets CH_EN[1:0] = 01b or the OTG pin is toggled.
7.4.2.5.3 Battery Voltage Protection (BSTLOWVI, BSTBATOVI)
During boosting, when battery voltage is above the battery overvoltage threshold, VBATMAX, or below the minimum
battery voltage threshold, VBATMIN, TPS65200 will turn off the PWM converter, reset CH_EN[1:0] bits to 00b
(OFF), set the BSTLOWVI or BSTBATOVI bit in the INT3 register, and issues an interrupt. Once the battery
voltage goes back to the normal level, the boost will start if the host sets CH_EN[1:0] = 01b or the OTG pin is
toggled.
7.4.3 High Impedance Mode
When CH_EN[1:0] bits in the CONTROL register are set to 00b, TPS65200 will operate in high impedance mode,
with the impedance looking into VBUS pin higher than 500kΩ.
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7.5 Programming
7.5.1 I2C Bus Operation
The TPS65200 hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment
addressing and is compliant to I2C standard 3.0.
Slave Address + R/nW
Start
G3
G2
G1
G0
A2
A1
Sub Address
A0
R/nW
ACK
S7
S6
S5
S4
S3
S2
Data
S1
S0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Stop
Figure 49. Subaddress in I2C Transmission
Start – Start Condition
ACK – Acknowledge
G(3:0) – Group ID: Address fixed at 1101
S(7:0) – Subaddress: defined per register map
A(2:0) – Device Address: Address fixed at 010
D(7:0) – Data; Data to be loaded into the device
R/nW – Read / not Write Select Bit
Stop – Stop Condition
The I2C bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 50. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate group and address bits are set for the device, then the device will issue an
acknowledge pulse and prepare the receive subaddress data. Subaddress data is decoded and responded to as
per the Register Map section of this document. Data transmission is completed by either the reception of a stop
condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high
transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must
occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address,
sub-address and data words. The I2C interface will auto-sequence through register addresses, so that multiple
data words can be sent for a given I2C transmission.
...
SDA
SCL
1
2
3
4
5
START CONDITION
6
7
8
9
...
ACKNOWLEDGE
STOP CONDITION
2
Figure 50. I C Start/Stop/Acknowledge Protocol
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7.6 Register Maps
Table 1. Register Address Map
36
REGISTER
ADDRESS
(HEX)
NAME
DEFAULT
VALUE
0
1
0
CONTROL
0000 1010
Enable control register
1
CONFIG_A
0000 0001
Charger current register
2
3
2
CONFIG_B
0001 1001
Charger voltage register
3
CONFIG_C
1000 1010
Special charger settings
4
4
CONFIG_D
0100 0000
Charger safety limits settings
5
5
WLED
0001 1111
WLED feedback voltage setting
6
6
STATUS_A
0100 0000
Status register A
7
7
STATUS_B
0000 0001
Status register B
8
8
INT1
0000 0000
Interrupt bits
9
9
INT2
0000 0000
Interrupt bits (charger)
10
0A
INT3
0000 0000
Interrupt bits (boost)
11
0B
MASK1
0000 0000
Interrupt masking bits
12
0C
MASK2
0000 0000
Interrupt masking bits
13
0D
MASK3
0000 0000
Interrupt masking bits
14
0E
CHIPID
0000 0000
Chip ID register
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DESCRIPTION
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7.6.1 Control Register (CONTROL)
Address – 0x00h
DATA BIT
FIELD NAME
D7
D6
STAT_EN[1:0]
D5
D4
D3
D2
SMON_EN
WLED_EN
LDO_EN
DPDM_EN
D1
D0
CH_EN [1:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
1
0
1
0
FIELD NAME
BIT DEFINITION
STAT enable bits
00 – AUTO (controlled by charger status)
STAT_EN[1:0
01 – ON (low impedance)
10 – OFF (high impedance)
11 – not defined
Shunt monitor enable bit
SMON_EN
0 – Disabled
1 – Enabled
WLED enable bit
WLED_EN
0 – Disabled
1 – Enabled
NOTE: WLED can also be enabled through CTRL pin.
LDO enable bit
LDO_EN
0 – Disabled
1 – Enabled
D+/D- detection enable
DPDM_EN
0 – Disabled
1 – Enabled
NOTE: Bit is automatically reset after detection is completed.
Charger enable bits
00 – Disabled / HiZ mode
CH_EN[1:0]
01 – Boost mode
10 – Charge
11 – Charge with automatic recharge
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7.6.2 Charger Config Register A (CONFIG_A)
Address – 0x01h
DATA BIT
D7
FIELD NAME
LMTSEL
D6
D5
D4
D3
D2
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
1
VICHRG[3:0]
D1
D0
VITERM[2:0]
BIT DEFINITION (1)
FIELD NAME
Input Current Limit selction
LMTSEL
0 – Input current limit is set to the higher of IIN_LIMIT[1:0] (CONFIG_B) and D+D- det. result
1 – IIN_LIMIT[1:0] (CONFIG_B) applied, D+D- detection result is ignored
Charge current sense voltage (current equivalent for 20 mΩ shunt)
0000 – 11 mV (550 mA)
0001 – 13 mV (650 mA)
0010 – 15 mV (75 mA)
0011 – 17 mV (850 mA)
0100 – 19 mV (950 mA)
0101 – 21 mV (105 mA)
VICHRG[3:0]
0101 – 21 mV (1050 mA)
0110 – 23 mV (1150 mA)
0111 – 25 mV (1250 mA)
1000 – 27 mV (1350 mA)
1001 – 29 mV (1450 mA)
1010 – 31 mV (1550 mA)
...
1111 – 31 mV (1550 mA)
Termination current sense voltage (current equivalent for 20 mΩ shunt)
000 – 1 mV (50 mA)
001 – 2 mV (100 mA)
010 – 3 mV (150 mA)
VITERM[2:0]
011 – 4 mV (200 mA)
100 – 5 mV (250 mA)
101 – 6 mV (300 mA)
110 – 7 mV (350 mA)
111 – 8 mV (400 mA)
(1)
38
During charging the lower value of VMCHRG[3:0] (CONFIG_D register) and VICHRG[2:0] applies.
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7.6.3 Charger Config Register B (CONFIG_B)
Address – 0x02h
DATA BIT
D7
FIELD NAME
D6
D5
D4
D3
IIN_LIMIT[1:0]
D2
D1
D0
VOREG[5:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
1
1
0
0
1
BIT DEFINITION (1)
FIELD NAME
Input current limit setting
00 – 100 mA
IIN_LIMIT[1:0]
01 – 500 mA
10 – 975 mA
11 – No input current limit
Battery regulation voltage / boost output voltage
00 0000 – 3.50 V / 4.425 V
00 0001 – 3.52 V / 4.448 V
00 0011 – 3.56 V / 4.471 V
...
VOREG[5:0]
01 1000 – 3.98 V / 4.077 V
01 1001 – 4.00 V / 5 V
01 1010 – 4.02 V / 5.023 V
...
10 1111 – 4.44 V / 5.5 V
...
11 1111 – 4.44 V / 5.5 V
(1)
During charging the lower value of VMREG[3:0] (CONFIG_D register) and VOREG[5:0] applies.
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7.6.4 Charger Config Register C (CONFIG_C)
Address – 0x03h
DATA BIT
D7
D6
D5
D4
D3
FIELD NAME
VS_REF
OTG_PL
OTG_EN
TERM_EN
LOW_CHG
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1
0
0
0
1
0
1
0
FIELD NAME
D2
D1
D0
VSREG[2:0]
BIT DEFINITION
VSHORT reference select
VS_REF
0 – Internal (2.1 V) reference
1 – Current source on VSHRT pin is enabled. Pin voltage is used as 0.5 x VSHORT threshold.
OTG pin polarity
OTG_PL
0 – Active low
1 – Active high
OTG pin enable
OTG_EN
0 – Pin is disabled
1 – Pin is enabled
Charge termination enable
TERM_EN
0 – Disabled
1 – Enabled
Low charge current enable bit (current equivalent for 20 mΩ shunt)
LOW_CHG
0 – Normal charge current sense voltage per register CONFIG_A
1 – 3 mV (150 mA)
Input voltage DPM regulation voltage
000 – 4.20 V
001 – 4.28 V
010 – 4.36 V
VSREG[2:0]
011 – 4.44 V
100 – 4.52 V
101 – 4.60 V
110 – 4.68 V
111 – 4.76 V
40
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7.6.5 Charger Config Register D (CONFIG_D)
Address – 0x04h
DATA BIT
D7
D6
FIELD NAME
D5
D4
D3
D2
VMCHRG[3:0]
D1
D0
VMREG[3:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
1
0
0
0
0
0
0
BIT DEFINITION (1)
FIELD NAME
Maximum charge current sense voltage (current equivalent for 20 mΩ shunt)
0000 – 11 mV (550 mA)
0001 – 13 mV (650 mA)
0010 – 15 mV (750 mA)
0011 – 17 mV (850 mA)
0100 – 19 mV (950 mA)
VMCHRG[3:0]
0101 – 21 mV (1050 mA)
0110 – 23 mV (1150 mA)
0111 – 25 mV (1250 mA)
1000 – 27 mV (1350 mA)
1001 – 29 mV (1450 mA)
1010 – 31 mV (1550 mA)
…
1111 – 31 mV (1550 mA)
Maximum battery regulation voltage
0000 – 4.20 V
0001 – 4.22 V
VMREG[3:0]
0010 – 4.24 V
…
1100 – 4.44 V
...
1111 – 4.44 V
(1)
CONFIG_D register is reset to its default value when VCSOUT voltage drops below VSHORT threshold (typ.2.05 V). After VCSOUT recovers
to VCSOUT > VSHORT CONFIG_D register value can be changed by the host until one of the other registers is written to. Writing to any
other register locks the CONFIG_D register from subsequent writes. If CONFIG_D is not the first register to be written after reset, the
default values apply. During charging the lower value of VMCHRG[3:0] and VICHRG[2:0] (CONFIG_A register), and VMREG[3:0] and
VOREG[5:0] (CONFIG_B register) apply.
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7.6.6 WLED Control Register (WLED)
Address – 0x05h
DATA BIT
D7
D6
D5
FIELD NAME
Not used
Not used
Not used
READ/WRITE
R
R
R
R/W
R/W
RESET VALUE
0
0
0
1
1
FIELD NAME
D4
D3
D2
D1
D0
R/W
R/W
R/W
1
1
1
VFB[4:0]
BIT DEFINITION
Not used
N/A
Not used
N/A
Not used
N/A
WLED feedback voltage
0 0000 – 0%
0 0001 – 2.5%
0 0010 – 4%
0 0011 – 5.5%
0 0100 – 7.5%
0 0101 – 8.5%
0 0110 – 10%
0 0111 – 11.5%
0 1000 – 13%
0 1001 – 14.5%
0 1010 – 16%
0 1011 – 17.5%
0 1100 – 19%
0 1101 – 22%
0 1110 – 25%
VFB[4:0
0 1111 – 28%
1 0000 – 31%
1 0001 – 34%
1 0010 – 37%
1 0011 – 40%
1 0100 – 43%
1 0101 – 46%
1 0110 – 49%
1 0111 – 52%
1 1000 – 58%
1 1001 – 64%
1 1010 – 70%
1 1011 – 76%
1 1100 – 82%
1 1101 – 88%
1 1110 – 94%
1 1111 – 100%
42
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7.6.7 Status Register A (STATUS_A)
Address – 0x06h
DATA BIT
D7
D6
D5
FIELD NAME
Not used
STANDB
Y
D4
MONITOR
READ/WRITE
R
R
R
R
R
RESET VALUE
0
1
0
0
0
D2
D1
D0
LDO
WLED
R
R
R
0
0
0
CHSTAT [2:0]
BIT DEFINITION (1)
FIELD NAME
Not used
D3
N/A
Standby status indicator
STANDBY
0 – Device is in ACTIVE mode
1 – Device is in STANDBY mode
Current shunt monitor status indicator
MONITOR
0 – Current shunt monitor is disabled
1 – Current shunt monitor is enabled
Charger status bit
000 – High impedance mode
001 – Charge in progress (fast charge)
010 – Charge done
CHSTAT [2:0]
011 – Boost mode
100 – Charge in progress (pre charge)
101 – Not defined
110 – Not defined
111 – Not defined
LDO status bit
LDO
0 – LDO is disabled (OFF)
1 – LDO is enabled (ON), no fault
WLED status bit
WLED
0 – WLED disabled (OFF)
1 – WLED enabled
(1)
Default values reflect state after Power-ON Reset, no charger plugged in, no faults present.
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7.6.8 Status Register B (STATUS_B)
Address – 0x07h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
RESET
Not used
Not used
Not used
Not used
DPDM_D
DPDM_R
OTG
READ/WRITE
W
R
R
R
R
R
R
R
RESET VALUE
0
0
0
0
0
0
0
1
BIT DEFINITION (1)
FIELD NAME
Reset
RESET
0 – No effect
1 – Reset all parameters to default values
NOTE: Read always returns “0”
Not used
N/A
Not used
N/A
Not used
N/A
Not used
N/A
D+/D- detection done bit
DPDM_D
0 – DPDM detection in progress or not started after initial power-up reset
1 – DPDM detection is complete
D+D- detection result
DPDM_R
0 – Standard USB port (500-mA current limit)
1 – USB charger (1000-mA current limit)
OTG pin status
OTG
0 – OTG pin at low level
1 – OTG pin at high level
(1)
Default values reflect state after Power-ON Reset, no charger plugged in, no faults present, OTG pin high..
7.6.9 Interrupt Register 1 (INT1)
Address – 0x08h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
Not used/
Reserved
Not used/
Reserved
Not used/
Reserved
WLEDI
FIELD NAME
TSDI
VBUSOVPI
Not used
Not used/
Reserved
READ/WRITE
R
R
R
R/W
R/W
R/W
R/W
R
RESET VALUE
0
0
0
0
0
0
0
0
FIELD NAME
TSDI
VBUSOVPI
Not used
Thermal shutdown fault. Set if die temperature exceeds thermal shutdown threshold. Reset when die
temperature drops below TSD release threshold.
VBUS overvoltage protection. Set when VBUS > VOVP-IN_USB is detected.
N/A
Not used / Reserved
N/A / Reserved
Not used / Reserved
N/A / Reserved
Not used / Reserved
N/A / Reserved
Not used / Reserved
N/A / Reserved
WLEDI
44
BIT DEFINITION
WLED driver over voltage
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7.6.10 Interrupt Register 2 (INT2)
Address – 0x09h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
CHTERMI
CHRCHGI
CH32MI
CHTREGI
CHDPMI
FIELD NAME
CHRVPI
CHBADI
CHBATOV
I
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
0
0
0
0
0
0
0
BIT DEFINITION (1)
FIELD NAME
CHRVPI
Charger fault. Reverse protection (VVBUS > VIN(MIN) and VVBUS < VCSOUT+VREV (fault)
CHBADI
Charger fault. Bad adaptor (VBUS < VIN(MIN))
CHBATOVI
Charger fault. Battery OVP
CHTERMI
Charge terminated
CHRCHGI
Recharge request (VCSOUT < VOREG – VRCH)
CH32MI
(1)
Charger fault. 32 m time-out (fault)
CHTREGI
Charger warning. Thermal regulation loop active.
CHDPMI
Charger warning. Input voltage DPM loop active.
All charger faults result in disabling the charger (CH_EN[1:0] = 00). Recharge request disables the charger only if CH_EN[1:0] = 10.
7.6.11 Interrupt Register 3 (INT3)
Address – 0x0Ah
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
BSTBUSO
VI
BSTOLI
BSTLOWV
I
BSTBATOVI
BST32SI
Not used
Not used
Not used
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
0
0
0
0
0
0
0
BIT DEFINITION (1)
FIELD NAME
BSTBUSOVI
BSTOLI
(1)
Boost fault. VBUS OVP (VBUS > VBUSOVP)
Boost fault. Over load.
BSTLOWVI
Boost fault. Battery voltage is too low.
BSTBATOVI
Boost fault. Battery over voltage.
BST32SI
Boost fault. 32-s time-out fault.
Not used
N/A
Not used
N/A
Not used
N/A
All BOOST faults result in disabling the boost converter (CH_EN[1:0] = 00).
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7.6.12 Interrupt Mask Register 1 (MASK1)
Address – 0x0Bh
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
TSDM
VBUSOV
PM
Not used
Not used
Not used
Not used
Not used
WLEDM
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
BIT DEFINITION (1)
FIELD NAME
TSD fault interrupt mask
TSDM
0 – Interrupt not masked
1 – Interrupt masked
VBUS OVP fault interrupt mask
VBUSOVPM
0 – Interrupt not masked
1 – Interrupt masked
Not used
N/A
Not used
N/A
Not used
N/A
Not used
N/A
Not used
N/A
WLED fault interrupt mask
WLEDM
0 – Interrupt not masked
1 – Interrupt masked
(1)
46
Setting any of the interrupt mask bits does not disable protection circuits. When set, the respective fault will not be signaled on the INT
pin.
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7.6.13 Interrupt Mask Register 2 (MASK2)
Address – 0x0Ch
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
CHTERMM
CHRCHGM
CH32MM
CHTREGM
CHDPMM
FIELD NAME
CHRVPM
CHBADM
CHBATOV
M
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
BIT DEFINITION (1)
FIELD NAME
Charger reverse protection interrupt mask
CHRVPM
0 – Interrupt not masked
1 – Interrupt masked
Charger Bad adaptor interrupt mask
CHBADM
0 – Interrupt not masked
1 – Interrupt masked
Charger battery overvoltage interrupt mask
CHBATOVM
0 – Interrupt not masked
1 – Interrupt masked
Charge terminated interrupt mask
CHTERMM
0 – Interrupt not masked
1 – Interrupt masked
Charger recharge request interrupt mask
CHRCHGM
0 – Interrupt not masked
1 – Interrupt masked
Charger 32m timeout interrupt mask
CH32MM
0 – Interrupt not masked
1 – Interrupt masked
Charger thermal regulation loop active interrupt mask
CHTREGM
0 – Interrupt not masked
1 – Interrupt masked
Charger input current DPM active interrupt mask
CHDPMM
0 – Interrupt not masked
1 – Interrupt masked
(1)
Setting any of the interrupt mask bits does not disable protection circuits. When set, the respective fault will not be signaled on the INT
pin
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7.6.14 Interrupt Mask Register 3 (MASK3)
Address – 0x0Dh
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
BSTBUSOV
M
BSTOLM
BSTLOWV
M
BSTBATOVM
BST32SM
Not used
Not used
Not used
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
BIT DEFINITION (1)
FIELD NAME
Boost VBUS overvoltage interrupt mask
BSTBUSOVM
0 – Interrupt not masked
1 – Interrupt masked
Boost over load interrupt mask
BSTOLM
0 – Interrupt not masked
1 – Interrupt masked
Boost low battery voltage interrupt mask
BSTLOWVM
0 – Interrupt not masked
1 – Interrupt masked
Boost battery overvoltage interrupt mask
BSTBATOVM
0 – Interrupt not masked
1 – Interrupt masked
Boost 32s time out interrupt mask
BST32SM
0 – Interrupt not masked
1 – Interrupt masked
(1)
48
Not used
N/A
Not used
N/A
Not used
N/A
Setting any of the interrupt mask bits does not disable protection circuits. When set, the respective fault will not be signaled on the INT
pin.
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7.6.15 Chip ID Register (CHIPID)
Address – 0x0Eh
DATA BIT
D7
D6
D5
D4
D3
D2
D0
VENDOR[1:0]
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
0
0
0
0
0
0
1 (1)
(1)
CHIP[2:0]
D1
FIELD NAME
REV[2:0]
Device dependent.
FIELD NAME
VENDOR[1:0]
BIT DEFINITION
Vendor code 00 – default
00 – Default
Chip ID
000 – TPS65200
CHIP[2:0]
001 – Future use
...
111 – Future use
Revision code
000 – Revision 1.0
REV[2:0]
001 – Revision 1.1
010 – Future use
...
111 – Future use
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS65200 device is designed to serve as a Li+ battery charger with an additional WLED driver and current
shunt monitor. A typical application design for this usage will be described in Typical Application.
8.2 Typical Application
L1
VLF4010ST-100MR80
C3
100 nF
U1
GND
D1
A1
C2
100 nF
A2
GND
A3
VDD
C4
VSHRT A5
A6
B1
GND
B2
B3
STAT
GND
VZERO
C10
10 F
L2
20 m
B4
B5
B6
C1
GND
VSYS
BAT
CSOUT
SWL
PGND
CSIN
DM
VDD
SCL
VSHRT
SDA
A4
1 F
GND
R5
10 H
SWC
C2
TEST
BOOT
PGND
COMP
PGND
FB
PGND
DP
STAT
VIO
SGND
VBUS
VZERO
VBUS
SWC
LDO
SWC
CTRL
SWC
INT
NR3012T1R0N
GND
10 F
C3
1 H
C9
OTG/NTC C4
C11
R7
GND
100 nF
470 k
C5
C6
OTG/NTC
PMID
VSHNT
PMID
VYSY
PMID
F6
SWL
MBR0540T1
F5
C1
470 nF
GND
GND
F4 DM
F3 SCL
F2 SDA
F1 BOOT
C5 SWC
10 nF
E6
C6
220 nF
E5 FB
GND
E4 DP
E3 VIO
E2
E1
VBUS
D6
VLDO
C7
1 F
C8
1 F
GND
GND
D5 CTRL
D4 INT
D3
D2
D1
PMID
C12
1 F
GND
TPS65200
Figure 51. Typical Application Schematic
8.2.1 Design Requirements
The key elements to identify for the design are the value of RSET, RSHRT, and RSNS as well as the desired LED
brightness. All other values should reflect those required in Pin Configuration and Functions or in Functional
Block Diagram.
50
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Typical Application (continued)
8.2.2 Detailed Design Procedure
To determine the value for RSET, simply take the desired ILED and divide it by the FB voltage. The FB voltage is
200 mV by default, but can be changed by the VFB[4:0] bits.
To determine the value for RSHRT, the desired pre-charge to fast-charge voltage threshold must be known. From
there, divide the voltage by two to account for an internal divider and then by the reference current for VSHRT of
10 uA to determine the resistance value.
To determine the value for RSNS, determine the desired output voltage for the current being monitored. Divide this
voltage by the gain, 25 V/V, and the output current to determine the sense resistor value.
Finally, the LED brightness is a function of either changing the feedback voltage through I2C or applying a PWM
signal to the CTRL pin.[Current Figure 43 WLED Dimming Linearity] gives some estimate as to the VFB level as
a function of the duty cycle of the input PWM. This should be fine-tuned for the particular LEDs being used.
Table 2. Recommended External Components (1)
PART NO.
VALUE
SIZE
MANUFACTURER
CHARGER INDUCTOR
NR3012T1R0N
1 µH
3 × 3 × 1.2
Taiyo Yuden
CPL2512T1R0M
1 µH
2.5 × 1.5 × 1.2
TDK
MDT2520CN
1 µH
TOKO
WLED BOOST INDUCTOR
ELL-VGG100M
10 µH
3 × 3 × 1.5
Panasonic
VLF4010ST-100MR80
10 µH
4.3 × 4 × 1
TDK
1098AS-100M
10 µH
3 × 3.2 × 1.2
TOKO
MBR0540
SOD-123
ON-SEMI
ZHCS400
SOD-323
ZETEX
WLED BOOST SCHOTTKY DIODE
(1)
Over operating free-air temperature range (unless otherwise noted).
8.2.3 Application Curves
VBUS = 5.5 V
VBAT = 3.3 V
IIN_limit = 975 mA
ICHARGE = 950 mA
VBUS = 5.5 V
Figure 52. I2C Controlled Start-Up
VBAT = 3.3 V
IIN - limit = 975 mA
ICHARGE = 950 mA
Figure 53. I2C Controlled Start-Up
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51
TPS65200
SLVSA48A – APRIL 2010 – REVISED SEPTEMBER 2015
0-A - 1-A Transient
on VSYS
VOREG = 4 V
www.ti.com
VBUS = 5.5 V
VBAT = 3.2 V
ICHARGE = 950 mA
IIN_limit = 975 mA
0-A - 1-A Transient
on VSYS
VOREG = 4 V
Figure 54. Transient Response
0-A - 1-A Transient
on VSYS
VOREG = 4 V
VBUS = 5.5 V
VBAT = 4 V
ICHARGE = 950 mA
IIN_limit = 975 mA
0-A - 1-A Transient
on VSYS
VOREG = 4 V
ICHARGE = 950 mA
IIN_limit = 975 mA
VBUS = 5.5 V
VBAT = 4 V
ICHARGE = 950 mA
IIN_limit = 975 mA
Figure 57. Transient Response
VBUS = 5.5 V
No Battery
ICHARGE = 950 mA
IIN_limit = 975 mA
0-A - 1-A Transient
on VSYS
VOREG = 4 V
Figure 58. Transient Response
52
VBAT = 3.2 V
Figure 55. Transient Response
Figure 56. Transient Response
0-A - 1-A Transient
on VSYS
VOREG = 4 V
VBUS = 5.5 V
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VBUS = 5.5 V
No Battery
ICHARGE = 950 mA
IIN_limit = 975 mA
Figure 59. Transient Response
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS65200
TPS65200
www.ti.com
SLVSA48A – APRIL 2010 – REVISED SEPTEMBER 2015
9 Power Supply Recommendations
This device should be connected to a single cell Li+ battery or to a 5-V VBUS supply. The current required from
VBUS will depend on the desired limit, maximum of 1.55 A.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and switching frequencies. If the layout is not carefully done, the DCDC converters might show noise problems
and duty cycle jitter. The input capacitors on VBUS and PMID pins should be placed as close as possible to the
input pins for good input voltage filtering. The inductors should be placed as close as possible to the switch pins
to minimize the noise coupling into other circuits. The output capacitors must be placed directly from the inductor
(charger buck) or Schottky diode (WLED boost) to GND to minimize the ripple current in these traces. All ground
pins must be connected directly to the ground plane as should all passive components with ground connections.
Figure 60 and Figure 61 show one example for placement and routing of the critical components on a four-layer
PCB. In this example all components are placed on the top layer and all routing is done on the top layer or
bottom layer. Layer 2 is a solid ground plane and layer 3 is not used for layout. All IC pin connections are notes
as [pin number]. For example, the VSYS pin is referenced as [C6].
• Place C9 and C10 (VSYS) as close to L2 as possible, with short connections to ground.
• Place C4 close to the IC. Trace current is low (
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