TPS65232
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SLVSA42 – FEBRUARY 2010
TRIPLE BUCK POWER MANAGEMENT IC
Check for Samples: TPS65232
FEATURES
1
•
•
•
Wide Input Supply Voltage Range
(10.8 V - 22 V)
One Adjustable PWM Buck Controller
– 10.8-V - 22-V Input Voltage Range
– 3.3-V - 6.1-V Output Voltage Range
– 500-kHz Switching Frequency
– Type III Compensation
– Programmable Current Limit
Two Adjustable Step-Down Converter With
Integrated Switching FETs:
– 4.75-V - 5.5-V Input
– 0.9-V-3.3-V Output Voltage Range
– 3-A Output Current
– 1-MHz Switching Frequency
– Type III Compensation
•
•
•
•
Pull-Up Current Sources on Buck Enable Pins
for Accurate Start-Up Timing Control with
Preset Default
Over Current Protection on All Rails
Thermal Shutdown to Protect Device During
Excessive Power Dissipation
Thermally Enhanced Package for Efficient
Heat Management (48-pin HTSSOP or
6-mm x 6-mm 40-Pin QFN)
APPLICATIONS
•
•
•
xDSL and Cable Modems
Wireless Access Points
STB, DTV, DVD and Home Gateway
DESCRIPTION/ORDERING INFORMATION
The TPS65232 provides one PWM buck controller, two adjustable, synchronous buck regulators. The SMPS
have integrated switching FETs for optimized power efficiency and reduced external component count. All power
blocks have thermal and over current/short circuit protection. The TPS65232 startup timing can be controlled
through buck enable pins. The buck controller and buck converters have internal pole/zero pairs to help
stabilizing the system with minimum external components.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS65232
SLVSA42 – FEBRUARY 2010
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FUNCTIONAL BLOCK DIAGRAM
12-V DC Supply
VINB2b
VINB2a
VINB3b
VIN
VINB3a
Optional
VINB and VINBQ pins must be tied
togther on PC board
12V
HDRV
BST1
VIN
Vout BUCK1
DIGITAL LOGIC
EN_BCK1
from enable logic
EN_BCK2
from enable logic
EN_BCK3
from enable logic
PH1
BUCK1
LDRV
FB1
CMP1
BST2
REF
PH2a
VINB2
Vout BUCK2
PH2b
TRIM
OSC
TSD
UVLO
BUCK2
FB2
CMP2
V3p3
V6V
BST3
INTERNAL
VOLTAGE RAILS
PH3a
VINB3
Vout BUCK3
PH3b
BUCK3
FB3
PGND
PGND
PGND
PGND
AGND
DGND
CMP3
ORDERING INFORMATION (1)
TA
0°C to 85°C
(1)
(2)
2
PACKAGE
(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
48-pin (HTSSOP) - DCA
Reel of 2000
TPS65232A2DCAR
TPS65232
40-pin (QFN) - RHA
Reel of 2500
TPS65232A0RHAR
TPS65232
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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SLVSA42 – FEBRUARY 2010
PIN OUT (DCA)
DCA PACKAGE
(TOP VIEW)
BG
1
48
AGND
VINBQ
2
47
AGND
V6V
3
46
AGND
VIN
4
45
AGND
FB2
5
44
AGND
CMP2
6
43
AGND
EN_BCK2
7
42
AGND
PGND2
8
41
AGND
PGND2
PH2
9
40
10
39
BST3
VINB3
PH2
11
38
VINB3
VINB2
12
37
PH3
VINB2
13
36
PH3
BST2
14
35
PGND3
DGND
15
34
PGND3
LDRV
16
17
33
32
EN_BCK3
CMP3
18
31
FB3
BST1
19
30
AGND
EN_BCK1
20
29
AGND
CMP1
21
28
AGND
FB1
22
27
AGND
SS
23
26
AGND
TRIP
24
25
V3P3
HDRV
PH1
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TERMINAL FUNCTIONS (DCA)
NO.
I/O
BG
NAME
1
I
Reference filter pin
VINBQ
2
I
Reference supply for BUCK2 and BUCK3
V6V
3
I
Filter pin for internal voltage regulator (6 V)
VIN
4
I
Input supply for BUCK1 and support circuitry
FB2
5
I
Feedback pin (BUCK2)
CMP2
6
I
Regulator Compensation (BUCK2)
7
I
Enable pin for BUCK2, active high
EN_BCK2
PGND2
8, 9
PH2
10, 11
VINB2
12, 13
BST2
14
DGND
15
DESCRIPTION
Power ground BUCK2
O
Switching pin (BUCK2)
I
Bootstrap input (BUCK2)
Input supply for BUCK2 (must be tied to VINB3, VINBQ)
Digital ground
LDRV
16
O
Low-side gate drive output (PWM controller)
HDRV
17
O
High-side gate drive output (PWM controller)
PH1
18
O
Switching pin (BUCK1)
BST1
19
I
Bootstrap input (BUCK1)
EN_BCK1
20
I
Enable pin for BUCK1, active high
CMP1
21
I
Regulator compensation (PWM controller)
FB1
22
I
Feedback pin (PWM controller)
SS
23
I
External capacitor for soft start
TRIP
24
I
BUCK1 over current trip point set-up
V3P3
25
I
Filter pin for internal voltage regulator (3.3 V)
AGND
26, 27, 28, 29,
30, 41, 42, 43,
44, 45, 46, 47, 48
Analog ground
FB3
31
I
Feedback pin (BUCK3)
CMP3
32
I
Regulator compensation (BUCK3)
EN_BCK3
33
I
Enable pin for BUCK3, active high
PGND3
34, 35
PH3
36, 37
O
VINB3
38, 39
I
Input supply for BUCK3 (must be tied to VINB2, VINBQ)
BST3
40
I
Bootstrap input (BUCK3)
4
Power ground BUCK3
Switching pin (BUCK3)
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SLVSA42 – FEBRUARY 2010
PIN OUT (RHA)
RHA PACKAGE
(TOP VIEW)
VINB3
PH3
PH3
EN_BCK3
CMP3
FB3
AGND
AGND
39
38
37
36
35
34
33
32
AGND
VINB3
40
31
BST3
1
AGND
2
AGND
3
28
V3P3
AGND
4
27
TRIP
BG
5
26
SS
VINBQ
6
25
FB1
V6V
7
24
CMP1
VIN
8
23
EN_BCK1
FB2
9
22
BST1
CMP2
10
21
PH1
Thermal
Pad
11
12
13
14
15
16
17
18
19
20
30
AGND
29
AGND
EN_BCK2
PGND2
PH2
PH2
VINB2
VINB2
BST2
DGND
LDRV
HDRV
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TERMINAL FUNCTIONS (RHA)
NO.
I/O
BG
NAME
5
I
Reference filter pin
VINBQ
6
I
Reference supply for BUCK2 and BUCK3
V6V
7
I
Filter pin for internal voltage regulator (6 V)
VIN
8
I
Input supply for BUCK1 and support circuitry
FB2
9
I
Feedback pin (BUCK2)
CMP2
10
I
Regulator compensation (BUCK2)
EN_BCK2
11
I
Enable pin for BUCK2, active high
PGND2
12
PH2
13, 14
VINB2
15, 16
BST2
17
DGND
18
DESCRIPTION
Power ground BUCK2
O
Switching pin (BUCK2)
I
Bootstrap input (BUCK2)
Input supply for BUCK2 (must be tied to VINB3, VINBQ)
Digital ground
LDRV
19
O
Low-side gate drive output (PWM controller)
HDRV
20
O
High-side gate drive output (PWM controller)
PH1
21
O
Switching pin (BUCK1)
BST1
22
I
Bootstrap input (BUCK1)
EN_BCK1
23
I
Enable pin for BUCK1, active high
CMP1
24
I
Regulator compensation (PWM controller)
FB1
25
I
Feedback pin (PWM controller)
SS
26
I
External capacitor for soft start
TRIP
27
I
BUCK1 over current trip point set-up
V3P3
28
I
Filter pin for internal voltage regulator (3.3 V)
AGND
2, 3, 4, 29, 30,
31, 32, 33
Analog ground
FB3
34
I
Feedback pin (BUCK3)
CMP3
35
I
Regulator Compensation (BUCK3)
EN_BCK3
36
I
Enable pin for BUCK3, active high
PH3
37, 38
O
Switching pin (BUCK3)
VINB3
39, 40
I
Input supply for BUCK3 (must be tied to VINB2, VINBQ)
BST3
1
I
Bootstrap input (BUCK3)
6
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SLVSA42 – FEBRUARY 2010
ABSOLUTE MAXIMUM RATINGS (1)
(2)
over operating free-air temperature range (unless otherwise noted)
Input voltage range at VIN
–0.3 to 25
V
Input voltage range at VINB, VINBQ
–0.3 to 7.0
V
Voltage range at EN_BCK1, EN_BCK2, EN_BCK3
–0.3 to 3.6
V
Voltage on HDRV, BST1
–0.3 to 31
V
Voltage on PH1
–0.3 to 24
V
Voltage on FB1, CMP1, FB2, CMP2, FB3, CMP3
–0.3 to 3.6
V
Voltage on PH2, PH3, LDRV
–0.3 to 7.0
V
Voltage on BST2, BST3
–0.3 to 15
V
3.8
A
Output current at BUCK2, BUCK3
Peak output current
Internally limited
ESD rating
Thermal resistance – Junction to ambient (3)
qJA
Continuous total power dissipation 55°C (3) no thermal
warning
TJ
Operating virtual junction temperature range
TA
Operating ambient temperature range
TSTG
Storage temperature range
(1)
(2)
(3)
Human body model (HBM)
2k
Charged device model (CDM)
500
TSSOP
25
QFN
18.1
TSSOP
2.6
QFN
2.5
0 to 150
V
°C/W
W
°C
0 to 85
°C
–65 to 150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Using JEDEC 51-5 (High K) board. This is based on standard 48DCA package, 4 layers, top/bottom layer: 2 oz Cu, inner layer: 1 oz Cu.
Board size: 114.3 x 76.2 mm (4.5 x 3 inches), board thickness: 1.6 mm (0.0629 inch).
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
TA
MIN
NOM
MAX
Input voltage range at VIN
10.8
12
22
UNIT
Input voltage range at VINB
4.75
6.1
Voltage range, EN_BCK1, EN_BCK2, EN_BCK3
0
3.3
V
Ambient operating temperature
0
50
°C
MAX
UNIT
V
ELECTRICAL CHARACTERISTICS
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, TJ = 0°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10.8
12
INPUT VOLTAGE
VIN
Input supply voltage
UVLO VIN
UVLO threshold – VIN (main supply)
UVLO VINB
UVLO threshold – VINB
(BUCK2/BUCK3 supply)
VIN rising
VIN falling
V
V
4.7
VINB rising
VINB falling
22
10.8
4.75
V
4.25
INPUT CURRENT
ICCQ
All regulators/USB switches
disabled
Input supply current
4
mA
BUCK ENABLE INPUTS (EN_BCK1,2,3)
VEN
Enable threshold
1.2
V
VENHYS
Enable voltage hysteresis
100
mV
IPULLUP
Pull-up current
RD
Discharge resistor
tD
Discharge time
tEN = 0.2 ms/nF
6
mA
1
Power-up
kΩ
5
ms
PWM CONTROLLER (BUCK1)
VOUT
Output voltage range (1)
VFB
Feedback voltage
LDRV
HDRV
High and low side drive voltage
R_ONLDRV
R_OFFLDRV
3.3
–2%
No load
0.804
6.1
V
2%
V
6
V
Low side ON resistance
8
Ω
Low side OFF resistance
1
Ω
R_ONHDRV
High side ON resistance
20
Ω
R_OFFHDRV
High side OFF resistance
1
Ω
(2)
d
Duty cycle
AMOD
Modulator gain
20
fSW
Switching frequency
ITRIP
Current source for setting OCP trip
point
TCTRIP
Temperature coefficient of ITRIP
RTRIP
Current-limit setting resistor
80
COUT
Output capacitance
(3)
L
Nominal inductance
80
%
12
TA = 25°C
500
kHz
10
mA
3700
22
Recommended
ppm/°C
250
kW
mF
4.7
mH
BUCK2
VOUT
Output voltage range (1)
VFB
Feedback voltage
(1)
(2)
(3)
8
0.9
– 2%
0.804
3.3
V
2%
V
Output voltage range is limited by the minimum and maximum duty cycle. VOUT(min) ~ d(min) x VINPUT and VOUT(max) ~ d(max) x
VINPUT.
Performance outside these limits is not guaranteed.
Absolute value. User should make allowances for tolerance and variations due to component selection.
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, TJ = 0°C to 150°C (unless otherwise noted)
PARAMETER
IOUT
Output current
h
Efficiency
RDS(ON)
ILIMIT
TEST CONDITIONS
MIN
IO = 2 A, VOUT = 3.3V
Low-side MOSFET On resistance
High-side MOSFET On resistance
VINB = 4.75 V - 6.1 V,
IOUT = 1 A
VLOADREG
Load regulation - DC
ΔVOUT/ΔIOUT
IOUT = 10 – 90% IOUT,MAX
VOUTTOL
DC set tolerance
Feedback resistor tolerance
not included
(2)
fSW
Switching frequency
COUT
Output capacitance
ESR
Capacitor ESR
L
Nominal inductance
mA
%
mΩ
5
Line regulation - DC
ΔVOUT/ΔVINB
Modulator gain
3000
36
–30
VLINEREG
Duty cycle
UNIT
32
VIN12V = 12 V
Current limit accuracy
AMOD
MAX
95
Switch current limit
d
TYP
A
30
%
1
%
0.5
–2
15
%/A
2
%
85
%
5
1
10 (3)
MHz
47
mF
50
mΩ
2.2
mH
BUCK3
VOUT
Output voltage range (4)
VFB
Feedback voltage
IOUT
Output current
h
Efficiency
RDS(ON)
ILIMIT
0.9
–2%
Low-side MOSFET On resistance
High-side MOSFET On resistance
5
Line regulation - DC
ΔVOUT/ΔVINB
VINB = 4.75 V - 6.1 V,
IOUT = 1000 mA
VLOADREG
Load regulation - DC
ΔVOUT/ΔIOUT
IOUT = 10 – 90% IOUT,MAX
VOUTTOL
DC Set Tolerance
Feedback resistor tolerance
not included
(5)
fSW
Switching frequency
COUT
Output capacitance
ESR
Capacitor ESR
L
Nominal inductance
(4)
(5)
mΩ
36
–30
VLINEREG
Modulator gain
A
%
32
VIN12V = 12 V
Current limit accuracy
Duty cycle
V
V
86
Switch current limit
AMOD
3.3
2%
3
IO = 2 A, VOUT = 1.2 V
d
0.804
A
30
%
1
%
0.5
–2
15
%/A
2
%
85
%
5
1
MHz
10
mF
50
2.2
mΩ
mH
Output voltage range is limited by the minimum and maximum duty cycle. VOUT(min) ~ d(min) x VINPUT and VOUT(max) ~ d(max) x
VINPUT.
Performance outside these limits is not guaranteed.
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, TJ = 0°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT START (BUCK1, 2, and 3)
ISS
Soft start current source
VSS,
Soft start ramp voltage
Ramp end
CSS
Soft start capacitor
tSS = 0.4 ms/nF
SSDONE_BK
Deglitch time
2.5
ms
SSDONE_DCH
SS discharge time
500
ms
MAX
2
mA
0.8
2
3.3
V
4.7
nF
THERMAL SHUTDOWN
Thot
Thermal warning
120
°C
Ttrip
Thermal s/d trip point
160
°C
Thyst
Thermal s/d hysteresis
20
°C
POWER-UP SEQUENCING
ON/OFF control and power sequencing of the three buck regulators is controlled through EN_BCK1, EN_BCK2,
and EN_BCK3 enable pins. Each pin is internally connected to a 6-mA constant-current source and monitored by
a comparator with Schmitt trigger input with defined threshold. Connecting EN_BCKn pin to ground disables
BUCKn and connecting EN_BCKn to V3p3 will enable the respective buck without delay. If more than one buck
enable pin is connected to V3p3 the default startup sequence is BUCK1, BUCK2, BUCK3 and the minimum
startup delay between rails is the soft-start time (typical 1.5 ms) plus 1 ms.
V3p3
(1)
V (EN pin)
To create a startup-sequence different from the default, capacitors are connected between the EN_BUCKn pins
and ground. At power-up the capacitors are first discharged and then charged to V3p3 level by internal current
sources (6 mA typical) creating a constant-slope voltage ramp. A regulator is enabled when its EN pin voltage
crosses the enable threshold (typical 1.2 V). A delay of 0.2 ms is generated for each 1-nF of capacitance
connected to the enable pin. If two enable pins are pulled high while the third regulator is starting up, the default
sequence will be applied to enable the remaining two regulators. To override default power-up sequence it is
recommended that delay times differ by more than the soft-start time (typical 1.3 ms) plus 1 ms.
V3p3
6uA
EN_BCKx
BUCK ENABLE
Enable
Threshold
Delay time = 0.2ms/nF
1.2V
(2)
BUCK A
Enable
BUCK C
Enable
BUCK B
Enable
Time
(1) Connect EN_BCKx pin to V3P3 to follow the default power-up sequence or
(2) Connect a capacitor from EN_BCKx to GND to generate a custom power-up sequence.
Figure 1. Customizing the Power-Up Sequence
10
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OVER CURRENT PROTECTION
Over current protection (OCP) for BUCK1 is achieved by comparing the drain-to-source voltage of the low-side
MOSFET to a set-point voltage, which is defined by both the internal current source, ITRIP, and the external
resistor connected between the TRIP pin and ground. Over current threshold is calculated as follows:
RTRIP · ITRIP
¾
ILIM = 10
· RDS(ON)
(1)
ITRIP has a typical value of 10 mA at 25°C and a temperature coefficient of 3700 ppm/°C to compensate the
temperature dependency of the MOS RDS(ON). The TPS65232 supports cycle-by-cycle over current limiting
control which means that the controller compares the drain-to-source voltage of the low-side FET to the set-point
voltage once per switching cycle and blanks out the next switching cycle if an over-current condition is detected.
If in the following cycle over current condition is detected again, the controller blanks out 2, then 4, 8, and up to
16 cycles before turning on the high-side driver again. In an over current condition the current to the load
exceeds the current to the output capacitor thus the output voltage will drop, and eventually cross the under
voltage protection threshold and shut down the BUCK controller. Buck 2 and 3 show a similar mode of operation.
All converters operate in “hiccup mode”: Once an over-current is sensed, the controller shuts off the converter for
a given time and then tries to start again. If the overload has been removed, the converter will ramp up and
operate normally. If this is not the case, the converter will see another over-current event and shuts down again
repeating the cycle until the failure is cleared.
SOFT START
Soft start for all three BUCKs is controlled by a single capacitor connected to the SS pin and an internal current
source. When one of the BUCKs is enabled, the SS capacitor is pre-charged to the output voltage divided by the
feed-back ratio before the internal SS current source starts charging the external capacitor. The output voltage of
the BUCK ramps up as the SS pin voltage increased from its pre-charged value to 0.8 V. The soft start time is
calculated from the SS supply current (ISS) and the capacitor value and has a typical value of 0.4 ms/nF or
1.3 ms for a 3.3-nF capacitor connected to the SS pin. Before the next rail is enabled, the SS cap is discharged
and the SS cycle starts over again.
UNDER VOLTAGE LOCKOUT (UVLO)
TPS65232 monitors VIN and VINB pin voltages and will disable one or more power paths depending on the
current use condition:
• If VIN drops below 4.7 V, BUCK1, 2, and 3 are disabled.
• If VINB drops below 4.25 V and either BUCK2 or BUCK3 are enabled, all three output rails are disabled.
UVLO state is not latched and the system recovers as soon as the input voltage rises above its respective
threshold. All three BUCK_ENx pins are discharged and remain discharged during UVLO to ensure proper power
sequencing when the system recovers.
THERMAL SHUTDOWN (TSD)
TPS65232 monitors junction temperature and will disable the power path (BUCK1-3) if junction temperature rises
above the specified trip point. All three BUCK_ENx pins are discharged and remain discharged during TSD to
ensure proper power sequencing when the system recovers.
LOOP COMPENSATION
All three BUCKs are voltage mode converters designed to be stable with ceramic capacitors. Refer to
Component Selection Procedure section for calculating feedback components.
3.3-V REGULATOR
The TPS65232 has a built-in 3.3-V regulator for powering internal circuitry. The 3.3-V rail can also be used for
enabling the BUCK regulators and/or the USB switches, but is not intended for supplying any other external
circuitry.
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6-V REGULATOR
The TPS65232 has a built-in 6-V regulator for powering internal circuitry.
THERMAL MANAGEMENT AND SAFE OPERATING AREA
Total power dissipation inside TPS65232 is limited not to exceed the maximum allowable junction temperature of
150°C. The maximum allowable power dissipation is a function of the thermal resistance of the package (qJA)
and ambient temperature. qJA itself is highly dependent on board layout. The maximum allowable power inside
the IC for operation at maximum ambient temperature without exceeding the temperature warning flag using the
JEDEC High-K board is calculated as follows.
DT = qJA · P
(2)
For TSSOP:
TMAX - Tambient 120°C - 55°C
PMAX = ¾
= ¾
qJA
25°C/W » 2.6 W
(3)
For QFN:
TMAX - Tambient 120°C - 75°C
PMAX = ¾
= ¾
qJA
18.1°C/W » 2.5 W
(4)
For different PCB layout arrangements the thermal resistance (qJA) will change as the following table shows.
BOARD TYPE
STACK-UP
qJA
8" x 10" FR4 PCB, four layers
1.5-oz Cu, 60% Cu coverage top layer, 80% Cu coverage bottom
layer, no airflow
0.5-oz 30% Cu coverage inner layers
29
8” x 10” FR4 PCB, two layers
1-oz Cu, 20% Cu coverage top layer, 90% Cu coverage bottom
layer, no airflow
44
A minimum of two layers of 1-oz Cu with 20% Cu coverage on the top and 90% coverage on the bottom and the
use of thermal vias to connect the thermal pad to the bottom layer is recommended. Note that the maximum
allowable power inside the device will depend on the board layout. For recommendations on board layout for
thermal management using TPS65232 consult your TI field application engineer.
3.5
3.5
3
3
3
2.5
2
S afe Operating Area
1.5
1
0.5
Current from BUCK3 [A] @ 3.3V
3.5
Cur rent fr om BUCK3 [A] @ 3.3V
Current from BUCK3 [A] @ 3 .3V
In the example shown above the maximum allowable power dissipation for the IC has been calculated. This
figure includes all heat sources inside the device including the power dissipated in BUCK1, BUCK2, BUCK3 and
all supporting circuitry. Power dissipated in BUCK1 and all supporting circuitry is approximately 0.4 W and almost
independent of the application. Power dissipated in BUCK2 and BUCK3 depends on the output voltage, output
current, and efficiency of the switching converters. The following examples of safe operating area assume 90%
efficiency for BUCK2 and BUCK3, 3.3-V output from BUCK3 and 1.2-V, 1.8-V, and 2.5-V output from BUCK2,
respectively.
2.5
2
Safe Operat ing Area
1.5
1
0.5
0
0.5
1
1.5
2
2.5
Curr ent from BUCK2 [A] @ 1.2V or less
3
3.5
2
Sa fe Operating Area
1.5
1
0.5
0
0
2.5
0
0
0.5
1
1.5
2
2.5
3
Curr ent from BUCK2 [A] @ 1.8V
3.5
0
0.5
1
1.5
2
2.5
3
3.5
Curre nt from BUCK2 [A] @ 2.5V
For any voltage / current comination inside the shaded area, the dissipated power inside the chip is below the allowable
maximum. The examples assume Tambient < 60°C, h = 90% and qJA < 44°C/W.
Figure 2. Examples of Thermal Safe Operating Area for V(BUCK3) = 3.3 V and
V(BUCK1) = 1.2 V, 1.8 V and 2.5 V, Respectively
12
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COMPONENT SELECTION PROCEDURE
The following example illustrates the design procedure for selecting external components for the three buck
converters. The example focuses on BUCK1 but the procedure can be directly applied to BUCK2 and BUCK3 as
well. The design goal parameters are given in the table below. A list of symbol definitions is found at the end of
this section. For this example the schematic in Figure 3 will be used.
L3
V1
2.2uH
C31
C32
47uF
0.1uF
1.2V 3A V3
R33
C36
20K
1000pF
C33
22uF
C34
22uF
R31
EN3
C37
22.1K
C35
C2
1uF
1uF
C3
VIN
1uF
12V
C12
100uF
C11
FB2
VIN
FB2
CMP2
100uF
AGND
AGND
1000pF
R32
AGND
AGND
V3P3
TRIP
SS
FB1
CMP1
EN_BCK1
BST1
PH1
TPS65232
44.2K
C5
1uF
210K
3.3nF
C18
R13
C16
1000pF
20K
1000pF
VIN
C10
C17
0.22uF
Q1A
L1
C13
22uF
C20
20K
0.1uF
V1
C27
C22
100pF
0.1uF
47uF
5V 6A
V1
C14
22uF
L2
2.2uH
C23
22uF
C21
100pF
4.7uH
FDS6982
Q1B
R23
C26
FB1
EN1
EN2
1000pF
R14
C4
DGND
LDRV
HDRV
C1
AGND
AGND
AGND
BG
VINBQ
V6V
EN_BCK2
V1
VINB2
VINB2
BST2
BST3
VINB3
0.1uF
PGND2
PH2
PH2
C30
VINB3
PH3
PH3
EN_BCK3
CMP3
FB3
AGND
100pF
1.8V 3A
V2
C24
22uF
C15
R11
1000pF
22.1K
FB1
R12
R21
4.22K
22.1K
C25
FB2
1000pF
R22
17.8K
Figure 3. Sample Schematic for TPS65232
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BUCK1 DESIGN GUIDELINE
PARAMETER
VIN
VIN
TEST CONDITIONS
Input supply voltage
RIPPLE
VOUT
VOUT
Input voltage ripple
TYP
MAX
UNIT
10.8
12
13.2
4.75
5
5.25
IOUT, BUCK1 = 6 A
Output voltage
75
V
mV
V
Line regulation
VIN = 10.8 V to 13.2 V
25
mV
Load regulation
IOUT, BUCK1 = 0 A to 6 A
25
mV
Output ripple
IOUT, BUCK1 = 6 A
VTRANS
Transient deviation
IOUT, BUCK1 = 1.5 A to 3 A
IOUT
Output current
VIN = 10.8 V to 13.2 V
fSW
Switching frequency
RIPPLE
MIN
75
50
0
mV
mV
6
500
A
kHz
INDUCTOR SELECTION (L1)
The inductor is typically sized for < 30% peak-to-peak ripple current (IRIPPLE). Given this target ripple current, the
required inductor size is calculated by Equation 5.
VIN(MAX) - VOUT
L= ¾
0.3 · IOUT
·
VOUT
¾
VIN(MAX)
·
1
¾
fSW
(5)
Solving Equation 5 with VIN(MAX) = 13.2 V, an inductor value of 3.5 mH is obtained. A standard value of 4.7 mH is
selected, resulting in 1.25-A peak-to-peak ripple. The RMS current through the inductor is approximated by
Equation 6.
¾2
¾
2
2
1 (I
1
IL(RMS) = Ö(IL(avg)2 + ¾
RIPPLE) ) = Ö(IOUT) + ¾ (IRIPPLE)
12
12
(6)
Using Equation 6, the maximum RMS current in the inductor is about 6.01 A.
OUTPUT CAPACITOR SELECTION (C13, C14)
The selection of the output capacitor is typically driven by the output load transient response requirement.
Equation 7 and Equation 8 estimate the output capacitance required for a given output voltage transient
deviation.
ITRAN(MAX)2 · L
COUT(MIN) = ¾
(VIN(MIN) - VOUT) · VTRAN
2
TRAN(MAX)
I
·L
COUT(MIN) = ¾
VOUT · VTRAN
when VIN(MIN) < 2 · VOUT
(7)
when VIN(MIN) > 2 · VOUT
(8)
For this example, Equation 8 is used in calculating the minimum output capacitance.
Based on a 1.5-A load transient with a maximum 50-mV deviation, a minimum of 42-mF output capacitance is
required. We choose two 22-mF capacitors in parallel for a total capacitance of 44 mF.
The output ripple is divided into two components. The first is the ripple generated by the inductor ripple current
flowing through the output capacitor’s capacitance, and the second is the voltage generated by the ripple current
flowing in the output capacitor’s ESR. The maximum allowable ESR is then determined by the maximum ripple
voltage and is approximated by Equation 9.
IRIPPLE
VRIPPLE(total) - ( ¾
VRIPPLE(total) - VRIPPLE(cap)
COUT · fSW )
ESRMAX = ¾
¾
=
IRIPPLE
IRIPPLE
(9)
Based on 44-mF of capacitance, 1.25-A ripple current, 500-kHz switching frequency and a design goal of 75-mV
ripple voltage, we calculate a capacitive ripple component of 56 mV and an maximum ESR of 15 mΩ. Two 1210,
47-mF, 10-V X5R ceramic capacitors are selected to provide significantly less than 15-mΩ of ESR.
14
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PEAK CURRENT RATING OF THE INDUCTOR
With output capacitance known, it is now possible to calculate the charging current during start-up and determine
the minimum saturation current rating of the inductor. The start-up charging current is approximated by
Equation 10.
VOUT · COUT
ICHARGE = ¾
TSS
(10)
Using the TPS65232’s recommended 1.3-ms soft-start time, COUT = 44 mF and VOUT = 5 V, ICHARGE is found to be
169 mA. The peak current rating of the inductor is now found by Equation 11.
1
IL(PEAK) = IOUT(MAX) + ¾
2 IRIPPLE + ICHARGE
(11)
For this example an inductor with a peak current rating of 6.79 A is required.
INPUT CAPACITOR SELECTION (C11, C12)
The input voltage ripple is divided between capacitance and ESR. For this design, VRIPPLE(CAP) = 50 mV and
VRIPPLE(ESR) = 25 mV. The minimum capacitance and maximum ESR are estimated by Equation 12 and
Equation 13.
ILOAD · VOUT
CIN(MIN) = ¾
VRIPPLE(cap) · VIN · fSW
(12)
VRIPPLE(ESR)
ESRMAX = ¾
1
ILOAD + ¾
2 IRIPPLE
(13)
For this design, CIN > 100 mF and ESR < 3.7 mΩ. The RMS current in the output capacitors is estimated by
Equation 14.
¾
2
1
VOUT VOUT · IOUT
IRMS(CIN) = IIN(RMS) - IIN(avg) = Ö((IOUT)2 + ¾
- ¾
12 (IRIPPLE) ) · ¾
VIN
VIN
(14)
With VIN = VIN(MAX), the input capacitors must support a ripple current of 1.4-A RMS. The two 1210, 47-mF X5R
ceramic capacitors with about 5-mΩ ESR and 2-A RMS current rating are selected. It is important to check the
DC bias voltage de-rating curves to ensure the capacitors provide sufficient capacitance at the working voltage.
BOOTSTRAP CAPACITOR (C10)
To ensure proper charging of the high-side MOSFET gate, limit the ripple voltage on the bootstrap capacitor to
< 5% of the minimum gate drive voltage.
20 · QGS, HSD
CBOOST = ¾
VIN(MIN)
(15)
Based on the FDS6982 MOSFET with a maximum total gate charge of 12 nC, calculate a minimum of 22-nF of
capacitance. A standard value of 220 nF is selected.
SHORT CIRCUIT PROTECTION (R14, C18) (BUCK1 ONLY)
The TPS65232 uses the forward drop across the low-side MOSFET during the OFF time to measure the inductor
current. The voltage drop across the low-side MOSFET is given by Equation 16.
VDS = IL(PEAK) · RDSON, LSD
(16)
When VIN = 10.8 V to 13.2 V, IPEAK = 7.4 A. Using the FDS6982 MOSFET with a RDSON,MAX at TJ = 25°C of
20 mΩ we calculate the peak voltage drop to be 148 mV. Solving Equation 1 for RTRIP and using ITRIP = 10 mA:
R14 = RTRIP = RDS(ON) · ILIM · 106
(17)
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We calculate a trip resistor value of 210 kΩ. Place a 1-nF capacitor parallel to R14. Please note that typical FET
RDS(ON) is specified at 10 mΩ. Since we used RDSON,MAX, for setting the current limit, the actual current flowing
through the inductor with a nominal FET can be higher than the peak current of 7.4 A before the current limit
kicks in. Make sure that the chosen inductor has the correct peak current capabilities.
FEEDBACK LOOP DESIGN
TPS65232 loop compensation looks like a type-II compensation network because an internal zero-pole pair can
provide additional phase boost to stabilize this voltage mode control DC/DC controller. The internal zero is
located at 45 kHz and the pole is located at 240 kHz. Ideally, the best cross-over frequency is around 1/10th of
the switching frequency.
FEEDBACK DIVIDER (R11, R12)
Select R11 between 10 kΩ and 100 kΩ. For this design select 22.1 kΩ. Next, R12 Is selected to produce the
desired output voltage when VFB = 0.8 V using the following formula:
VFB · R11
R12 = ¾
VOUT - VFB
(18)
VFB = 0.8 V and R11 = 22.1 KΩ for VOUT = 5.0 V, R12 = 4.22 kΩ.
Error Amplifier Pole-Zero Selection
The design guidelines for TPS65232 Buck1 loop compensation are as follows:
1. Place a compensation zero at 8 kHz to boost the phase margin at the anticipated cross-over frequency.
2. Set the value of R and C of this to zero: C16 = 1000 pF and R13 = 20 kΩ.
3. Add an additional pole by making C17 = 100 pF. This pole is used to attenuate high frequency noise.
4. If VIN is 20 V - 24 V, make C17 = 200 pF.
BUCK2 DESIGN GUIDELINE
PARAMETER
VIN
VIN
TEST CONDITIONS
Input supply voltage
RIPPLE
VOUT
VOUT
Input voltage ripple
MIN
TYP
MAX
UNIT
4.75
5
6
V
75
mV
IOUT, BUCK1 = 3 A
Output voltage
RIPPLE
1.8
V
Line regulation
VIN = 3 V to 6 V
18
mV
Load regulation
IOUT, BUCK1 = 0 A to 3 A
18
mV
Output ripple
IOUT, BUCK1 = 3 A
VTRANS
Transient deviation
IOUT
Output current
fSW
Switching frequency
36
IOUT, BUCK1 = 1.5 A to 3 A
50
VIN = 3 V to 6 V
0
mV
3
1000
mV
A
kHz
INDUCTOR SELECTION (L2)
The inductor is typically sized for < 30% peak-to-peak ripple current (IRIPPLE). Given this target ripple current, the
required inductor size is calculated by Equation 5.
VIN(MAX) - VOUT
L= ¾
0.3 · IOUT
·
VOUT
¾
VIN(MAX)
·
1
¾
fSW
(19)
Solving Equation 19 with VIN(MAX) = 6 V, an inductor value of 1.4 mH is obtained. A standard value of 2.2 mH is
selected, resulting in 0.37-A peak-to-peak ripple. The RMS current through the inductor is approximated by
Equation 6.
¾2
¾
2
2
1 (I
1
IL(RMS) = Ö(IL(avg)2 + ¾
RIPPLE) ) = Ö(IOUT) + ¾ (IRIPPLE)
12
12
(20)
Using Equation 20, the maximum RMS current in the inductor is about 3.002 A.
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OUTPUT CAPACITOR SELECTION (C23, C24)
The selection of the output capacitor is typically driven by the output load transient response requirement.
Equation 21 and Equation 22 estimate the output capacitance required for a given output voltage transient
deviation.
ITRAN(MAX)2 · L
¾
COUT(MIN) =
(VIN(MIN) - VOUT) · VTRAN
2
TRAN(MAX)
I
·L
COUT(MIN) = ¾
VOUT · VTRAN
when VIN(MIN) < 2 · VOUT
(21)
when VIN(MIN) > 2 · VOUT
(22)
For this example, Equation 22 is used in calculating the minimum output capacitance.
Based on a 1-A load transient with a maximum 54-mV deviation, a minimum of 26-mF output capacitance is
required. We choose two 22-mF capacitors in parallel for a total capacitance of 44 mF.
The output ripple is divided into two components. The first is the ripple generated by the inductor ripple current
flowing through the output capacitor’s capacitance, and the second is the voltage generated by the ripple current
flowing in the output capacitor’s ESR. The maximum allowable ESR is then determined by the maximum ripple
voltage and is approximated by Equation 23.
IRIPPLE
VRIPPLE(total) - ( ¾
VRIPPLE(total) - VRIPPLE(cap)
COUT · fSW )
ESRMAX = ¾ = ¾
IRIPPLE
IRIPPLE
(23)
Based on 44-mF of capacitance, 0.37-A ripple current, 1-MHz switching frequency and a design goal of 36-mV
ripple voltage, we calculate a maximum ESR of 76 mΩ. Two 1210, 22-mF, 10-V X5R ceramic capacitors are
selected to provide significantly less than 76-mΩ of ESR.
PEAK CURRENT RATING OF THE INDUCTOR
With output capacitance known, it is now possible to calculate the charging current during start-up and determine
the minimum saturation current rating of the inductor. The start-up charging current is approximated by
Equation 24.
VOUT · COUT
ICHARGE = ¾
TSS
(24)
Using the common start time (1 ms), COUT = 44 mF and VOUT = 1.8 V, ICHARGE is found to be 79 mA. The peak
current rating of the inductor is now found by Equation 25.
1
IL(PEAK) = IOUT(MAX) + ¾
2 IRIPPLE + ICHARGE
(25)
For this example an inductor with a peak current rating of 3.264 A is required.
INPUT CAPACITOR SELECTION (C21, C22)
The input voltage ripple is divided between capacitance and ESR. For this design, VRIPPLE(CAP) = 50 mV and
VRIPPLE(ESR) = 25 mV. The minimum capacitance and maximum ESR are estimated by Equation 26 and
Equation 27.
ILOAD · VOUT
CIN(MIN) = ¾
VRIPPLE(cap) · VIN · fSW
(26)
VRIPPLE(ESR)
ESRMAX = ¾
1
ILOAD + ¾
2 IRIPPLE
(27)
For this design, CIN > 32 mF and ESR < 7.8 mΩ. The RMS current in the output capacitors is estimated by
Equation 28.
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¾
2
1
VOUT VOUT · IOUT
IRMS(CIN) = IIN(RMS) - IIN(avg) = Ö((IOUT)2 + ¾
- ¾
12 (IRIPPLE) ) · ¾
VIN
VIN
(28)
With VIN = VIN(TYP), the input capacitors must support a ripple current of 0.58-A RMS. The two 1210, 47-mF X5R
ceramic capacitors with about 5-mΩ ESR and 2-A RMS current rating are selected. It is important to check the
DC bias voltage de-rating curves to ensure the capacitors provide sufficient capacitance at the working voltage.
BOOTSTRAP CAPACITOR (C20)
A standard value of 100 nF is selected.
SHORT CIRCUIT PROTECTION
Current limits for BUCK2 are internally set to 5 A.
FEEDBACK LOOP DESIGN
TPS65232 loop compensation looks like a type-II compensation network because an internal zero-pole pair can
provide additional phase boost to stabilize this voltage mode control DC/DC controller. The internal zero is
located at 45 kHz and the pole is located at 240 kHz. Ideally, the best cross-over frequency is around 1/10th of
the switching frequency.
FEEDBACK DIVIDER (R21, R22)
Select R21 between 10 kΩ and 100 kΩ. For this design select 22.1 kΩ. Next, R22 Is selected to produce the
desired output voltage when VFB = 0.8 V using the following formula:
VFB · R21
R22 = ¾
VOUT - VFB
(29)
VFB = 0.8 V and R21 = 22.1 KΩ for VOUT = 1.8 V, R22 = 17.8 kΩ.
Error Amplifier Pole-Zero Selection
The design guidelines for TPS65232 BUCK2 loop compensation are as follows:
1. Place a compensation zero at 8 kHz to boost the phase margin at the anticipated cross-over frequency.
2. Set the value of R and C of this to zero: C26 = 1000 pF and R23 = 20 kΩ.
3. Add an additional pole by making C27 = 100 pF. This pole is used to attenuate high frequency noise.
BUCK3 DESIGN GUIDELINE
Both BUCK2 and BUCK3 have the same internal structure. Thus, BUCK2’s design guideline can be applied to
BUCK3’s design directly.
OTHER COMPONENTS
A
•
•
•
•
1-µF ceramic capacitor should be connected as close as possible to the following pins:
BG: Bandgap reference
VIN: Bypass capacitor
V6V: Internal 6-V supply
V3P3: Internal 3.3-V supply
SIX RAIL POWER SYSTEM
The following example illustrates two TPS65232 ICs can provide six power rails and the low output voltage rail is
capable of delivering 10-A load current with high efficiency.
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L3
V1
2.2uH
C31
C32
47uF
0.1uF
1.2V 3A V3
R33
C36
20K
1000pF
C33
22uF
C34
22uF
R31
EN3
C37
22.1K
C35
C2
1uF
1uF
C3
VIN
1uF
12V
C12
100uF
C11
FB2
VIN
FB2
CMP2
100uF
AGND
AGND
1000pF
R32
AGND
AGND
V3P3
TRIP
SS
FB1
CMP1
EN_BCK1
BST1
PH1
TPS65232
44.2K
C5
1uF
210K
3.3nF
R13 C16
C18
20K
VIN
C10
C17
0.22uF
Q1A
L1
100pF
0.1uF
V1
C27
C22
100pF
0.1uF
C21
47uF
5V 6A
4.7uH
C13
22uF
C20
20K
1000pF
EN1
FDS6982
Q1B
R23
C26
FB1
1000pF
EN2
1000pF
R14
C4
DGND
LDRV
HDRV
C1
AGND
AGND
AGND
BG
VINBQ
V6V
EN_BCK2
V1
VINB2
VINB2
BST2
BST3
VINB3
0.1uF
PGND2
PH2
PH2
C30
VINB3
PH3
PH3
EN_BCK3
CMP3
FB3
AGND
100pF
V1
C14
22uF
L2
2.2uH
C23
22uF
1.8V 3A
V2
C24
22uF
C15
R11
1000pF
22.1K
FB1
R12
R21
4.22K
22.1K
C25
FB2
1000pF
R22
17.8K
Figure 4. Six Rail Power System Part I: 5 V, 1.8 V and 1.2 V
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L6
V1
2.2uH
C312
C322
47uF
0.1uF
1.5V 3A V6
R332 C362
20K
C332
22uF
C342
22uF
1000pF
R312
EN6
C372
22.1K
C352
C22
1uF
1uF
C32
VIN
12V
C122
100uF
1uF
FB5
VIN
FB2
CMP2
C112
100uF
AGND
AGND
1000pF
R322
AGND
C52
AGND
1uF
V3P3
TRIP
C42
SS 3.3nF
FB1
CMP1
EN4
EN_BCK1
BST1
C102
0.22uF
PH1
TPS65232
DGND
LDRV
HDRV
C12
AGND
AGND
AGND
BG
VINBQ
V6V
EN_BCK2
V1
VINB2
VINB2
BST2
BST3
VINB3
0.1uF
PGND2
PH2
PH2
C302
VINB3
PH3
PH3
EN_BCK3
CMP3
FB3
AGND
100pF
25.5K
R142
30.1K
FB4
VIN
100pF
C202
0.1uF
V1
C272
C222
100pF
0.1uF
C212
47uF
1.0V 10A V4
L4
20K
L5
C232
22uF
3.3V 3A
C142
22uF
3.4uH
CSD16323
2.2uH
1000pF
C172
Q1 CSD16409
Q2
R232
1000pF
20K
1000pF
EN5
C262
R132 C162
C182
C132
22uF
V5
C152
C242
22uF
1000pF
R112
22.1K
FB4
R122
R212
88.7K
22.1K
C252
FB5
1000pF
R222
6.98K
Figure 5. Six Rail Power System Part II: 3.3 V, 1.5 V and 1 V
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Product Folder Link(s): TPS65232
TPS65232
www.ti.com
SLVSA42 – FEBRUARY 2010
FDS6982
5.0V 3A
Buck 1
L1
12V
C1
C2
1.8V 3A
5.0V
Buck 2
L2
C3
1.2V 3A
Buck 3
L3
TPS65232
C4
CSD16409
1.0V 10A
Buck 1
L4
12V
C5
CSD16323
3.3V 3A
Buck 2
L5
C6
1.5V 3A
Buck 3
L6
TPS65232
C7
Figure 6. Six Rail Power System Block Diagram
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS65232
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65232A0RHA
ACTIVE
VQFN
RHA
40
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
TPS65232A0RHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
TPS65232A2DCA
ACTIVE
HTSSOP
DCA
48
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
TPS65232A2DCAR
ACTIVE
HTSSOP
DCA
48
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
TPS
65232
A0
0 to 85
TPS
65232
TPS65232
A2
0 to 85
TPS65232
A2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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