TPS65250
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SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012
4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK
CONVERTER WITH INTEGRATED FET AND DYING GASP STORAGE AND RELEASE
CIRCUIT
Check for Samples: TPS65250
FEATURES
1
•
•
•
•
•
•
•
•
Wide Input Supply Voltage Range
(4.5 V - 18 V)
0.8 V, 1% Accuracy Reference
Continuous Loading: 3 A (Buck 1),
2 A (Buck 2 and 3)
Maximum Current: 3.5 A (Buck 1),
2.5 A (Buck 2 and 3)
Adjustable Switching Frequency
300 kHz - 2.2 MHz Set By External Resistor
External Synchronization Pin for Oscillator
External Enable/Sequencing and Soft Start
Pins
Adjustable Current Limit Set By External
Resistor
•
•
•
•
•
•
Soft Start Pins
Current-Mode Control With Simple
Compensation Circuit
Power Good and Reset Generator
Storage and Release Circuit Optimized for
Reduction of Storage Capacitance in Dying
Gasp Mode (Option)
Low Power Mode Set By External Signal
QFN Package, 40-Pin 6 mm x 6 mm RHA
APPLICATIONS
•
•
•
•
•
•
xDSL/xPON Modems
Cable Modems
Power Line Modem
Home Gateway and Access Point Networks
Wireless Routers
Set Top Box
DESCRIPTION/ORDERING INFORMATION
The TPS65250 features three synchronous wide input range high efficiency buck converters. The converters are
designed to simplify its application while giving the designer the option to optimize their usage according to the
target application.
The converters can operate in 5-, 9-, 12- and 15-V systems and have integrated power transistors. The output
voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus 1 V.
Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that
allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables
designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The COMP
pin allows optimizing transient versus dc accuracy response with a simple RC compensation.
The switching frequency of the converters can either be set with an external resistor connected to ROSC pin or
can be synchronized to an external clock connected to SYNC pin if needed. The switching regulators are
designed to operate from 300 kHz to 2.2 MHz. Both Bucks 2 and Buck 3 run in-phase and 180° out of phase with
Buck 1 to minimize input filter requirements.
TPS65250 features a unique storage and release circuitry for dying gasp mode. The storage capacitor is
separated from input capacitor during normal operation. The storage and release circuit will charge the storage
capacitor with a controlled circuit to reduce the inrush current from the adaptor supply to a storage voltage of
20 V to accumulate as much energy as possible taking advantage of the ½ CV² feature.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
TPS65250
SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012
www.ti.com
TPS65250 continuously monitors the input voltage. Once the input voltage drops below a release voltage of
10.5 V, the circuit tries to transfer charge from storage capacitor to the input capacitor keeping the input voltage
closer to release value for as long as possible. The release voltage should be set lower than the processor dying
gasp detect voltage. This feature greatly reduces the capacitance required to support the dying gasp operation.
The storage and release circuitry is completely on chip except for the charge and storage capacitors. The control
circuit makes sure that the current charging the storage capacitor is limited during power up and the storage
capacitor is fully charged to its target value before the end of reset (PGOOD pin) flag to the processor is
released. The circuit also features a flag signal issued to the host circuit to indicate that the ‘dump’ stage is in
process (GASP pin). This signal can be used to initiate the dying gasp process and reduce the system
complexity. During the release process Buck 3 must stay enabled, but Buck 1 and Buck 2 can be disabled to
maximize the release time.
TPS65250 features a supervisor circuit that monitors Buck 1 and Buck 3 output voltage and generates an
internal power good (PG) signal. The PGOOD pin is asserted once sequencing is done, all PG signals are
reported and a selectable end of reset time lapses. The polarity of the PGOOD signal is active high.
TPS65250 also features a low power mode enabled by an external signal, which allows for a reduction on the
input power supplied to the system when the host processor is in stand-by (low activity) mode.
TPS65250 is packaged in a small, thermally efficient QFN RHA40 package.
2
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SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
12V
+
VPULL
VINDG
GASP
Biasing
CV3P 3
LDODG
V3V
Pump & dump
CV7
V7V
From Host
GND if not used
CLDODG
STRG
BSTDG
SYNC
CK&SYNC
ROSC
Storage cap
RBSTDG
+
CBSTDG
ROSC
BST 1
VIN1
CSS1
CIDC1
RILIM1
CBST1
SS1
LX1
RLIM1
LX1
BUCK1
V3V
External
enable
for automatic
start-up
Low Power
mode
EN1
FB 1
SS2
BUCK2
Low Power
mode
EN2
RCMP2
VPULL
for automatic
start-up
CCMP22
CBST3
LX3
RLIM3
5 /7.7/12V
LX3
BUCK3
L DC3
RFB 3U
CODC3
FB 3
EN3
RFB 3L
CMP3
Low Power
mode
for sequenced
start-up
PGOOD
CODC2
CCMP2
BST 3
SS3
V3V
External
enable
RFB 2U
RFB 2L
CMP2
VIN3
RILIM3
2.5V
L DC2
FB 2
for sequenced
start-up
CSS3
CBST2
LX2
V3V
CIDC3
CCMP1
CCMP11
LX2
RILIM2
for automatic
start-up
CODC1
RFB 1L
BST 2
RLIM2
External
enable
RFB 1U
RCMP1
VIN2
CIDC2
3.3V
L DC1
CMP1
for sequenced
start-up
CSS2
CSTRG
LX3
RCMP3
PG&RST
generator
LOW_P
CCMP3
From Host
AGND
ORDERING INFORMATION (1)
TA
–40°C to 125°C
(1)
(2)
PACKAGE (2)
40-pin (QFN) - RHA
ORDERABLE PART NUMBER
Reel of 2500
TPS65250RHAR
Reel of 250
TPS65250RHAT
TOP-SIDE MARKING
TPS65250
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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4
AGND
V3V
V7V
PGOOD
GND
LOW_P
FB2
COMP2
SS2
RLIM2
PIN OUT
30
29
28
27
26
25
24
23
22
21
GASP
31
20
EN2
LDODG
32
19
BST2
VINDDG
33
18
VIN2
STRG
34
17
LX2
BSTDG
35
16
LX2
LX3
36
15
LX1
LX3
37
14
LX1
VIN3
38
13
VIN1
BST3
39
12
BST1
EN3
40
11
EN1
2
3
4
5
6
7
8
9
SS3
COMP3
FB3
SYNC
ROSC
FB1
COMP1
SS1
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10
RLIM1
1
RLIM3
TPS65250
QFN RHA40
Copyright © 2010–2012, Texas Instruments Incorporated
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SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012
TERMINAL FUNCTIONS (DCA)
NAME
NO.
I/O
DESCRIPTION
RLIM3
1
I
Current limit setting for Buck 3. Fit a resistor from this pin to ground to set
the peak current limit on the output inductor.
SS3
2
I
Soft start pin for Buck 3. Fit a small ceramic capacitor to this pin to set the
converter soft start time.
COMP3
3
O
Compensation for Buck 3. Fit a series RC circuit to this pin to complete
the compensation circuit of this converter.
FB3
4
I
Feedback input for Buck 3. Connect a divider set to 0.8V from the output
of the converter to ground.
SYNC
5
I
Synchronous clock input. If there is a sync clock in the system, connect to
the pin. When not used connect to GND.
ROSC
6
I
Oscillator set. This resistor sets the frequency of internal autonomous
clock. If there is no synchronous clock, the operating frequency of the
regulators is set to the internal autonomous clock. If external
synchronization is used resistor should be fitted and set to ~70% of
external clock frequency.
FB1
7
I
Feedback pin for Buck 1. Connect a divider set to 0.8 V from the output of
the converter to ground.
COMP1
8
O
Compensation pin for Buck 1. Fit a series RC circuit to this pin to
complete the compensation circuit of this converter.
SS1
9
I
Soft start pin for Buck 1. Fit a small ceramic capacitor to this pin to set the
converter soft start time.
RLIM1
10
I
Current limit setting pin for Buck 1. Fit a resistor from this pin to ground to
set the peak current limit on the output inductor.
EN1
11
I
Enable pin for Buck 1. A low level signal on this pin disables it. If pin is
left open a weak internal pull-up to V3V will allow for automatic enable.
For a delayed start-up add a small ceramic capacitor from this pin to
ground.
BST1
12
I
Bootstrap capacitor for Buck 1. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
VIN1
13
I
Input supply for Buck 1. Fit a 10-µF ceramic capacitor close to this pin.
LX1
14, 15
O
Switching node for Buck 1
LX2
16, 17
O
Switching node for Buck 2
VIN2
18
I
Input supply for Buck 2. Fit a 10-µF ceramic capacitor close to this pin.
BST2
19
I
Bootstrap capacitor for Buck 2. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
EN2
20
I
Enable pin for Buck 2. A low level signal on this pin disables it. If pin is
left open a weak internal pull-up to V3V will allow for automatic enable.
For a delayed start-up add a small ceramic capacitor from this pin to
ground.
RLIM2
21
I
Current limit setting for Buck 2. Fit a resistor from this pin to ground to set
the peak current limit on the output inductor.
SS2
22
I
Soft start pin for Buck 2. Fit a small ceramic capacitor to this pin to set the
converter soft start time.
COMP2
23
O
Compensation pin for Buck 2. Fit a series RC circuit to this pin to
complete the compensation circuit of this converter
FB2
24
I
Feedback input for Buck 2. Connect a divider set to 0.8 V from the output
of the converter to ground.
LOW_P
25
I
Low power operation mode(active high) input for TPS65250
GND
26
PGOOD
27
O
Power good. Open drain output asserted after all converters are
sequenced and within regulation. Polarity is factory selectable (active high
default).
V7V
28
O
Internal supply. Connect a 10-µF ceramic capacitor from this pin to
ground.
V3V
29
O
Internal supply. Connect a 10-µF ceramic capacitor from this pin to
ground.
AGND
30
Ground pin
Analog ground. Connect all GND pins and the power pad together.
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TERMINAL FUNCTIONS (DCA) (continued)
NO.
I/O
GASP
NAME
31
O
Open drain output to signal dying gasp operation to host (active low).
DESCRIPTION
LDODG
32
O
Dying gaps 18-V supply output. Decouple with a 10-µF, 25-V ceramic
capacitor.
VINDG
33
I
Dying gasp circuit connection to input supply. Fit a 10-µF ceramic
capacitor close to this pin.
STRG
34
O
Reservoir capacitor for dying gasps "storage and release" operation.
BSTDG
35
I
Bootstrap capacitor for dying gasp circuit. Fit a ceramic capacitor from
this pin to the switching node of Buck 3.
LX3
36, 37
O
Switching node for Buck 3
VIN3
38
BST3
39
I
Bootstrap capacitor for Buck 3. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
EN3
40
I
Enable pin for Buck 3. A low level signal on this pin disables it. If pin is
left open a weak internal pull-up to V3V will allow for automatic enable.
For a delayed start-up add a small ceramic capacitor from this pin to
ground.
Input supply for Buck 3. Fit a 10-µF ceramic capacitor close to this pin.
PAD
Power pad. Connect to ground.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage range at STRG
–0.3 to 30
V
Voltage range at VIN1,VIN2, VIN3, VINDG, LDODG, LX1, LX2, LX3
–0.3 to 18
V
Voltage range at LX1, LX2, LX3 (maximum withstand voltage transient < 10 ns)
–1 to 18
V
Voltage at BST1, BST2, BST3, BSTDG, referenced to Lx pin
–0.3 to 7
V
Voltage at V7V, COMP1, COMP2, COMP3
–0.3 to 7
V
Voltage at V3V, RLIM1, RLIM2, RLIM3, EN1,EN2,EN3, SS1, SS2,SS3, FB1, FB2, FB3,
PGOOD, GASP, SYNC, ROSC, LOW_P
–0.3 to 3.6
V
Voltage at AGND, GND
–0.3 to 0.3
V
TJ
Operating virtual junction temperature range
–40 to 125
°C
TSTG
Storage temperature range
–55 to 150
°C
(1)
6
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
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SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input operating voltage
4.5
18
V
TJ
Junction temperature
–40
125
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
MAX
UNIT
Human body model (HBM) all pins but LDODG
2000
V
Human body model, LDODG
1000
V
500
V
Charge device model (CDM), VINDG
PACKAGE DISSIPATION RATINGS (1)
(1)
PACKAGE
θJA (°C/W)
TA = 25°C
POWER RATING (W)
TA = 55°C
POWER RATING (W)
TA = 85°C
POWER RATING (W)
RHA
30
3.33
2.30
1.33
Based on JEDEC 51.5 HIGH K environment measured on a 76.2 x 114 x .6-mm board with the following layer arrangement:
(a) Top layer: 2 Oz Cu, 6.7% coverage
(b) Layer 2: 1 Oz Cu, 90% coverage
(c) Layer 3: 1 Oz Cu, 90% coverage
(d) Bottom layer: 2 Oz Cu, 20% coverage
ELECTRICAL CHARACTERISTICS
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, TJ = –40°C to 125°C, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE
VIN
Input voltage range
IDDSDN
Shutdown
EN pin = low for all converters
1.3
mA
IDDQ
Quiescent, low power disabled (Lo)
Converters enabled, no load
Buck 1 = 3.3 V, Buck 2 = 2.5 V,
Buck 3 = 7.5 V,
L = 4.7 µH , fSW = 800 kHz
20
mA
IDDQ_LOW_P
Quiescent, low power enabled (Hi)
Converters enabled, no load
Buck 1 = 3.3 V, Buck 2 = 2.5 V,
Buck 3 = 7.5 V,
L = 4.7 µH , fSW = 800 kHz
1.5
mA
UVLOVIN
VIN under voltage lockout
UVLODEGLITCH
4.5
18
Rising VIN
4.22
Falling VIN
4.1
Both edges
V
V
110
µs
V3V
Internal biasing supply
3.3
V
V7V
Internal biasing supply
6.25
V
V7VUVLO
UVLO for internal V7V rail
V7VUVLO_DEGLITCH
Rising V7V
3.8
Falling V7V
3.6
Falling edge
110
V
µs
BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT START, SWITCHING FREQUENCY AND SYNC CIRCUIT, LOW POWER MODE)
Enable threshold high
V3p3 = 3.2 V - 3.4 V,
VENX rising
1.55
Enable high level
V3p3 = 3.2 V - 3.4 V
0.66 x
V3p3
Enable threshold Low
V3p3 = 3.2 V - 3.4 V,
VENX falling
1.24
Enable low level
V3p3 = 3.2 V - 3.4 V
0.33 x
V3p3
VIH
VIL
ICHEN
Pull up current enable pin
tD
Discharge time enable pins
ISS
Soft start pin current source
Power-up
V
1.1
µA
10
ms
5
µA
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TPS65250
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, TJ = –40°C to 125°C, fSW = 1 MHz (unless otherwise noted)
MAX
UNIT
FSW_BK
Converter switching frequency range
PARAMETER
Set externally with resistor
TEST CONDITIONS
MIN
0.3
TYP
2.2
MHz
RFSW
Frequency setting resistor
Depending on set frequency
50
600
kΩ
fSW_TOL
Internal oscillator accuracy
fSW = 800 kHz
-10
10
%
VSYNCH
External clock threshold high
V3p3 = 3.3 V
1.55
VSYNCL
External clock threshold low
V3p3 = 3.3 V
SYNCRANGE
Synchronization range
0.2
SYNCCLK_MIN
Sync signal minimum duty cycle
40
SYNCCLK_MAX
Sync signal maximum duty cycle
VIHLOW_P
Low power mode threshold high
V3p3 = 3.3 V, VENX rising
VILLOW_P
Low power mode threshold Low
V3p3 = 3.3 V, VENX falling
V
1.24
V
2.2
MHz
%
60
1.55
%
V
1.24
V
FEEDBACK, REGULATION, OUTPUT STAGE
VIN = 12 V , TJ = 25°C
-1%
0.8
1%
VIN = 4.5 to 18V
-2%
0.8
2%
80
120
ns
95
%
VFB
Feedback voltage
tON_MIN
Minimum on time
(current sense blanking)
D
Duty cycle range
VLINEREG
Line regulation - DC
∆VOUT/∆VINB
VINB = 4.5 V to 18 V,
IOUT = 1000 mA
0.5
%/V
VLOADREG
Load regulation - DC
∆VOUT/∆IOUT
IOUT = 10 % - 90%
IOUT,MAX
0.5
%/A
COUT
Output capacitance
Recommended fSW = 1.14 MHz
22
µF
L
Nominal Inductance
Recommended fSW = 1.14 MHz
4.7
µH
RDS_ON_HI_BUCK1
Turn-On resistance high side Buck 1
VIN = 12 V, TJ = 25°C
95
mΩ
RDS_ON_LO_BUCK1
Turn-On resistance low side Buck 1
VIN = 12 V, TJ = 25°C
50
mΩ
RDS_ON_HI_BUCK23
Turn-On resistance high side Buck 2 and 3
VIN = 12 V, TJ = 25°C
120
mΩ
RDS_ON_LO_BUCK23
Turn-On resistance low side Buck 2 and 3
VIN = 12 V, TJ = 25°C
80
mΩ
VUTTOLTRAN
1
Transient VOUT variation during load
transient measured at feedback point
∆I = 1 A in ∆t =1 µs,
CLOAD = 22 µF, ceramic
1.5
%
VUTTOLTRAN
2
Transient VOUT variation during load
transient measured at feedback point
I = 0.75 A in ∆t = 1 µs,
CLOAD = 22 µF, ceramic
1.5
%
VUTTOLTRAN
3
Transient VOUT variation during load
transient measured at feedback point
I = 0.75 A in ∆t = 1 µs,
CLOAD = 22 µF, ceramic
1.5
%
5
10
V
ILIMIT1
Peak inductor current limit range
1
4
A
ILIMIT2
Peak inductor current limit range
1
3
A
ILIMIT3
Peak inductor current limit range
1
3
A
POWER GOOD RESET GENERATOR
VUVBUCKX
Threshold voltage for buck under voltage
Output falling (device will be
disabled after tON_HICCUP )
85
Output rising (PG will be asserted)
90
%
tUV_deglitch
Deglitch time (both edges)
Each buck
11
ms
tON_HICCUP
Hiccup mode ON time
VUVBUCKX asserted
12
ms
tOFF_HICCUP
Hiccup mode OFF time
All converters disabled. Once
tOFF_HICCUP elapses, all converters
will go through sequencing again.
20
ms
Threshold voltage for buck over voltage
Output rising (high side fet will be
forced off)
109
VOVBUCKX
Output falling (high side fet will be
allowed to switch )
107
tRP
minimum reset period
%
Measured after the later of Buck1 or
Buck 3 power-up successfully
1000
0.1
0.15
A
2
3
A
ms
DYING GASP STORAGE AND RELEASE CIRCUIT
IPRECHARGE_LIMIT
Inrush current storage
VIN = 12 V, storage charging from 0
V to VIN
ISTORAGE_LIMIT
Current limit for current dumped from
storage to VIN
Dump mode. Current flowing from
VSTRG to VIN
8
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, TJ = –40°C to 125°C, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.2
TYP
MAX
UNIT
ILDO_LIMIT
Pump and dump LDO current limit
VIN = 12 V, maximum charge current
supplied by VIN
tPRECHARGE
Time to charge storage capacitor to VIN
with IPRECHARGE_LIMIT
VIN = 12 V, VSTORAGE = 18 V.
RBST = 10 Ω, CBST = 20 nF,
CSTORAGE = 1000 µF
100
ms
tCHARGE
Time to charge storage capacitor from VIN
to final charge value
VIN = 12 V, VSTORAGE = 18 V.
RBST = 10 Ω, CBST = 20 nF,
CSTORAGE = 1000 µF
100
ms
VSTORAGE
Storage Voltage range
30
V
VBST_PD
Bootstrap pin range
30
V
VLDOPD
Pump and dump LDO pin range
20
V
VLDOPD
Dying gasp Release voltage
VIN = 9 V to 15 V range
-5%
10.5
5%
V
Dying gasp Storage voltage
Storage voltage must be smaller
than ~2VIN - 1.5 V.
-5%
20.1
5%
V
VSTORAGE
0.4
0
A
THERMAL SHUTDOWN
TTRIP_OTS
Thermal shut down trip point
Rising temperature
THYST
Thermal shut down hysteresis
Device re-starts when
TJ < (TTRIP_OTS - THYST)
TTRIP_DEGLITCH
Thermal shut down deglitch
160
°C
20
°C
110
µs
CURRENT LIMIT PROTECTION
RLIM1
Limit resistance range Buck 1
RLIM2&3
Limit resistance range Bucks 2 and 3
75
300
kΩ
100
300
kΩ
1.2
5.5
A
ILIM1
Buck 1 adjustable current limit range
VIN = 12 V, fSW = 500 kHz,
see Figure 33
ILIM2
Buck 2 adjustable current limit range
VIN = 12 V, fSW = 500 kHz,
see Figure 34
1
4.1
A
ILIM3
Buck 3 adjustable current limit range
VIN = 12 V, fSW = 500 kHz,
see Figure 35
1.3
4.4
A
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STATE MACHINE
Reset state
Reset state
(VIN is low)
Read EEPROM
VIN>1.5
Check Internal
Rails (VIN, V3,
and V7)
PreCharge
nPUC=LO or
BU_EN=LO
Vstorage charges
toward VIN
VIN>Vrelease
&&
BU_EN
Faultint=1 OR
Faultext=1
Discharge
Enable
capacitors for
10msec
VIN 100 mA is applied to any of the converters,
its output will switch to PWM mode.
Always on LDOs
Two LDOS rated 3.3 V, 10 mA and 6.5 V, 10 mA are available as
long as input supply is higher than UVLO threshold.
Reduced footprint
Integrated fets in all converters plus integrated driver circuits for
storage and release, minimize the real state required by power
stage. Selectable frequency allow to reduce size of inductor plus
input/output capacitors.
Voltage supervisor and reset generator
All rails are monitored and a Power Good signal is issued after an
adjustable time-out elapses.
DETAILED DESCRIPTION
Adjustable Switching Frequency
To select the internal switching frequency connect a resistor from ROSC to ground. Figure 30 shows the required
resistance for a given switching frequency.
Figure 30. ROSC vs Switching Frequency
ROSC(kW) = 174 · f
-1.122
(1)
For operation at 800 kHz a 230-kΩ resistor is required.
Synchronization
The status of the SYNC pin will be ignored during start-up and the TPS65250’s control will only synchronize to
an external signal after the PGOOD signal is asserted. The status of the SYNC pin will be ignored during start-up
and the TPS65250 will only synchronize to an external clock if the PGOOD signal is asserted. When
synchronization is applied, the PWM oscillator frequency must be lower than the sync pulse frequency to allow
the external signal trumping the oscillator pulse reliably. When synchronization is not applied, the SYNC pin
should be connected to ground.
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Out-of-Phase Operation
Buck 1 has a low conduction resistance compared to Buck 2 and 3. Normally buck 1 is used to drive higher
system loads. Buck 2 and 3 are used to drive some peripheral loads like I/O and line drivers . The combination of
buck 2 and 3’s loads may be on par with Buck 1’s. In order to reduce input ripple current, buck 2 operates in
phase with buck 3; buck 1 and buck 2 operate 180 degrees out-of-phase. This enables the system, having less
input ripple, to lower component cost, save board space and reduce EMI.
Delayed Start-Up
If a delayed start-up is required on any of the buck converters fit a ceramic capacitor to the ENx pins. The delay
added is ~1.67 ms per nF connected to the pin. Note that the EN pins have a weak 1-MΩ pull-up to the 3V3 rail.
Soft Start Time
The device has an internal pull-up current source of 5 µA that charges an external slow start capacitor to
implement a slow start time. Equation 2 shows how to select a slow start capacitor based on an expected slow
start time. The voltage reference (VREF) is 0.8 V and the slow start charge current (Iss) is 5 µA. The soft start
circuit requires 1 nF per 200 µS to be connected at the SS pin. A 1-ms soft-start time is implemented for all
converters fitting 4.7 nF to the relevant pins.
( )
Css(nF)
Tss(ms) = VREF(V) · Iss(µA)
(2)
Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use 1%
tolerance or better divider resistors. In order to improve efficiency at light load, start with 40.2 kΩ for the R1
resistor and use the Equation 3 to calculate R2.
æ 0.8V ö
R 2 = R1 × ç
÷
è VO - 0.8V ø
(3)
Vo
TPS65250
R1
FB
R2
0.8V
+
Figure 31. Voltage Divider Circuit
Error Amplifier
The device has a transconductance error amplifier. The transconductance of the error amplifier is 130 µA/V
during normal operation. The frequency compensation network is connected between the COMP pin and ground.
Loop Compensation
TPS65250 is a current mode control dc/dc converter. The error amplifier is a 130-µA/V transconductance
amplifier. A type-II compensation circuit is adequate for the converter to have a phase margin between 60 and 90
degrees.
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Vo
iL
Co
RL
Gm=10A/V
RESR
Cff
R1
Current Sense
I/V Gain
FBx
g M = 130 u
Vref = 0.8V
COMPx
R2
Rc
CRoll
Cc
Figure 32. Loop Compensation
The design guidelines for TPS65250 loop compensation are as follows:
1. Set up cross over frequency fc.
2. RC can be determined by:
RC =
2p × fc × Vo × Co
g M × Vref × gm ps
(4)
Where is the GM amplifier gain (130 µA/V), is the power stage gain (10 A/V).
3. Place a compensation zero at the dominant pole,
fp =
1
CO × RL × 2p
(5)
CC can be determined by:
CC =
RL × Co
R3
(6)
4. C2 is optional. It can be used to cancel the zero from Co’s ESR.
C2 =
Re sr × Co
R3
(7)
In some applications the transient response performance is the primary goal, a type-III compensation circuit
allows the system having one more zero. The additional zero provides extra phase margin and the system can
achieve an extra high crossover frequency. C3 can be added at the upper leg of the output divider to form a zero
with R1.
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To calculate the external compensation components follow the following steps:
TYPE II CIRCUIT
TYPE III CIRCUIT
Select switching frequency that is appropriate for
application depending on L, C sizes, output ripple, EMI
concerns and etc. Switching frequencies between 500 kHz
and 1 MHz give best trade off between performance and
cost. When using smaller L and Cs, switching frequency
can be increased. To optimize efficiency, switching
frequency can be lowered.
Use type III circuit for switching
frequencies higher than 500 kHz.
Select cross over frequency (fc) to be less than 1/5 to 1/10
of switching frequency.
Suggested
fc = fs/10
RC =
Set and calculate Rc.
2p × fc × Vo × Co
g M × Vref × gm ps
Calculate Cc by placing a compensation zero at or before
the converter dominant pole
Cc =
1
fp =
CO × RL × 2p
Suggested
fc = fs/10
RL × Co
Rc
RC =
2p × fc × Co
g M × gm ps
Cc =
RL × Co
Rc
Add CRoll if needed to remove large signal coupling to high
impedance COMP node. Make sure that
fpRoll =
1
2 × p × RC × CRoll
CRoll =
Re sr × Co
RC
CRoll =
Re sr × Co
RC
is at least twice the cross over frequency.
Calculate Cff compensation zero at low frequency to boost
the phase margin at the crossover frequency. Make sure
that the zero frequency (fzff is smaller than soft start
equivalent frequency (1/Tss).
NA
C ff =
1
2 × p × fz ff × R1
Slope Compensation
The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic
oscillations in peak current mode control.
Power Good
The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below
85% of the nominal output voltage. The PGOOD is pulled up when Buck 1 and 3 converters’ outputs are more
than 90% of its nominal output voltage. The default reset time is 1000 ms. The polarity of the PGOOD is active
high.
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Current Limit Protection
Figure 33 shows the (peak) inductor current limit for Buck 1. The typical limit can be approximated with the
following graph.
Figure 33. Buck 1
Figure 34 shows the (peak) inductor current limit for Buck 2. The typical limit can be approximated with the
following graph.
Figure 34. Buck 2
Figure 35 shows the (peak) inductor current limit for Buck 3. The typical limit can be approximated with the
following graph.
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Figure 35. Buck 3
All converters operate in hiccup mode: Once an over-current lasting more than 10 ms is sensed in any of the
converters, they will shuts down for 10 ms and then the start-up sequencing will be tried again. If the overload
has been removed, the converter will ramp up and operate normally. If this is not the case the converter will see
another over-current event and shuts-down again repeating the cycle (hiccup) until the failure is cleared.
If an overload condition lasts for less than 10 ms, only the relevant converter affected will go into and out of
under-voltage and no global hiccup mode will occur. The converter will be protected by the cycle-by-cycle current
limit during that time.
Overvoltage Transient Protection
The device incorporates an overvoltage transient protection (OVP) circuit to minimize voltage overshoot. The
OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVTP
threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVTP
threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output
overshoot. When the FB voltage drops lower than the OVTP threshold which is 107%, the high side MOSFET is
allowed to turn on the next clock cycle.
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The
thermal shutdown hysteresis is 20°C.
Power Dissipation
The total power dissipation inside TPS65250 should not to exceed the maximum allowable junction temperature
of 125°C. The maximum allowable power dissipation is a function of the thermal resistance of the package (RJA)
and ambient temperature.
To
1.
2.
3.
calculate the temperature inside the device under continuous loading use the following procedure.
Define the set voltage for each converter.
Define the continuous loading on each converter. Make sure do not exceed the converter maximum loading.
Determine from the graphs below the expected losses in watts per converter inside the device. The losses
depend on the input supply, the selected switching frequency, the output voltage and the converter chosen.
4. To calculate the maximum temperature inside the IC use the following formula:
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THOT_SPOT = TA + PDIS · qJA
(8)
Where:
TA is the ambient temperature
PDIS is the sum of losses in all converters
θJA is the junction to ambient thermal impedance of the device and it is heavily dependant on board layout
Figure 36. Buck 1
VIN = 12 V, fSW = 500 kHz
Figure 37. Buck 1
VIN = 12 V, fSW = 1.1 MHz
Figure 38. Buck 2 and 3
VIN = 12 V, fSW = 500 kHz
Figure 39. Buck 2 and 3
VIN = 12 V, fSW = 1.1 MHz
Low Power Mode Operation
By pulling the Low_p pin high all converters will operate in pulse-skipping mode, greatly reducing the overall
power consumption at light and no load conditions. Although each buck converter has a skip comparator that
makes sure regulation is not lost when a heavy load is applied and low power mode is enabled, system design
needs to make sure that the LP pin is pulled low for continuous loading in excess of 100 mA.
When low power is implemented, the peak inductor current used to charge the output capacitor is:
IN - VOUT
ILIMIT = 0.25 · TSLEEP_CLK · V
¾
L
(9)
Where TSLEEP_CLK is half of the converter switching period, 2/fSW.
The size of the additional ripple added to the output is:
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1 ·
DVOUT = ¾
C
(
www.ti.com
VIN
L · ILIMIT2
ILOAD
- ¾
¾· ¾
2
VOUT · (VIN - VOUT) fSLEEP_CLK
)
(10)
And the peak output voltage during low power operation is:
DVOUT
VOUT_PK = VOUT + ¾
2
(11)
VOUT_PK
VOUT
Figure 40. Peak Output Voltage During Low Power Operation
APPLICATION INFORMATION
Design Guide - Step-By-Step Design Procedure
The following example illustrates the design procedure for selecting external components for the three buck
converters. For this example the following schematic will be used.
24
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1
2
3
4
5
6
GND
J3
VIN
GND
GND
R2
0
R6
0
C33
19
C24
47nF
GND
TP16
20
GND
C29
FB2A
47nF
C18
41
GND
EN2
PwrPad
V3V
1
2
3
LDODG
GASP
R16
487k
R15
16.9K
C25
C8
3
47nF
VIN
38
C9
4.7nF
DNI
GND
C34
GND
JP6
TDK-SLF7055
10uF
GND
2
L3
GND GND
37
C11
4.7uH
36
35
7.5V@0.2A
VOUT3
TP4
VOUT3
C14
R8
22nF
10
22uF
R10
0
TP9
GND
34
VOUT3
B
TP11 VIN
33
C15
TP13
32
C19
10uF
31
TP17
GASP
GND
100uF 10uF
C20
C30
C21
C22
1000uF 1000uF
4.7nF
C23
R20
35.7K
DNP
FB3
TP1
GND
GND GND
30
1
J6
TP8
FB3A
GND GND GND
R13
4.22K
TP2
GND
3.3V@2A
TP14
GND
TP3
29
47nF
GND
TP20
GND
TP15
GND
GND
V3V
R18
JP5
C28
C
V7V
TP19
PGOOD
R17
20K
4.7nF
TP18
GND
C6
39
R14
100K
AGND
FB2
28
Pin 25 SDA
and Pin 26
SCLK access
27
GND
PGOOD
GND
FB2
C26
C27
10uF
3.3uF
C
3.3V@2A
GND GND
GND
GND
JP9
R32
1.8K
R33
1.8K
D1
LTST-C190CKT
VOUT1
4
VINDG
BST2
100K
35.7K
GND
D
RLIM3
FB1
VIN2
ENB3
40
R11
4.7nF
VIN
5
6
7
8
9
SS1
RLIM1
STRG
26
R12
11.5K
18
10uF
LX2
AGND
C17
GND
JP4
BSTDG
V3V
VIN
4.7uH
LX2
24
J2
C16
22uF
LX3
TPS65250
V7V
VOUT2
R21
0
3
LX1
PGOOD
TP12
2
R9
35.7K
FB1
17
LX3
25
TP10
FB1A
GND
VOUT2
LX1
23
4.7nF
16
L2
JP3
EN3
VIN3
22
C13
TDK-SLF7055
2.5V@1.2A
1
15
U1
VIN1
21
GND
4.7uH
R4
220k
BST3
GND (SCLK)
C12
22uF
VOUT2
R19
0
10uF
14
VOUT1
3
C10
GND
TP5
B
J1
GND
VOUT1
V3V
1
13
GND
L1
3.3V@2A
R3 4.7nF
20K
BST1
LOW_P (SDA)
TDK-SLF7055
VOUT1
2
VIN
FB2
47nF
EN1
COMP2
12
SS2
11
47nF 7 C
RLIM2
ENB1
C5
4.7nF C3
JP1
FB3
FB1
CMP1
10
V3V
JP2
DNI
232K
R7
R5
20K
SYNC
180k 4.7nF
GND
A
GND
DNI
4.7nF
C4
ROSC
R1
SS3
C2
GND
C31
10uF
35V
GND
C1
C32
FB3
GND
2
COMP3
1
A
R38
20K
Q3
MMBT2222A
GND
VOUT2
R34
1.8K
D2
LTST-C190CKT
R39
6.8K
Q4
MMBT2222A
GND
VOUT3
R37
1.8K
D3
LTST-C190CKT
R40
6.8K
Q5
MMBT2222A
R22
1.8K
D4
LTST-C190GKT
PGOOD R43
6.8K
GND
Q1
MMBT2222A
D5
LTST-C190GKT
GASP
R23
GND
D
Q8
MMBT2222A
6.8K
Title
Size
GND
B
Texas Instruments
Number
sion
Revi
TPS65250
0p2
Date:
12/2/201
0 heet of
S
File: :\CMSCProjects\..\Troika_250_02_25_2010.SchDocDrawn By:
1
2
3
4
5
6
Figure 41. TPS65250 Reference Design
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The control and power signals used in the design are shown in Table 2.
Table 2. Control and Power Signals
SIGNAL
TYPE
STATUS
FUNCTION
POWER
VIN
I
12-V DC main supply to TPS65250
GND
System ground. All ground pins and power pad should be connected together.
3.3V
O
Output of Buck 1
2.5V
O
Output of Buck 2
7.5V
O
Output of Buck 3
VPULL
O
Voltage used to connect the pull-up resistors of the Open Drain outputs
(PGOOD, GASP).
CONTROL
EN1, EN2
I
Active high
Enable signals for Buck 1 and Buck 2. Left open they will start automatically
once power is applied. If capacitors are fitted to their enable pins, start-up will be
delayed.
EN3
I
Active high
Enable signal for Buck 3. Externally enabled by host processor. During the
release stage (GASP) Buck 3 must stay enabled.
LOW_P
I
Active high
External processor signal to force buck converters in low power mode and
reduce input power.
SYNC
I
PGOOD
O
Active low
PGOOD (end of reset signal) to processor. Buck 1 and Buck 3 are monitored.
GASP
O
Active low
Release stage of the pump and dump procedure. Input supply collapsed and
energy stored in CSTG capacitor is released in a controlled way to the input
supply.
External 1.14-MHz clock. Device will start with an internal frequency set to
0.8 MHz.
The following example illustrates the design procedure for selecting external components for the three buck
converters. The example focuses on BUCK 1, but the procedure can be directly applied to BUCK 2 and 3 as
well. The design goal parameters are given in Table 3.
Table 3. Design Parameters
Output voltage
3.3 V
Transient response 0.5-A to 2-A load step
165 mV
Maximum output current
2A
Input voltage
12 V nom, 9.6 V to 14.4 V
Output voltage ripple
< 30 mV p-p
Switching frequency
500 kHz
Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, you will want to choose the
highest switching frequency possible since this will produce the smallest solution size. The high switching
frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. However, the highest switching frequency causes extra switching losses, which
hurt the converter’s performance. The converter is capable of running from 300 kHz to 2.2 MHz. Unless a small
solution size is an ultimate goal, a moderate switching frequency of 500 kHz is selected to achieve both a small
solution size and a high efficiency operation. Note however that for xDSL applications is desirable to synchronize
the converter to the system clock running at either 1.1 MHz or 2.2 MHz. If 1.1 MHz is to be used, set the external
resistor to 232 kΩ for PMIC switching at 800 KHz (~70% of clock frequency).
Output Inductor Selection
To calculate the value of the output inductor, use Equation 12. KIND is a coefficient that represents the amount
of inductor ripple current relative to the maximum output current. In general, KIND is normally from 0.1 to 0.3 for
the majority of applications.
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For this design example, use KIND = 0.2 and the inductor value is calculated to be 5.4 µH. For this design, a
nearest standard value was chosen: 4.7 µH. For the output filter inductor, it is important that the RMS current
and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 13 and Equation 14.
Lo =
Vin - Vout Vout
×
Io × K ind Vin × fsw
Iripple =
(12)
Vin - Vout Vout
×
Lo
Vin × fsw
(13)
1 æ Vo × (Vin max - Vo) ö
ILrms = Io + × ç
÷
12 è Vin max× Lo × fsw ø
2
2
(14)
Iripple
ILpeak = Iout +
2
(15)
Output Capacitor
There are two primary considerations for selecting the value of the output capacitor. The output capacitors are
selected to meet load transient and output ripple’s requirements.
Equation 16 gives the minimum output capacitance to meet the transient specification. For this example, LO = 4.7
µH, ΔIOUT = 2 A – 0.5 A = 1.5 A and ΔVOUT = 165 mV. Using these numbers gives a minimum capacitance of
19.4 µF. A standard 22-µF ceramic capacitor is chose in the design.
Co >
DI OUT 2 × Lo
Vout × DVout
(16)
Equation 17 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, VRIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. From Equation 13, the output
current ripple is 0.46 A. From Equation 17, the minimum output capacitance meeting the output voltage ripple
requirement is 1.74 µF.
Co >
1
1
×
8 × fsw Vripple
Iripple
(17)
After considering both requirements, for this example, one 22-µF, 6.3-V X7R ceramic capacitor with 3 mΩ of
ESR will be used.
Input Capacitor
A minimum 10-µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These
capacitors should be connected as close as physically possible to the input pins of the converters as they handle
the RMS ripple current shown in Equation 18. For this example, IOUT = 2 A, VOUT = 3.3 V, VINmin = 9.6 V, from
Equation 18, the input capacitors must support a ripple current of 1.81 A RMS.
Icirms = Iout ×
Vout (Vin min - Vout )
×
Vin min
Vin min
(18)
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 19. Using the design example values, IOUTmax = 2 A, CIN = 10 µF, fSW = 1100 kHz,
yields an input voltage ripple of 45 mV.
DVin =
Iout max× 0.25
Cin × fsw
(19)
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Bootstrap Capacitor Selection
A 0.047-µF ceramic capacitor must be connected between the BST to LX pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or
higher voltage rating.
Adjustable Current Limiting Resistor Selection
The converter uses the voltage drop on the high-side MOSFET to measure the inductor current. The over current
protection threshold can be optimized by changing the trip resistor. Figure 33 governs the threshold of over
current protection for Buck 1. When selecting a resistor, do not exceed the graph limits. In this example, the over
current threshold is 3.2 A. In order to prevent a premature limit trip, the minimum line is used and the resistor is
100 kΩ.
When setting high-side current limit to large current values, ensure that the additional load immediately prior to
an overcurrent condition will not cause the switching node voltage to exceed 20 V. Additionally, ensure during
worst case operation, with all bucks loaded immediately prior to current limit, the maximum virtual junction
temperature of the device does not exceed 125°C.
Bootstrap Capacitors
The device has three integrated boot regulators and requires a small ceramic capacitor between the BST and LX
pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.047 µF. For the pump circuit use 0.022 nF. A ceramic capacitor with an X7R or X5R grade dielectric is
recommended because of the stable characteristics over temperature and voltage.
Output Voltage and Feedback Resistors Selection
For the example design, 35.7 kΩ was selected for R10. VOUT is 3.3 V, VREF = 0.8 V. Using Equation 3, R7 is
calculated as 11.5 kΩ. A standard 80.6-kΩ resistor is chose in this design.
Compensation
TPS65250 is a current mode control dc/dc converter. It uses a transconductance error amplifier. A type-II
compensation circuit is adequate for the converter to have a phase margin between 60 and 90 degrees. The
following equations show the procedure of designing a peak current mode control dc/dc converter.
The compensation design takes the following steps:
1. Set up the anticipated cross-over frequency. Use Equation 4 to calculate the compensation network’s resistor
value. In this example, the anticipated cross-over frequency (fc) is 65 kHz. The power stage gain ( ) is 10A/V
and the GM amplifier gain (gmps ) is 130 µA/V.
2. Place compensation zero at low frequency to boost the phase margin at the crossover frequency. From the
procedures above, the compensation network includes a 20-kΩ resistor (R12) and a 4700-pF capacitor (C1).
3. An additional pole can be added to attenuate high frequency noise.
In some applications the transient response performance is the primary goal, a type-III compensation circuit
allows the system having one more zero. The additional zero provides extra phase margin and the system can
achieve an extra high crossover frequency. In this example, a 4.7-nF capacitor can be added at the upper leg of
the output divider. C15 and R10 form a zero, which boost the phase margin and lift the gain so that the converter
has a high crossover frequency at 100 kHz.
28
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3.3-V and 6.5 LDO Regulators
The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:
• 10 µF for V7V pin 28
• 3.3 µF for V3V pin 29
Choice of Converter for Pump Operation And Sequencing Requirement
Figure 42. Pump and Dump Pins
Although any converter can be used to feed the pump circuit buck 3 is the best option that allows for an easy
layout as the input of the pump circuit (BSTG pin 35) is next to its switching node and allows for a short
connection for a trace associated to a high frequency switching node. Connect a 22-nF capacitor in series with a
10-Ω resistor from the LX3 node to the BSTDG pin.
The storage capacitor charges in two stages:
1. When VIN is applied the capacitor charges in a controlled way to a voltage close to VIN at a rate of 0.1 ms/µF.
2. Once the capacitor is charged Buck 3 is enabled and its switching node provides the energy to charge the
capacitor to the final storage voltage. Once this voltage is achieved the pump circuit will only provide current
to compensate the self-discharge of the storage capacitor.
Note that it is important that these two charge stages do not overlap. In other words buck 3 must be enabled only
after the first stage of charging is achieved.
Based on these considerations the following sequencing requirement is required:
Table 4. Sequencing
CONVERTER
V
FUNCTION
SEQUENCING
SOFT START
Buck 1
3.3
System, SoC
1st supply to start, no delay. EN1 tied to
V3P3.
Use 4.7 nF to achieve SS ~0.5 ms.
Buck 2
2.5
MEM, I/O, SoC
Simultaneous start with buck 1. EN2 tied
to v3P3.
Use 3.9 nF to achieve rationometric startup with respect to Buck 1.
Buck 3
7.5
Line drivers
Enabled by SoC. Must start after storage
capacitor settles tI ~VIN.
Use 4.7 nF.
If a 2000-µF capacitor is used for storage, Buck 3 must start at least 200 ms after Buck 1 and Buck 3 are
enabled. There are two possible options to cover the sequencing requirement on Buck 3:
• Use a GPIO from the SoC connected To EN3. There will be a delay of hundreds of ms to a few seconds
before the line drivers are enabled. By then the storage capacitor will be charged to ~VIN.
• Fit a capacitor at the EN pin. With a delay of 1.67 ms/nF, a 470-nF capacitor will provide a delay of ~784 ms
from the time when Buck 1 and Buck 2 are enabled to the time when Buck 3 is enabled. This will provide
ample time for the storage capacitor to settle at ~VIN and also for addition of more storage capacitance if
required.
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Capacitance Reduction With TPS65250 Pump and Dump Circuit
Table 6 shows the capacitance reduction achieved compared to the typical application where the storage
capacitor is connected to the adapter supply the following formula applies.
1 C (V 2 - V 2)
Dt = ¾
LOW
2 IN DET
(20)
Where:
P = Gasp power
∆t = Gasp time, 60 ms
VDET = Detection voltage (at this point is assumed input supply has disappeared), 11 V
VLOW = Minimum gasp voltage, 8.5 V
Size of Storage Capacitor
On choosing the capacitor for storage the following considerations should be taken into account:
• Capacitor type: Given the relatively high values required for gasp applications electrolytic are typically the
choice of capacitor due to their low cost.
• Capacitor voltage rating and derating: The electrolytic capacitors of interest for a 12-V application are rated at
25 V. Assuming an 80% derating factor, this will match the storage voltage. Bear in mind that the accuracy of
this voltage is 5%, therefore calculations should include the worst case number. For a 20-V setting the
storage voltage will be in the 19 V - 21 V range.
• Capacitor dimension: For this particular example a 25-mm height restriction is in place.
• Capacitor tolerance and life: As electrolytic capacitors degrade with time the choice of capacitor will dictate
the overall system life expectancy. It is recommended to add the following adjustment factors to the chosen
capacitor value.
• Capacitor package: Surface mount devices are considerably more expensive than through hole devices.
Based on these considerations the series M of Panasonic through hole capacitors is chosen.
http://industrial.panasonic.com/www-data/pdf/ABA0000/ABA0000CE12.pdf
Good savings and real estate reductions can be obtained if 25-V capacitors are used. As Table 5 shows only the
1000-µF part meets the height restriction of the design.
Table 5. 25-V Capacitors That
Can Be Used in TPS65250
Pump and Dump Circuit to
Support 2.85 W
C (µF)
HEIGHT (mm)
1000
20
2200
25 (too tall)
3300
25 (too tall)
4700
31 (too tall)
Table 6 shows the tabulated results for the TPS65250 P&D circuit with a gasp time of 60 ms, power levels of 1
W to 4 W, showing the capacitance (CSTRG) required for 20-V storage. The column CIN shows the capacitance
required using the typical approach of adding capacitance to the input supply. The data clearly shows that the
pump and dump circuit allows for a major reduction in the storage capacitor.
Table 6. Storage Capacitance required with TPS65250 Pump and Dump Circuit
PVGASP →
30
P = 1W
P=2W
P=3W
P=4W
VSTRG↓
CIN (µF)
CSTRG (µF)
CIN (µF)
CSTRG (µF)
CIN (µF)
CSTRG (µF)
CIN (µF)
CSTRG (µF)
20
2,462
602
4,923
1,203
7,385
1,805
9,846
2,406
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Going through the iterative procedure, using only two 1000-µF, 25-V capacitors will allow for a gasp power in
excess of 2.85 W, instead of the 6 required in the application without the pump and dump feature.
Table 7. 25-V Capacitors Used in TPS65250 Pump and Dump Circuit to Support 2.85 W
ECA1CM222B
C (µF)
P_GASP (W)
COMMENT
1
1000
1.63
Too little
2
2000
3.26
About right
3
3000
4.89
Too much
Note that the final capacitor value needs to be adjusted for the worst case of tolerance (typically -20%) and
reduction of capacitor value at the end of tis life expectancy (typically 20%).
Pump and Dump Plots
Figure 43 shows the pump stage plots. Green trace is the input supply (12 V), yellow trace is the storage
capacitor voltage, purple trace is the Buck 3 supply and blue trace is the PGOOD signal. The storage capacitor is
2000 µF and it takes ~200 ms to charge to the input supply. BUCK has a 470-nF capacitor connected to the EN
pin provides a delay of ~800 ms from the time when the input voltage is applied and the storage capacitor
charges to the 20-V target and the PGOOD signal has a 2-s delay before being asserted.
Figure 44 shows the dump stage plots. Yellow trace is the storage capacitor voltage, purple trace is the VIN
supply and blue trace is the 7.5-V Buck 3 signal green trace is Buck 3 current. The total gasp time is ~70 ms
which is consistent with the calculations shown.
STRG
V in
BUCK3
I_BUCK3
Figure 43. Pump Operation
Figure 44. Dump Operation
Table 8 shows the loading on the rails plus rail efficiency to show the total power of ~3.18 W provided by the 12V adapter supply.
Table 8. Rail Loading for TPS65250 Pump and Dump Circuit Verification
RAIL
V
I (A)
PO (W)
EFFICIENCY
PIN (W)
Buck 1
3.3
0.22
0.73
85%
0.85
Buck 2
2.5
0.21
0.53
87%
0.6
Buck 3
7.5
0.2
1.5
87%
1.72
12 V
12
0.02
Total
0.24
2.75
3.42
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65250RHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS
65250
TPS65250RHAT
ACTIVE
VQFN
RHA
40
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS
65250
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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