TPS65252 High Current, Synchronous Step
Down Two Buck Switcher Evaluation Module
User's Guide
Literature Number: SLVU438
January 2011
2
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© 2011, Texas Instruments Incorporated
1
2
3
4
5
Introduction ........................................................................................................................ 5
Background ........................................................................................................................ 5
Schematic .......................................................................................................................... 5
Placement .......................................................................................................................... 7
Bench Test Setup Conditions .............................................................................................. 10
6
7
...................................................................... 10
5.2
Jumpers ................................................................................................................. 11
5.3
Test Points and Placement ........................................................................................... 11
Power-Up Procedure .......................................................................................................... 12
Bill of Materials ................................................................................................................. 12
5.1
Headers Description and Jumper Placement
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Table of Contents
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3
www.ti.com
List of Figures
1
TPS65252 Schematic ...................................................................................................... 6
2
Top Layer .................................................................................................................... 7
3
Layer 1
8
4
Layer 2
8
5
6
7
.......................................................................................................................
.......................................................................................................................
Layer 3 .......................................................................................................................
Layer 4 .......................................................................................................................
Headers Description and Jumper Placement ..........................................................................
9
9
10
List of Tables
4
1
Input Voltage and Output Current Summary ............................................................................ 5
2
Jumpers ..................................................................................................................... 11
3
Test Points and Placement............................................................................................... 11
4
Bill of Materials
............................................................................................................
List of Figures
12
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1
Introduction
This document presents the information required to power the TPS65252 PMIC as well as the support
documentation including schematic and bill of materials.
2
Background
The TPS65252 PMIC is designed to provide 3-A and 2-A continuous outputs with an operational range of
4.5 V to 18 V and a externally set switching frequency ranging from 300 kHz to 2.2 MHz. When the PMIC
is not fully loaded, buck1 can be loaded to 3.5 A and buck 2 to 2.5 A. It also features a power distribution
switch with selectable current limit.
As there are many possible options to set the converters, Table 1 presents the performance specification
summary for the EVM.
Table 1. Input Voltage and Output Current Summary
EVM
TEST CONDITIONS
TPS65252EVM
VIN = 4.5 V to 16 V
fsw = 500 kHz
OUTPUT CURRENT RANGE
Buck1, 1.2 V, 3 A
Buck2, 1.8 V, 2 A
(25°C ambient)
This evaluation module is designed to provide access to the features of the TPS65252. Some
modifications can be made to this module to test performance at different input and output voltages,
current and frequency operation. Please contact TI Field Applications Group for advice on these matters.
3
Schematic
See next page.
The resistor and capacitor values have been chosen according to the guidelines presented on the
TPS65252 spec available at http://focus.ti.com/docs/prod/folders/print/TPS65252.html.
Note that for the purpose of gains-phase measurements R9 and R11 (0 Ω on the EVM) need to be
replaced by suitable low value resistors as per the network analyzer setup required. Test points are
provided on either end of the resistors to allow for easy measurement.
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List of Tables
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5
Schematic
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Figure 1. TPS65252 Schematic
6
List of Tables
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Placement
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4
Placement
Figure 2. Top Layer
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List of Tables
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7
Placement
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Figure 3. Layer 1
Figure 4. Layer 2
8
List of Tables
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Placement
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Figure 5. Layer 3
Figure 6. Layer 4
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List of Tables
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9
Bench Test Setup Conditions
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5
Bench Test Setup Conditions
5.1
Headers Description and Jumper Placement
TP
LOW P
Vin: 4.5 V – 16 V
EN 2
TP
TP
TP
TP
TP
TP
TP
Vout 2
TP
Vout_1
USB_IN
TP
TP
TP
USB_OUT
EN 1
TP
TP
TP
Figure 7. Headers Description and Jumper Placement
Test points:
Black – GND
White – Each output, feed-back, power good and VIN. All marking on PCB.
10
List of Tables
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Bench Test Setup Conditions
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5.2
Jumpers
Table 2. Jumpers
5.3
JUMPER
NO.
FUNCTION
PLACEMENT
COMMENT
JP15
BUCK1 enable (EN1)
For sequencing do not fit jumper.
To disable converter fit jumper to GND.
Fit according to test requirement
JP6
BUCK2 enable (EN2)
For sequencing do not fit jumper.
To disable converter fit jumper to GND.
Fit according to test requirement
JP20
LOW_P
Low power: Power save mode ON/OFF.
If need low power mode test, should connect
V3V.
Fit according to test requirement.
During normal operation jumper must
be fitted.
JP24
PGOOD
Pulls PGOOD signal to internal 3V3 rail or
grounds pin
Fit according to test requirement
JP25
USB_EN
Enables power switch when tied to 3v3.
Disables power switch when tied to GND.
Fit according to test requirement
JP26
USB_nILIM
When fitted connects USB switch alarm to
internal 3V3 rail
Fit according to test requirement
Test Points and Placement
Buck converter outputs are white and have a label for easy location. Close to any of these test points
there are black ground test points to allow for DVM measurement or to use a metal exposed scope probe
to reduce common mode noise measurements. All test points are described in Table 3.
Table 3. Test Points and Placement
TEST
POINT
NAME
SIGNAL
COLOR
TP1, TPS, TP3,
TP4, TP5
GND
Ground
Black
TP8
VIN
Input supply
White
TP9, TP9A
VOUT1
Buck1 output
White
Input for gain-phase measurement Buck1
White
TP9B
TP11, TP11A
VOUT2
TP11B
Buck2 output
White
Input for gain-phase measurement Buck2
White
TP20
LowP
Low Power input
White
TP23
rUSB
USB switch current set pin
White
TP24
PGOOD
Power Good
(open drain connected to Buck1 output)
White
TP25
USB_EN
Enable pin for USB swtich
White
TP26
USB_nILIM
USB switch alarm pin
White
TP27
USB_VIN
USB switch input
White
TP28
USB_Vo
USB switch output
White
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COMMENT
Normally not used
Normally not used
List of Tables
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11
Power-Up Procedure
6
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Power-Up Procedure
1. Define which converters are to be enabled or disabled by connecting the correct jumpers accordingly.
2. Apply a DC voltage to jumper J8. Polarity is clearly marked on the silk-screen.
3. Verify that the relevant converters are powered up by the output voltages. The whole start-up process
will take less than 100 ms. PGOOD will be asserted after 256 ms.
4. Apply loads to the output connectors.
5. To power the USB switch apply a suitable voltage to jumper 27 and enable the switch by connecting
JP25 to 3V3 or leave it open.
7
Bill of Materials
Table 4. Bill of Materials
ITEM
QUANTITY
DESIGNATOR
VALUE
FOOTPRINT
MANUFACTURER
MANUFACTURER
PART NO.
VENDER PART
NO.
DESCRIPTION
1
2
DNI: C2A,
C18a
Do not
install
100 pF
603
Panasonic-ECG
ECJ-1VC1H101J
PCC101ACVDKRND
CAP CERAMIC
100 pF 50 V 0603
SMD
2
2
C7, C14
47 nF
603
Panasonic-ECG
ECJ-1VB1E473K
PCC1771DKR-ND
CAP 47000 pF 25 V
CERM X7R 0603
3
2
C8, C13
10 µF
1210
Murata Electroics
North America
GRM32ER7YA1
06KA12L
490-5314-6-ND
CAP CER 10 µF
35 V X7R 10%
1210
4
2
C9, C11
22 µF
1210
Panasonic-ECG
ECJ-4YB1E226M
PCC2333DKR-ND
CAP CERAMIC
22 µF 25 V X5R
1210
5
3
C21, C27, C28
10 µF
603
Panasonic-ECG
ECJ-1VB1A106M
PCC2479DKR-ND
CAP CERAMIC
10 µF 10 V 0603
X5R
6
1
C22
4.7 µF
603
Panasonic-ECG
ECJ-1VB0J475M
PCC2318DKR-ND
CAP CERAMIC
4.7 µF 6.3 V X5R
0603
7
2
DNI: C27A,
C28A
Do not
purchase
item
Do not purchase
item
Do not purchase
item
8
5
J8, J9, J11,
J27, J28
ED555/
2DS
9
3
10
Do not purchase item
TB_2X3.5MM
On Shore Technology
ED555/2DS
ED1514-ND
TERMINAL BLOCK
3.5 mm 2POS PCB
JP6, JP15,
JP26
JMP0.2
Mil-Max
800-10-064-10001000
ED7264-ND
SIP HEADER 64
POS STRAIGHT
PCB
3
JP20, JP24,
JP25
JMP0.3
Mil-Max
800-10-064-10001000
ED7264-ND
SIP HEADER 64
POS STRAIGHT
PCB
11
2
L9, L11
4.7 µH
IND_SLF7055
TDK Corporation
SLF7055T4R7N3R1-3PF
445-4563-2-ND
Magnetic-Core
Inductor
12
1
R1
383 kΩ
603
Panasonic-ECG
ERJ-3EKF3833V
P383KHDKR-ND
RES 383 kΩ 1/10 W
1% 0603 SMD
13
2
R2, R18
20 kΩ
603
Panasonic-ECG
ERJ-3EKF2002V
P20.0KHCT-ND
RES 20 kΩ 1/10 W
1% 0603 SMD
14
3
R5, R24, R26
100 kΩ
603
Panasonic-ECG
ERJ-3EKF1003V
P100KHCT-ND
RES 100 kΩ 1/10 W
1% 0603 SMD
15
2
R9, R11
0
603
Vishay/Dale
CRCW06030000
Z0EA
541-0.0GDKR-ND
RES 0 Ω 1/10 W
5% 0603 SMD
16
2
R9a, R11a
40.2 kΩ
603
Panasonic-ECG
ERJ-3EKF4022V
P40.2KHDKR-ND
RES 40.2 kΩ
1/10 W 1% 0603
SMD
17
1
R9b
80.6 kΩ
603
Panasonic-ECG
ERJ-3EKF8062V
P80.6KHDKR-ND
RES 80.6 kΩ
1/10 W 1% 0603
SMD
18
1
R11b
32.4 kΩ
603
Yageo
RC0603FR0732K4L
311-32.4KHRDKRND
RES 32.4 kΩ
1/10 W 1% 0603
SMD
19
1
R16
120 kΩ
603
Panasonic-ECG
ERA-3AEB124V
P120KDBDKR-ND
RES 120 kΩ 1/10 W
.1% 0603 SMD
12
List of Tables
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Bill of Materials
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Table 4. Bill of Materials (continued)
ITEM
QUANTITY
DESIGNATOR
VALUE
FOOTPRINT
MANUFACTURER
MANUFACTURER
PART NO.
VENDER PART
NO.
DESCRIPTION
20
1
R23
124 kΩ
603
Panasonic-ECG
ERJ-3EKF1243V
P124KHDKR-ND
RES 124 kΩ 1/10 W
1% 0603 SMD
21
14
TP8, TP9,
TP9A, TP9B,
TP11, TP11A,
TP11B, TP20,
TP23, TP24,
TP25, TP26,
TP27, TP28
TEST POINT
0.042
Keystone Electronics
5002
5002K-ND
TEST POINT PC
MINI .040" D
WHITE
22
5
TP1, TP2, TP3,
TP4, TP5
TEST POINT
0.042
Keystone Electronics
5001
5001K-ND
TEST POINT PC
MINI .040" D
BLACK
23
1
U1
QFN28 [RHD]
25
8
C2, C4, C6,
C9A, C1, 1A,
C15, C17, C18
4.7 nF
603
Panasonic-ECG
ECJ-1VB1H472K
PCC1780TR-ND
CAP 4700 pF 50 V
CERAMIC X7R
0603
26
1
C1, Do not
install
DNI:
22 µF
1210
AVX Corp
12103D226KAT2A
478-5999-6-ND
CAP CER 22 µF
25 V X5R 10%
1210
TPS65252
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List of Tables
© 2011, Texas Instruments Incorporated
13
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EVM Warnings and Restrictions
It is important to operate this EVM within the input voltage range of and the output voltage range of .
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than . The EVM is designed to operate
properly with certain components above as long as the input and output ranges are maintained. These components include but are
not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be
identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices
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