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Table of Contents
User’s Guide
TPS65253 Buck Converter Evaluation Module User's
Guide
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Background.............................................................................................................................................................................3
3 Schematic................................................................................................................................................................................4
4 Placement................................................................................................................................................................................5
5 Bench Test Setup Conditions................................................................................................................................................ 8
5.1 Headers Description and Jumper Placement.....................................................................................................................8
5.2 Jumpers..............................................................................................................................................................................9
5.3 Test Points and Placement.................................................................................................................................................9
6 Power-Up Procedure............................................................................................................................................................ 10
7 Bill of Materials......................................................................................................................................................................11
8 Revision History................................................................................................................................................................... 12
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1
Introduction
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1 Introduction
This document presents the information required to power the TPS65253 PMIC as well as the support
documentation including schematic and bill of materials.
2
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Background
2 Background
The TPS65253 PMIC is designed to provide 3.5-A and 2.5-A continuous outputs with an operational range of 4.5
V to 16 V and an externally set switching frequency ranging from 300 kHz to 1.2 MHz. When the PMIC is not
fully loaded, buck1 can be loaded to 4 A and buck 2 to 3 A.
As there are many possible options to set the converters, Table 2-1 presents the performance specification
summary for the EVM.
Table 2-1. Input Voltage and Output Current Summary
EVM
TEST CONDITIONS
TPS65253EVM
VIN = 4.5 V to 16 V
fsw = 500 kHz
OUTPUT CURRENT RANGE
Buck1, 1.2 V, 3.5 A
Buck2, 3.3 V, 2.5 A
(25°C ambient)
This evaluation module is designed to provide access to the features of the TPS65253. Some modifications
can be made to this module to test performance at different input and output voltages, current and frequency
operation. Please contact TI Field Applications Group for advice on these matters.
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Schematic
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3 Schematic
Figure 3-1 illustrates the TPS65253 EVM schematic.
The resistor and capacitor values have been chosen according to the guidelines presented on the TPS65253 spec available at http://focus.ti.com/docs/
prod/folders/print/TPS65253.html.
R24
100K
3
1
4
2
S26
R26
TP24
24
TP25
25
TP26
JP26
0
27
V7V
C26
0.1uF
DNI
26
TP28
28
20K
15
EN2
RLIM2
16
17
SS2
COMP2
18
19
FB2
20
V3p3
VIN2
U1
PGOOD
LX2
TPS65253
PB
LX2
MR/SCL
LX1
LH
LX1
INT
R28
100K
VIN1
14
C13
10uF
25V
VIN
13
TP11a
11
4.7uH
L11
10
TP8
VIN
C8
10uF
25V
C3
4.7nF
TP9b
L9
C9 TP9a
22uF
R9
0
1
1.8V@2A VOUT2
J9
1.2V@3A VOUT1
2
R9a
C9a
4.7nF
7
6
4
3
5
R5
100K
47nF
C7
JP6
TP11b
R9b FB1
80.6K
C6
4.7nF
R3
20K
C4
4.7nF
FB1
C3a
DNI 100pF
TP1 TP2 TP3 TP4 TP5
2
1
R1
383K
2
TP11
4.7uH
8
VIN
J8
1
R11
0
TP9
9
2
J11
22uF
C11
12
VIN
C11a
4.7nF
R11a
40.2K
40.2K
V3p3
1
FB2
47nF
C14
BST1
23
C15
4.7nF
R11b
32K
BST2
EN1
TP23
V3p3
V3p3
RLIM1
4.5V
22
SS1
JP25
C22
3.3uF
JP23 V3p3
COMP1
C25
0.1uF
DNI
FB1
S25
0
LOW_P/SDA
21
2
PP
ROSC
4
29
R25
V7V
V3p3
1
JP15
TP20
FB2
V7V
3
R16 150K
C21
10uF
C17
4.7nF
SDA
V3p3
R18
DNI C18a
JP20
C18 4.7nF
100pF
Note that for the purpose of gains-phase measurements R9 and R11 (0 Ω on the EVM) need to be replaced by suitable low value resistors as per the
network analyzer setup required. Test points are provided on either end of the resistors to allow for easy measurement. Also, R3, R4, C10, and C12 can
be populated if users desire to reduce overshoot at LX pins due to parasitic L and C resonance.
Figure 3-1. TPS65253 Schematic
4
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Placement
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4 Placement
Figure 4-1. Part Placement
Figure 4-2. Top Layer
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Placement
Figure 4-3. Mid-Layer 1
Figure 4-4. Mid-Layer 2
6
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Placement
Figure 4-5. Bottom Layer
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Bench Test Setup Conditions
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5 Bench Test Setup Conditions
5.1 Headers Description and Jumper Placement
LOW_P
EN2
Vin:4.5V – 16V
PGOOD
Vout2
Vout1
EN1
Figure 5-1. Headers Description and Jumper Placement
Test points:
Black – GND
White – Each output, feed-back, power good and VIN. All marking on PCB.
8
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Bench Test Setup Conditions
5.2 Jumpers
Table 5-1. Jumpers
JUMPER
NO.
FUNCTION
PLACEMENT
COMMENT
JP6
BUCK1 enable (EN1)
For sequencing do not fit jumper.
To disable converter fit jumper to GND.
Fit according to test requirement
JP15
BUCK2 enable (EN2)
For sequencing do not fit jumper.
To disable converter fit jumper to GND.
Fit according to test requirement
JP20
LOW_P
Low power: Power save mode ON/OFF.
If need low power mode test, should connect V3V.
Fit according to test requirement.
During normal operation jumper must be
fitted.
JP24
PGOOD
Pulls PGOOD signal to internal 3V3 rail or
grounds pin
Fit according to test requirement
5.3 Test Points and Placement
Buck converter outputs are white and have a label for easy location. Close to any of these test points there
are black ground test points to allow for DVM measurement or to use a metal exposed scope probe to reduce
common mode noise measurements. All test points are described in Table 5-2.
Table 5-2. Test Points and Placement
TEST
POINT
NAME
SIGNAL
COLOR
TP1, TPS, TP3,
TP4, TP5
GND
Ground
Black
TP8
VIN
Input supply
White
TP9, TP9A
VOUT1
Buck1 output
White
Input for gain-phase measurement Buck1
White
Buck2 output
White
TP9B
TP11, TP11A
VOUT2
TP11B
Input for gain-phase measurement Buck2
White
TP20
Low_P
Low Power input
White
TP24
PGOOD
Power Good
(open drain connected to Buck1 output)
White
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COMMENT
Normally not used
Normally not used
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Power-Up Procedure
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6 Power-Up Procedure
1. Define which converters are to be enabled or disabled by connecting the correct jumpers accordingly.
2. Apply a DC voltage to jumper J8. Polarity is clearly marked on the silk-screen.
3. Verify that the relevant converters are powered up by the output voltages. The whole start-up process will
take less than 100 ms. PGOOD will be asserted high 32 ms after all converter outputs have reached 90% of
nominal voltages.
4. Apply loads to the output connectors (J9 and J11).
10
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Bill of Materials
7 Bill of Materials
Table 7-1. Bill of Materials
ITEM
QUANTITY
DESIGNATOR
VALUE
FOOTPRINT
MANUFACTURER
MANUFACTURER
PART NO.
VENDER PART
NO.
DESCRIPTION
1
2
DNI
C2A, C18a
100 pF
603
Panasonic-ECG
ECJ-1VC1H101J
PCC101ACVDKRND
CAP CERAMIC
100 pF 50 V 0603
SMD
2
2
C7, C14
47 nF
603
Panasonic-ECG
ECJ-1VB1E473K
PCC1771DKR-ND
CAP 47000 pF 25 V
CERM X7R 0603
3
2
C8, C13
10 µF
1210
Murata Electroics
North America
GRM32ER7YA1
06KA12L
490-5314-6-ND
CAP CER 10 µF
35 V X7R 10% 1210
4
4
C5, C3, C9,
C11
22 µF
1210
Panasonic-ECG
ECJ-4YB1E226M
PCC2333DKR-ND
CAP CERAMIC
22 µF 25 V X5R
1210
5
1
C2
10 µF
603
Panasonic-ECG
ECJ-1VB1A106M
PCC2479DKR-ND
CAP CERAMIC
10 µF 10 V 0603
X5R
6
1
C22
4.7 µF
603
Panasonic-ECG
ECJ-1VB0J475M
PCC2318DKR-ND
CAP CERAMIC
4.7 µF 6.3 V X5R
0603
7
1
C2
2.2 nF
603
TDK Corporation
C1608X7R1H222M
445-5083-6-ND
CAP CERAMIC
2200 pF 50 V X 7R
0603
8
3
J8, J9, J11
ED555/
2DS
TB_2X3.5MM
On Shore
Technology
ED555/2DS
ED1514-ND
TERMINAL BLOCK
3.5 mm 2POS PCB
9
2
JP6, JP15
JMP0.2
Mil-Max
800-10-064-10-00100
0
ED7264-ND
SIP HEADER 64
POS STRAIGHT
PCB
10
2
JP20, JP24
JMP0.3
Mil-Max
800-10-064-10-00100
0
ED7264-ND
SIP HEADER 64
POS STRAIGHT
PCB
11
2
L9, L11
2.2 µH
10X10MM
Wurth Electronics
7440650022
732-1055-2-ND
INDUCTOR POWER
2.2 µH 6.2 A SMD
12
1
R1
383 kΩ
603
Panasonic-ECG
ERJ-3EKF3833V
P383KHDKR-ND
RES 383 kΩ 1/10 W
1% 0603 SMD
13
1
R18
10 kΩ
603
Panasonic-ECG
ERJ-3EKF1002V
P10.0KHCT-ND
RES 10 kΩ 1/10 W
1% 0603 SMD
14
1
R24
100 kΩ
603
Panasonic-ECG
ERJ-3EKF1003V
P100KHCT-ND
RES 100 kΩ 1/10 W
1% 0603 SMD
15
2
R9, R11
0
603
Vishay/Dale
CRCW06030000
Z0EA
541-0.0GDKR-ND
RES 0 Ω 1/10 W 5%
0603 SMD
16
2
R9a, R11a
40.2 kΩ
603
Panasonic-ECG
ERJ-3EKF4022V
P40.2KHDKR-ND
RES 40.2 kΩ
1/10 W 1% 0603
SMD
17
1
R9b
80.6 kΩ
603
Panasonic-ECG
ERJ-3EKF8062V
P80.6KHDKR-ND
RES 80.6 kΩ
1/10 W 1% 0603
SMD
18
1
R11b
32.4 kΩ
603
Yageo
RC0603FR- 0732K4L
311-32.4KHRDKRND
RES 32.4 kΩ
1/10 W 1% 0603
SMD
19
2
DNI
C10, C12
3.3 nF
603
Reserved for
snubber
20
2
DNI
R3, R4
4.99
603
Reserved for
snubber
21
10
TP8, TP9,
TP9a, TP9b,
TP11, TP11a,
TP11b, TP20,
TP23, TP24
TEST POINT
0.042
Keystone
Electronics
5002
5002K-ND
TEST POINT PC
MINI .040" D WHITE
22
5
TP1, TP2, TP3,
TP4, TP5
TEST POINT
0.042
Keystone
Electronics
5001
5001K-ND
TEST POINT PC
MINI .040" D BLACK
23
1
U1
QFN28 [RHD]
5
C4, C6, C15,
C17, C18
PCC1780TR-ND
CAP 4700 pF 50 V
CERAMIC X7R 0603
24
4.7 nF
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603
TPS65253
Panasonic-ECG
ECJ-1VB1H472K
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11
Revision History
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Table 7-1. Bill of Materials (continued)
ITEM
QUANTITY
DESIGNATOR
VALUE
FOOTPRINT
MANUFACTURER
MANUFACTURER
PART NO.
VENDER PART
NO.
DESCRIPTION
25
1
DNI
C1
22 µF
1210
AVX Corp
12103D226KAT2A
478-5999-6-ND
CAP CER 22000 pF
25 V CERM X7R
0603
26
2
C9A, C11A
22 µF
603
Panasonic-ECG
ECJ-1VB1E223K
PCC1767DKR-ND
CAP 4700 pF 50 V
CERAMIC X7R 0603
27
1
R2
5 kΩ
603
Vishay/Dale
PNM0603E5001BST5
PNM0603-5.0KBDK
R-ND
RES 5.0 kΩ
15W 0.1% 0603
SMD
28
2
R5, R16
49.9 kΩ
603
Panasonic-ECG
ERJ-3EKF4992V
P49.9KHDKR-ND
RES 49.9 kΩ
1/10W 1% 0603
SMD
8 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2015) to Revision B (May 2021)
Page
• Updated user's guide title................................................................................................................................... 2
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................2
Changes from Revision * (June 2011) to Revision A (November 2015)
Page
• Updated schematic image.................................................................................................................................. 4
12
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