TPS65265RHBR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS65265 SLVSD86A – DECEMBER 2015 – REVISED DECEMBER 2015 TPS65265 4.5-V to 17-V Input Voltage, 5-A/3-A/2-A Output Current Triple Synchronous Step-Down Converter 1 Features 3 Description • • • • The TPS65265 incorporates triple synchronous buck converters with 4.5-V to 17-V wide input voltage range that encompassed most intermediate bus voltage operating off 5-, 9-, 12- or 15-V power bus or battery. The converter with constant frequency peak current mode is designed to simplify its application while giving designers options to optimize the system according to targeted applications. The switching frequency of the converters can be adjustable from 250 kHz to 2.3 MHz with an external resistor or external clock. 120° out-of-phase operation between Buck1, Buck2, and Buck3 minimizes the input filter requirements. 1 • • • • • • • • • Operating Input Voltage Range 4.5 V to 17 V Feedback Reference Voltage 0.6 V ±1.33% Continuous Output Current 5 A/3 A/2 A Adjustable Clock Frequency from 250 kHz to 2.3 MHz External Synchronization Oscillator 120° Out of Phase for Buck1, Buck2, Buck3 Dedicated Enable Pins for Each Buck Fixed SS Time for Each Buck (2.4 ms) Automatic Power-Up/Power-Down Sequence and Adjustable Interval Time Between Bucks (6 Combinations) Support Pulse Skipping Mode (PSM) and Forced Continuous Current Mode (FCCM) Output Voltage Power Good Indicator and Adjustable Delay Time Thermal Overloading Protection 32-Pin QFN (RHB) 5-mm × 5-mm Package The TPS65265 operates in pulse skipping mode (PSM) with driving MODE pin to high or leaving float and operates in force continuous current mode (FCC) with connecting MODE pin to GND. PSM mode provides high efficiency by reducing switching losses at light load and FCC mode reduces noise susceptibility and RF interference. The TPS65265 is available in a 32-pin thermal enhanced QFN (RHB) 5-mm × 5-mm thin package. 2 Applications • • • • Device Information(1) DTV Set-Top Boxes/OTT Home Gateway and Access Point Networks Surveillance PART NUMBER TPS65265 PACKAGE BODY SIZE (NOM) VQFN (32) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. SPACE Efficiency vs Output Load 100% Simplified Application Circuit 90% Vin VOUT1 PVINx 80% LX1 TPS65265 MODE PSM PG_DLY SEQ_DLY ENx PGOOD ROSC AGND PGND LX2 VOUT2 FB3 60% 50% 40% 30% FB2 LX3 Efficiency 70% FB1 VOUT3 20% 10% 0 0.01 PSM Mode, VOUT = 1.2 V PWM Mode, VOUT = 1.2 V 0.1 Output Current (A) 1 5 D100 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65265 SLVSD86A – DECEMBER 2015 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Related Parts .......................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 5 7.1 7.2 7.3 7.4 7.5 7.6 5 5 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 13 8.4 Device Functional Modes........................................ 24 9 Application and Implementation ........................ 26 9.1 Application Information............................................ 26 9.2 Typical Application ................................................. 26 10 Power Supply Recommendations ..................... 37 11 Layout................................................................... 37 11.1 Layout Guidelines ................................................. 37 11.2 Layout Example .................................................... 38 12 Device and Documentation Support ................. 39 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 39 39 39 39 13 Mechanical, Packaging, and Orderable Information ........................................................... 39 4 Revision History Changes from Original (December 2015) to Revision A • 2 Page Changed device status to production data and released full data sheet .............................................................................. 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65265 TPS65265 www.ti.com SLVSD86A – DECEMBER 2015 – REVISED DECEMBER 2015 5 Related Parts PART NUMBER DESCRIPTION COMMENTS TPS65261/-1 4.5 V to 18 V, triple bucks with input Triple bucks 3-A/2-A/2-A output current, features an open drain RESET signal to voltage power failure indicator monitor input power failure, automatic power sequencing TPS65262/-1 4.5 V to 18 V, triple bucks with dual adjustable LDOs Triple bucks 3-A/1-A/1-A output current, automatic power sequencing, dual LDOs 100 mA/200 mA for TPS65262, 350 mA/150 mA for TPS65262-1 TPS65263 4.5 V to 18 V, triple bucks with I2C interface Triple bucks 3-A/2-A/2-A output current, I2C controlled dynamic voltage scaling (DVS) TPS65266 2.7 V to 6.5 V, triple bucks Triple bucks 3-A/2-A/2-A 6 Pin Configuration and Functions PG_DLY COMP1 FB1 AGND ROSC FB3 COMP3 SEQ_DLY RHB Package 32-Lead Plastic QFN Top View 24 23 22 21 20 19 18 17 BST1 25 16 BST3 PGND1 26 15 PGND3 PGND1 27 14 LX3 LX1 28 13 PVIN3 Thermal Pad PVIN1 31 10 PGND2 PSM 32 9 1 2 3 4 5 6 7 8 MODE LX2 COMP2 11 FB2 30 EN3 PVIN1 EN2 PVIN2 EN1 12 PGOOD 29 V7V LX1 BST2 NOTE:: There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65265 3 TPS65265 SLVSD86A – DECEMBER 2015 – REVISED DECEMBER 2015 www.ti.com Pin Functions PIN NO. DESCRIPTION NAME 1 V7V Internal LDO for gate driver and internal controller. Connect a 1 µF capacitor from the pin to power ground 2 PGOOD An open drain output, asserts low if output voltage of any buck beyond regulation range due to thermal shutdown, over-current, under-voltage or ENx shut down. 3 EN1 Enable for buck1. Float to enable. Can use this pin to adjust the input undervoltage lockout (UVLO) of buck1 with a resistor divider. 4 EN2 Enable for buck2. Float to enable. Can use this pin to adjust the input UVLO of buck2 with a resistor divider. 5 EN3 Enable for buck3. Float to enable. Can use this pin to adjust the input UVLO of buck3 with a resistor divider. 6 FB2 Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider. 7 COMP2 Error amplifier output and Loop compensation pin for buck2. Connect a series resistor and capacitor to compensate the control loop of buck2 with peak current PWM mode. 8 MODE When floating, Buck1/2/3 are controlled separate by EN1/2/3. When tied to HIGH or tied to GND, an automatic power-up/power-down sequence is provided according to states of EN1, EN2 and EN3 pins. 9 BST2 Boot strapped supply to the high side floating gate driver in buck2. Connect a capacitor (recommend 47nF) from BST2 pin to LX2 pin. 10 PGND2 Power ground connection of buck2. Connect PGND2 pin as close as practical to the (-) terminal of PVIN2 input ceramic capacitor. 11 LX2 Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is from a diode voltage below the ground up to PVIN2 voltage. 12 PVIN2 Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10 µF). 13 PVIN3 Input power supply for buck3. Connect PVIN3 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10 µF). 14 LX3 Switching node connection to the inductor and bootstrap capacitor for buck3. The voltage swing at this pin is from a diode voltage below the ground up to PVIN3 voltage. 15 PGND3 Power ground connection of buck3. Connect PGND3 pin as close as practical to the (-) terminal of PVIN3 input ceramic capacitor. 16 BST3 Boot strapped supply to the high side floating gate driver in buck3. Connect a capacitor (recommend 47nF) from BST3 pin to LX3 pin. 17 SEQ_DLY Delay time programmable between bucks at automatic power sequencing mode. Connect an external capacitor to set the interval delay time. 18 COMP3 Error amplifier output and Loop compensation pin for buck3. Connect a series resistor and capacitor to compensate the control loop of buck3 with peak current PWM mode. 19 FB3 Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 resistor divider. 20 ROSC Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency. 21 AGND Analog ground common to buck controllers and other analog circuits. 22 FB1 Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 resistor divider. 23 COMP1 Error amplifier output and Loop compensation pin for buck1. Connect a series resistor and capacitor to compensate the control loop of buck1 with peak current PWM mode. 24 PG_DLY PGOOD delay programmable pin. Connect an external capacitor to set the delay time. 25 BST1 Boot strapped supply to the high side floating gate driver in buck1. Connect a capacitor (recommend 47nF) from BST1 pin to LX1 pin. 26, 27 PGND1 Power ground connection of Buck1. Connect PGND1 pin as close as practical to the (-) terminal of PVIN1 input ceramic capacitor. 28, 29 LX1 Switching node connection to the inductor and bootstrap capacitor for buck1. The voltage swing at this pin is from a diode voltage below the ground up to PVIN1 voltage. 30, 31 PVIN1 Input power supply for buck1. Connect PVIN1 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 22 µF). 32 PSM Ties to HIGH or leaves floating, PSM mode; Ties to GND, FCCM mode. PAD 4 There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65265 TPS65265 www.ti.com SLVSD86A – DECEMBER 2015 – REVISED DECEMBER 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT PVIN1, PVIN2, PVIN3, PGOOD –0.3 20 V LX1, LX2, LX3 –1.0 19 V LX1, LX2, LX3 (maximum withstand voltage transient