TPS65276VDAPR

TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 4.5-V TO 18-V INPUT VOLTAGE, 6-A/3.5-A DUAL SYNCHRONOUS STEP-DOWN CONVERTER WITH I2C CONTROLLED VID Check for Samples: TPS65276V FEATURES 1 • • • • • • • • • 4.5-V to 18-V Wide Input Voltage Range I2C Controlled 7-Bits VID Programmable Output Voltage from 0.68 V to 1.95 V with 10-mV Steps for Each Buck; Output Voltage Can Also be Set By Resistor Divider Programmable Slew Rate Control for Output Voltage Transition Up to 6-A Maximum Continuous Output Current in Buck 1 and 3.5-A in Buck 2 I2C Compatible Interface With Standard Mode (100 kHz) and Fast Mode (400 kHz) I2C Read Back Power Good Status and Die Temperature Warning Pulse Skipping Mode to Achieve High Efficiency in Light Load Adjustable Switching Frequency 200 kHz - 1.6 MHz Set by External Resistor Dedicated Enable and Soft-Start for Each Buck • • • • • Peak Current-Mode Control with Simple Compensation Circuit Cycle-by-Cycle Over Current Protection 180° Out-of-Phase Operation to Reduce Input Capacitance and Power Supply Induced Noise Over Temperature Protection Available in 32-Pin Thermally Enhanced HTSSOP (DAP) and 36-Pin QFN 6-mm x 6-mm (RHH) Packages APPLICATIONS • • • • • DTV TCON BDVD Set Top Boxes Tablet PC DESCRIPTION/ORDERING INFORMATION TPS65276V is a monolithic dual synchronous buck converter with wide 4.5V to 18V operating input voltage range that encompassed most intermediate bus voltage operating off 5-, 9-, 12- or 15-V power bus or battery. The converter with constant frequency peak current mode control is designed to simplify its application while giving the designers options to optimize their usage according to the target applications. Each buck converter in TPS65276V has external feedback resistors that can be used for setting the initial start up voltage. The feedback voltage reference for this start-up option is 0.6 V. Once the VID DAC is updated via the I2C, the buck converter switches feedback resistors from external to internal. The output voltage in each buck can be programmable from 0.68 V to 1.95 V in 10-mV steps with I2C Controlled 7-Bits VID. Each buck converter in TPS65276V can also be I2C controlled for enabling/disabling output voltage, setting the pulse skipping mode and reading the power good status and die temperature warning. The switching frequency of the converters can be set from 200 kHz to 1.6 MHz with an external resistor. Two converters have clock signal with 180° out-of-phase. TPS65276V features dedicated enable pin when I2C interface is not used. Independent soft-start pin provides flexibility in power up programmability. Constant frequency peak current mode control simplifies the compensation and provides fast transient response. Cycle-by-cycle over current protection and hiccup mode operation limit MOSFET power dissipation in short circuit or over loading fault conditions. Low side reverse over current protection also prevents excessive sinking current from damaging the converter. TPS65273V also features a light load pulse skipping mode (PSM) that can be controlled by I2C or MODE pin configuration. The PSM mode allows a power loss reduction on the input power supplied to the system to achieve high efficiency at light loading. The TPS65273V is available in a 32-pin thermally enhanced HTSSOP (DAP) package and 36-pin QFN 6-mm x 6-mm (RHH) package. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013–2014, Texas Instruments Incorporated TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) 2 PACKAGE (2) ORDERABLE PART NUMBER 32-pin HTSSOP (DAP) TPS65276VDAPR 36-pin QFN (RHH) TPS65276VRHHR TOP-SIDE MARKING TPS65276V For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TYPICAL APPLICATION R1 100K 1 FB2 EN2 VOUT2 2 R2 100K PGND2 LX2 PVIN2 LX2 5 PVIN2 SS2 ADDR COMP2 8 Power Pad R24 C26 23 R23 22 SS1 PVIN1 12 PVIN1 LX1 PGND1 LX1 PGND1 BST1 13 C23 C22 21 L1 4.7uH VOUT1=0.68V~1.95V Res. = 10mV Max. Io1=6A 20 14 C19 47nF 19 33 15 C20 5x22uF 18 SDA VOUT1 SCL FB1 16 SCL R26 24 ROSC 11 SDA VOUT2=0.68V~1.95V Res. = 10mV Max. Io1=3.5A COMP1 VIN R15 10K 25 AGND MODE 9 V7V R16 10K C27 26 10 DVCC L2 4.7uH 28 27 7 C14 10uF C29 5x22uF C30 47nF 29 6 VIN 4.5V~18V R31 30 BST2 PGND2 4 C9 1uF C31 31 3 C3 10uF R32 32 EN1 C18 17 R18 R17 Power Ground Analog Ground Figure 1. Dual Mode Operation to Deliver 6 A at Buck 1 and 3.5 A at Buck 2 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 3 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com FUNCTIONAL BLOCK DIAGRAM VIN 10 V7V 9 ADDR 7 SDA 15 EN1 EN2 V7V LDO Bias, BG, LDOs 24 ROSC 5,6 PVIN2 30 BST2 OSC/Phase Shift DVCC CLK2 I 2C Bus SCL CLK1 2 iENx 7 I 2C 7 En_buck2 16 clk V7V ENABLE VIN V7V BST BUCK2 PGND FB Vfb1 SS LX2 3,4 PGND2 27 SS2 32 FB2 31 VOUT2 26 COMP2 0.68V-1.95V Max. Io2=3.5A Vfb2 PGOOD OT warning COMP Power Good 28,29 LX MODE VIN Vfb2 MUX Over Temp MODE 8 EN1 1 En_buck1 iEN1 7-BIT 2 I C Reg. 2 I C Reg. clk V7V ENABLE VIN 12,13 En_buck1 19 BST BUCK1 LX MODE EN2 2 PGND COMP iEN2 En_buck2 FB BST1 20,21 LX1 13,14 PGND1 22 SS1 17 FB1 18 VOUT1 23 COMP1 VIN, 4.5V~18V 0.68V-1.95V Max. Io1=6A Vfb1 SS PVIN1 AGND 25 ENS=BGOK & OTOK & LDOOK MUX I2 C Reg. 4 Submit Documentation Feedback 7-BIT I2 C Reg. Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 PIN OUT DAP PACKAGE (TOP VIEW) 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 EN1 FB2 EN2 VOUT2 PGND2 BST2 PGND2 LX2 PVIN2 LX2 PVIN2 SS2 ADDR COMP2 AGND MODE Power Pad 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 V7V ROSC VIN COMP1 PVIN1 SS1 PVIN1 LX1 PGND1 LX1 PGND1 BST1 VOUT1 SDA SCL FB1 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 5 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com PGND2 PGND2 PGND2 EN2 EN1 FB2 VOUT2 BST2 LX2 RHH PACKAGE (TOP VIEW) 36 35 34 33 32 31 30 29 28 PVIN2 1 27 LX2 PVIN2 2 26 LX2 ADDR 3 25 SS2 MODE 4 24 COMP2 V7V 5 Thermal Pad 23 AGND 22 ROSC VIN 6 6 10 11 12 13 14 15 16 17 18 VOUT1 BST1 LX1 LX1 19 LX1 FB1 PGND1 9 SCL 20 SS1 SDA PVIN1 8 PGND1 21 COMP1 PGND1 PVIN1 7 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 TERMINAL FUNCTIONS NAME NO. (HTSSOP) NO. (QFN) DESCRIPTION EN1, EN2 1, 2 32, 33 PGND2 3, 4 34, 35, 36 PVIN2 5, 6 1, 2 ADDR 7 3 I2C address configuration pin. Connect this pin to low, high or leave it open to select different I2C slave address. MODE 8 4 Operation mode control pin. Connect this pin to ground to choose forced PWM mode without current sharing; leave the pin open for pulse skipping mode (PSM) operation at light load condition; connect this pin to V7V to choose forced PWM mode and current sharing with paralleling two bucks. V7V 9 5 Internal low-drop linear regulator (LDO) output to power internal driver and control circuits. Decouple this pin to power ground with a minimum 1-µF ceramic capacitor. Output regulates to typical 6.3 V for optimal conduction on-resistances of internal power MOSFETs. In PCB design, the power ground and analog ground should have one-point common connection at the (-) terminal of V7V bypass capacitor. If VIN is lower than 6.3 V, V7V will be slightly lower than VIN. Power supply of the internal LDO and controllers VIN Enable pin. Adjust the input under-voltage lockout with two resistors. Power ground of Buck 2, place the input capacitor’s ground pin as close as possible to this pin. Power input. Input power supply to the power switches of the power converter 2. 10 6 PVIN1 11, 12 7, 8 PGND1 13, 14 9, 10, 11 SDA 15 12 I2C interface data pin SCL 16 13 I2C interface clock pin FB1 17 14 Feedback sensing pin for the external feedback resistors in Buck 1. Before I2C controlled VID selection is enabled, an external resistor divider connects to this pin to pre-set the output voltage. VOUT1 18 15 Buck 1 output voltage sensing pin; When I2C controlled VID selection is enabled, output voltage can be programmed from 0.68 V to 1.95 V with 10-mV steps. In current sharing application, this pin is the output voltage sensing pin. BST1 19 16 Add a bootstrap capacitor between BST1 and LX1. The voltage on this capacitor carries the gate drive voltage for the high-side MOSFET. LX1 20, 21 17, 18, 19 SS1 22, 27 20, 25 Soft-start and voltage tracking in Buck 1. An external capacitor connected to this pin sets the internal voltage reference rise time. Since the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. In current sharing application, this pin serves as the soft-start pin. COMP1 23 21 Error amplifier output and loop compensation pin for Buck 1. Connect frequency compensation to this pin; In current sharing application, this pin serves as the compensation pin. ROSC 24 22 Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency. When connected to an external clock, the internal oscillator synchronizes to the external clock. AGND 25 23 Analog ground of the controllers COMP2 26 24 Error amplifier output and loop compensation pin for Buck 2. Connect frequency compensation to this pin. In current sharing application, connect this pin to ground. SS2 27 25 Soft-start and voltage tracking in Buck 2. An external capacitor connected to this pin sets the internal voltage reference rise time. Since the voltage on this pin overrides the internal reference, it can be used for tracking and power sequencing. In current sharing application, connect this pin to ground. LX2 28, 29 26, 27, 28 Power input. Input power supply to the power switches of the power converter 1. Power ground of Buck 1, place the input capacitor’s ground pin as close as possible to this pin. Switching node of Buck 1 Switching nodes Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 7 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com TERMINAL FUNCTIONS (continued) NO. (HTSSOP) NO. (QFN) BST2 30 29 Add a bootstrap capacitor between BST2 and LX2. The voltage on this capacitor carries the gate drive voltage for the high-side MOSFET of Buck 2. VOUT2 31 30 Buck 2 output voltage sensing pin; When I2C controlled VID selection is enabled, output voltage can be programmed from 0.68 V to 1.95 V with 10-mV steps. In current sharing application, connect this pin to the ground. FB2 32 31 Feedback sensing pin for the external feedback resistors in Buck 2. Before I2C controlled VID selection is enabled, an external resistor divider connects to this pin to pre-set the output voltage. Exposed Thermal Pad 33 37 Exposed thermal pad of the package. Connect to the power ground. Always solder thermal pad to the board, and have as many vias as possible on the PCB to enhance power dissipation. There is no electric signal down bonded to the thermal pad inside the IC package. NAME ABSOLUTE MAXIMUM RATINGS DESCRIPTION (1) over operating free-air temperature range (unless otherwise noted) Voltage range at VIN, PVIN1,PVIN2 –0.3 to 20 V Voltage range at LX1, LX2 (maximum withstand voltage transient < 20 ns) –4.5 to 20 V Voltage at BST1, BST2, referenced to LX1, LX2 pin –0.3 to 7 V Voltage at V7V, EN1, EN2, VOUT1, VOUT2, MODE –0.3 to 7 V Voltage at SS1, SS2, FB1, FB2, COMP1, COMP2 –0.3 to 3 V Voltage at SDA, SCL, ADDR, EN1, EN2, ROSC –0.3 to 7 Voltage at AGND, PGND1, PGND2 –0.3 to 0.3 V TJ Operating virtual junction temperature range –40 to 150 °C TSTG Storage temperature range –55 to 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. THERMAL INFORMATION TPS65276V THERMAL METRIC θJA Junction-to-ambient thermal resistance (1) θJCtop Junction-to-case (top) thermal resistance (2) θJB Junction-to-board thermal resistance (3) (4) DAP RHH 32 PINS 36 PINS 35 30.8 17.7 18.8 19 6 0.5 0.2 ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (5) 18.9 6 θJCbot Junction-to-case (bottom) thermal resistance (6) 1.3 0.7 (1) (2) (3) (4) (5) (6) 8 UNITS °C/W The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input operating voltage 4.5 18 V TA Ambient temperature –40 85 °C ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN Human body model (HBM) Charge device model (CDM) MAX UNIT 1000 V 250 V ELECTRICAL CHARACTERISTICS TJ = 25°C, VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input Voltage range VIN1 and VIN2 IDDSDN Shutdown supply current EN1 = EN2 = low 4.5 10 µA IDDQ_NSW Switching quiescent current with no load at DCDC output EN1 = EN2 = 3.3 V Without bucks switching 1.2 mA IDDQ_SW Switching quiescent current with no load at DCDC output, Buck switching EN1 = EN2 = 3.3 V With bucks switching 10 mA Rising VIN UVLO VIN under voltage lockout Falling VIN 4.25 3.5 Hysteresis V7V load current = 0 A, VIN = 12 V 18 V 4.50 3.75 V 0.5 V7V 6.3 V LDO 6.10 6.3 6.5 V IOCP_V7V Current limit of V7V LDO 200 VENR Enable threshold 1.21 VENF Enable threshold 1.17 V IENR Enable Input current EN = 1 V 3 µA IENF Enable hysteresis current EN = 1.5 V 3 µA mA ENABLE 1.10 1.26 V OSCILLATOR FSW Switching frequency TSYNC_w Clock sync minimum pulse width VSYNC_HI Clock sync high threshold VSYNC_LO Clock sync low threshold VSYNC_D Clock falling edge to LX rising edge delay FSYNC Clock sync frequency range 200 ROSC = 100 kΩ (1%) 340 1600 400 460 20 ns 2 0.8 ns 1600 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V V V 66 200 kHz kHz 9 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.594 0.6 0.606 V 8 10 12 BUCK 1, BUCK 2 CONVERTERS 0 A < IOUT1 < 6 A, 0 A < IOUT2 < 3.5 A Vref(min) Voltage reference VOUT1,2 Output voltage step size (VID 0x00 – 0x7F) VLINEREG3 Line regulation-DC IOUT = 2 A 0.5 %/V VLOADREG3 Load regulation-DC IOUT = (10-90%) x IOUT_max 0.5 %/A Gm_EA3 Error amplifier trans-conductance -2 µA < ICOMP < 2 µA 1350 µs Gm_SRC3 COMP voltage to inductor current Gm ILX = 0.5 A 10 A/V ISSx Soft-start pin charging current SS1, SS2 6 µA ILIMIT1 Buck 1 peak inductor current limit 8 A ILIMIT2 Buck 2 peak inductor current limit 5 A ILIMITLSx Low side sinking current limit Rdsonx_HS On resistance of high side FET V7V = 6.3 V 31 mΩ Rdsonx_LS On resistance of low side FET VIN = 12 V 23 mΩ Tminon Minimum on time 94 VbootUV Boot-LX UVLO 2.1 Thiccupwait Hiccup wait time Thiccup_re Hiccup time before re-start -2.6 mV A ns 3 V 512 cycles 16384 cycles I2C READ BACK FAULT STATUS VPGOOD Twarn PGOOD trip levels Feedback lower voltage rising (with respect to 0.6 V ) 94 Feedback lower voltage falling (with respect to 0.6 V) 92.5 Feedback upper voltage rising (with respect to 0.6 V) 107.5 Feedback upper voltage falling (with respect to 0.6 V) 105.5 % Temperature warning threshold 125 °C 160 °C THERMAL SHUTDOWN TTRIP Thermal protection trip point THYST Thermal protection hysteresis Rising temperature 20 °C I2C INTERFACE 0x60H if ADDR = 0; 0x61H if ADDR = high; 0x62H if ADDR = open Address VIH SDA, SCL Input high voltage VIL SDA, SCL Input low voltage II Input current SDA, SCL, VI = 0.4 V to 4.5 V VOL SDA SDA output low voltage SDA open drain, IOL = 4 mA f(SCL) Maximum SCL clock frequency 400 kHz tBUF Bus free time between a STOP and START condition 1.3 µs tHD_STA Hold time (Repeated) START condition 0.6 µs tSU_STO Setup time for STOP condition 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU_STA Setup time for a repeated START condition 0.6 µs 10 1.3 0.4 Submit Documentation Feedback -10 V V 10 0.4 µA V Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V (unless otherwise noted) PARAMETER tSU_DAT Data setup time tHD_DAT Data hold time TEST CONDITIONS MIN TYP MAX 0.1 UNIT µs 0 0.9 µs 300 ns tRCL Rise time of SCL signal Capacitance of one bus line (pF) 20 + 0.1CB tRCL1 Rise time of SCL signal after a repeated START condition and after an acknowledge BIT Capacitance of one bus line (pF) 20 + 0.1CB 300 ns tFCL Fall time of SCL sgnal Capacitance of one bus line (pF) 20 + 0.1CB 300 ns tRDA Rise time of SDA signal Capacitance of one bus line (pF) 20 + 0.1CB 300 ns tFDA Fall time of SDA signal Capacitance of one bus line( pF) 20 + 0.1CB 300 ns CB Capacitance of one bus line (SCL and SDA) 400 pF Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 11 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS 90 90 80 80 70 70 60 60 Efficiency (%) Efficiency (%) TA = 25°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted) 50 40 30 20 50 40 30 20 Forced PWM 10 0 0 1 2 3 4 5 Loading (A) Forced PWM 10 auto PWM-PSM auto PWM-PSM 0 6 0 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) 0.3 0.4 0.5 C003 Figure 3. 0.8-V Efficiency, Light Load VIN = 12 V, VOUT = 0.8 V 60 50 40 30 60 50 40 30 20 20 Forced PWM 10 0 1 2 3 4 5 Loading (A) Forced PWM 10 auto PWM-PSM 0 auto PWM-PSM 0 6 0 0.1 0.2 0.3 0.4 0.5 Loading (A) C004 Figure 4. 1.8-V Efficiency VIN = 12 V, VOUT = 1.8 V C005 Figure 5. 1.8-V Efficiency, Light Load VIN = 12 V, VOUT = 1.8 V 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) 0.2 Loading (A) C002 Figure 2. 0.8-V Efficiency VIN = 12 V, VOUT = 0.8 V 60 50 40 30 60 50 40 30 20 20 Forced PWM 10 0 1 2 3 4 Loading (A) 5 Forced PWM 10 auto PWM-PSM 0 auto PWM-PSM 0 6 0 C006 Figure 6. 3.3-V Efficiency VIN = 12 V, VOUT = 3.3 V 12 0.1 0.1 0.2 0.3 0.4 Loading (A) 0.5 C007 Figure 7. 3.3-V Efficiency, Light Load VIN = 12 V, VOUT = 3.3 V Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) TA = 25°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted) 60 50 40 30 60 50 40 30 20 20 Forced PWM 10 0 0 1 2 3 4 5 Loading (A) Forced PWM 10 auto PWM-PSM auto PWM-PSM 0 6 0 0.2 0.3 0.4 0.5 Loading (A) C008 Figure 8. 5-V Efficiency VIN = 12 V, VOUT = 5 V C009 Figure 9. 5-V Efficiency, Light Load VIN = 12 V, VOUT = 5 V 0.81 1.81 1.80 VOUT (V) 0.80 VOUT (V) 0.1 0.79 0.78 1.79 1.78 1.77 Forced PWM Forced PWM auto PWM-PSM auto PWM-PSM 0.77 1.76 0 1 2 3 4 5 Loading (A) 6 0 1 2 3 4 5 Loading (A) C010 Figure 10. 0.8-V Load Regulation VIN = 12 V, VOUT = 0.8 V 6 C011 Figure 11. 1.8-V Load Regulation VIN = 12 V, VOUT = 1.8 V 4.95 3.25 3.24 4.90 VOUT (V) VOUT (V) 3.23 3.22 4.85 3.21 4.80 3.20 Forced PWM Forced PWM auto PWM-PSM auto PWM-PSM 3.19 4.75 0 1 2 3 4 5 Loading (A) 6 0 C012 Figure 12. 3.3-V Load Regulation VIN = 12 V, VOUT = 3.3 V 1 2 3 4 5 Loading (A) Product Folder Links: TPS65276V C013 Figure 13. 5-V Load Regulation VIN = 12 V, VOUT = 5 V Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated 6 13 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) 0.82 1.82 0.81 1.81 0.8 1.8 VOUT (V) VOUT (V) TA = 25°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted) 0.79 0.78 0.77 1.79 1.78 1.77 forced PWM 0 A forced PWM 4.5 A auto PSM-PWM 0 A 0.76 0.75 6 7 8 9 10 11 12 13 14 15 16 17 VIN (V) forced PWM 0 A forced PWM 4.5 A auto PSM-PWM 0 A 1.76 1.75 18 6 7 9 10 11 12 13 14 15 16 17 VIN (V) Figure 14. 0.8-V Line Regulation VOUT = 0.8 V 18 C015 Figure 15. 1.8-V Line Regulation VOUT = 1.8 V 3.29 4.93 3.27 4.91 4.89 VOUT (V) 3.25 VOUT (V) 8 C014 3.23 3.21 4.87 4.85 4.83 3.19 3.15 6 7 8 9 10 11 12 13 14 15 16 VIN (V) 14 4.81 forced PWM 0 A forced PWM 4.5 A auto PSM-PWM 0 A 3.17 17 forced PWM 0 A forced PWM 4.5 A auto PSM-PWM 0 A 4.79 4.77 18 6 7 8 9 10 11 12 13 14 15 16 17 VIN (V) C016 Figure 16. 3.3-V Line Regulation VOUT = 3.3 V Figure 17. 5-V Line Regulation VOUT = 5 V Figure 18. Output Ripple at 0 A, Forced PWM Figure 19. Output Ripple at 3.5 A, Forced PWM Submit Documentation Feedback 18 C017 Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted) Figure 20. Output Ripple, Buck1 at 0.05 A, Buck 2 at 0.2 A Auto PSM-PWM Mode Figure 21. Startup With Enable Figure 22. Shutdown With Enable Figure 23. Load Transient, Buck 1 2.5 A - 4.5 A, Buck2 0.5 A - 2.5 A Figure 24. Load Transient, Buck 1 (0.5 A - 2.5 A) Figure 25. Load Transient, Buck 2 (0.5 A - 2.5 A) Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 15 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted) 16 Figure 26. Over Current Protection Buck 1 Figure 27. Hiccup Recover, Buck 1 Figure 28. Over Current Protection, Buck 2 Figure 29. Hiccup Recover, Buck 2 Figure 30. Voltage Change With I2C Control Buck 1, 0.68 V - 1.95 V, SR = 10 mV/16 Tsw, Buck 2, 1.95 V - 0.68 V, SR = 10 mV/128 Tsw Figure 31. Synchronization at 500 kHz Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 OVERVIEW TPS65276V is a dual 6.3-A/3.5-A output current, synchronous step-down (buck) converter with integrated n-channel MOSFETs. A wide 4.5-V to 18-V input supply range to buck encompasses most intermediate bus voltages operating off 9-V, 12-V or 15-V power bus. TPS65276V is equipped with I2C compatible bus for sophisticated control and communication with SoC. With I2C interface, SoC can enable or disable the power converters, set output voltage and read status registers. The buck regulator has external feedback resistors that can be used for setting the initial start up voltage. The feedback voltage reference for this start-up option is 0.6V. Once the voltage identification VID DAC is updated via the I2C, output voltage of each channel can be independently programmed with 7 bits VID from 0.68 V to 1.95 V in 10-mV steps. Output voltage transitions begin once the I2C interface receives the command for GO bit in command registers. In light loading condition, low pulse skipping mode can be I2C controlled or selected with MODE pin configuration. TPS65276V implements a constant frequency, peak current mode control which simplifies external frequency compensation. The wide switching frequency of 200 kHz to 1600 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency can be adjusted with an external resistor to ground on the ROSC pin. The TPS65276V also has an internal phase lock loop (PLL) controlled by the ROSC pin that can be used to synchronize the switching cycle to the falling edge of an external system clock. 180° outof-phase operation between two channels reduces input filter and power supply induced noise. TPS65276V has been designed for safe monotonic startup into pre-biased loads. The default start up is when VIN is typically 4.5 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for automatically starting up the TPS65276V with the internal pull up current. The integrated MOSFETs of each channel allow for high efficiency power supply designs with continuous output currents up to 6 A and 3.5 A respectively. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications. The TPS65276V reduces the external component count by integrating the boot recharge circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and LX pins. The boot capacitor voltage is monitored by a BOOT to LX UVLO (BOOT-LX UVLO) circuit allowing LX pin to be pulled low to recharge the boot capacitor. The TPS65276V can operate at 100% duty cycle as long as the boot capacitor voltage is higher than the preset BOOT-LX UVLO threshold which is typically 2.1 V. The TPS65276V has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through internal feedback voltage. I2C can read the power good status with commanding register. The SS (soft start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor or resistor divider should be coupled to the pin for soft start or critical power supply sequencing requirements. The TPS65276V is protected from output overvoltage, overload and thermal fault conditions. The TPS65276V minimizes excessive output overvoltage transients by taking advantage of the power good comparator. When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning on until the internal feedback voltage is lower than 108% of the 0.6-V reference voltage. The TPS65276V implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections which help control the inductor current and avoid current runaway. If the over current condition has lasted for more than the hiccup wait time, the TPS65276V will shut down and re-start after the hiccup time. The TPS65276V also shuts down if the junction temperature is higher than thermal shutdown trip point. When the junction temperature drops 20°C typically below the thermal shutdown trip point, the built-in thermal shutdown hiccup timer is triggered. The TPS65276V will be restarted under control of the soft start circuit automatically after the thermal shutdown hiccup time is over. Furthermore, if the over-current condition has lasted for more than the hiccup wait time which is programmed for 512 switching cycles, the TPS65276V will shut down itself and re-start after the hiccup time which is set for 16384 cycles. The hiccup mode helps to reduce the device power dissipation under severe over-current conditions. The TPS65276V operates at any load conditions unless the COMP pin voltage drops below the COMP pin start switching threshold which is typically 0.25 V. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 17 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com When PSM mode operation is enabled, the TPS65276V monitors the peak switch current of the high-side MOSFET. Once the peak switch current is lower than typically 1 A, the device stops switching to boost the efficiency until the peak switch current is higher than typically 1 A again. 18 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 DETAILED DESCRIPTION Adjusting the Output Voltage The output voltage is set with a resistor divider from the output node (VOUT) to the FB pin. It is recommended to use 1% tolerance or better divider resistors. Vo IC R1 FB R2 0.6V Figure 32. Voltage Divider Circuit æ ö 0.6V R 2 = R1 × ç ÷ è VOUT - 0.6V ø (1) Start with a 40.2-kΩ for R1 and use Equation 1 to calculate R2. To improve efficiency at light loads consider using larger value resistors. If the values are too high, the regulator is more susceptible to noise and voltage errors from the FB input current are noticeable. Output voltage can also be changed by I2C controlled VID in a 7-bit register. The minimum output voltage and maximum output voltage can be limited by the minimum on time of the highside MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in Minimum Output Voltage and Bootstrap Voltage (BOOT) and Low Dropout Operation. Enable and Adjusting Under-Voltage Lockout The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low Iq state. The EN pin has an internal pull-up current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 500mV. If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN, in split rail applications, then the EN pin can be configured as shown in Figure 33. When using the external UVLO function it is recommended to set the hysteresis to be greater than 500 mV. The EN pin has a small pull-up current IP which sets the default state of the pin to enable when no external components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 2 and Equation 3. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 19 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com Figure 33. Adjustable VIN Under-Voltage Lockout VENFALLING ) - VSTOP VENRISING V IP (1 - ENFALLING ) + Ih VENRISING VSTART ( R1 = R2 = VSTOP (2) R1 ´ VENFALLING - VENFALLING + R1(Ih + Ip ) (3) Where Ih = 3 µA, IP = 3 µA, VENRISING = 1.21 V, VENFALLING = 1.17 V. Adjustable Switching Frequency and Synchronization The ROSC pin can be used to set the switching frequency of the device in two mode. The resistor mode is to connect a resistor between ROSC pin and GND. The switching frequency of the device is adjustable from 200 kHz to 1600 kHz. The other mode called synchronization mode is to connect an external clock signal directly to the ROSC pin. The device is synchronized to the external clock frequency with PLL. Synchronization mode overrides the resistor mode. The device is able to detect the proper mode automatically and switch from synchronization mode to resistor mode. Adjustable Switching Frequency (Resistor Mode) To determine the ROSC resistance for a given switching frequency, use Equation 4 or the curve in Figure 34. To reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply efficiency and minimum controllable on time should be considered. 20 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 Figure 34. ROSC vs Switching Frequency -1.019 Rosc (kW) = 45580 × fsw (kHz) (4) Synchronization An internal phase locked loop (PLL) has been implemented to allow synchronization between 200 kHz and 1600 kHz, and to easily switch from Resistor mode to Synchronization mode. To implement the synchronization feature, connect a square wave clock signal to the ROSC pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The start of the switching cycle is synchronized to the falling edge of ROSC pin. In applications where both Resistor mode and Synchronization mode are needed, the device can be configured as shown in Figure 35. Before the external clock is present, the device works in Resistor mode and the switching frequency is set by ROSC resistor. When the external clock is present, the Synchronization mode overrides the Resistor mode. The first time the ROSC pin is pulled above the ROSC high threshold (2 V), the device switches from the Resistor mode to the Synchronization mode and the ROSC pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from the Synchronization mode back to the Resistor mode because the internal switching frequency drops to 100 kHz first before returning to the switching frequency set by ROSC resistor. Mode Selection IC ROSC ROSC Figure 35. Resistor Mode and Synchronization Mode Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 21 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com Soft Start Time The start-up of buck output is controlled by the voltage on the respective SS pin. When the voltage on the SS pin is less than the internal 0.6-V reference, the TPS65276V regulates the internal feedback voltage to the voltage on the SS pin instead of 0.6 V. The SS pin can be used to program an external soft-start function or to allow output of buck to track another supply during start-up. The device has an internal pull-up current source of 6 µA that charges an external soft-start capacitor to provide a linear ramping voltage at SS pin. The TPS65276V regulates the internal feedback voltage according to the voltage on the SS pin, allowing VOUT to rise smoothly from 0 V to its final regulated voltage. The total soft-start time will be calculated approximately: æ 0.6 × V ö Tss(ms) = Css(nF) × ç ÷ è 6 × mA ø (5) VID Control When I2C is not in function, the output voltage of TPS65276V is solely set by an external resistor divider. If system wants to control the output voltage, VID (voltage identification) DAC can be controlled via I2C interface to the Output Voltage Selection register of 0x00H (Buck 1) and 0x1H (Buck 2). Output voltage is required to be preset by the external resistor divider. When VID DAC is selected via I2C interface and the “GO” bit in command register is set, the output voltage is set with the internal voltage divider over the external voltage divider. Out-of-Phase Operation In order to reduce input ripple current, Buck 1 and Buck 2 operate 180° out-of-phase. This enables the system having less input ripple, then to lower component cost, save board space and reduce EMI. Output Overvoltage Protection (OVP) The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some applications with small output capacitance, the power supply output voltage can respond faster than the error amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by comparing the FB pin voltage to the OVP threshold. If the FB pin voltage is greater than the OVP threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle. Bootsrap Voltage (BOOT) and Low Dropout Operation The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and LX pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT pin voltage is less than VIN and BOOT-LX voltage is below regulation. The value of this ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to LX pin voltage is greater than the BOOT-LX UVLO threshold which is typically 2.1 V. When the voltage between BOOT and LX drops below the BOOT-LX UVLO threshold the high-side MOSFET is turned off and the low-side MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails. 100% duty cycle operation can be achieved as long as (VIN – PVIN) > 4 V. Over Current Protection The device is protected from over current conditions by cycle-by-cycle current limiting on both the high-side MOSFET and the low-side MOSFET. 22 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 High-Side MOSFET Over Current Protection The device implements current mode control which uses the COMP pin voltage to control the turn off of the highside MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current and the current reference generated by the COMP pin voltage are compared, when the peak switch current intersects the current reference the high-side switch is turned off. Low-Side MOSFET Over Current Protection While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing current limit at the start of a cycle. The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are off until the start of the next cycle. Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart after the hiccup time of 16384 cycles. The hiccup mode helps to reduce the device power dissipation under severe overcurrent conditions. Thermal Shutdown The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 160°C typically. Once the junction temperature drops below 140°C typically, the internal thermal hiccup timer will start to count. The device reinitiates the power up sequence after the built-in thermal shutdown hiccup time (16384 cycles) is over. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 23 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com APPLICATION INFORMATION Output Inductor Selection To calculate the value of the output inductor, use Equation 18. LIR is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for the majority of applications. V V out - Vout L = inmax × Io × LIR Vinmax × fsw (6) For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 8 and Equation 9. V V out - Vout Iripple = inmax × L Vinmax × fsw (7) Vout × (Vinmax - Vout ) 2 ) Vinmax × L × fsw 2 ILrms = IO + 12 I ripple ILpeak = Iout + 2 ( (8) (9) The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. Output Capacitor Selection There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the most stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 10 shows the minimum output capacitance necessary to accomplish this. 2 × DIout Co = fsw × DVout (10) Where ΔIOUT is the change in output current, fSW is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example, the transient load response is specified as a 5% change in VOUT for a load step of 3 A. For this example, ΔIOUT = 3 A and ΔVOUT = 0.05 x 3.3 = 0.165 V. Using these numbers gives a minimum capacitance of 75.8 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. 24 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 Equation 11 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fSW is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Ioripple is the inductor ripple current. 1 1 Co > × V 8 × fsw oripple Ioripple (11) Equation 12 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Voripple Resr < Ioripple (12) Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 13 can be used to calculate the RMS ripple current the output capacitor needs to support. V × (Vinmax - Vout ) Icorms = out 12 × Vinmax × L × fsw (13) Input Capacitor Selection The TPS65276V requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10-µF of effective capacitance on the PVIN input voltage pins. In some applications additional bulk capacitance may also be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS65276V. The input ripple current can be calculated using Equation 14. Iinrms = Iout × Vout (Vinmin - Vout ) × Vinmin Vinmin (14) The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage. TPS65276V may operate from a single supply. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 15. I × 0.25 DVin = out max Cin × fsw (15) Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 25 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com Loop Compensation Integrated buck DC/DC converter in TPS65276V incorporates a peak current mode control scheme. The error amplifier is a transconductance amplifier with a gain of 1350 µA/V. A typical type II compensation circuit adequately delivers a phase margin between 60° and 90°. Cb adds a high frequency pole to attenuate high frequency noise when needed. To calculate the external compensation components, follow the following steps. 1. Select switching frequency fsw that is appropriate for application depending on L and C sizes, output ripple, EMI, and etc. Switching frequency between 500 kHz to 1 MHz gives best trade off between performance and cost. To optimize efficiency, lower switching frequency is desired. 2. Set up cross over frequency, fc, which is typically between 1/5 and 1/20 of fsw. 3. RC can be determined by: RC = 2p × fc × Vo × Co g M × Vref × gm ps Where is the error amplifier gain (1350 µA/V) is the power stage voltage to current conversion gain (10 A/V). 4. Calculate CC by placing a compensation zero at or before the dominant pole: 1 (fp = )×s CO × RL × 2p (16) CC = RL × Co RC (17) 5. Optional Cb can be used to cancel the zero from the ESR associated with CO. R × Co Cb = ESR RC (18) VOUT RESR iL RL Current Sense g = 10 A / V mps I/V Converter Co R1 C1 VFB COMP EA g M = 1350µs Vref = 0.6V R2 Rc Cb Cc Figure 36. DC/DC Loop Compensation 26 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 Serial Interface Description I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The TPS65276V device works as a slave and supports the following data transfer modes, as defined in the I2CBus Specification: standard mode (100 kbps), and fast mode (400 kbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as supply voltage remains above 4.5 V (typical). The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as F/S-mode in this document. The TPS65276V device supports 7-bit addressing; 10-bit addressing and general call address are not supported. The TPS65276V device has a 7-bit address with the 2 LSB bits set by ADDR pin. Connecting ADDR to ground set the address 0x60H, connecting to high set the address 0x61H, leaving this pin open set the address 0x62H. Table 1. I2C Address Selection ADDR PIN I2C ADDRESS Connect to Ground 0x60H Open 0x61H Connect to High 0x62H Figure 37. I2C Interface Timing Diagram Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 27 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com TPS65276V I2C Update Sequence The TPS65276V requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receipt of each byte, TPS65276V device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the TPS65276V. TPS65276V performs an update on the falling edge of the LSB byte. When the TPS65276V is in hardware shutdown (EN1 and EN2 pin tied to ground) the device can not be updated via the I2C interface. Conversely, the I2C interface is fully functional during software shutdown (EN1 and EN2 bit = 0). S 0 A 7-Bit Slave Address Register Address A Data Byte A P Figure 38. I2C Write Data Format S 0 A 7-Bit Slave Address Register1 Address A Sr 7-Bit Slave Address 1 A N P Data Byte Figure 39. I2C Read Data Format A: Acknowledge N: Not Acknowledge S: Start System Host P: Stop Chip Sr: Repeated Start Register Description Register descriptions are shown in the below tables. Table 2. Register Addresses 28 NAME BITS ADDRESS Vout1_SEL 8 0x00H Vout2_SEL 8 0x01H Vout1_COM 8 0x02H Vout2_COM 8 0x03H Sys_STATUS 8 0x04H Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 Table 3. Vout1 Voltage Selection Register NUMBER OF BITS ACCESS NAME DEFAULT VALUE Vout1_SEL 7 address: 0x00H Bit 7 R/W Vout1_Bit7 0 Bit 6 R/W Vout1_Bit6 0 Bit 5 R/W Vout1_Bit5 0 Bit 4 R/W Vout1_Bit4 0 Bit 3 R/W Vout1_Bit3 0 Bit 2 R/W Vout1_Bit2 0 Bit 1 R/W Vout1_Bit1 0 Bit 0 R/W Vout1_Bit0 0 DESCRIPTION 10-mV step, from 0.68 V to 1.95 V Go bit, must set “1” to enable I2C voltage control 0x00H: 0.68V; 0x7FH: 1.95V Table 4. Vout2 Voltage Selection Register NUMBER OF BITS ACCESS NAME DEFAULT VALUE Vout2_SEL 7 address: 0x01H Bit 7 R/W Vout2_Bit7 0 Bit 6 R/W Vout2_Bit6 0 Bit 5 R/W Vout2_Bit5 0 Bit 4 R/W Vout2_Bit4 0 Bit 3 R/W Vout2_Bit3 0 Bit 2 R/W Vout2_Bit2 0 Bit 1 R/W Vout2_Bit1 0 Bit 0 R/W Vout2_Bit0 0 DESCRIPTION 10-mV step, from 0.68 V to 1.95 V Go bit, must set “1” to enable I2C voltage control 0x00H: 0.68V; 0x7FH: 1.95V Table 5. Vout1 Command Register NUMBER OF BITS ACCESS NAME DEFAULT VALUE Bit 6 R/W Slew Rate 3 0 Bit 5 R/W Slew Rate 2 0 Bit 4 R/W Slew Rate 1 0 Bit 2 R/W PSM Mode 0 Bit 1 R/W PSM Mode 0 Bit 0 R/W Disable1 0 Vout1_COM 8 address: 0x02H Bit 7 DESCRIPTION Reserved Bit 3 Vout slew rate control. 000: 10 mV/cycle; 001: 10 mV/2 cycles; 010: 10 mV/4 cycles; 011: 10 mV/8 cycles; 100: 10 mV/16cycles; 101: 10 mV/32cycles; 110: 10 mV/64cycles; 111: 10 mV/128 cycles Reserved 00: select by MODE pin; 01: forced PWM mode; 10: auto PSM-PWM mode; 11: reserved 0: output enabled; 1: output disabled Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 29 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com Table 6. Vout2 Command Register NUMBER OF BITS ACCESS NAME DEFAULT VALUE Bit 6 R/W Slew Rate 3 0 Bit 5 R/W Slew Rate 2 0 Bit 4 R/W Slew Rate 1 0 Bit 2 R/W PSM Mode 0 Bit 1 R/W PSM Mode 0 Bit 0 R/W Disable2 0 Vout2_COM 8 address: 0x03H Bit 7 DESCRIPTION Reserved Bit 3 Vout slew rate control. 000: 10 mV/cycle; 001: 10 mV/2 cycles; 010: 10 mV/4 cycles; 011: 10 mV/8 cycles; 100: 10 mV/16cycles; 101: 10 mV/32cycles; 110: 10 mV/64cycles; 111: 10 mV/128 cycles Reserved 00: select by MODE pin; 01: forced PWM mode; 10: auto PSM-PWM mode; 11: reserved 0: output enabled; 1: output disabled Table 7. System Status Register NUMBER OF BITS ACCESS NAME DEFAULT VALUE 8 address: 0x04H Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 30 DESCRIPTION SYS_STATUS Reserved Bit 2 R Temperature Warning (> 125°C) Bit 1 R PGOOD2 0 1: Vout2 in power good regulation range; 0: Vout2 not in power good regulation range Bit 0 R PGOOD 1 0 1: Vout1 in power good regulation range; 0: Vout1 not in power good regulation range Submit Documentation Feedback 0 1: Die temperature over 125°C; 0: Die temperature below 125°C Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 Table 8. Vout1 and Vout2 Output Voltage Setting VOUT_SEL OUTPUT VOLTAGE (V) VOUT_SEL OUTPUT VOLTAGE (V) VOUT_SEL OUTPUT VOLTAGE (V) VOUT_SEL OUTPUT VOLTAGE (V) 0 0.68 1 0.69 20 1 40 1.32 60 1.64 21 1.01 41 1.33 61 2 1.65 0.7 22 1.02 42 1.34 62 1.66 3 0.71 23 1.03 43 1.35 63 1.67 4 0.72 24 1.04 44 1.36 64 1.68 5 0.73 25 1.05 45 1.37 65 1.69 6 0.74 26 1.06 46 1.38 66 1.7 7 0.75 27 1.07 47 1.39 67 1.71 8 0.76 28 1.08 48 1.4 68 1.72 9 0.77 29 1.09 49 1.41 69 1.73 A 0.78 2A 1.1 4A 1.42 6A 1.74 B 0.79 2B 1.11 4B 1.43 6B 1.75 C 0.8 2C 1.12 4C 1.44 6C 1.76 D 0.81 2D 1.13 4D 1.45 6D 1.77 E 0.82 2E 1.14 4E 1.46 6E 1.78 F 0.83 2F 1.15 4F 1.47 6F 1.79 10 0.84 30 1.16 50 1.48 70 1.8 11 0.85 31 1.17 51 1.49 71 1.81 12 0.86 32 1.18 52 1.5 72 1.82 13 0.87 33 1.19 53 1.51 73 1.83 14 0.88 34 1.2 54 1.52 74 1.84 15 0.89 35 1.21 55 1.53 75 1.85 16 0.9 36 1.22 56 1.54 76 1.86 17 0.91 37 1.23 57 1.55 77 1.87 18 0.92 38 1.24 58 1.56 78 1.88 19 0.93 39 1.25 59 1.57 79 1.89 1A 0.94 3A 1.26 5A 1.58 7A 1.9 1B 0.95 3B 1.27 5B 1.59 7B 1.91 1C 0.96 3C 1.28 5C 1.6 7C 1.92 1D 0.97 3D 1.29 5D 1.61 7D 1.93 1E 0.98 3E 1.3 5E 1.62 7E 1.94 1F 0.99 3F 1.31 5F 1.63 7F 1.95 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 31 TPS65276V SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 www.ti.com PCB Layout Guideline TPS65276V can be layout on 2-layer PCB illustrated below. Layout is a critical portion of good power supply design. See Figure 40 for a PCB layout example. The top layer contains the main power traces for VIN, VOUT, and VLX. Also on the top layer are connections for the remaining pins of the TPS65276V and a large top side area filled with ground. The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor and directly under the TPS65276V device to provide a thermal path from the exposed thermal pad land to ground. The bottom layer acts as ground plane connecting analog ground and power ground. The GND pin should be tied directly to the power pad under the IC and the power pad. For operation at full rated load, the top side ground area together with the internal ground plane, must provide adequate heat dissipating area. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a low ESR ceramic capacitor with X5R or X7R dielectric. Since the LX connection is the switching node, the output inductor should be located close to the LX pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width. The additional external components can be placed approximately as shown. EN1 EN2 PGND PGND PGND G PGND VIN2 LX2 2 LX2 VOUT2 AGND V7V VIN1 PGND G PGND PGND LX1 1 LX1 VOUT1 SDA SCL PGND DVCC Figure 40. TPS65276V Layout on 2-layer PCB 32 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V TPS65276V www.ti.com SLVSBW0B – FEBRUARY 2013 – REVISED JANUARY 2014 REVISION HISTORY Changes from Revision A (June 2013) to Revision B Page • Changed FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................ 4 • Changed ABSOLUTE MAXIMUM RATINGS table ............................................................................................................... 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPS65276V 33 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS65276VDAPR ACTIVE HTSSOP DAP 32 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS65276V TPS65276VRHHR ACTIVE VQFN RHH 36 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 65276V TPS65276VRHHT ACTIVE VQFN RHH 36 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 65276V (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of