TPS65279DAP

Sample & Buy Product Folder Technical Documents Support & Community Tools & Software TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 TPS65279 4.5- to 18-V Input, 5-A/5-A Dual Synchronous Step-Down Converter With Current Sharing 1 Features 3 Description • • TPS65279 is a monolithic dual synchronous buck converter with wide 4.5-V to 18-V operating input voltage range that encompassed most intermediate bus voltage operating off 5-, 9-, 12- or 15-V power bus or battery. The converter with constant frequency peak current mode control is designed to simplify its application while giving the designers options to optimize their usage according to the target applications. 1 • • • • • • • • • • 4.5-V to 18-V Wide Input Voltage Range Programmable Slew Rate Control for Output Voltage Transition Up to 5-A Maximum Continuous Output Current in Buck 1 and Buck 2 Buck 1 and Buck 2 can be Paralleled to Deliver up to 10-A Current Pulse Skipping Mode to Achieve High Efficiency in Light Load Adjustable Switching Frequency 200 kHz to 1.6 MHz Set by External Resistor Dedicated Enable and Soft-Start for Each Buck Peak Current-Mode Control With Simple Compensation Circuit Cycle-by-Cycle Overcurrent Protection 180° Out-of-Phase Operation to Reduce Input Capacitance and Power Supply Induced Noise Over Temperature Protection Available in 32-Pin Thermally Enhanced HTSSOP (DAP) and 36-Pin VQFN 6-mm × 6-mm (RHH) Packages Two bucks in TPS65279 can be paralleled to delivery up to 10-A load current by using current sharing mode, connect ISHARE pin high. Two phase operation in current sharing reduces system filtering capacitance and inductance, alleviates EMI and improves output voltage ripple and noise. TPS65279 features a dedicated enable pin. An independent soft-start pin provides flexibility in power up programmability. Constant frequency peak current mode control simplifies the compensation and provides fast transient response. Cycle-by-cycle overcurrent protection and hiccup mode operation limit MOSFET power dissipation in short circuit or over loading fault conditions. Device Information(1) 2 Applications • • • • • PART NUMBER DTV Telecom and Network Point-of-Load Set Top Boxes Tablet PC TPS65279 PACKAGE BODY SIZE (NOM) HTSSOP (32) 6.20 mm × 11.00 mm VQFN (36) 6.00 mm × 6.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. SPACE Typical Application Schematic EN1 TPS65279 EN2 R2 PGND2 C3 FB2 C30 LX2 PVIN2 LX2 ISHARE R31 BST2 PVIN2 COMP2 V7V ROSC VIN COMP1 R26 LX1 PVIN1 LX1 C26 DVCC PGND1 R15 PGOOD1 RLIM1 PGOOD2 FB1 50% 40% 20% C23 Forced PWM 10% VOUT1 C19 BST1 60% 30% L1 C14 70% R24 R23 PVIN1 80% C29 L2 VOUT2 C9 VIN 90% R32 RLIM2 Efficiency R1 R16 Efficiency vs Loading 100% R18 C20 0% 0 Auto PSM-PWM 1 2 3 Loading (A) 4 5 C009 R17 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 5 7.1 7.2 7.3 7.4 7.5 7.6 5 5 5 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 8.1 Overview ................................................................. 11 8.2 Functional Block Diagram ....................................... 12 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 15 9 Application and Implementation ........................ 16 9.1 Application Information............................................ 16 9.2 Typical Applications ................................................ 16 10 Power Supply Recommendations ..................... 26 11 Layout................................................................... 27 11.1 Layout Guidelines ................................................. 27 11.2 Layout Example .................................................... 27 12 Device and Documentation Support ................. 28 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 28 28 28 28 13 Mechanical, Packaging, and Orderable Information ........................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (December 2013) to Revision C Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Updated conditions for Electrical Characteristics from TJ = 25°C to TJ = –40°C to 125°C .................................................... 6 • Updated UVLO minimum for falling VIN to 3.4 from 3.5 ........................................................................................................ 6 • Updated enable threshold rising maximum to 1.3 and falling minimum to 1.0, from 1.26 and 1.10, respectively ................. 6 Changes from Revision A (December 2013) to Revision B Page • Changed ILIMIT2 test conditions................................................................................................................................................ 6 • Changed Functional Block Diagram ..................................................................................................................................... 12 • Changed Current Sharing Operation section ....................................................................................................................... 15 • Changed Loop Compensation section ................................................................................................................................. 20 2 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 5 Description (continued) Low-side reverse overcurrent protection also prevents excessive sinking current from damaging the converter. TPS65279 also features a light load pulse skipping mode (PSM) controlled by MODE pin configuration. The TPS65279 is available in a 32-pin thermally-enhanced HTSSOP (DAP) package and 36-pin 6-mm × 6-mm VQFN (RHH) package. 6 Pin Configuration and Functions DAP Package 32-Pin HTSSOP Top View RLIM2 BST2 LX2 30 EN2 FB2 3 FB2 EN1 31 EN2 2 PGND2 32 PGND2 1 EN1 PGND2 RHH Package 36-Pin VQFN Top View 36 35 34 33 32 31 30 29 28 RLIM 2 PGND2 BST2 4 29 5 28 PGND2 LX2 LX2 PVIN2 6 27 PVIN2 PVIN2 1 27 LX2 PVIN2 2 26 LX2 ISHARE 3 25 SS2 MODE 4 24 COMP2 V7V 5 Thermal Pad 23 AGND SS2 22 ROSC VIN 6 ROSC V7V 10 VIN 20 SS1 PGND1 9 19 LX1 23 COMP1 11 22 12 21 13 20 14 19 15 18 16 17 PVIN1 SS1 10 11 12 13 14 15 16 17 18 LX1 24 LX1 Power Pad BST1 AGND 9 21 COMP1 PVIN1 8 RLIM1 MODE PVIN1 7 FB1 COMP2 PGOOD2 25 PGOOD1 8 ISHARE PGND1 26 PGND1 7 LX1 PVIN1 PGND1 LX1 PGND1 BST1 RLIM 1 PGOOD1 PGOOD2 FB1 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 3 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com Pin Functions PIN NAME HTSSOP DESCRIPTION VQFN EN1, EN2 1, 2 32, 33 PGND2 3, 4 34, 35, 36 PVIN2 5, 6 1, 2 ISHARE 7 3 Logic pin to configure current sharing mode, tie to high to parallel two buck converters, in current sharing mode, buck1 will be used; tie to low to run in separate mode. MODE 8 4 Connecting this pin to ground, the buck converter forces a continuous current mode (CCM) operation. Connecting this pin to V7V, the buck converter automatically operates in pulse skipping mode (PSM) at light load condition to save the power. 5 Internal low-drop linear regulator (LDO) output to power internal driver and control circuits. Decouple this pin to power ground with a minimum 1-µF ceramic capacitor. Output regulates to typical 6.3 V for optimal conduction on-resistances of internal power MOSFETs. In PCB design, the power ground and analog ground should have one-point common connection at the (-) terminal of V7V bypass capacitor. If VIN is lower than 6.3 V, V7V will be slightly lower than VIN. Power supply of the internal LDO and controllers V7V 9 VIN Enable pin. Adjust the input under-voltage lockout with two resistors. Power ground of buck2, place the input capacitor’s ground pin as close as possible to this pin. Power input. Input power supply to the power switches of the power converter 2. 10 6 PVIN1 11, 12 7, 8 PGND1 13, 14 9, 10, 11 PGOOD1 15 12 Power Good pin for buck1, open drain output, when output is within range, output high impedance, a 100-kΩ resistor is recommended to connect to this pin. PGOOD2 16 13 Power Good pin for buck2, open drain output, when output is within range, output high impedance, a 100-kΩ resistor is recommended to connect to this pin. FB1 17 14 Feedback sensing pin for buck1 output voltage. Connect this pin to the resistor divider of buck1 output. The feedback reference voltage is 0.6 V ±1%. RLIM1 18 15 Current limit threshold set pin for buck1, connect a resistor between this pin to GND to set the OCP. BST1 19 16 Add a bootstrap capacitor between BST1 and LX1. The voltage on this capacitor carries the gate drive voltage for the high-side MOSFET. LX1 20, 21 17, 18, 19 SS1 22, 27 20, 25 COMP1 23 21 Error amplifier output and loop compensation pin for buck1. Connect frequency compensation to this pin; In current sharing application, this pin serves as the compensation pin. ROSC 24 22 Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency. When connected to an external clock, the internal oscillator synchronizes to the external clock. AGND 25 23 Analog ground of the controllers COMP2 26 24 Error amplifier output and loop compensation pin for buck2. Connect frequency compensation to this pin. In current sharing application, float this pin. SS2 27 25 Soft-start and voltage tracking in buck2. An external capacitor connected to this pin sets the internal voltage reference rise time. Since the voltage on this pin overrides the internal reference, it can be used for tracking and power sequencing. In current sharing application, float this pin. LX2 28, 29 26, 27, 28 BST2 30 29 Add a bootstrap capacitor between BST2 and LX2. The voltage on this capacitor carries the gate drive voltage for the high-side MOSFET of buck2. RLIM2 31 30 Current limit threshold set pin for buck2, connect a resistor between this pin to GND to set the OCP. FB2 32 31 Feedback sensing pin for buck2 output voltage. Connect this pin to the resistor divider of buck2 output. The feedback reference voltage is 0.6 V ±1%. In current sharing mode, connect this pin to ground. Exposed Thermal Pad 33 37 Exposed thermal pad of the package. Connect to the power ground. Always solder thermal pad to the board, and have as many vias as possible on the PCB to enhance power dissipation. There is no electric signal down bonded to the thermal pad inside the IC package. 4 Power input. Input power supply to the power switches of the power converter 1. Power ground of buck1, place the input capacitor’s ground pin as close as possible to this pin. Switching node of buck1 Soft-start and voltage tracking in buck1. An external capacitor connected to this pin sets the internal voltage reference rise time. Since the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. In current sharing application, this pin serves as the soft-start pin. Switching nodes Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Voltage at VIN, PVIN1, PVIN2 –0.3 20 V Voltage at LX1, LX2 (maximum withstand voltage transient < 20 ns) –4.5 23 V Voltage at BST1, BST2, referenced to LX1, LX2 pin –0.3 7 V Voltage at V7V, EN1, EN2, RLIM1, RLIM2, PGOOD1, PGOOD2, MODE, ISHARE, ROSC –0.3 7 V Voltage at SS1, SS2, FB1, FB2, COMP1, COMP2 –0.3 3.6 V Voltage at AGND, PGND1, PGND2 –0.3 0.3 V TJ Operating virtual junction temperature –40 150 °C Tstg Storage temperature –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human body model (HBM) 2000 Charge device model (CDM) 1000 UNIT V 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX 4.5 18 V 0 5 A Output voltage 0.6 9 V Enable voltage 0 6 V –40 125 °C VIN Supply input voltage range IOUT1, IOUT2 Load current Vout EN TJ Operating junction temperature UNIT 7.4 Thermal Information TPS65279 THERMAL METRIC (1) DAP (HTSSOP) RHH (VQFN) 32 PINS 36 PINS UNIT 35 30.8 °C/W RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 17.7 18.8 °C/W RθJB Junction-to-board thermal resistance 19 6 °C/W ψJT Junction-to-top characterization parameter 0.5 0.2 °C/W ψJB Junction-to-board characterization parameter 18.9 6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.3 0.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 5 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com 7.5 Electrical Characteristics TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input voltage range VIN1 and VIN2 IDDSDN Shutdown supply current EN1 = EN2 = low 4.5 10 µA IDDQ_NSW Switching quiescent current with no load at DCDC output EN1 = EN2 = 3.3 V With power skip mode, without bucks switching 1.2 mA IDDQ_SW Switching quiescent current with no load at DCDC output, Buck switching EN1 = EN2 = 3.3 V With bucks switching 10 mA UVLO VIN undervoltage lockout Rising VIN Falling VIN 4.25 3.4 Hysteresis V7V 6.3 V LDO IOCP_V7V Current limit of V7V LDO V7V load current = 0 A 18 V 4.50 3.75 V 0.5 6.10 6.3 6.5 200 V mA ENABLE VENR Enable threshold Rising VENF Enable threshold Falling IENR Enable Input current IENF Enable hysteresis current 1.21 1.0 1.3 V 1.17 V EN = 1 V 3 µA EN = 1.5 V 3 µA OSCILLATOR FSW Switching frequency tSYNC_w Clock sync minimum pulse width VSYNC_HI Clock sync high threshold VSYNC_LO Clock sync low threshold VSYNC_D Clock falling edge to LX rising edge delay FSYNC Clock sync frequency range 200 ROSC = 100 kΩ (1%) 340 1600 400 460 20 kHz ns 2 0.8 V V 66 200 ns 1600 kHz 0.606 V BUCK 1, BUCK 2 CONVERTERS Vref(min) Voltage reference 0 A < IOUT1 < 6 A, 0 A < IOUT2 < 3.5 A VLINEREG Line regulation-DC IOUT = 2 A VLOADREG Load regulation-DC IOUT = (10-90%) x IOUT_max Gm_EA Error amplifier trans-conductance -2 µA < ICOMP < 2 µA Gm_SRC COMP voltage to inductor current Gm ILX = 0.5 A ISSx Soft-start pin charging current ILIMIT1 Buck 1 peak inductor current limit ILIMIT2 Buck 2 peak inductor current limit ILIMITLSx Low side sinking current limit Rdsonx_HS On resistance of high side FET V7V = 6.3 V 31 mΩ Rdsonx_LS On resistance of low side FET VIN = 12 V 23 mΩ Tminon Minimum on time 94 ns VbootUV Boot-LX UVLO 2.1 Thiccupwait Hiccup wait time 512 cycles Thiccup_re Hiccup time before re-start 16384 cycles 6 0.594 0.6 0.5 %/V 0.5 %/A 1350 µS 10 A/V 6 µA RLIM1 = 60.4 kΩ 7.3 A RLIM2 = 60.4 kΩ 7.3 A -2.6 A Submit Documentation Feedback 3 V Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 Electrical Characteristics (continued) TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PGOOD VPGOOD PGOOD trip levels FB rising to PGOOD high 94% FB falling to PGOOD low 92.5% FB rising to PGOOD low 107.5% FB falliong to PGOOD high 105.5% THERMAL SHUTDOWN TTRIP Thermal protection trip point THYST Thermal protection hysteresis Rising temperature 160 20 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 °C °C 7 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com 7.6 Typical Characteristics 90% 90% 80% 80% 70% 70% 60% 60% Efficiency Efficiency TA = 25°C, VIN = 12 V, ƒSW = 625 kHz (unless otherwise noted) 50% 40% 50% 40% 30% 30% 20% 20% Forced PWM 10% 0% 0 1 2 3 4 Forced PWM 10% Auto PSM-PWM 0% 0 5 Auto PSM-PWM 0.1 0.2 0.5 C004 Figure 2. 0.8-V Efficiency, Light Load VIN = 12 V, VOUT = 0.8 V 100% 100% 90% 90% 80% 80% 70% 70% 60% 60% Efficiency Efficiency Figure 1. 0.8-V Efficiency VIN = 12 V, VOUT = 0.8 V 50% 40% 30% 50% 40% 30% 20% 20% Forced PWM 10% 0 1 2 3 4 Forced PWM 10% Auto PSM-PWM 0% 0% 0 5 Auto PSM-PWM 0.1 Loading (A) 0.2 0.3 0.4 0.5 Loading (A) Figure 3. 1.8-V Efficiency VIN = 12 V, VOUT = 1.8 V C006 Figure 4. 1.8-V Efficiency, Light Load VIN = 12 V, VOUT = 1.8 V 100% 100% 90% 90% 80% 80% 70% 70% 60% 60% Efficiency Efficiency 0.4 Loading (A) Loading (A) 50% 40% 30% 50% 40% 30% 20% 20% Forced PWM 10% 0 1 2 3 4 Forced PWM 10% Auto PSM-PWM 0% 5 0% 0 Loading (A) Auto PSM-PWM 0.1 0.2 0.3 0.4 Loading (A) Figure 5. 3.3-V Efficiency VIN = 12 V, VOUT = 3.3 V 8 0.3 0.5 C008 Figure 6. 3.3-V Efficiency, Light Load VIN = 12 V, VOUT = 3.3 V Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 Typical Characteristics (continued) TA = 25°C, VIN = 12 V, ƒSW = 625 kHz (unless otherwise noted) 90% 80% 80% 70% 70% 60% 60% Efficiency 100% 90% Efficiency 100% 50% 40% 50% 40% 30% 30% 20% 20% Forced PWM 10% 0% 0 1 2 3 4 Auto PSM-PWM 0% 0 5 Loading (A) Forced PWM 10% Auto PSM-PWM 0.1 0.3 0.4 0.5 Loading (A) C009 Figure 7. 5-V Efficiency VIN = 12 V, VOUT = 5 V Figure 8. 5-V Efficiency, Light Load VIN = 12 V, VOUT = 5 V 0.81 1.81 1.80 VOUT (V) 0.80 VOUT (V) 0.2 0.79 0.78 1.79 1.78 1.77 Forced PWM Forced PWM Auto PSM-PWM Auto PSM-PWM 0.77 1.76 0 1 2 3 4 5 6 0 1 2 3 Loading (A) 4 5 Loading (A) Figure 9. 0.8-V Load Regulation VIN = 12 V, VOUT = 0.8 V 6 C012 Figure 10. 1.8-V Load Regulation VIN = 12 V, VOUT = 1.8 V 4.95 3.25 3.24 4.90 VOUT (V) VOUT (V) 3.23 3.22 4.85 3.21 4.80 3.20 Forced PWM Forced PWM Auto PSM-PWM Auto PSM-PWM 3.19 4.75 0 1 2 3 4 5 6 0 Loading (A) 1 2 3 4 5 6 Loading (A) Figure 11. 3.3-V Load Regulation VIN = 12 V, VOUT = 3.3 V Figure 12. 5-V Load Regulation VIN = 12 V, VOUT = 5 V Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 9 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com Typical Characteristics (continued) 0.82 1.82 0.81 1.81 0.8 1.8 VOUT (V) VOUT (V) TA = 25°C, VIN = 12 V, ƒSW = 625 kHz (unless otherwise noted) 0.79 0.78 0.77 1.79 1.78 1.77 forced PWM 0 A forced PWM 4.5 A auto PSM-PWM 0 A 0.76 0.75 6 7 8 9 10 11 12 13 14 15 16 17 VIN (V) forced PWM 0 A forced PWM 4.5 A auto PSM-PWM 0 A 1.76 1.75 18 6 7 9 10 11 12 13 14 15 16 17 VIN (V) Figure 13. 0.8-V Line Regulation VOUT = 0.8 V 18 C016 Figure 14. 1.8-V Line Regulation VOUT = 1.8 V 3.29 4.93 3.27 4.91 4.89 VOUT (V) 3.25 VOUT (V) 8 C015 3.23 3.21 4.87 4.85 4.83 3.19 4.81 forced PWM 0 A forced PWM 4.5 A auto PSM-PWM 0 A 3.17 3.15 6 7 8 9 10 11 12 13 14 15 VIN (V) 16 17 forced PWM 0 A forced PWM 4.5 A auto PSM-PWM 0 A 4.79 4.77 18 6 C017 Figure 15. 3.3-V Line Regulation VOUT = 3.3 V 10 Submit Documentation Feedback 7 8 9 10 11 12 13 14 15 VIN (V) 16 17 18 C018 Figure 16. 5-V Line Regulation VOUT = 5 V Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 8 Detailed Description 8.1 Overview TPS65279 is a dual 5-A/5-A output current, synchronous step-down (buck) converter with integrated N-channel MOSFETs. A wide 4.5-V to 18-V input supply range to buck encompasses most intermediate bus voltages operating off 9-V, 12-V or 15-V power bus. TPS65279 implements a constant frequency, peak current mode control which simplifies external frequency compensation. The wide switching frequency of 200 kHz to 1600 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency can be adjusted with an external resistor to ground on the ROSC pin. The TPS65279 also has an internal phase lock loop (PLL) controlled by the ROSC pin that can be used to synchronize the switching cycle to the falling edge of an external system clock. 180° out-ofphase operation between two channels reduces input filter and power supply induced noise. TPS65279 has been designed for safe monotonic startup into prebiased loads. The default start up is typically 4.5 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for automatically starting up the TPS65279 with the internal pullup current. The integrated MOSFETs of each channel allow for high efficiency power supply designs with continuous output currents up to 5 A. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications. The TPS65279 reduces the external component count by integrating the boot recharge circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and LX pins. The boot capacitor voltage is monitored by a BOOT to LX UVLO (BOOT-LX UVLO) circuit allowing LX pin to be pulled low to recharge the boot capacitor. The TPS65279 can operate at 100% duty cycle as long as the boot capacitor voltage is higher than the preset BOOT-LX UVLO threshold which is typically 2.1 V. The TPS65279 has a power good comparator with hysteresis which monitors the output voltage through internal feedback voltage. The SS (soft start/tracking) pin is used to minimize inrush current or provide power supply sequencing during power up. A small value capacitor or resistor divider should be coupled to the pin for soft start or critical power supply sequencing requirements. The TPS65279 is protected from output overvoltage, overload, and thermal fault conditions. The TPS65279 minimizes excessive output overvoltage transients by taking advantage of the power good comparator. When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning on until the internal feedback voltage is lower than 107.5% of the 0.6-V reference voltage. The TPS65279 implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections which help control the inductor current and avoid current runaway. If the over current condition has lasted for more than the hiccup wait time, the TPS65279 will shut down and re-start after the hiccup time. The TPS65279 also shuts down if the junction temperature is higher than thermal shutdown trip point. When the junction temperature drops 20°C typically below the thermal shutdown trip point, the built-in thermal shutdown hiccup timer is triggered. The TPS65279 will be restarted under control of the soft start circuit automatically after the thermal shutdown hiccup time is over. Furthermore, if the over-current condition has lasted for more than the hiccup wait time which is programmed for 512 switching cycles, the TPS65279 will shut down itself and restart after the hiccup time which is set for 16384 cycles. The hiccup mode helps to reduce the device power dissipation under severe over-current conditions. The TPS65279 operates at any load conditions unless the COMP pin voltage drops below the COMP pin start switching threshold which is typically 0.25 V. When PSM mode operation is enabled, the TPS65279 monitors the peak switch current of the high-side MOSFET. Once the peak switch current is lower than typically 1 A, the device stops switching to boost the efficiency until the peak switch current is higher than typically 1 A again. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 11 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com 8.2 Functional Block Diagram VIN 10 V7V 9 EN1 EN2 V7V LDO Bias, BG, LDOs CLK1 clk V7V ENABLE VIN 30 BUCK2 PGOOD2 Mode 16 PVIN2 V7V BST Power Good 5,6,7 CLK2 En_buck2 15 ROSC OSC/Phase Shift DVCC PGOOD1 24 MODE 28,29 LX COMP vfb1 PGND RLIM vfb2 FB LX 2 3,4 PGND2 27 SS2 32 FB2 31 RLIM 2 26 COMP2 Max. Io1 = 5 A vfb2 SS VIN, about 4.5 to 18 V BST2 MODE EN1 8 Mode En_buck1 1 clk V7V ENABLE VIN en_buck1 BST Mode MODE BUCK1 LX COMP EN2 PGND 2 V7V 12,13 19 PVIN1 VIN BST1 20,21 LX 1 13,14 PGND1 Max. Io1 = 5 A RLIM 1 en_buck2 SS 22 SS1 17 FB1 18 RLIM 1 23 COMP1 vfb1 FB AGND 25 ENS=BGOK & OTOK & LDOOK 8.3 Feature Description 8.3.1 Enable and Adjusting Undervoltage Lockout (UVLO) The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low Iq state. The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 500 mV. 8.3.2 Adjustable Switching Frequency and Synchronization The ROSC pin can be used to set the switching frequency of the device in two mode. The resistor mode is to connect a resistor between ROSC pin and GND. The switching frequency of the device is adjustable from 200 kHz to 1600 kHz. The other mode called synchronization mode is to connect an external clock signal directly to the ROSC pin. The device is synchronized to the external clock frequency with PLL. Synchronization mode overrides the resistor mode. The device is able to detect the proper mode automatically and switch from synchronization mode to resistor mode. 12 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 Feature Description (continued) 8.3.2.1 Synchronization An internal phase locked loop (PLL) has been implemented to allow synchronization between 200 kHz and 1600 kHz, and to easily switch from Resistor mode to Synchronization mode. To implement the synchronization feature, connect a square wave clock signal to the ROSC pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The start of the switching cycle is synchronized to the falling edge of ROSC pin. In applications where both Resistor mode and Synchronization mode are needed, the device can be configured as shown in Figure 17. Before the external clock is present, the device works in Resistor mode and the switching frequency is set by ROSC resistor. When the external clock is present, the Synchronization mode overrides the Resistor mode. The first time the ROSC pin is pulled above the ROSC high threshold (2 V), the device switches from the Resistor mode to the Synchronization mode and the ROSC pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from the Synchronization mode back to the Resistor mode because the internal switching frequency drops to 100 kHz first before returning to the switching frequency set by ROSC resistor. Mode Selection TPS65279 ROSC ROSC Figure 17. Resistor Mode and Synchronization Mode 8.3.3 Soft-Start Time The start-up of buck output is controlled by the voltage on the respective SS pin. When the voltage on the SS pin is less than the internal 0.6-V reference, the TPS65279 regulates the internal feedback voltage to the voltage on the SS pin instead of 0.6 V. The SS pin can be used to program an external soft-start function or to allow output of buck to track another supply during start-up. The device has an internal pullup current source of 6 µA that charges an external soft-start capacitor to provide a linear ramping voltage at SS pin. The TPS65279 regulates the internal feedback voltage according to the voltage on the SS pin, allowing VOUT to rise smoothly from 0 V to its final regulated voltage. The total soft-start time will be calculated approximately: æ 0.6 V ö t SS (ms) = Css(nF) ´ ç ÷ è 6 mA ø (1) 8.3.4 Out-of-Phase Operation In order to reduce input ripple current, Buck 1 and Buck 2 operate 180° out-of-phase. This enables the system having less input ripple, then to lower component cost, save board space and reduce EMI. 8.3.5 Output Overvoltage Protection (OVP) The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some applications Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 13 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com Feature Description (continued) with small output capacitance, the power supply output voltage can respond faster than the error amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by comparing the FB pin voltage to the OVP threshold. If the FB pin voltage is greater than the OVP threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle. 8.3.6 Bootstrap Voltage (BOOT) and Low Dropout Operation The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and LX pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT pin voltage is less than VIN and BOOT-LX voltage is below regulation. The value of this ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to LX pin voltage is greater than the BOOT-LX UVLO threshold which is typically 2.1 V. When the voltage between BOOT and LX drops below the BOOT-LX UVLO threshold the high-side MOSFET is turned off and the low-side MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails, 100% duty cycle operation can be achieved as long as (VIN – PVIN) > 4 V. 8.3.7 Overcurrent Protection The device is protected from over current conditions by cycle-by-cycle current limiting on both the high-side MOSFET and the low-side MOSFET. 8.3.7.1 High-Side MOSFET Overcurrent Protection The device implements current mode control which uses the COMP pin voltage to control the turn off of the highside MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current and the current reference generated by the COMP pin voltage are compared, when the peak switch current intersects the current reference the high-side switch is turned off. TPS65279 features adjustable overcurrent protection trip point. The peak current limit can be set by external resistors connected between pin RLIM1/2 to ground. By setting lower current limit, lower current rating inductor can be used to reduce system cost. Figure 18. Peak Current Limit vs Rlimit Ilim (A) = 168.98 × Rlimit (kΩ)–0.763 14 (2) Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 Feature Description (continued) 8.3.7.2 Low-Side MOSFET Overcurrent Protection While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing current limit at the start of a cycle. The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are off until the start of the next cycle. Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart after the hiccup time of 16384 cycles. The hiccup mode helps to reduce the device power dissipation under severe overcurrent conditions. When one channel is in OCP, the other channel is not impacted and remains independent. 8.3.8 Current Sharing Operation As TPS65279 uses peak current mode control method, the two buck converters can be paralleled together to provide large current. Paralleling two bucks provides some advantages over single buck operation, such as smaller input and output ripple, faster response in load transient, and so forth. The converters will work in current sharing mode by connecting the iShare pin to high. Once in current mode, signal pins in Buck 2 are not active, for example, FB2, COMP2, SS2, these pins will be neglected. Connecting FB2 to GND and floating COMP2, SS2, PGOOD2 are recommended. 8.3.9 Thermal Shutdown The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 160°C typically. Once the junction temperature drops below 140°C typically, the internal thermal hiccup timer will start to count. The device reinitiates the power up sequence after the built-in thermal shutdown hiccup time (16384 cycles) is over. 8.4 Device Functional Modes 8.4.1 CCM Operation Mode When the VIN/PVINx are above UVLO threshold and ENx are above the threshold, two switchers operate in continuous current mode(CCM) when MODE pin connects to GND. In CCM, the converters work in peak current mode for easy loop compensation and cycle-by-cycle high side MOSFET current limit. 8.4.2 PSM Operation Mode When connect MODE pin to V7V, PSM mode is enabled. The devices are designed to operate in high-efficiency PSM under light load conditions. Pulse skipping is initiated when the switch current falls to 0 A. During pulse skipping, the low-side FET is turned off when the switch current falls to 0 A. The switching node (LX) waveform takes on the characteristics of DCM operation and the apparent switching frequency decreases. 8.4.3 Current Sharing Mode When ISHARE pin connects to high, SW1/SW2 pair output are shared, the responding pairs current sharing mode is enabled and the two buck converters are paralleled together to provide large current. For the detail configuration, see current sharing application schematics. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 15 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The devices are step-down DC-DC converters. They are typically used to convert a higher dc voltage to a lower dc voltage with a maximum available output current of 5/5 A. The following design procedure can be used to select component values for the TPS65279. Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process. 9.2 Typical Applications 9.2.1 Dual Buck Operation Mode Application R1 100 kΩ EN1 FB2 EN2 RLIM 2 30 3 PGND2 BST2 PGND2 LX2 PVIN2 LX2 29 4 C3 10 µF 27 COMP2 MODE AGND Power Pad 9 V7V 22 PVIN1 SS1 PVIN1 LX1 21 C26 R23 C23 C22 L1 4.7 µH Io2 = 5 A 20 13 LX1 PGND1 19 14 BST1 PGND1 15 24 R24 23 12 R15 100 kΩ R26 COMP1 VIN 11 R16 100 kΩ 25 ROSC 10 DVCC Io1 = 5 A C27 26 ISHARE 8 C14 10 µF C29 22 µF × 4 L2 4.7 µH SS2 PVIN2 7 VIN About 4.5 to 18 V C30 47 nF R31 28 5 6 C9 1 µF C31 31 2 R2 100 kΩ R32 32 1 33 C19 47 nF C20 22 µF × 4 18 PGOOD1 RLIM1 PGOOD2 FB1 16 C18 17 R18 R17 Power Ground Analog Ground Figure 19. Dual Mode Operation to Deliver 5 A at Buck1 and 5 A at Buck2 16 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 Typical Applications (continued) 9.2.1.1 Design Requirements For this design example, use the following in Table 1 as the input parameters. Table 1. Design Parameters PARAMETER EXAMPLE VALUE Input voltage range 4.5 to 18 V Output voltage 1.2 V/1.8 V ΔVout = ±5% Transient response, 1.5-A load step Input ripple voltage 400 mV Output ripple voltage 30 mV Output current rating 5A Operating frequency 600 kHz 9.2.1.2 Detailed Design Procedure 9.2.1.2.1 Adjusting the Output Voltage The output voltage is set with a resistor divider from the output node (VOUT) to the FB pin. TI recommends to use 1% tolerance or better divider resistors. Vo TPS65279 R1 FB R2 0.6 V Figure 20. Voltage Divider Circuit æ ö 0.6 V R2 = R1 ´ ç ÷ è VOUT - 0.6 V ø (3) Start with a 40.2-kΩ for R1 and use Equation 3 to calculate R2. To improve efficiency at light loads consider using larger value resistors. If the values are too high, the regulator is more susceptible to noise and voltage errors from the FB input current are noticeable. The minimum output voltage and maximum output voltage can be limited by the minimum on time of the highside MOSFET and bootstrap voltage (BOOT-LX voltage) respectively. See Bootstrap Voltage (BOOT) and Low Dropout Operation for more information. 9.2.1.2.2 Adjusting UVLO If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN, in split rail applications, then the EN pin can be configured as shown in Figure 21. When using the external UVLO function, TI recommends to set the hysteresis to >500 mV. The EN pin has a small pullup current IP which sets the default state of the pin to enable when no external components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 4 and Equation 5. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 17 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com Figure 21. Adjustable VIN UVLO VENFALLING ) - VSTOP VENRISING V IP (1 - ENFALLING ) + Ih VENRISING VSTART ( R1 = R2 = VSTOP (4) R1 ´ VENFALLING - VENFALLING + R1(Ih + Ip ) where • • • • Ih = 3 µA IP = 3 µA VENRISING = 1.21 V VENFALLING = 1.17 V (5) 9.2.1.2.3 Adjustable Switching Frequency (Resistor Mode) To determine the ROSC resistance for a given switching frequency, use Equation 6 or the curve in Figure 22. To reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply efficiency and minimum controllable on time should be considered. Figure 22. ROSC vs Switching Frequency 18 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 -1.019 Rosc (kW) = 45580 ´ ƒ sw (kHz) (6) 9.2.1.2.4 Output Inductor Selection To calculate the value of the output inductor, use Equation 7. LIR is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for the majority of applications. V V out - Vout L = inmax ´ Io ´ LIR Vinmax ´ ƒ sw (7) For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 9 and Equation 10. V V out - Vout Iripple = inmax ´ L Vinmax ´ ƒ sw (8) Vout ´ (Vinmax - Vout ) 2 ) Vinmax ´ L ´ ƒSW 2 ILrms = IO + 12 I ripple ILpeak = Iout + 2 ( (9) (10) The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. 9.2.1.2.5 Output Capacitor Selection There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the most stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 11 shows the minimum output capacitance necessary to accomplish this. 2 ´ DIout Co = ƒ sw ´ DVout where • • • ΔIOUT is the change in output current. ƒSW is the regulators switching frequency. ΔVOUT is the allowable change in the output voltage. (11) For this example, the transient load response is specified as a 5% change in VOUT for a load step of 3 A. For this example, ΔIOUT = 3 A and ΔVOUT = 0.05 x 3.3 = 0.165 V. Using these numbers gives a minimum capacitance of 75.8 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 19 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com Equation 12 calculates the minimum output capacitance needed to meet the output voltage ripple specification. 1 1 Co > ´ 8 ´ ƒ sw Voripple Ioripple where • • • ƒSW is the switching frequency. Voripple is the maximum allowable output voltage ripple. Ioripple is the inductor ripple current. (12) Equation 13 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Voripple Resr < Ioripple (13) Additional capacitance deratings for aging, temperature, and DC bias should be factored in which increases this minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 14 can be used to calculate the RMS ripple current the output capacitor needs to support. V ´ (Vinmax - Vout ) Icorms = out 12 ´ Vinmax ´ L ´ ƒ sw (14) 9.2.1.2.6 Input Capacitor Selection The TPS65279 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10-µF of effective capacitance on the PVIN input voltage pins. In some applications additional bulk capacitance may also be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS65279. The input ripple current can be calculated using Equation 15. Iinrms = Iout ´ (Vinmin - Vout ) Vout ´ Vinmin Vinmin (15) The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage. TPS65279 may operate from a single supply. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 16. I ´ 0.25 DVin = out max Cin ´ ƒ sw (16) 9.2.1.2.7 Loop Compensation Integrated buck DC/DC converter in TPS65279 incorporates a peak current mode control scheme. The error amplifier is a transconductance amplifier with a gain of 1350 µA/V. A typical type II compensation circuit adequately delivers a phase margin between 60° and 90°. Cb adds a high frequency pole to attenuate high frequency noise when needed. To calculate the external compensation components, follow the following steps. 1. Select switching frequency ƒsw that is appropriate for application depending on L and C sizes, output ripple, EMI, and etc. Switching frequency between 500 kHz to 1 MHz gives best trade off between performance and cost. To optimize efficiency, lower switching frequency is desired. 20 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 2. Set up cross over frequency, ƒc, which is typically between 1/5 and 1/20 of ƒsw. 3. RC can be determined by: 2p ´ ƒc ´ VO ´ CO RC = gM ´ Vref ´ gmps where • • gM is the error amplifier gain (1350 μA/V). gmps is the power stage voltage to current conversion gain (10 A/V). 4. Calculate CC by placing a compensation zero at or before the dominant pole: 1 (ƒP = ) CO ´ RL ´ 2p (17) R ´ Co CC = L RC (18) 5. Optional Cb can be used to cancel the zero from the ESR associated with CO. R ´ Co Cb = ESR RC (19) VOUT RESR iL RL Current Sense g = 10 A / V mps I/V Converter Co R1 C1 VFB COMP EA gM = 1350 µS Vref = 0.6 V R2 Rc Cb Cc Figure 23. DC/DC Loop Compensation Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 21 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com 9.2.1.3 Application Curves 22 Figure 24. Output Ripple at 0 A, Forced PWM Figure 25. Output Ripple at 3.5 A, Forced PWM Figure 26. Output Ripple, Buck1 at 0.05 A, Buck2 at 0.2 A Auto PSM-PWM Mode Figure 27. Startup With Enable Figure 28. Shutdown With Enable Figure 29. Load Transient, Buck1 2.5 A - 4.5 A, Buck2 0.5 A - 2.5 A Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 Figure 30. Load Transient, Buck1 (0.5 A - 2.5 A) Figure 31. Load Transient, Buck2 (0.5 A - 2.5 A) Figure 32. Overcurrent Protection Buck1 Figure 33. Hiccup Recover, Buck1 Figure 34. Overcurrent Protection, Buck2 Figure 35. Hiccup Recover, Buck2 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 23 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com Figure 36. Synchronization at 500 kHz 9.2.2 Current Sharing Mode Operation Application R1 100 kΩ 32 1 EN1 FB2 EN2 RLIM2 31 2 R2 100 kΩ 30 3 BST2 PGND2 29 4 C3 10 µF PGND2 LX2 PVIN2 LX2 27 SS2 PVIN2 26 7 ISHARE COMP2 25 8 MODE C9 1 µF 24 22 11 R23 C23 SS1 PVIN1 21 12 R15 100 kΩ C20 4x22 µF 23 COMP1 VIN DVCC R24 ROSC 10 C14 10 µF Io = 10 A AGND Power Pad 9 V7V VIN About 4.5 to 18 V L2 4.7 µH 28 5 6 V7V C30 47 nF C22 LX1 PVIN1 L1 4.7 µH 20 13 PGND1 LX1 PGND1 BST1 19 14 C19 47 nF 33 18 15 PGOOD1 RLIM 1 PGOOD2 FB1 C18 17 16 R18 R17 Power Ground Analog Ground Figure 37. Share Mode Operation to Deliver 10 A 9.2.2.1 Design Requirements See previous Design Requirements. 9.2.2.2 Detailed Design Procedure As TPS65279 utilizes peak current mode control method, the two buck converters can be paralleled together to provide large current. The converters will work in current sharing mode by connecting the iShare pin to high. Once in current mode, signal pins in Buck 2 are not active, for example, FB2, COMP2, SS2, these pins will be neglected. Connecting FB2 to GND and floating COMP2, SS2, PGOOD2 are recommended. For other component selection, refer to previous Detailed Design Procedure. 24 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 9.2.2.3 Application Curves Figure 38. Current Share Mode Startup Figure 39. Steady State of Current Share Mode Operation (IO = 0 A) Figure 40. Steady State of Current Share Mode Operation (IO = 10 A) Figure 41. Output Ripple, Current Share Mode Operation (IO = 10 A) Figure 42. Load Transient, Current Share Mode Operation (IO = 4 A - 9 A) Figure 43. Hiccup Recover, Current Share Mode Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 25 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com 4.96 100 4.94 90 80 4.92 VOUT (V) VOUT (V) 70 4.90 4.88 4.86 60 50 40 30 4.84 20 4.82 10 4.80 0 0 2 4 6 8 Loading (A) 10 0 Figure 44. Current Share Mode, 5-V Load Regulation 2 4 6 8 Loading (A) C039 10 C040 Figure 45. Current Share Mode, 5-V Load Efficiency 10 Power Supply Recommendations This device is designed to operate from an input voltage supply range between 4.5 and 18 V. This input power supply should be well regulated. If the input supply is located more than a few inches from the TPS65400 converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 22 μF is a typical choice. 26 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 TPS65279 www.ti.com SLVSC85C – AUGUST 2013 – REVISED MAY 2015 11 Layout 11.1 Layout Guidelines The designer can layout the TPS65279 on a 2-layer PCB as shown in Figure 46. Layout is a critical portion of good power supply design. See Figure 46 for a PCB layout example. The top layer contains the main power traces for VIN, VOUT, and VLX. Also on the top layer are connections for the remaining pins of the TPS65279 and a large top side area filled with ground. The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor and directly under the TPS65279 device to provide a thermal path from the exposed thermal pad land to ground. The bottom layer acts as ground plane connecting analog ground and power ground. The GND pin should be tied directly to the power pad under the IC and the power pad. For operation at full rated load, the top side ground area together with the internal ground plane, must provide adequate heat dissipating area. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a low ESR ceramic capacitor with X5R or X7R dielectric. Since the LX connection is the switching node, the output inductor should be located close to the LX pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width. The additional external components can be placed approximately as shown. 11.2 Layout Example EN1 EN2 PGND PGND PGND PGND G PGND PGND VIN2 LX2 LX22 LX2 LX2 VOUT2 AGND V7V VIN1 PGND PGND PGND G PGND PGND LX1 LX1 1 LX1 LX1 VOUT1 SDA SCL PGND DVCC Figure 46. TPS65279 Layout on 2-Layer PCB Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 27 TPS65279 SLVSC85C – AUGUST 2013 – REVISED MAY 2015 www.ti.com 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.2 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65279 PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPS65279DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65279 TPS65279DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS65279 TPS65279RHHR ACTIVE VQFN RHH 36 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 65279 TPS65279RHHT ACTIVE VQFN RHH 36 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 65279 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65279DAPR HTSSOP DAP 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1 TPS65279RHHR VQFN RHH 36 2500 330.0 TPS65279RHHT VQFN RHH 36 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 16.4 6.3 6.3 1.1 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65279DAPR HTSSOP DAP 32 2000 367.0 367.0 45.0 TPS65279RHHR VQFN RHH 36 2500 367.0 367.0 38.0 TPS65279RHHT VQFN RHH 36 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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