TPS65280RGER

TPS65280 www.ti.com SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 DUAL POWER DISTRIBUTION SWITCH AND MONOLITHIC SYNCHRONOUS BUCK REGULATOR WITH 5.5-V TO 18-V INPUT VOLTAGE, FIXED 5-V OUTPUT VOLTAGE AND 4-A MAXIMUM CURRENT Check for Samples: TPS65280 FEATURES 1 INTEGRATED DUAL POWER DISTRIBUTION SWITCHES • • • • • • • • • • Operating Input Voltage Range: 2.5 V to 6 V Integrated Back-to-Back Power MOSFETs With 80-mΩ On-Resistance Up to 1-A Maximum Load Current Current Limiting at Typical 1.2 A (0.8 A,1.6 A or 2 A Available With Manufacture Trim Options) Latch-off Over Current Protection Versions Reverse Input-Output Voltage Protection Built-In Soft-Start 4-kV HBM and 200-V MM ESD Protection at Power Switch Output Pins 15-kV ESD Protection per IEC 61000-4-2 With 10-µF External Capacitance Over Temperature Protection 24-Lead QFN (RGE) 4-mm x 4-mm Package xxx xxx xxx xxx • • • • • • • • INTEGRATED BUCK DC/DC CONVERTER Wide Input Voltage Range: 5.5 V to 18 V Maximum Continuous 4-A Output Load Current Fixed Output Voltage: 5 V ±1% Adjustable 300-kHz to 1.4-MHz Switching Frequency External Clock Synchronization Adjustable Soft Start and Tracking With Built-In 1-ms Internal Soft-start Time Cycle-by-Cycle Current Limit Output Over-voltage Protection APPLICATIONS • • • • • USB Ports and Hubs Digital TV Set-Top Boxes VOIP Phones Tablet PC DESCRIPTION/ORDERING INFORMATION The TPS65280 incorporates dual N-channel MOSFET power switches for USB power distribution systems that require dual power switches in a single package. It also integrates a buck converter which regulates an accurate 5-V output voltage from a 5.5-V to 18-V power bus to supply the power for power switches. The device is intended to provide a total USB power distribution solution for digital TV, set-top boxes, VOIP phones and tablet PC applications, where precision current limiting is required or heavy capacitive loads or short circuits are encountered. A dual 85-mΩ independent power distribution switch limits the output current to a typical 1.2 A (manufacture trim 0.8 A, 1.6 A, and 2 A available options) when output current load exceeds the current limit threshold. TPS65280 device limits output current to a safe level by using a constant current mode when output load exceeds the current limit threshold. After delitching time, TPS65280 provides circuit breaker functionality by latching off the power switch during over-current or reverse-voltage situations. Two back-to-back power MOSFETs prevent the current injects from output to input in shutdown. An internal reverse-voltage comparator disables the power switch when the output voltage is driven higher than the input to protect the circuits on the input side of the switch in normal operation. The nFAULT1/2 output asserts low during over-current and reverse-voltage conditions. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS65280 SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 www.ti.com The buck DC/DC converter integrates power MOSFETs for optimized power efficiency and reduced external component count for a fixed 5-V output voltage. A wide 5.5-V to 18-V input supply range to buck encompasses most intermediate bus voltages operating off a 9-V, 12-V or 15-V power bus. Constant frequency peak current mode control simplifies the compensation and fast transient response. Equipped with enable and soft-start pins, the DC/DC can be precisely sequenced and ramp up in order to align with other rails in the system. Cycle-bycycle over-current protection and operating in hiccup mode limit MOSFET power dissipation during buck output short circuit or over loading fault conditions. The switching frequency of the converter can be programmed from 300 kHz to 1.4 MHz with an external resistor at the ROSC pin. With the ROSC pin connecting to the V7V pin, floating, or grounding, a default fixed switching frequency can be selected to reduce the external component. The internal oscillator can be synchronized with a free-run external clock in frequency. When continuous heavy overload or short circuit increases power dissipation in the buck converter or power switches, the internal thermal protection circuit shuts off both the buck regulator and power switches to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. The TPS65280 is available in a 24-lead thermally enhanced QFN (RGE) 4-mm x 4-mm thin package. ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) 2 PACKAGE 24-Pin QFN (RGE) (2) ORDERABLE PART NUMBER Reel 3000 TPS65280RGER Reel 250 TPS65280RGET TOP-SIDE MARKING TPS65280 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 TPS65280 www.ti.com SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TYPICAL APPLICATION L1 4.7uH C6 47nF 19 20 C1 10uF VIN 5.5V~18V 21 22 R1 100kΩ PGND SW_OUT1 PGND AGND VIN NC TPS65280 VIN R2 100kΩ SW_IN 13 14 SW_IN FB 16 LX 15 17 LX BST 18 +5V C7 22uF SW_OUT2 USB Data 12 11 C8 10uF USB Port 1 10 9 C9 10uF USB Port 2 USB Data 7 USB1 fault signal USB2 fault signal 6 5 3 4 1 EN C2 1uF 8 EN_SW1 nFALUT2 EN_SW2 V7V ROSC nFALUT1 SS MODE/SYNC COMP 24 2 23 Enable USB1 control signal C4 4.7nF USB2 control signal R4 10kΩ Analog Ground Power Ground Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 3 TPS65280 SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 www.ti.com FUNCTION BLOCK DIAGRAM V7V BUCK 24 21 LDO 5V Voltage Reference Current Bias Preregulator 22 VIN VIN HS current sensing 1 .25 M CS 18 1 .25 M EN BST 1 enable buffer COMP FB HS driver 2 17 Current Sensing (0 .1 V/ A) Buck Controller 15 16 PWM comparator LX LX V7 V SS 420 K 12p 80 K 0 .8 V slope comp LS driver 3 19 error amplifer CS LS current sensing 5V 1ms Internal Soft Start Oscillotor Mode/Sync 10uA ROSC MODE/SYNC PGND 4 23 20 PGND POWER SWITCH2 EN_SW1 enable buffer 5 10ms Degl . Time 1 .25M Driver 7 Current Limit nFAULT 2 1 .25M Charge Pump 4 ms Degl. Time 9 current sensing CS reverse voltage comparator SW_IN SW_IN 11 14 UVLO POR 13 10 SW_OUT2 AGND NC reverse voltage comparator 12 CS SW_OUT1 current sensing Charge Pump 4 ms Degl. Time 1 .25M Driver 8 Current Limit nFAULT 1 1 .25 M EN_SW1 6 10ms Degl . Time enable buffer POWER SWITCH1 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 TPS65280 www.ti.com SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 PIN OUT RGE PACKAGE (TOP VIEW) BST LX LX FB SW_IN SW_IN 18 17 16 15 14 13 PGND 19 12 SW_OUT1 PGND 20 11 AGND VIN 21 10 NC Thermal Pad VIN 22 9 SW_OUT2 1 2 3 4 5 6 ROSC EN_SW2 EN_SW1 7 nFAULT2 SS V7V 24 COMP 8 nFAULT1 EN MODE/SYNC 23 There is no electric signal down boned to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 5 TPS65280 SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 www.ti.com TERMINAL FUNCTIONS NAME NO. DESCRIPTION EN 1 Enable for buck converter. Logic high enables buck converter and bias supply to power switches. Forcing the pin below 0.4 V shuts down the entire device, reducing the quiescent current to approximately 7 µA. There is a 1.25-MΩ pull-up resistor connecting this pin to internal 5-V power rail. Not recommend floating this pin. The device can be automatically started up with connecting EN pin to VIN though a 10-kΩ resistor or connecting a capacitor to program the delay of enabling the device. COMP 2 Error amplifier output and Loop compensation pin for buck. Connect a series resistor and capacitor to compensate the control loop of buck converter with peak current PWM mode. SS 3 Soft-start and tracking input for buck converter. An internal 5-µA pull-up current source is connected to this pin. An external soft-start can be programmed by connecting a capacitor between this pin and ground. Leave the pin floating to have a default 1 ms of soft-start time. This pin allows the start-up of buck output to track an external voltage using an external resistor divider at this pin. ROSC 4 Oscillator clock frequency control pin. Connect the pin to ground for a fixed 300-kHz switching frequency. Connect the pin to V7V or float the pin for a fixed 600-kHz switching frequency. Other switch frequency between 300 kHz to 1.4 MHz can be programmed using a resistor connected from this pin to ground. An internal 10-µA pull-up current develops a voltage to be used in oscillator. Directly adjusting the ROSC pin voltage can linearly adjust switching frequency. EN_SW2 5 Enable power switch 2. Logic high turns on power switch. Forcing the pin below 0.4 V shuts down power switch. Not recommend floating this pin, though there is a 1.25-MΩ pull-up resistor connecting this pin. EN_SW1 6 Enable power switch 1. Logic high turns on power switch. Forcing the pin below 0.4 V shuts down power switch. Not recommend floating this pin, though there is a 1.25-MΩ pull-up resistor connecting this pin. nFAULT2 7 Active low open drain output, asserted during over-current or reverse-voltage condition of power switch 2. nFAULT1 8 Active low open drain output, asserted during over-current or reverse-voltage condition of power switch 1. SW_OUT2 9 Power switch 2 output. NC 10 No connection. Connection to ANGD recommended. AGND 10, 11 SW_OUT1 SW_IN 12 13, 14 Analog ground common to buck controller and power switch controller. Pin 10 must be routed separately from high current power grounds to the (-) terminal of bypass capacitor of internal V7V LDO output. Power switch 1 output. Power switch input voltage. Connect to buck output, or other power supply input. FB 15 LX 16, 17 Switching node connection to the inductor and bootstrap capacitor for buck converter. This pin voltage swings from a diode voltage below the ground up to VIN voltage. 18 Bootstrapped supply to the high side floating gate driver in buck converter. Connect a capacitor (47 nF recommended) from this pin to LX. BST Kelvin sensing pin for +5-V buck output voltage. Connect this pin to the (+) terminal of buck output capacitor. The internal feedback resistor divider (420 kΩ/80 kΩ) in buck converter sets a fixed 5-V ±1% output voltage at room temperature. PGND 19, 20 Power ground connection. Connect this pin as close as practical to the (-) terminal of input ceramic capacitor. VIN 21, 22 Input power supply for buck. Connect this pin as close as practical to the (+) terminal of an input ceramic capacitor (10 µF recommended). MODE/SYNC 23 External synchronization input to internal clock oscillator in forced continuous mode. When an external clock is applied to this pin, the internal oscillator will force the rising edge of clock signal to be synchronized with the rising edge of the external clock. When not synchronizing to an external clock, connecting this pin to ground forces a continuous current mode (CCM) operation of Buck. V7V 24 Internal low-drop linear regulator (LDO) output. The internal driver and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum 1-µF ceramic capacitor. The output voltage level of LDO is regulated to typical 6.3 V for optimal conduction on-resistances of internal power MOSFETs. In PCB design, the power ground and analog ground should have one-point common connection at the (-) terminal of V7V bypass capacitor. Thermal PAD 6 Exposed pad beneath the IC. Connect to the power ground. Always solder thermal pad to the board, and have as many vias as possible on the PCB to enhance power dissipation. There is no electric signal down bonded to the thermal pad inside the IC package. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 TPS65280 www.ti.com SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VIN, LX –0.3 to 18 V LX (Maximum withstand voltage transient < 20ns) –1.0 to 18 V BST referenced to LX pin –0.3 to 7 V SW_IN, SW_OUT1, SW_OUT2 –0.3 to 7 V EN, EN_SW1, EN_SW2, nFAULT1, nFAULT2, V7V, ROSC, MODE/SYNC –0.3 to 7 V SS, COMP –0.3 to 3.6 V V7, R AGND, PGND –0.3 to 0.3 V TJ Operating virtual junction temperature range –40 to 125 °C TSTG Storage temperature range –55 to 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input operating voltage 5.5 18 V TA Ambient temperature –40 85 °C ELECTROSTATIC DISCHARGE (ESD) PROTECTION (1) MIN Human body model (HBM) Charge device model (CDM) (1) MAX UNIT 2000 V 500 V SW_OUT1/2 pins’ human body model (HBM) ESD protection rating 4 kV, and machine model (MM) rating 200V. THERMAL INFORMATION TPS65280 THERMAL METRIC (1) RGE UNITS 24 PINS Junction-to-ambient thermal resistance (2) θJA 38.1 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 16.9 ψJT Junction-to-top characterization parameter (5) 0.9 ψJB Junction-to-board characterization parameter (6) θJCbot (1) (2) (3) (4) (5) (6) (7) Junction-to-case (bottom) thermal resistance 45.3 (7) °C/W 16.9 6.2 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 7 TPS65280 SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULTx = 100 kΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input voltage range VIN1 and VIN2 IDDSDN Shutdown supply current EN = EN_SW1 = EN_SW2 = low 5.5 IDDQ_NSW Switching quiescent current with no load at DCDC output EN = high, EN_SWx = low, FB = 6 V With Buck not switching 0.8 mA IDDQ_SW Switching quiescent current with no load at DCDC output, Buck switching EN = high, EN_SWx = low, FB = 5 V With Buck switching 13 mA UVLO VIN under voltage lockout 7 V 20 µA Rising VIN 4 4.25 4.50 Falling VIN 3.75 4 4.25 V 6.45 V 1400 kHz Hysteresis V7V 18 0.25 Internal biasing supply V7V load current = 0 A, VIN = 12 V 6.05 Switching frequency range Set by external resistor ROSC 300 6.25 OSCILLATOR fSW_BK ROSC = 51 kΩ fSW 500 ROSC = 140 kΩ Programmable frequency 1400 ROSC floating or connected to V7V 510 600 690 ROSC connected to ground 255 300 345 4.95 5 5.05 4.9 5 5.1 kHz BUCK CONVERTER VIN Input supply voltage For a fixed 5-V output 5.5 VCOMP = 1.2 V, TJ = 25°C 18 V VOUT Regulated +5-V output voltage VLINEREG Line regulation - DC IOUT = 2 A 0.5 %/V VLOADREG Load regulation - DC IOUT = (10% - 90%) x IOUT_max 0.5 %/A Gm_EA Error amplifier trans-conductance (1) -2 µA < ICOMP < 2 µA 520 µs Gm_SRC COMP voltage to inductor current Gm (1) ILX = 0.5 A 10 A/V VENH EN high level input voltage VENL EN low level input voltage ISS Soft-start charging current tSS_INT Internal soft-start time ILIMIT Buck peak inductor current limit Rdson_HS On resistance of high side FET in buck Rdson_LS On resistance of low side FET in buck VCOMP = 1.2 V, TJ = -40°C to 125°C 2 V 0.4 4.5 SS pin floats 0.5 V 1 V µA 1.5 ms 5.2 A V7V = 6.25 V 80 mΩ VIN = 12 V 50 mΩ POWER DISTRIBUTION SWITCH VSW_IN Power switch input voltage range VUVLO_SW RDSON_SW 2.5 Input under-voltage lock out Power switch NDMOS on-resistance 6 V VSW_IN rising 2.15 2.25 2.35 V VSW_IN falling 2.05 2.15 2.25 V Hysteresis 100 mV VSW_INx = 5 V, ISW_OUT = 0.5 A, TJ = 25°C, including bond wire resistance 100 VSW_Inx = 2.5 V, ISW_OUT = 0.5 A, TJ = 25°C, includes bond wire resistance 100 VSW_IN = 5 V, CL = 1 µF, RL = 100 Ω (see Figure 1) 1.1 ms mΩ tD_on Turn-on delay time tD_off Turn-off delay time 1.2 ms tr Output rise time 0.6 ms tf Output fall time 0.3 ms IOCP_SW Current limit threshold (maximum DC current delivered to load) and short circuit current, SW_OUTx connect to ground tIOS Response time to short circuit (1) 8 1.05 VSW_IN = 5 V 1.2 2 1.35 A us Specified by design. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 TPS65280 www.ti.com SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULTx = 100 kΩ (unless otherwise noted) PARAMETER TEST CONDITIONS tDEGLITCH(OCP) Switch over current fault deglitch Fault assertion or de-assertion due to overcurrent condition VL_nFAULT nFAULTx pin output low voltage InFAULTx = 1 mA VEN_SWH EN_SWx high level input voltage EN_SW1, EN_SW2 VEN_SWL EN_SWx high level input voltage EN_SW1, EN_SW2 RDIS Discharge resistance VSW_IN = 5 V, EN_SW1/EN_SW2 = 0 V MIN TYP MAX 7 10 13 150 UNIT ms mV 2 V 0.4 100 V Ω THERMAL SHUTDOWN TTRIP_BUCK Thermal protection trip point THYST_BUCK Thermal protection hysteresis Rising temperature 160 20 50% 50% tD_on tr tD_off tf °C °C VEN_SWx 90% VOUT_SWx 10% 90% 10% Figure 1. Power Switches Test Circuit and Voltage Waveforms Figure 2. Response Time to Short Circuit Waveform Figure 3. Output Voltage vs Current Limit Threshold Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 9 TPS65280 SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULTx = 100 kΩ (unless otherwise noted) 10 Figure 4. Buck Start Up by EN Pin With Internal Soft-Start (SS Pin Open) Figure 5. Buck Start Up by EN Pin With an External 22-nF SS Capacitor Figure 6. Ramp VIN to Start Up Buck With an External 22-nF SS Capacitor Figure 7. Ramp VIN to Power Down With an External 22-nF SS Capacitor Figure 8. Buck Output Voltage Ripple (Chan3: VOUT, 10 mV/DIV; Chan4: IO, 2A/DIV; Time: 2 µs/DIV) Figure 9. Buck Output Load Transient Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 TPS65280 www.ti.com SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULTx = 100 kΩ (unless otherwise noted) Figure 10. Buck Load Regulation Figure 11. Buck Line Regulation Figure 12. Oscillator Frequency vs Rosc Voltage (Note that Select ROSC Resistance = VROSC x 100 kΩ for Desired Frequency) Figure 13. Buck Efficiency Figure 14. Buck Hiccup Response to Hard-Short Circuit Figure 15. Zoom In Buck Output Hard Short Response Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 11 TPS65280 SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULTx = 100 kΩ (unless otherwise noted) 12 Figure 16. Power Switch 1 Turn On Delay and Rise Time ROUT = 5 Ω, COUT = 22 µF Figure 17. Power Switch 1 Turn Off Delay and Fall Time ROUT = 5 Ω, COUT = 22 µF Figure 18. Power Switch 2 Turn On Delay and Rise Time ROUT = 5 Ω, COUT = 22 µF Figure 19. Power Switch 2 Turn Off Delay and Fall Time ROUT = 5 Ω, COUT = 22 µF Figure 20. Power Switch 1 Enable Into Short Circuit Figure 21. Power Switch 2 Enable Into Short Circuit Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 TPS65280 www.ti.com SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULTx = 100 kΩ (unless otherwise noted) Figure 22. Power Switch 1 No Load to Short-Circuit Transient Response Figure 23. Power Switch 2 No Load to Short-Circuit Transient Response Figure 24. . Power Switch Reponses Time (TIOS) to Output Hard Short Figure 25. Power Switch No Load to 1-Ω Transient Response Figure 26. Power Switch Reverse Voltage Protection Response Figure 27. Bode Plot VIN = 12 V, Vout_buck = 5 V/0.5 A, Isw1 = Isw2 = 0.8 A Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 13 TPS65280 SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULTx = 100 kΩ (unless otherwise noted) Figure 28. Loop Stability Bode Plot VIN = 12 V, Buck Loads 0.5 A, Power Switch 1 and 2 Have No Load 14 Submit Documentation Feedback Figure 29. Loop Stability Bode Plot VIN = 12 V, Buck Load 0.5 A, Power Switch 1 and 2 Load 0.8 A Each Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 TPS65280 www.ti.com SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 OVERVIEW TPS65280 PMIC integrates two independent current-limited, power distribution switches using N-channel MOSFETs for applications where short circuits or heavy capacitive loads will be encountered and provide up to 1-A of continuous load current. Additional device features include over temperature protection and reversevoltage protection. The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from the input voltage of power switches as low as 2.5 V and requires little supply current. The driver controls the gate voltage of the power switch. The driver incorporates circuitry that controls the rise and fall times of output voltage to limit large current and voltage surges and provides built-in soft-start functionality. TPS65280 device limits output current to a safe level when the output load exceeds the current limit threshold. After deglitching time, device latches off when the load exceeds the current limit threshold. The device asserts the nFAULT1/2 signal during the over current or reverse voltage faulty condition. TPS65280 PMIC also integrates a synchronous step-down converter with a fixed 5-V output voltage to provide the power for power switches in the USB ports. The synchronous buck converter incorporates an 80-mΩ high side power MOSFET and 50-mΩ low side power MOSFET to achieve high efficiency power conversion. The converter supports an input voltage range from 5.5 V to 18 V for a fixed 5-V output. The converter operates in continuous conduction mode with peak current mode control for simplified loop compensation. The switching clock frequency can be programmed from 300 kHz to 1.4 MHz from the ROSC pin connection. The peak inductor current limit threshold is internally set at 5 A. The soft-start time can be adjusted with connecting an external capacitor at the SS pin, or fixed at 1 ms with floating at the SS pin. POWER SWITCH DETAILED DESCRIPTION Over Current Condition The TPS65280 responds to over-current conditions on power switches by limiting the output currents to the IOCP_SW level, which is fixed internally. The load current is less than the current-limit threshold and the device does not limit current. During normal operation the N-channel MOSFET is fully enhanced, and VSW_OUT = VSW_IN - (ISW_OUT x Rdson_SW). The voltage drop across the MOSFET is relatively small compared to VSW_IN, and VSW_OUT ≈ VSW_IN. When an over current condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. During current-limit operation, the N-channel MOSFET is no longer fully enhanced and the resistance of the device increases. This allows the device to effectively regulate the current to the current-limit threshold. The effect of increasing the resistance of the MOSFET is that the voltage drop across the device is no longer negligible (VSW_IN ≠ VSW_OUT), and VSW_OUT decreases. The amount that VSW_OUT decreases is proportional to the magnitude of the overload condition. The expected VSW_OUT can be calculated by IOCP_SW × RLOAD, where IOCP_SW is the current-limit threshold and RLOAD is the magnitude of the overload condition. The manufacture trim options are available for the current limiting thresholds at 0.8 A, 1.2 A, 1.6 A and 2 A. Three possible overload conditions can occur as summarized in Table 1. Table 1. Possible Overload Conditions CONDITIONS BEHAVIORS Short circuit or partial short circuit present when the device is powered up or enabled The output voltage is held near zero potential with respect to ground and the TPS65280 ramps output current to IOCP_SW. The device limits the current to IOS until the overload condition is removed or the internal deglitch time (10 ms typical) is reached and the device is turned off. The device will remain off until power is cycled or the device enable is toggled. Gradually increasing load ( DIOUT 2 × L Vout × DVout (7) The selection of COUT is driven by the effective series resistance (ESR). Equation 8 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fSW is the switching frequency, ΔVOUT is the maximum allowable output voltage ripple, and ΔiL is the inductor ripple current. In this case, the maximum output voltage ripple is 50 mV (1% of regulated 5 V). From Equation 4, the output current ripple is 1 A. From Equation 8, the minimum output capacitance meeting the output voltage ripple requirement is 4.6 µF with 3-mΩ esr resistance. 1 1 Co > × 8 × fsw DVout - esr DiL (8) After considering both requirements, for this example, one 22 µF 6.3 V X7R ceramic capacitor with 3 mΩ of ESR will be used. Input Capacitor Selection A minimum 10 µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These capacitors should be connected as close as physically possible to the input pins of the converters, as they handle the RMS ripple current shown in Equation 9. For this example, IOUT = 2 A, VOUT = 5 V, minimum Vin_min = 9.6 V. Tthe input capacitors must support a ripple current of 1 A RMS. Iinrms = Iout × Vout (Vinmin - Vout ) × Vinmin Vinmin (9) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 21 TPS65280 SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 www.ti.com The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 10. Using the design example values, Iout_max = 2 A, CIN = 10 µF, fSW = 600 kHz, yields an input voltage ripple of 83 mV. I × 0.25 DVin = out max Cin × fsw (10) To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current must be used. Output Capacitor Selection The external bootstrap capacitor connected to the BST pins supply the gate drive voltages for the topside MOSFETs. The capacitor between BST pin and LX pin is charged through an internal diode from V7V when the LX pin is low. When high side MOSFETs are to be turned on, the driver places the bootstrap voltage across the gate-source of the desired MOSFET. This enhances the top MOSFET switch and turns it on. The switch node voltage, LX, rises to VIN and the BST pin follows. With the internal high side MOSFET on, the bootstrap voltage is above the input supply: VBST = VIN + V7V. The selection on bootstrap capacitance is related with internal high side power MOSFET gate capacitance. A 0.047-μF ceramic capacitor is recommended to be connected between the BST to LX pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or higher voltage rating. Loop Compensation The integrated buck DC/DC converter in TPS65280 incorporates a peak current mode. The error amplifier is a trans-conductance amplifier with a gain of 350 µA/V. A typical type II compensation circuit adequately delivers a phase margin between 60° and 90°. Cb adds a high frequency pole to attenuate high frequency noise when needed. To calculate the external compensation components, follow these steps: 1. Select switching frequency, fSW, that is appropriate for application depending on L and C sizes, output ripple and EMI. Switching frequency between 500 kHz and 1 MHz gives the best trade off between performance and cost. To optimize efficiency, a lower switching frequency is desired. 2. Set up cross over frequency, fc, which is typically between 1/5 and 1/20 of fSW. 3. RC can be determined by: 2p × fc × Vo × Co RC = gM × Vref × gmps (11) where gm is the error amplifier gain (350 µA/V) and gmps is the power stage voltage to current conversion gain (10 A/V). 1 fp = CO × RL × 2p . 4. Calculate CC by placing a compensation zero at or before the dominant pole, R × Co CC = L RC (12) 5. Optional Cb can be used to cancel the zero from the ESR associated with CO. Re sr × Co Cb = RC 22 Submit Documentation Feedback (13) Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 TPS65280 www.ti.com SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 SW _IN Buck Output : +5V iL R ESR RL Current Sense I/V Converter g mps = 10 A / V Co R1 C1 420 K 12 pF Vfb COMP EA g M = 350uS Rc Vref = 0. 8V R2 80 K Cb Cc Figure 32. DC/DC Loop Compensation Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 23 TPS65280 SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 www.ti.com APPLICATION INORMATION Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C. The thermal shutdown forces the buck converter to stop switching when the junction temperature exceeds thermal trip threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The thermal shutdown hysteresis is 20°C. Power Dissipation and Junction Temperature The total power dissipation inside TPS65280 should not exceed the maximum allowable junction temperature of 125°C. The maximum allowable power dissipation is a function of the thermal resistance of the package, θJA, and ambient temperature. The analysis below gives an approximation in calculating junction temperature based on the power dissipation in the package. However, it is important to note that thermal analysis is strongly dependent on additional system level factors. Such factors include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating power. Good thermal design practice must include all system level factors in addition to individual component analysis. To calculate the temperature inside the device under continuous load, use the following procedure. 1. Define the total continuous current through the buck converter (including the load current through power switches). Make sure the continuous current does not exceed the maximum load current requirement. 2. From the graphs below, determine the expected losses (Y axis) in Watts for the buck converter inside the device. The loss PD_BUCK depends on the input supply and the selected switching frequency. Please note, the data is measured in the provided evaluation board (EVM). 3. Determine the load current IOUT1 and IOUT2 through the power switches. Read RDS(on)1/2 of the power switch from the typical characteristics graph. 4. The power loss through power switches can be calculated by: PD_PW = RDS1(on) × IOUT1 + RDS2(on) × IOUT2 (14) 5. The Dissipating Rating Table provides the thermal resistance, θJA, for specific packages and board layouts. 6. The maximum temperature inside the IC can be calculated by: TJ = PD_BUCK + PD_PW × θJA + TA (15) Where: TA = Ambient temperature (°C) θJA = Thermal resistance (°C/W) PD_BUCK = Total power dissipation in buck converter (W) PD_PW = Total power dissipation in power switches (W) 24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 TPS65280 www.ti.com SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 Figure 33. Buck Loss vs Output Current (VIN = 9 V, 12 V and 15 V, fSW = 300 kHz) Figure 34. Buck Loss vs Output Current (VIN = 9 V, 12 V and 15 V, fSW = 600 kHz) Figure 35. Buck Loss vs Output Current (VIN = 9 V, 12 V and 15 V, fSW = 1 MHz) Figure 36. Buck Loss vs Output Current (VIN = 9 V, 12 V and 15 V, fSW = 1.4 MHz) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 25 TPS65280 SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 www.ti.com Auto-Retry Functionality Some applications require that an over-current condition disables the part momentarily during a fault condition and re-enables after a pre-set time. This auto-retry functionality can be implemented with an external resistor and capacitor shown in Figure 37. During a fault condition, nFAULT pulls low disabling the part. The part is disabled when EN is pulled low, and nFAULT goes high impedance allowing CRETRY to begin charging. The part reenables when the voltage on EN_SW reaches the turn-on threshold, and the auto-retry time is determined by the resistor/capacitor time constant. The part will continue to cycle in this manner until the fault condition is removed. L1 4.7uH C6 47nF 19 20 C1 10uF 21 VIN 4.5V~18V 22 14 13 PGND C7 22uF PGND USB Port 1 10 NC TPS65280 C8 10uF 11 AGND VIN USB Data 12 SW_OUT1 VIN RFAULT 2 100kΩ SW_IN LX FB SW_IN 15 16 LX BST 17 18 +5V RFAULT 1 100kΩ C9 10uF 9 SW_OUT2 USB Port 2 USB Data nFALUT1 V7V nFALUT2 8 EN_SW1 7 6 5 ROSC SS 2 1 EN COMP C2 1uF EN_SW2 MODE/SYNC 4 24 3 23 Enable C4 4.7nF Analog Ground R4 10kΩ CRETRY 1 0.1u CRETRY 2 0.1u Power Ground Figure 37. Auto Retry Functionality Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal. Figure 38 shows how an external logic signal can drive EN_SW through RFAULT and maintain auto-retry functionality. The resistor/capacitor time constant determines the auto-retry time-out period. L1 4.7uH C6 47nF +5V 13 SW_IN 14 SW_IN 15 FB LX 16 17 VIN SW_OUT2 nFALUT2 C8 10uF 11 C9 10uF 9 8 CRETRY 1 0.1u USB Port 2 USB Data 7 CRETRY 2 0.1u RFAULT 1 100kΩ Enable external logic signal & driver C4 4.7nF Analog Ground USB Port 1 10 6 1 EN C2 1uF USB Data 12 EN_SW1 nFALUT1 V7V EN_SW2 MODE/SYNC 5 24 TPS65280 ROSC 23 NC VIN 4 22 AGND PGND COMP VIN 4.5V~18V 21 SS C1 10uF 3 20 SW_OUT1 PGND 2 19 LX BST 18 C7 22uF R4 10kΩ RFAULT 2 100kΩ Power Ground Figure 38. Auto Retry Functionality With External Enable Signal 26 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 TPS65280 www.ti.com SLVSBE4A – JUNE 2012 – REVISED SEPTEMBER 2012 PCB Layout Recommendation When laying out the printed circuit board, the following guidelines should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 39. • There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. This capacitor provides the AC current into the internal power MOSFETs. Connect the (+) terminal of the input capacitor as close as possible to the VIN pin, and connect the (-) terminal of the input capacitor as close as possible to the PGND pin. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the power ground PGND connections. • Since the LX connection is the switching node, the output inductor should be located close to the LX pin, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. Keep the switching node, LX, away from all sensitive small-signal nodes. • Connect V7V decoupling capacitor (connected close to the IC), between the V7V and the power ground PGND pin. This capacitor carries the MOSFET drivers’ current peaks. • Place the output filter capacitor of the buck converter close to SW_IN pins and AGND pin. Try to minimize the ground conductor length while maintaining adequate width. • The AGND pin should be separately routed to the (-) terminal of V7V bypass capacitor to avoid switching grounding path. A ground plane is recommended connecting to this ground path. • The compensation should be as close as possible to the COMP pins. The COMP and ROSC pins are sensitive to noise so the components associated to these pins should be located as close as possible to the IC and routed with minimal lengths of trace. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of the power components. You can connect the copper areas to PGND, AGND, VIN or any other DC rail in your system. • There is no electric signal internal connected to thermal pad in the device. Nevertheless connect the exposed pad beneath the IC to ground. Always solder the thermal pad to the board, and have as many vias as possible on the PCB to enhance power dissipation. Figure 39. 2-Layers PCB Layout Recommendation Diagram Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS65280 27 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS65280RGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 65280 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of