TPS65282RGER

TPS65282 www.ti.com SLVSBU5 – MARCH 2013 DUAL POWER DISTRIBUTION SWITCHES WITH 4.5-V to 18-V INPUT VOLTAGE, 4-A OUTPUT CURRENT SYNCHRONOUS BUCK REGULATOR Check for Samples: TPS65282 FEATURES 1 INTEGRATED POWER DISTRIBUTION SWITCH • • • • • • • • • • • Operating Input Voltage Range: 2.5 V to 6.5 V Integrated Back-to-Back Power MOSFETs With 100-mΩ On-Resistance Adjustable Current Limit: 75 mA - 2.7 A (typical) ±6% Current-Limit Accuracy at 1.7 A (typical) Latch-Off Over Current Protection Versions Reverse Input-Output Voltage Protection Built-In Soft-Start 4-kV HBM and 200-V MM ESD Protection at Power Switch Output Pins xxx INTEGRATED BUCK DC/DC CONVERTER Wide Input Voltage Range: 4.5 V to 18 V Maximum Continuous 4-A Output Current Feedback Reference Voltage: 0.8 V ±1 % • • • • • • • • Adjustable 300-kHz to 1.4-MHz Switching Frequency Pulse Skipping Mode at Light Load Efficiency Adjustable Soft-Start and Tracking With Built-In 1.2-ms Internal Soft-Start Time Cycle-by-Cycle Current Limit Output Over-Voltage Protection Power Good Indicator Over Temperature Protection 24-Lead QFN (RGE) 4-mm x 4-mm Package APPLICATIONS • • • • • USB Ports and Hubs Digital TV Set-Top Boxes VOIP Phones Tablet PC DESCRIPTION The TPS65282 incorporates dual N-channel MOSFET power switches for USB power distribution systems that require dual power switches in a single package. It also integrates a buck monolithic converter. The device is intended to provide a total USB power distribution solution for digital TV, set-top boxes, tablet PC and VOIP phones etc applications, where precision current limiting is required or heavy capacitive loads or short circuits are encountered. Dual 100-mΩ independent power distribution switch limits the output current to a programmable current limit threshold between typical 75 mA and 2.7 A by using an external resistor. The current limit accuracy can be achieved as tight as ±6% at higher current limit setting. TPS65282 device limits output current to a safe level by using a constant current mode when output load exceeds the current limit threshold. After deglitching time, TPS65282 provides circuit breaker functionality by latching off the power switch during over-current or reversevoltage situations. Two back-to-back power MOSFETs prevents the current injects from output to input in shutdown. An internal reverse-voltage comparator disables the power switch when the output voltage is driven higher than the input to protect the circuits on the input side of the switch in normal operation. The nFAULT1/2 output asserts low during over-current and reverse-voltage conditions. The buck DC/DC converter integrates power MOSFETs for optimized power efficiency and reduced external component. A wide 4.5-V to 18-V input supply range to buck encompasses most intermediate bus voltages operating off 5-V, 9-V, 12-V or 15-V power bus. Peak current mode control simplifies the compensation and fast transient response. Equipped with enable and soft-start pin, the DC/DC can be precisely sequenced and ramp up in order to align with other rails in the system. Cycle-by-cycle over-current protection and operating in hiccup mode limit MOSFET power dissipation during buck output short circuit or over loading fault conditions. The switching frequency of the converter can be programmed from 300 kHz to 1.4 MHz with an external resistor at ROSC pin. With ROSC pin connecting to V7V pin, floating, or grounding, a default fixed switching frequency can be selected. The buck also features a pulse skipping mode (PSM), which allows a power loss reduction on the input power supplied to the system to achieve high efficiency at light loading. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS65282 SLVSBU5 – MARCH 2013 www.ti.com The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C. The thermal shutdown forces the device to stop operating when the junction temperature exceeds thermal trip threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The thermal shutdown hysteresis is 20°C. The TPS65282 is available in a 24-lead thermally enhanced QFN (RGE) 4-mm X 4-mm thin package. ORDERING INFORMATION (1) TA –40°C to 125°C (1) (2) 2 PACKAGE (2) 24-Pin QFN (RGE) ORDERABLE PART NUMBER Reel 3000 TPS65282REGR Reel 250 TPS65282RGET TOP-SIDE MARKING TPS65282 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 TPS65282 www.ti.com SLVSBU5 – MARCH 2013 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TYPICAL APPLICATION C6 47nF L1 4.7uH +5V C7 22uF 13 R4 7.68kΩ SW_IN 14 SW_IN FB 16 LX LX BST 15 17 18 R3 40.2kΩ R2 100kΩ R1 100kΩ USB Data 19 20 C1 10uF VIN 6V-18V 21 22 PGND SW_OUT1 PGND AGND VIN RLIM TPS65282 VIN SW_OUT2 12 USB Port 1 C8 10uF 11 10 C9 10uF 9 USB Data nFALUT2 7 USB1 fault signal USB2 fault signal 6 5 COMP EN 1 2 8 EN_SW1 V7V C2 1uF EN_SW2 nFALUT1 ROSC PGOOD SS 24 4 23 3 V7V USB Port 2 Enable USB1 control signal C4 4.7nF USB2 control signal R4 10kΩ Analog Ground Power Ground Figure 1. 12-V Power Bus C6 47nF L1 4.7uH +2.5V C7 22uF R3 40.2kΩ 13 SW_IN SW_IN 14 15 FB LX 16 17 LX BST 18 VIN=5V R1 100kΩ R4 18.9kΩ R2 100kΩ USB Data 19 20 C1 10uF VIN=5V 21 22 SW_OUT1 PGND AGND PGND RLIM VIN TPS65282 VIN SW_OUT2 12 11 C8 10uF USB Port 1 10 9 C9 10uF USB Port 2 USB Data 8 EN_SW1 7 USB1 fault signal USB2 fault signal 6 5 4 EN 1 Enable EN_SW2 nFALUT2 ROSC V7V C2 1uF SS nFALUT1 COMP 24 PGOOD 3 23 2 V7V USB1 control signal C4 4.7nF USB2 control signal R4 10kΩ Analog Ground Power Ground Figure 2. 5-V Power Bus Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 3 TPS65282 SLVSBU5 – MARCH 2013 www.ti.com FUNCTION BLOCK DIAGRAM V7V BUCK 24 21 LDO 5V 22 Voltage Reference Current Bias Preregulator VIN VIN HS current sensing 1.25 M CS 18 1.25 M EN COMP FB BST 1 enable buffer HS driver 2 17 Current Sensing (0.1V/ A) Buck Controller 15 16 PWM comparator V7V slope comp LX LX LS driver 0.8V SS 3 error amplifer CS 5V LS current sensing 1ms Internal Soft Start ROSC 4 Oscillotor PGND 11uA 20 0. 86V 23 0.74V EN_SW2 19 PGND PGOOD enable buffer 5 10ms Degl . Time 1.25M Driver 7 Current Limit Charge Pump 4ms Degl. Time current sensing 9 CS reverse voltage comparator SW_IN SW_IN nFAULT 2 POWER SWITCH2 1.25M 11 14 SW_OUT2 AGND UVLO POR 13 10 RLIM reverse voltage comparator 12 CS SW_OUT1 current sensing Charge Pump 4ms Degl. Time 1.25M Driver 8 Current Limit nFAULT 1 1.25 M EN_SW1 6 10ms Degl . Time enable buffer POWER SWITCH1 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 TPS65282 www.ti.com SLVSBU5 – MARCH 2013 PIN OUT RGE PACKAGE (TOP VIEW) BST LX LX FB SW_IN SW_IN 18 17 16 15 14 13 PGND 19 12 SW_OUT1 PGND 20 11 AGND VIN 21 10 RLIM Thermal Pad VIN 22 9 SW_OUT2 1 2 3 4 5 6 ROSC EN_SW2 EN_SW1 7 nFAULT2 SS V7V 24 COMP 8 nFAULT1 EN PGOOD 23 There is no electric signal down boned to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 5 TPS65282 SLVSBU5 – MARCH 2013 www.ti.com TERMINAL FUNCTIONS NAME NO. DESCRIPTION EN 1 Enable for buck converter. Logic high enables buck converter and bias supply to power switches. Forcing the pin below 0.4 V shuts down the entire device, reducing the quiescent current to approximately 7 µA. There is a 1.25-MΩ pull-up resistor connecting this pin to internal 5-V power rail. Not recommend floating this pin. The device can be automatically started up with connecting EN pin to VIN though a 10-kΩ resistor or connecting a capacitor to program the delay of enabling the device. COMP 2 Error amplifier output and Loop compensation pin for buck. Connect a series resistor and capacitor to compensate the control loop of buck converter with peak current PWM mode. SS 3 Soft-Start and tracking input for buck converter. An internal 5-µA pull-up current source is connected to this pin. An external soft-start can be programmed by connecting a capacitor between this pin and ground. Leave the pin floating to have a default 1-ms of soft-start time. This pin allows the start-up of buck output to track an external voltage using an external resistor divider at this pin. ROSC 4 Oscillator clock frequency control pin. Connect the pin to ground for a fixed 300-kHz switching frequency. Connect the pin to V7V or float the pin for a fixed 600-kHz switching frequency. Other switch frequencies between 300 kHz and 1.4 MHz can be programmed using a resistor connected from this pin to ground. An internal 11-µA pull-up current develops a voltage to be used in oscillator. Directly adjusting the ROSC pin voltage can linearly adjust switching frequency. EN_SW2 5 Enable power switch 2. Logic high turns on power switch. Forcing the pin below 0.4 V shuts down power switch. Not recommend floating this pin, though there is a 1.25-MΩ pull-up resistor connecting this pin. EN_SW1 6 Enable power switch 1. Logic high turns on power switch. Forcing the pin below 0.4 V shuts down power switch. Not recommend floating this pin, though there is a 1.25-MΩ pull-up resistor connecting this pin. nFAULT2 7 Active low open drain output, asserted during over-current or reverse-voltage condition of power switch 2. nFAULT1 8 Active low open drain output, asserted during over-current or reverse-voltage condition of power switch 1. SW_OUT2 9 Power switch 2 output. RLIM 10 Power switch current limit control pin. An external resistor used to set current limit threshold of power switch. Recommended 9.1 kΩ ≤ RLIM ≤ 232 kΩ. AGND 11 Analog ground common to buck controller and power switch controller. 12 Power switch 1 output. SW_OUT1 SW_IN 13,14 FB 15 LX 16,17 BST 18 Power switch input voltage. Connect to buck output, or other power supply input. Feedback sensing pin for buck output voltage. Connect this pin to the resistor divider of buck output. The feedback reference voltage is 0.8 V ±1%. Switching node connection to the inductor and bootstrap capacitor for buck converter. This pin voltage swings from a diode voltage below the ground up to VIN voltage. Bootstrapped supply to the high side floating gate driver in buck converter. Connect a capacitor (recommend 47 nF) from this pin to LX. PGND 19,20 Power ground connection. Connect this pin as close as practical to the (-) terminal of input ceramic capacitor. VIN 21,22 Input power supply for buck. Connect this pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10 µF). PGOOD 23 Power good. This pin is active high, Open drain output that indicates if the regulator output voltage is within regulation. V7V 24 Internal low-drop linear regulator (LDO) output. The internal driver and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum 1-µF ceramic capacitor. The output voltage level of LDO is regulated to typical 6.3 V for optimal conduction on-resistances of internal power MOSFETs. In PCB design, the power ground and analog ground should have one-point common connection at the (-) terminal of V7V bypass capacitor. Power PAD 6 Exposed pad beneath the IC. Connect to the ground. Always solder power pad to the board, and have as many thermal vias as possible on the PCB to enhance power dissipation. There is no ground or any other electric signal downbonded to the pad inside the IC package. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 TPS65282 www.ti.com SLVSBU5 – MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VIN –0.3 to 20 V LX (Maximum withstand voltage transient < 20ns) –1.0 to 20 V BST referenced to LX pin –0.3 to 7 V SW_IN, SW_OUT1, SW_OUT2 –0.3 to 7 V EN, EN_SW1, EN_SW2, nFAULT1, nFAULT2, V7V, ROSC, PGOOD, RLIM –0.3 to 7 V SS, COMP –0.3 to 3.6 V AGND, PGND –0.3 to 0.3 V TJ Operating virtual junction temperature range –40 to 125 °C TSTG Storage temperature range –55 to 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input operating voltage 4.5 18 V TA Ambient temperature –40 125 °C ELECTROSTATIC DISCHARGE (ESD) PROTECTION (1) MIN Human body model (HBM) Charge device model (CDM) (1) MAX UNIT 2000 V 500 V SW_OUT1/2 pins’ human body model (HBM) ESD protection rating 4 kV, and machine model (MM) rating 200V. THERMAL INFORMATION TPS65282 THERMAL METRIC (1) RGE UNITS 24 PINS Junction-to-ambient thermal resistance (2) θJA 38.1 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 16.9 ψJT Junction-to-top characterization parameter (5) 0.9 ψJB Junction-to-board characterization parameter (6) θJCbot (1) (2) (3) (4) (5) (6) (7) Junction-to-case (bottom) thermal resistance 45.3 (7) °C/W 16.9 6.2 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 7 TPS65282 SLVSBU5 – MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input voltage range IDDSDN Shutdown supply current EN = EN_SW1 = EN_SW2 = low 4.5 IDDQ_NSW Switching quiescent current with no load at DCDC output EN = high, EN_SWx = low With Buck switching UVLO VIN under voltage lockout 7 V 20 µA 0.5 mA Rising VIN 4 4.25 4.50 Falling VIN 3.75 4 4.25 V 6.45 V 1400 kHz Hysteresis V7V 18 0.25 Internal biasing supply V7V load current = 0 A, VIN = 12 V 6.15 Switching frequency range Set by external resistor ROSC 300 6.3 OSCILLATOR fSW_BK fSW Programmable frequency ROSC = 51 kΩ 560 ROSC = 130 kΩ 1400 ROSC floating or connected to V7V 510 600 690 ROSC connected to ground 225 300 345 VCOMP = 1.2 V, TJ = 25°C 0.792 0.8 0.808 VCOMP = 1.2 V, TJ = -40°C to 125°C 0.784 0.8 0.816 kHz BUCK CONVERTER VFB Feedback voltage VLINEREG Line regulation - DC IOUT = 2 A 0.5 %/V VLOADREG Load regulation - DC IOUT = (10% - 90%)IOUT_max 0.5 %/A Gm_EA Error amplifier trans-conductance -2 µA < ICOMP < 2 µA 600 µs Gm_SRC COMP voltage to inductor current Gm (1) ILX = 0.5 A 36 A/V VENH EN high level input voltage VENL EN low level input voltage 0.98 ISS Soft-start charging current 5 µA tSS_INT Internal soft-start time 1.2 ms ILIMIT Buck peak inductor current limit Rdson_HS On resistance of high side FET in buck V7V = 6.2.5 V including banding wire Rdson_LS On resistance of low side FET in buck VIN = 12 V including banding wire 2 SS pin floats 1.24 V V 0.4 V 5.2 A 100 mΩ 60 mΩ POWER GOOD RESET GENERATOR Output falling 91.6 Output rising (PG will be asserted) 94.4 VUVBUCK Threshold voltage for buck under voltage VOVBUCK Threshold voltage for buck over voltage TD-L PGOOD H-L delay time Change FB from 0.8 V to 1 V, Measure the delay from FB = 1 V to PGOOD low 100 µs TD-H PGOOD L-H delay time Change FB from 1 V to 0.8 V, Measure the delay from FB = 0.8 V to PGOOD high 130 µs VPGOOD PGOOD pin output low voltage Force FB = 1 V to create fault condition, Sink 1-mA current to PGOOD pin, Measure the PGOOD pin voltage 100 300 Output rising (high side FET will be forced off) 105.4 Output falling (high side FET will be allowed to switch) 104.2 % % mV POWER DISTRIBUTION SWITCH VSW_IN Power switch input voltage range VUVLO_SW Input under-voltage lock out 6 V VSW_IN rising 2.15 2.5 2.25 2.35 V VSW_IN falling 2.05 2.15 2.25 Hysteresis (1) 8 100 V mV Specified by design. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 TPS65282 www.ti.com SLVSBU5 – MARCH 2013 ELECTRICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted) PARAMETER RDSON_SW TEST CONDITIONS Power switch NDMOS on-resistance MIN TYP VSW_INx = 5 V, ISW_OUT = 0.5 A, TJ = 25°C, including bond wire resistance 100 VSW_INx = 2.5 V, ISW_OUT = 0.5 A, TJ = 25°C, includes bond wire resistance 100 MAX UNIT mΩ tD_on Turn-on delay time from EN_SW turns high 0.66 1.5 ms tD_off Turn-off delay time from EN_SW turns low 1.6 2 ms tr Output rise time 1.1 1.5 ms tf Output fall time 1.2 1.5 ms IOS Current limit threshold (maximum DC current delivered to load) and short circuit current, SW_OUT connect to ground VSW_IN = 5 V, CL = 1 µF, RL = 100 Ω (see Figure 3) RLIM = 15 kΩ 1.57 1.68 1.79 RLIM = 20 kΩ 1.18 1.26 1.34 RLIM = 51 kΩ 0.47 0.5 0.53 tIOS Response time to short circuit VSW_IN = 5 V 2 tDEGLITCH(OCP) Switch over current fault deglitch Fault assertion or de-assertion due to overcurrent condition VL_nFAULT nFAULTx pin output low voltage InFAULTx = 1 mA VEN_SWH EN_SW high level input voltage EN_SWx high level input voltage VEN_SWL EN_SW high level input voltage EN_SWx low level input voltage 0.97 RDIS Discharge resistance VSW_IN = 5 V, EN_SWx = 0 V 160 A us 7 10 13 ms 150 300 mV 2 1.29 V 0.4 V Ω THERMAL SHUTDOWN TTRIP_BUCK Thermal protection trip point THYST_BUCK Thermal protection hysteresis Rising temperature 160 20 50% 50% tD_on tr tD_off tf °C °C VEN_SWx 90% VOUT_SWx 10% 90% 10% Figure 3. Power Switches Test Circuit and Voltage Waveforms Figure 4. Response Time to Short Circuit Waveform Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 9 TPS65282 SLVSBU5 – MARCH 2013 www.ti.com Figure 5. Output Voltage vs Current Limit Threshold 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 TPS65282 www.ti.com SLVSBU5 – MARCH 2013 TYPICAL CHARACTERISTICS TJ = 25°C, VIN = 12 V, VOUT = 5 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted) Figure 6. Buck Efficiency at VOUT = 5 V Figure 7. Buck Efficiency at VOUT = 2.5 V Figure 8. Buck Line Regulation at VOUT = 5 V Figure 9. Buck Line Regulation at VOUT = 2.5 V Figure 10. Buck Load Regulation at VOUT = 5 V Figure 11. Buck Load Regulation at VOUT = 2.5 V Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 11 TPS65282 SLVSBU5 – MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V, VOUT = 5 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted) Vin Vin Vout Vout EN EN SS SS Figure 12. Buck Start Up by EN Pin With External 22-nF SS Capacitor Figure 13. Buck Start Up by EN Pin With Internal SoftStart (SS Pin Open) Vin Vin Vout Vout EN EN SS SS Figure 14. Ramp VIN to Start Up Buck With External 22-nF SS Capacitor Figure 15. Ramp VIN to Power Down Buck With External 22-nF SS Capacitor Vout Vout LX LX IL IL Figure 16. Buck Output Voltage Ripple IOUT = 0.1 A 12 Figure 17. Buck Output Voltage Ripple IOUT = 4 A Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 TPS65282 www.ti.com SLVSBU5 – MARCH 2013 TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V, VOUT = 5 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted) Vout Vout Iout Iout Figure 18. Buck Output Load Transient IOUT = 0 A - 1 A Figure 19. Buck Output Load Transient IOUT = 1 A - 3 A Vout Vout LX LX Iout Iout Figure 20. Buck Hiccup Response to Hard-Short Circuit Figure 21. Zoom in Buck Output Hard-Short Response Vin Vout Vout LX PGOOD PGOOD Figure 22. Power Up and PGOOD, No Load Figure 23. Over Current and PGOOD Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 13 TPS65282 SLVSBU5 – MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V, VOUT = 5 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted) Vsw_in1 Vsw_in2 Vsw_out1 Vsw_out2 EN_sw1 EN_sw2 nFAULT1 nFAULT2 Figure 24. Power Switch1 Turn On Delay and Rise Time Vsw_in1 Vsw_in2 Vsw_out1 Vsw_out2 EN_sw1 EN_sw2 nFAULT1 nFAULT2 Figure 26. Power Switch1 Turn Off Delay and Fall Time ROUT = 5 Ω, COUT = 22 µF Figure 27. Power Switch2 Turn Off Delay and Fall Time ROUT = 5 Ω, COUT = 22 µF Vsw_in1 Vsw_in2 Vsw_out1 Vsw_out2 nFAULT1 nFAULT2 Isw_out1 Isw_out2 Figure 28. Power Switch1 Enable Into Short Circuit 14 Figure 25. Power Switch2 Turn On Delay and Rise Time Figure 29. Power Switch2 Enable Into Short Circuit Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 TPS65282 www.ti.com SLVSBU5 – MARCH 2013 TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VIN = 12 V, VOUT = 5 V, fSW = 600 kHz, RnFAULT = 100 kΩ (unless otherwise noted) Vsw_in1 Vsw_in2 Vsw_out1 Vsw_out2 nFAULT1 nFAULT2 Isw_out1 Isw_out2 Figure 30. Power Switch1 Current Limit Operation Figure 31. Power Switch2 Current Limit Operation Vsw_in2 Vsw_in1 Vsw_out2 Vsw_out1 EN_sw1 EN_sw2 nFAULT1 nFAULT2 Figure 32. Power Switch1 Reverse Voltage Protection Response Figure 33. Power Switch2 Reverse Voltage Protection Response Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 15 TPS65282 SLVSBU5 – MARCH 2013 www.ti.com OVERVIEW TPS65282 PMIC integrates a current-limited, power distribution switch using N-channel MOSFETs for applications where short circuits or heavy capacitive loads will be encountered and provide a precision current limit protection. Additional device features include over termperature protection and reverse-voltage protection. The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to the driver circuit and provide the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltage of power switch as low as 2.5 V and requires little supply current. The driver incorporates circuitry that controls the rise and fall times of output voltage to limit large current and voltage surges and provides built-in soft-start functionality. TPS65282 device limits output current to a safe level by using a constant current mode when the output load exceeds the current limit threshold. TPS65282 device lacthes off when the load exceeds the current limit threshold. The device asserts the nFAULT signal during over current or reverse voltage faulty condition. TPS65282 PMIC also integrates a synchronous step-down converter with regulated 0.8-V ±1% feedback reference voltage. The synchronous buck converter incorporates 100-mΩ high side power MOSFET and 60-mΩ low side power MOSFET to achieve high efficiency power conversion. The converter supports input voltage range from 4.5 V to 18 V for a fixed 5-V output. The converter operates in continuous conduction mode with peak current mode control for simplified loop compensation. The switching clock frequency can be programmed from 300 kHz to 1.4 MHz from ROSC pin connection. The peak inductor current limit threshold is internally set at 5.2 A. The soft-start time can be adjusted with connecting an external capacitor at SS pin, or fixed at 1.2 ms with floating at SS pin. POWER SWITCH DETAILED DESCRIPTION Over Current Condition The TPS65282 responds to over-current conditions on power switches by limiting the output currents to the IOCP_SW level. The load current is less than the current-limit threshold and the device does not limit current. During normal operation the N-channel MOSFET is fully enhanced, and VSW_OUT = VSW_IN - (ISW_OUT x Rdson_SW). The voltage drop across the MOSFET is relatively small compared to VSW_IN, and VSW_OUT ≈ VSW_IN. When an over current condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. During current-limit operation, the N-channel MOSFET is no longer fully enhanced and the resistance of the device increases. This allows the device to effectively regulate the current to the current-limit threshold. The effect of increasing the resistance of the MOSFET is that the voltage drop across the device is no longer negligible (VSW_IN ≠ VSW_OUT), and VSW_OUT decreases. The amount that VSW_OUT decreases is proportional to the magnitude of the overload condition. The expected VSW_OUT can be calculated by IOS × RLOAD, where IOS is the current-limit threshold and RLOAD is the magnitude of the overload condition. Three possible overload conditions can occur as summarized in Table 1. Table 1. Possible Overload Conditions CONDITIONS BEHAVIORS Short circuit or partial short circuit present when the device is powered up or enabled The output voltage is held near zero potential with respect to ground and the TPS65282 ramps output current to IOCP_SW. The TPS65282 limits the current to IOS until the overload condition is removed or the internal deglitch time (10 ms typical) is reached and the device is turned off. The device will remain off until power is cycled or the device enable is toggled. Gradually increasing load ( DIOUT 2 × L Vout × DVout (9) The selection of COUT is driven by the effective series resistance (ESR). Equation 10 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fSW is the switching frequency, ΔVOUT is the maximum allowable output voltage ripple, and ΔiL is the inductor ripple current. In this case, the maximum output voltage ripple is 50 mV (1% of regulated 5 V). From Equation 6, the output current ripple is 1 A. From Equation 10, the minimum output capacitance meeting the output voltage ripple requirement is 4.6 µF with 3-mΩ esr resistance. 1 1 Co > × 8 × fsw DVout - esr DiL (10) After considering both requirements, for this example, one 22 µF 6.3 V X7R ceramic capacitor with 3 mΩ of ESR will be used. 24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 TPS65282 www.ti.com SLVSBU5 – MARCH 2013 Input Capacitor Selection A minimum 10 µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These capacitors should be connected as close as physically possible to the input pins of the converters, as they handle the RMS ripple current shown in Equation 11. For this example, IOUT = 3 A, VOUT = 5 V, minimum Vin_min = 9.6 V. Tthe input capacitors must support a ripple current of 1 A RMS. Iinrms = Iout × Vout (Vinmin - Vout ) × Vinmin Vinmin (11) The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 12. Using the design example values, Iout_max = 3 A, CIN = 10 µF, fSW = 600 kHz, yields an input voltage ripple of 125 mV. I × 0.25 DVin = out max Cin × fsw (12) To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current must be used. Bootstrap Capacitor Selection The external bootstrap capacitor connected to the BST pins supply the gate drive voltages for the topside MOSFETs. The capacitor between BST pin and LX pin is charged through an internal diode from V7V when the LX pin is low. When high side MOSFETs are to be turned on, the driver places the bootstrap voltage across the gate-source of the desired MOSFET. This enhances the top MOSFET switch and turns it on. The switch node voltage, LX, rises to VIN and the BST pin follows. With the internal high side MOSFET on, the bootstrap voltage is above the input supply: VBST = VIN + V7V. The selection on bootstrap capacitance is related with internal high side power MOSFET gate capacitance. A 0.047-μF ceramic capacitor is recommended to be connected between the BST to LX pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or higher voltage rating. Loop Compensation The integrated buck DC/DC converter in TPS65282 incorporates a peak current mode. The error amplifier is a trans-conductance amplifier with a gain of 600 µA/V. A typical type II compensation circuit adequately delivers a phase margin between 60° and 90°. Cb adds a high frequency pole to attenuate high frequency noise when needed. To calculate the external compensation components, follow these steps: 1. Select switching frequency, fSW, that is appropriate for application depending on L and C sizes, output ripple and EMI. Switching frequency between 500 kHz and 1 MHz gives the best trade off between performance and cost. To optimize efficiency, a lower switching frequency is desired. 2. Set up cross over frequency, fc, which is typically between 1/5 and 1/20 of fSW. 3. RC can be determined by: 2p × fc × Vo × Co RC = gM × Vref × gmps (13) where gm is the error amplifier gain (600 µA/V) and gmps is the power stage voltage to current conversion gain (36 A/V). 1 fp = CO × RL × 2p . 4. Calculate CC by placing a compensation zero at or before the dominant pole, R × Co CC = L RC (14) 5. Optional Cb can be used to cancel the zero from the ESR associated with CO. Re sr × Co Cb = RC Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 (15) 25 TPS65282 SLVSBU5 – MARCH 2013 www.ti.com SW _IN Buck Output : +5V iL R ESR RL Current Sense I/V Converter gmps = 36 A / V Co R1 40.2 kW C1 300 pF Vfb COMP EA g M = 600µs Rc Vref = 0. 8V R2 7.7 kW Cb Cc Figure 39. DC/DC Loop Compensation 26 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 TPS65282 www.ti.com SLVSBU5 – MARCH 2013 APPLICATION INORMATION Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C. The thermal shutdown forces the buck converter to stop switching when the junction temperature exceeds thermal trip threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The thermal shutdown hysteresis is 20°C. Power Dissipation and Junction Temperature The total power dissipation inside TPS65282 should not exceed the maximum allowable junction temperature of 125°C. The maximum allowable power dissipation is a function of the thermal resistance of the package, θJA, and ambient temperature. The analysis below gives an approximation in calculating junction temperature based on the power dissipation in the package. However, it is important to note that thermal analysis is strongly dependent on additional system level factors. Such factors include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating power. Good thermal design practice must include all system level factors in addition to individual component analysis. To calculate the temperature inside the device under continuous load, use the following procedure. 1. Define the total continuous current through the buck converter (including the load current through power switches). Make sure the continuous current does not exceed the maximum load current requirement. 2. From the graphs below, determine the expected losses (Y axis) in Watts for the buck converter inside the device. The loss PD_BUCK depends on the input supply and the selected switching frequency. Please note, the data is measured in the provided evaluation board (EVM). 3. Determine the load current IOUT through the power switch. Read RDS(on) of the power switch from the Electrical Characteristics table. 4. The power loss through power switches can be calculated by: PD_PW = RDS1(on) × IOUT1 + RDS2(on) x IOUT2 (16) 5. The Dissipating Rating Table provides the thermal resistance, θJA, for specific packages and board layouts. 6. The maximum temperature inside the IC can be calculated by: TJ = PD_BUCK + PD_PW × θJA + TA (17) Where: TA = Ambient temperature (°C) θJA = Thermal resistance (°C/W) PD_BUCK = Total power dissipation in buck converter (W) PD_PW = Total power dissipation in power switches (W) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 27 TPS65282 SLVSBU5 – MARCH 2013 www.ti.com Auto-Retry Functionality Some applications require that an over-current condition disables the part momentarily during a fault condition and re-enables after a pre-set time. This auto-retry functionality can be implemented with an external resistor and capacitor shown in Figure 40. During a fault condition, nFAULT pulls low disabling the part. The part is disabled when EN is pulled low, and nFAULT goes high impedance allowing CRETRY to begin charging. The part reenables when the voltage on EN_SW reaches the turn-on threshold, and the auto-retry time is determined by the resistor/capacitor time constant. The part will continue to cycle in this manner until the fault condition is removed. C6 47nF L1 4.7uH +5V C7 22uF R3 40.2kΩ 19 C1 10uF SW_IN 13 14 SW_IN 16 15 LX FB PGND 20 R1 100kΩ SW_OUT1 PGND 21 VIN 6V-18V LX BST 17 18 R4 7.68kΩ AGND VIN 22 RLIM TPS65282 VIN SW_OUT2 R2 100kΩ USB Data 12 USB Port 1 C8 10uF 11 10 C9 10uF 9 USB Port 2 USB Data nFALUT2 5 7 6 SS EN COMP 1 2 8 EN_SW1 V7V C2 1uF EN_SW2 nFALUT1 ROSC 24 PGOOD 3 23 4 V7V Enable C4 4.7nF R4 10kΩ Analog Ground CRETRY1 0.1uF CRETRY2 0.1uF Power Ground Figure 40. Auto Retry Functionality Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal. Figure 41 shows how an external logic signal can drive EN_SW through RFAULT and maintain auto-retry functionality. The resistor/capacitor time constant determines the auto-retry time-out period. L1 4.7uH C6 47nF +5V C7 22uF R3 40.2kΩ SW_IN 13 14 SW_IN 15 16 LX FB LX BST 17 18 R4 7.68kΩ USB Data SW_OUT2 nFALUT1 V7V nFALUT2 2 1 EN C2 1uF EN_SW1 PGOOD EN_SW2 24 RLIM TPS65282 VIN 5 23 VIN 12 10 C9 10uF 9 8 CRETRY1 0.1uF USB Port 2 USB Data 7 CRETRY2 0.1uF Enable C4 4.7nF Analog Ground USB Port 1 C8 10uF 11 6 V7V AGND SS 22 PGND ROSC 21 SW_OUT1 3 C1 10uF VIN 6V-18V PGND 4 20 COMP 19 external logic signal & driver external logic signal & driver R4 10kΩ Power Ground Figure 41. Auto Retry Functionality With External Enable Signal 28 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 TPS65282 www.ti.com SLVSBU5 – MARCH 2013 PCB Layout Recommendation When laying out the printed circuit board, the following guidelines should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 42. • There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. This capacitor provides the AC current into the internal power MOSFETs. Connect the (+) terminal of the input capacitor as close as possible to the VIN pin, and connect the (-) terminal of the input capacitor as close as possible to the PGND pin. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the power ground PGND connections. • Since the LX connection is the switching node, the output inductor should be located close to the LX pin, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. Keep the switching node, LX, away from all sensitive small-signal nodes. • Connect V7V decoupling capacitor (connected close to the IC), between the V7V and the power ground PGND pin. This capacitor carries the MOSFET drivers’ current peaks. • Place the output filter capacitor of the buck converter close to SW_IN pins and AGND pin. Try to minimize the ground conductor length while maintaining adequate width. • The AGND pin should be separately routed to the (-) terminal of V7V bypass capacitor to avoid switching grounding path. A ground plane is recommended connecting to this ground path. • The compensation should be as close as possible to the COMP pins. The COMP and ROSC pins are sensitive to noise so the components associated to these pins should be located as close as possible to the IC and routed with minimal lengths of trace. • Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of the power components. You can connect the copper areas to PGND, AGND, VIN or any other DC rail in your system. • There is no electric signal internal connected to thermal pad in the device. Nevertheless connect the exposed pad beneath the IC to ground. Always solder the thermal pad to the board, and have as many vias as possible on the PCB to enhance power dissipation. Top Side Ground Area VOUT_BUCK output inductor boot capacitor PGND SW_IN SW_IN FB LX LX BST PGND output capacitor VOUT1 SW_OUT1 AGND AGND PGND Input bypass capacitor VIN power switch output capacitor RLIM VIN VIN VOUT2 SW_OUT2 PGOOD nFAULT 1 nFAULT 2 EN_SW1 ROSC SS COMP EN EN_SW2 nFAULT 1 V7V nFAULT 2 EN1 EN2 Top Side Analog Ground Area Thermal VIA Signal VIA Figure 42. 2-Layers PCB Layout Recommendation Diagram Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65282 29 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS65282RGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 65282 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of