TPS65283RGET

Order Now Product Folder Support & Community Tools & Software Technical Documents TPS65283, TPS65283-1 ZHCSCO8E – JUNE 2014 – REVISED MAY 2019 具有配电开关的 TPS65283/TPS65283-1 4.5V 至 18V 输入电压、最大电流 为 3.5A 和 2.5-A 的同步双路降压转换器 1 特性 2 应用 降压转换器 – 4.5V 至 18V 宽输入电压范围 – 集成双路降压转换器，最大持续电流为 3.5A (Buck1)/2.5A (Buck2) – 反馈基准电压为 0.6V ±1% – 可调节开关频率范围：200kHz 至 2MHz – 内置软启动时间 2.4ms – 外部时钟同步 – 逐周期电流限制 – 适用于每种降压模式的电源正常状态指示器 – 在轻负载条件下以持续电流模式 (TPS65283) 或 脉冲跳跃模式 (PSM) (TPS65283-1) 运行 配电开关 – 集成导通电阻为 60mΩ 的配电开关 – 工作输入电压范围为 2.4V 至 6V – 可调电流限制高达 2.7A – 在 1.25A（典型值）时电流限制精度为 ±10% – 自动恢复过流保护 – 反向输入至输出电压保护 – 过热保护 – 24 引脚 VQFN (RGE) 4mm × 4mm 封装 • 1 • • • • • • • USB 端口和集线器 机顶盒 数字电视 DSL/电缆调制解调器，无线路由器 家庭网关和接入点网络 汽车信息娱乐系统 3 说明 TPS65283/-1 采用耐热增强型 4mm × 4mm VQFN 封 装，是一款功能全面的 4.5V 至 18V 输入电压 Vin、3.5A/2.5A 输出电流同步 降压直流到直流 (DC-DC) 转换器，通过高效率和集成 的高侧和低侧金属氧化物半导体场效应晶体管 (MOSFET) 对小型设计进行了优化。该器件还整合了 一个适用于配电系统的 N 通道 MOSFET 电源开关。 此器件提供一个总体配电解决方案，适用于需要精密限 流和快速保护响应的情况。 器件信息(1) 器件型号 TPS65283 TPS65283-1 封装 封装尺寸（标称值） VQFN (24) 4.00mm x 4.00mm (1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附 录。 效率，Vin = 12V， ，PSM 4 典型电路原理图 100% TPS65283 TPS65283-1 90% 80% 18 19 20 Vout1 21 22 VIN 23 DVCC 24 PGOOD1 PGOOD2 1 2 3 FB1 COMP1 BST1 LX1 PGND1 VIN1 V7V PGOOD1 FB2 COMP2 14 70% 13 12 BST2 LX2 PGND2 VIN2 SW_IN SW_OUT 11 Vout2 10 EN2 50% 40% VIN 20% 8 7 0% 0.002 6 5 Buck2 at 5 V 10% Vswout nFAULT SW_EN 60% 30% 9 PGOOD2 EN1 Efficiency (%) 17 nFAULT Buck1 at 1.2 V 0.02 0.2 Loading (A) 2 C001 Copyright © 2016, Texas Instruments Incorporated 1 本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确 性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。 English Data Sheet: SLVSCL3 TPS65283, TPS65283-1 ZHCSCO8E – JUNE 2014 – REVISED MAY 2019 www.ti.com.cn 目录 1 2 3 4 5 6 7 8 9 特性 .......................................................................... 应用 .......................................................................... 说明 .......................................................................... 典型电路原理图 ........................................................ 修订历史记录 ........................................................... 说明 （续） .............................................................. Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 3 5 8.1 8.2 8.3 8.4 8.5 8.6 5 5 5 5 6 9 Absolute Maximum Ratings ...................................... Handling Ratings ...................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 9.1 Overview ................................................................. 12 9.2 Functional Block Diagram ....................................... 13 9.3 Feature Description................................................. 13 9.4 Device Functional Modes........................................ 21 10 Application and Implementation........................ 22 10.1 Application Information.......................................... 22 10.2 Typical Application ................................................ 22 11 Power Supply Recommendations ..................... 31 12 Layout................................................................... 31 12.1 Layout Guidelines ................................................. 31 12.2 Layout Example .................................................... 33 13 器件和文档支持 ..................................................... 34 13.1 13.2 13.3 13.4 文档支持 ............................................................... 商标 ....................................................................... 静电放电警告......................................................... Glossary ................................................................ 34 34 34 34 14 机械、封装和可订购信息 ....................................... 34 5 修订历史记录 注：之前版本的页码可能与当前版本有所不同。 Changes from Revision D (August 2017) to Revision E • Page Added ROSC resistor in Figure 26 ........................................................................................................................................ 17 Changes from Revision C (August 2014) to Revision D Page • 已更改 将“特性”项目符号中的“...100mA 至 2.7A”更改为“....高达 2.7A” .................................................................................. 1 • 已删除 在“说明”的第 2 段的第 1 个句子中删除了文本“介于典型值 100mA 和 约 2.7A 之间” ................................................. 3 • Changed "232 kΩ" to "80.6 kΩ" in the Description for RSET in the Pin Functions table. ..................................................... 4 • Added IOS spec condition for RSET = 80.6 kΩ ........................................................................................................................ 7 • Changed from "RSET is 9.1 kΩ ≤ RLIM ≤ 232 kΩ" to "RSET is 9.1 kΩ ≤ RLIM ≤ 80.6 kΩ" in the Programming the Current-Limit Threshold section. .......................................................................................................................................... 15 • Changed from "...adjustable 75 mA to 2.7 A" to "up to 2.7 mA..." in the Comments section of Table 2 (4 places). .......... 22 Changes from Revision B (July 2014) to Revision C Page • Updated V7V and VSYNC_LO minimum in Electrical Characteristics .......................................................................................... 6 • Updated transition voltage to lower than 0.4 V for clock signal amplitude........................................................................... 17 Changes from Revision A (June 2014) to Revision B • Page 将器件状态更改为生产数据..................................................................................................................................................... 1 Changes from Original (June 2014) to Revision A Page • Changed Equation 3 From: ƒosc (kHz) = 41008 × R (kΩ)–0.979 To: ƒosc (kHz) = 47863 × R (kΩ)–0.988 .................................. 16 2 版权 © 2014–2019, Texas Instruments Incorporated TPS65283, TPS65283-1 www.ti.com.cn ZHCSCO8E – JUNE 2014 – REVISED MAY 2019 6 说明 （续） 60mΩ 独立配电开关通过使用一个外部电阻器将输出电流限制在可编程电流限制阈值。在电流典型值为 1.25A 时， 可获得达到 ±10% 的电流限制精度。nFAULT 输出在过流和反向电压条件下被置为低电平。 DC-DC 转换器中的恒定频率峰值电流模式控制简化了补偿，并且优化了瞬态响应。周期性过流保护和运行在断续 模式限制了 MOSFET 在降压输出短路或过载条件下的功率耗散。当芯片温度超过过热负载阈值时，过热保护会将 器件关断。 空白 7 Pin Configuration and Functions 24 Leads Plastic VQFN (RGE) (Top View) COMP1 FB1 AGND RSET FB2 COMP2 18 17 16 15 14 13 12 BST2 BST1 19 11 LX2 LX1 20 PGND1 21 10 PGND2 Thermal Pad VIN1 22 9 VIN2 8 SW_IN V7V 23 7 SW_OUT 3 4 EN1 EN2 ROSC/SYNC 5 6 nFAULT 2 SW_EN 1 PGOOD2 PGOOD1 24 (There is no electric signal down boned to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.) Pin Functions PIN NAME DESCRIPTION NO. PGOOD2 1 Power good indicator pin. Asserts low if the output voltage of buck2 is out of range due to thermal shutdown, dropout, over-voltage, EN, shutdown, or during slow start. EN1 2 Enable pin for buck 1. A high signal on this pin enables buck1. For a delayed start-up, add a small ceramic capacitor from this pin to ground. EN2 3 Enable pin for buck 2. A high signal on this pin enables buck2. For a delayed start-up, add a small ceramic capacitor from this pin to ground. ROSC/SYNC 4 Automatically select clock frequency program mode and clock synchronization mode. Program the switching frequency of the device from 200 kHz to 2 MHz with an external resistor connecting to the pin. In clock synchronization mode, the device automatically synchronizes to an external clock applied to the pin. SW_EN 5 Enable power switch. Float to enable. nFAULT 6 Active low open-drain output. Asserted during overcurrent or reverse-voltage condition of power switch. Copyright © 2014–2019, Texas Instruments Incorporated 3 TPS65283, TPS65283-1 ZHCSCO8E – JUNE 2014 – REVISED MAY 2019 www.ti.com.cn Pin Functions (continued) PIN NAME DESCRIPTION NO. SW_OUT 7 Power switch output SW_IN 8 Power switch input VIN2 9 Input power supply for buck2. Connect this pin as close as possible to the (+) terminal of input ceramic capacitor (10 µF suggested). PGND2 10 Power ground connection. Connect this pin as close as possible to the (–) terminal of input capacitor of buck2. LX2 11 Switching node connection to the inductor and bootstrap capacitor for buck2 converter. This pin voltage swings from a diode voltage below the ground up to input voltage of buck2. BST2 12 Bootstrapped supply to the high-side floating gate driver in buck converter. Connect a capacitor (47 nF recommended) from this pin to LX2. COMP2 13 Error amplifier output and loop compensation pin for buck2. Connect a series resistor and capacitor to compensate the control loop of buck2 with peak current PWM mode. FB2 14 Feedback sensing pin for buck2 output voltage. Connect this pin to the resistor divider of buck2 output. The feedback reference voltage is 0.6 V ±1%. RSET 15 Power switch current limit control pin. An external resistor used to set current limit threshold of power switch. Recommended 9.1 kΩ ≤ RSET ≤ 80.6 kΩ. AGND 16 Analog ground common to buck controller and power switch controller. AGND must be routed separately from high current power grounds to the (–) terminal of bypass capacitor of internal V7V LDO output. FB1 17 Feedback sensing pin for buck1 output voltage. Connect this pin to the resistor divider of buck1 output. The feedback reference voltage is 0.6 V ±1%. COMP1 18 Error amplifier output and loop compensation pin for buck1. Connect a series resistor and capacitor to compensate the control loop of buck1 converter with peak current PWM mode. BST1 19 Bootstrapped supply to the high side floating gate driver in buck converter. Connect a capacitor (recommend 47 nF) from this pin to LX1. LX1 20 Switching node connection to the inductor and bootstrap capacitor for buck1. This pin voltage swings from a diode voltage below the ground up to input voltage of buck1. PGND1 21 Power ground connection. Connect this pin as close as possible to the (–) terminal of input capacitor of buck1. VIN1 22 Input power supply for buck1 and internal analog bias circuitries. Connect this pin as close as possible to the (+) terminal of an input ceramic capacitor (10 µF suggested). V7V 23 Internal linear regulator (LDO) output with input from VIN1. The internal driver and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum 1-µF ceramic capacitor. The output voltage level of LDO is regulated to typical 6.3 V for optimal conduction on-resistances of internal power MOSFETs. In PCB design, the power ground and analog ground should have one-point common connection at the (–) terminal of V7V bypass capacitor. PGOOD1 24 Power good indicator pin. Asserts low if the output voltage of buck1 is out of range due to thermal shutdown, dropout, over-voltage, EN shutdown or during slow start. PowerPAD™ — Exposed pad beneath the IC. Connect to the power ground. Always solder power pad to the board, and have as many vias as possible on the PCB to enhance power dissipation. There is no electric signal down bonded to paddle inside the IC package. 4 Copyright © 2014–2019, Texas Instruments Incorporated TPS65283, TPS65283-1 www.ti.com.cn ZHCSCO8E – JUNE 2014 – REVISED MAY 2019 8 Specifications 8.1 Absolute Maximum Ratings (Operating in a typical application circuit) over operating free-air temperature range and all voltages are with respect to AGND (unless otherwise noted) (1) VIN1, LX1, VIN2, LX2 MIN MAX –0.3 20 V LX1, LX2 (Maximum withstand voltage transient