TPS65288
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SLVSBX3 – MAY 2013
4.5-V to 18-V Input, High Current, Synchronous Step Down Three DC-DC Converter with
Integrated FET and 2 Power Switches
Check for Samples: TPS65288
FEATURES
1
•
•
•
•
•
•
•
•
•
Wide Input Supply Voltage Range:
4.5 V - 18 V
0.8-V, 1% Accuracy Reference
Continuous Loading:
3 A (Buck1), 2 A (Buck2 and 3)
Maximum Current:
3.5 A (Buck 1), 2.5 A (Buck2 and 3)
300-kHz – 2.2-MHz Switching Frequency Set
By External Resistor
External Enable Pins With Built-In Current
Source for Easy Sequencing
External Soft Start Pins
Adjustable Cycle-by-Cycle Current Limit Set
by External Resistor
Current-Mode Control With Simple
Compensation Circuit
•
•
•
•
•
•
•
Pulse Skipping Mode to Achieve High Light
Load Efficiency, Allowing for an Output Ripple
Better than 2%
Forced PWM Mode
Support Pre-Biased Outputs
Power Good Supervisor and Reset Generator
2 USB Power Switches current limiting at
typical 1.2A (0.8/1.0/1.4/1.6/1.8/2.0/2.2A
Available with Manufacture Trim Options)
Small, Thermally Efficient 40-Pin 6-mm x 6-mm
RHA (QFN) package
-40°C to 125°C Junction Temperature Range
DESCRIPTION/ORDERING INFORMATION
TPS65288 is a power management IC with three step-down buck converters. Both high-side and low-side
MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. The converters are
designed to simplify its application while giving the designer the option to optimize their usage according to the
target application.
The converters can operate in 5-, 9-, 12- or 15-V systems. The output voltage can be set externally using a
resistor divider to any value between 0.8 V and the input supply minus the resistive drops on the converter path.
Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that
allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIM) pin that enables
designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. All converters
operate in ‘hiccup mode’: Once an over-current lasting more than 10 ms is sensed in any of the converters, they
will shut down for 10 ms and then the start-up sequencing will be tried again. If the overload has been removed,
the converter will ramp up and operate normally. If this is not the case the converter will see another over-current
event and shuts down again repeating the cycle (hiccup) until the failure is cleared. If an overload condition lasts
for less than 10 ms, only the relevant converter affected will shut-down and re-start and no global hiccup mode
will occur.
The switching frequency of the converters is set by an external resistor connected to ROSC pin. The switching
regulators are designed to operate from 300 kHz to 2.2 MHz. The converters operate with 180° phase between
then to minimize the input filter requirements. All converters have peak current mode control which simplifies
external frequency compensation.
The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic
oscillations in peak current mode control. A traditional type II compensation network can stabilize the system and
achieve fast transient response. Moreover, an optional capacitor in parallel with the upper resistor of the
feedback divider provides one more zero and makes the crossover frequency over 100 kHz.
All converters feature an automatic low power pulse skipping mode (PSM) which improves efficiency during light
loads and standby operation, while guaranteeing a very low output ripple, allowing for a value of less than 2% at
low output voltages.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS65288
SLVSBX3 – MAY 2013
www.ti.com
The device incorporates an overvoltage transient protection circuit to minimize voltage overshoot. The OVP
feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVP threshold
which is 106% of the internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the
high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot.
When the FB voltage drops lower than the OVP lower threshold which is 104%, the high side MOSFET is
allowed to turn on the next clock cycle.
TPS65288 features a supervisor circuit which monitors each buck’s output and the PGOOD pin is asserted once
sequencing is done. The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck
converter is pulled below 85% of the nominal output voltage. The PGOOD is pulled up when all converter outputs
are more than 90% of its nominal output voltage. The default reset time is 100 ms. The polarity of the PGOOD is
active high.
The 2 USB switches provide up to 1.2A of current as required by downstream USB devices. When the output
load exceeds the current-limit threshold or a short is present, the PMU limits the output current to a safe level by
switching into a constant-current mode and pulling the over current logic output low. When continuous heavy
overloads or short circuits increase the power dissipation in the switch, causing the junction temperature to rise,
a thermal warning protection circuit shuts off the USB switch and allows the buck converters to carry on
operating.
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop operating when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The
thermal shutdown hysteresis is 20°C.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
-40°C to 125°C
(1)
(2)
2
40-Pin (QFN) - RHA
Reel of 2500
PART NUMBER
TOP-SIDE MARKING
TPS65288RHAR
TPS65288
For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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SLVSBX3 – MAY 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
USB1_nFAULT
USB1_VO
USB1_VIN
USB1_EN
V3V
V7V
Biasing
USB_SWITCHS
USB2_nFAULT
USB2_VO
USB2_VIN
ROSC
CLOCK
USB2_EN
BST1
VIN1
SS1
LX1
RLIM1
BUCK1
4µA
LX1
FB1
EN1
Pluse Skip Modulation
COMP1
0.8V
VIN2
SS2
BST2
LX2
RLIM2
BUCK2
4µA
LX2
FB2
EN2
Pluse Skip Modulation
0.8V
VIN3
COMP2
BST3
SS3
LX3
RLIM3
BUCK3
4µA
EN3
FB3
Pluse Skip Modulation
0.8V
PGOOD
LX3
PG&RST
generator
COMP3
F_PWM
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TYPICAL APPLICATION
V PULL
Error
USB1_EN
35
USB1_nFAULT
36
LX3
37
LX3
22
SS2
RLIM2
23
FB2
COMP2
25
24
21
16
LX1
15
Vout2
Vout1
14
13
VIN1
FB1
VIN3
SS1
RLIM1
10
COMP1
8
9
FB1
7
11
FB1
6
FB3
EN1
12
Host
FB3
1
USB2_EN
BST3
EN3
ROSC
BST1
5
39
40
VIN1
7
LX2
LX1
4
38
18
17
VIN1
SS3
VIN3
FB2
19
LX2
TPS65288
COMP3
Vout2
BST2
20
USB1_VO
34
Error
VPULL
EN2
VIN2
33
3
Host
USB1_VIN
RLIM3
USB1_VO
32
2
USB1_VIN
F_PWM
26
PGOOD
27
28
V3V
USB2_VIN
USB2_nFAULT
31
V7V
U SB2_VO
USB2_VIN
29
30
USB2_VO
FB2
Host
Host
4
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PGOOD
USB2_nFAULT
F_PWM
FB2
COMP2
SS2
RLIM2
29
V7V
30
V3V
USB2_VO
PIN OUT
28
27
26
25
24
23
22
21
USB2_VIN
31
20
EN2
USB1_VIN
32
19
BST2
USB1_VO
33
18
VIN2
USB1_EN
34
17
LX2
USB1_nFAULT
35
16
LX2
TPS65288
LX3
36
15
LX1
LX3
37
14
LX1
VIN3
38
13
VIN1
BST3
39
12
BST1
EN3
40
11
EN1
1
2
3
4
5
6
7
8
9
10
RLIM1
SS1
COMP1
FB1
ROSC
USB2_EN
FB3
COMP3
SS3
RLIM3
8
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TERMINAL FUNCTIONS
NAME
NO.
I/O
DESCRIPTION
RLIM3
1
I
Current limit setting for Buck3. Fit a resistor from this pin to ground to set
the peak current limit on the output inductor.
SS3
2
I
Soft start pin for Buck3. Fit a small ceramic capacitor to this pin to set the
converter soft start time.
COMP3
3
O
Compensation for Buck3. Fit a series RC circuit to this pin to complete
the compensation circuit of this converter.
FB3
4
I
Feedback pin for Buck3. Connect a divider set to 0.8 V from the output of
the converter to ground.
USB2_EN
5
I
Enable input, high turns on the switch
ROSC
6
I
Oscillator set. This resistor sets the frequency of internal autonomous
clock.
FB1
7
I
Feedback pin for Buck1. Connect a divider set to 0.8 V from the output of
the converter to ground.
COMP1
8
O
Compensation pin for Buck1. Fit a series RC circuit to this pin to complete
the compensation circuit of this converter.
SS1
9
I
Soft-start pin for Buck1. Fit a small ceramic capacitor to this pin to set the
converter soft-start time.
RLIM1
10
I
Current limit setting pin for Buck1. Fit a resistor from this pin to ground to
set the peak current limit on the output inductor.
EN1
11
I
Enable pin for Buck1. A high signal on this pin enables the regulator
Buck. For a delayed start-up add a small ceramic capacitor from this pin
to ground.
BST1
12
VIN1
13
I
Input supply for Buck1. Fit a 10-µF ceramic capacitor close to this pin.
LX1
14, 15
O
Switching node for Buck1
LX2
16, 17
O
Switching node for Buck2
VIN2
18
I
Input supply for Buck2. Fit a 10-µF ceramic capacitor close to this pin.
BST2
19
EN2
20
I
Enable pin for Buck2. A high signal on this pin enables the regulator. For
a delayed start-up add a small ceramic capacitor from this pin to ground.
RLIM2
21
I
Current limit setting pin for Buck2. Fit a resistor from this pin to ground to
set the peak current limit on the output inductor.
SS2
22
I
Soft-start pin for Buck2. Fit a small ceramic capacitor to this pin to set the
converter soft-start time.
COMP2
23
O
Compensation pin for Buck2. Fit a series RC circuit to this pin to complete
the compensation circuit of this converter.
FB2
24
I
Feedback input for Buck2. Connect a divider set to 0.8 V from the output
of the converter to ground.
F_PWM
25
I
Forces PWM operation in all converters when set high. If low converters
will operate in automatic PFM/PWM mode.
USB2_nFAULT
26
O
USB2 fault flag output, open drain, active low. Asserted when over
current or over temperature condition is detected in the switch.
PGOOD
27
O
Power good. Open drain output asserted low after all converters and
sequenced and within regulation. Polarity is factory selectable (active high
default).
V7V
28
O
Internal supply. Connect a 4.7-μF to 10-μF ceramic capacitor from this pin
to ground.
V3V
29
O
Internal supply. Connect a 3.3-μF to 10-μF ceramic capacitor from this pin
to ground.
USB2_VO
30
O
USB switch output
USB2_VIN
31
I
USB switch input supply
USB1_VIN
32
I
USB switch Input supply
USB1_VO
33
O
USB switch output
6
Bootstrap capacitor for Buck1. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
Bootstrap capacitor for Buck2. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
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TERMINAL FUNCTIONS (continued)
NO.
I/O
USB1_EN
NAME
34
I
Enable input, high turns on the switch
DESCRIPTION
USB1_nFAULT
35
O
USB1 fault flag output, open drain, active low. Asserted when overcurrent
or overtemperature condition is detected in the switch.
LX3
36, 37
O
Switching node for Buck3
VIN3
38
I
Input supply for Buck3. Fit a 10-µF ceramic capacitor close to this pin.
BST3
39
EN3
40
Bootstrap capacitor for Buck3. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
Enable pin for Buck3. A high signal on this pin enables the converter. For
a delayed start-up add a small ceramic capacitor from this pin to ground.
I
PowerPAD. Connect to system ground for electrical and thermal
connection.
PowerPAD
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted, all voltages are with respect to GND)
Voltage range at VIN1,VIN2, VIN3, LX1, LX2, LX3
–0.3 to 20
V
Voltage range at LX1, LX2, LX3 (maximum withstand voltage transient < 10 ns)
–3 to 20
V
Voltage at BST1, BST2, BST3 referenced to LX pin
–0.3 to 7
V
Voltage at V7V, COMP1, COMP2, COMP3, USB1_VIN, USB1_VO, USB2_VIN, USB2_VO,
USB1_EN, USB2_EN, USB1_nFAULT, USB2_nFAULT, PGOOD
–0.3 to 7
V
Voltage at V3V, RLIM1, RLIM2, RLIM3, SS1, SS2, SS3, FB1, FB2, FB3 , ROSC, EN1,
EN2, EN3, F_PWM
–0.3 to 3.6
V
TJ
Operating junction temperature range
–40 to 125
°C
TSTG
Storage temperature range
–55 to 150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input operating voltage
4.5
18
V
TA
Junction temperature
–40
85
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION (1)
MIN
Human body model (HBM)
Charge device model (CDM)
(1)
MAX
UNIT
2000
V
500
V
USB1_Vo, USB2_Vo pins’ human body model (HBM) ESD protection rating 4KV, and machine model (MM) rating 200V.
PACKAGE DISSIPATION RATINGS (1)
(1)
PACKAGE
θJA (°C/W)
TA = 25°C
POWER RATING (W)
TA = 55°C
POWER RATING (W)
TA = 85°C
POWER RATING (W)
RHA
30
3.33
2.3
1.3
Based on JEDEC 51.5 HIGH K environment measured on a 76.2 x 114 x 0.6-mm board with the following layer arrangement:
(a) Top layer: 2 Oz Cu, 6.7% coverage
(b) Layer 2: 1 Oz Cu, 90% coverage
(c) Layer 3: 1 Oz Cu, 90% coverage
(d) Bottom layer: 2 Oz Cu, 20% coverage
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ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 12 V, fSW = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE
VIN
Input voltage range
IDDSDN
Shutdown
EN pin = low for all converters
180
µA
Quiescent (push-button pull-up
current not included)
Converters enabled, no load
Buck1 = 1.2 V
Buck2 = 1.8 V
Buck3 = 3.3 V
TA = 25°C, F_PWM = Low
700
µA
Quiescent, forced PWM
Converters enabled, no load
F_PWM = High
24
mA
IDDQ
UVLO
4.5
VIN under voltage lockout
UVLODEGLITCH
18
Rising VIN
4.22
Falling VIN
4.1
Both edges
V
V
110
µs
V3p3
Internal biasing supply
3.3
V
V7V
Internal biasing supply
6.25
V
V7VUVLO
UVLO for internal V7V rail
V7VUVLO_DEGLITCH
Rising V7V
3.8
Falling V7V
3.6
Falling edge
120
V
µs
BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT-START AND SWITCHING FREQUENCY)
VIH_ENx
Enable threshold high
V3p3 = 3.2 V - 3.4 V,
VENx rising
0.66 x
V3p3
VIL_ENx
Enable threshold low
V3p3 = 3.2 V - 3.4 V,
VENx falling
VIH_F_PWM
Enable threshold high
V3p3 = 3.2 V - 3.4 V,
VENx rising
VIL_F_PWM
Enable treshold low
V3p3 = 3.2 V - 3.4 V,
VENx falling
ICHEN
Pull up current enable pin
tD
Discharge time enable pins
ISS
Soft-start pin current source
FSW_BK
Converter switching frequency range
Set externally with resistor
0.3
2.2
MHz
fSW_TOL
Internal oscillator accuracy
fSW = 800 kHz
-10
10
%
V
0.33 x
V3p3
0.66 x
V3p3
V
0.33 x
V3p3
Power-up
V
V
4
µA
10
ms
5
µA
FEEDBACK, REGULATION, OUTPUT STAGE
VFB
Feedback voltage
tON_MIN
Minimum on time (current sense
blanking)
ILIMIT1
Peak inductor current limit range
ILIMIT2
Peak inductor current limit range
ILIMIT3
Peak inductor current limit range
VIN = 12 V , TA = 25°C
-1%
0.8
1%
VIN = 4.5 V to 18 V
-2%
0.8
2%
V
135
ns
0.75
4
A
0.75
3
A
0.75
3
A
MOSFET (BUCK 1)
H.S. Switch
On resistance of high side FET on
CH1
25°C, BOOT = 6.5 V
95
mΩ
L.S. Switch
On resistance of low side FET on
CH1
25°C, VIN = 12 V
50
mΩ
8
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ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VIN = 12 V, fSW = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOSFET (BUCK 2)
H.S. Switch
On resistance of high side FET on
CH2
25°C, BOOT = 6.5 V
L.S. Switch
On resistance of low side FET on
CH2
25°C, VIN = 12 V
H.S. Switch
On resistance of high side FET on
CH3
25°C, BOOT = 6.5 V
L.S. Switch
On resistance of low side FET on
CH3
25°C, VIN = 12 V
120
mΩ
80
mΩ
120
mΩ
80
mΩ
MOSFET (BUCK 3)
ERROR AMPLIFIER
gM
Error amplifier transconductance
-2 µA < ICOMP < 2 µA
130
µS
gmPS1
COMP to ILX gm of Buck1 (1)
ILX = 0.5 A
10
A/V
gmPS2
COMP to ILX gm of Buck2 and 3 (1)
ILX = 0.5 A
8
A/V
POWER GOOD RESET GENERATOR
Output falling
85
Output rising (PG will be
asserted)
90
VUVBUCKX
Threshold voltage for buck under
voltage
tUV_deglitch
Deglitch time (both edges)
11
ms
tON_HICCUP
Hiccup mode ON time
VUVBUCKX asserted
14
ms
tOFF_HICCUP
Hiccup mode OFF time
All converters disabled. Once
tOFF_HICCUP elapses, all
converters will go through
sequencing again.
20
ms
VOVBUCKX
Threshold voltage for buck over
voltage
tRP
minimum reset period
Output rising (high side FET will
be forced off)
106
Output falling (high side FET will
be allowed to switch )
104
Measured after the later of
Buck1 or Buck3 power-up
successfully
100
%
%
ms
USB SWITCHES
VINUSB
USB input voltage range
2.5
6
0.66x
V3p3
V
VIH_USB_EN
USB_EN high level input voltage
V3p3 = 3.2-3.4 V, VUSB_EN rising
VIL_USB_EN
USB_EN low level input voltage
V3p3 = 3.2-3.4 V, VUSB_EN falling
RDS_USB
Static drain-source on-state
resistance
USB_VIN = 5 V and
Io_USB = 0.5 A, TJ = 2 5°C
135
mΩ
ICS_USB
USB current limit
Increasing USB_Vo current
di/dt
DI OUT 2 × Lo
Vout × DVout
(4)
The following equation calculates the minimum output capacitance needed to meet the output voltage ripple
specification.
1
1
×
Co >
8 × fsw VRIPPLE
I RIPPLE
(5)
Where fSW is the switching frequency, VRIPPLE is the maximum allowable output voltage ripple, and VRIPPLE is the
inductor ripple current.
Input Capacitor
A minimum 10-µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND of
each converter. The input capacitor must handle the RMS ripple current shown in the following equation.
Icirms = Iout ×
Vout (Vin min - Vout )
×
Vin min
Vin min
(6)
Bootstrap Capacitor
The device has two integrated boot regulators and requires a small ceramic capacitor between the BST and LX
pins to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.047 µF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable
characteristics over temperature and voltage.
Delayed Start-Up
If a delayed start-up is required on any of the buck converters fit a ceramic capacitor to the ENx pins. The delay
added is ~1.67 ms per nF connected to the pin. Note that the EN pins have a weak 1 MΩ pull-up to the 3V3 rail.
20
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Vin
V7V
V3V
EN threshold
EN1
EN rise time
dictated by CEN
EN2
EN3
Enable discharge
10-12ms
Pre-bias timing
4-5ms
Buck3
Pre-biased output
PG asserted
Buck2
Buck1
Soft start rise time
dictated by Css
Soft start timer
10ms watchdog
PGOOD
PG timer 11ms
Figure 49. Delayed Start-Up
Out-of-Phase Operation
In order to reduce input ripple current, buck 1 and buck 2 operate 180 degree out-of-phase. This enables the
system having less input ripple, then to lower component cost, save board space and reduce EMI.
Soft-Start Time
The device has an internal pull-up current source of 5 µA that charges an external soft-start capacitor to
implement a slow start time. Equation 7 shows how to select a soft-start capacitor based on an expected slow
start time. The voltage reference (VREF) is 0.8 V and the soft-start charge current (Iss) is 5 µA. The soft-start
circuit requires 1 nF per around 167 µs to be connected at the SS pin. A 0.8-ms soft-start time is implemented for
all converters fitting 4.7 nF to the relevant SS pin.
( )
Css(nF)
Tss(ms) = VREF(V) · Iss(µA)
(7)
The Power Good circuit for the bucks has a 11-ms watchdog. Therefore the soft-start time should be lower than
this value. It is recommended not to exceed 5 ms.
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Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use 1%
tolerance or better divider resistors. In order to improve efficiency at light load, start with a value close to 40 kΩ
for the R1 resistor and use Equation 8 to calculate R2.
æ 0.8V ö
R 2 = R1 × ç
÷
è VO - 0.8V ø
(8)
Vo
TPS65257
TPS65288
R1
FB
R2
0.8V
+
Figure 50. Voltage Divider Circuit
Loop Compensation
TPS65288 is a current mode control DC/DC converter. The error amplifier is a transconductance amplifier with a
gM of 130 µA/V. A typical compensation circuit could be type II (Rc and Cc) to have a phase margin between 60°
and 90°, or type III (Rc and Cc and Cff to improve the converter transient response. CRoll adds a high frequency
pole to attenuate high-frequency noise when needed. It may also prevent noise coupling from other rails if there
is possibility of cross coupling in between rails when layout is very compact.
VO
iL
CO
RL
RESR
Gm = 10 A/V
Cff
R1
Current Sense
I/V Gain
FBx
g M = 130 m
VREF = 0.8 V
COMPx
R2
RC
CRoll
CC
Figure 51. Loop Compensation Scheme
22
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To calculate the external compensation components follow the following steps:
TYPE II CIRCUIT
Select switching frequency that is appropriate for
application depending on L, C sizes, output ripple, EMI
concerns and etc. Switching frequencies around 500 kHz
yield best trade off between performance and cost. When
using smaller L and C, switching frequency can be
increased. To optimize efficiency, switching frequency can
be lowered.
Type III circuit recommended for
switching frequencies higher than
500 kHz.
Select cross over frequency (fc) to be at least 1/5 to 1/10 of
switching frequency (fs).
Suggested
fc = fs/10
RC =
Set and calculate Rc.
2p × fc × Vo × Co
g M × Vref × gm ps
Calculate Cc by placing a compensation zero at or before
the converter dominant pole
Cc =
1
fp =
CO × RL × 2p
TYPE III CIRCUIT
RL × Co
Rc
Suggested
fc = fs/10
RC =
2p × fc × Vo × Co
g M × Vref × gm ps
Cc =
RL × Co
Rc
Add CRoll if needed to remove large signal coupling to high
impedance CMP node. Make sure that
fpRoll =
1
2 × p × RC × CRoll
CRoll =
Re sr × Co
RC
CRoll =
Re sr × Co
RC
is at least twice the cross over frequency.
Calculate Cff compensation zero at low frequency to boost
the phase margin at the crossover frequency. Make sure
that the zero frequency (fzff) is smaller than equivalent
soft-start frequency (1/Tss).
NA
C ff =
1
2 × p × fz ff × R1
Slope Compensation
The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic
oscillations in peak current mode control.
Power Good
The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below
85% of the nominal output voltage. The PGOOD is pulled up when both buck converters’ outputs are more than
90% of its nominal output voltage.
The default reset time is 100 ms. The polarity of the PGOOD is active high.
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Current Limit Protection
The TPS65288 current limit trip is set by the following formulae:
TYPE II CIRCUIT
I LIM 1 ( A) =
268.5
+ 0.613
RLIM 1(k W)
(9)
I LIM 2 ( A) =
324.8
+ 0.543
RLIM 1(k W)
(10)
I LIM 3 ( A) =
208.7
+ 0.731
RLIM 2(k W)
(11)
All converters operate in hiccup mode: Once an over-current lasting more than 11 ms is sensed in any of the
converters, they will shut down for 11 ms and then the start-up sequencing will be tried again. If the overload has
been removed, the converter will ramp up and operate normally. If this is not the case the converter will see
another over-current event and shuts-down again repeating the cycle (hiccup) until the failure is cleared.
If an overload condition lasts for less than 11 ms, only the relevant converter affected will shut-down and re-start
and no global hiccup mode will occur.
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Overvoltage Transient Protection
The device incorporates an overvoltage transient protection (OVP) circuit to minimize voltage overshoot. The
OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVTP
threshold which is 106% of the internal voltage reference. If the FB pin voltage is greater than the OVTP
threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output
overshoot. When the FB voltage drops lower than the OVTP threshold which is 104%, the high side MOSFET is
allowed to turn on the next clock cycle.
Low Power/Pulse Skipping Operation
When a buck synchronous converter operates at light load or standby conditions, the switching losses are the
dominant source of power losses. Under these load conditions, TPS65288 uses a pulse skipping modulation
technique to reduce the switching losses by keeping the power transistors in the off-state for several switching
cycles, while maintaining a regulated output voltage. Figure 52 shows the output voltage and load plus the
inductor current.
Figure 52. Low Power/Pulse Skipping
During the burst mode, the converter continuously charges up the output capacitor until the output voltage
reaches a certain limit threshold. The operation of the converter in this interval is equivalent to the peak inductor
current mode control. In each switch period, the main switch is turned on until the inductor current reaches the
peak current limit threshold. As the load increases the number of pulses increases to make sure that the output
voltage stays within regulation limits. When the load is very light the low power controller has a zero crossing
detector to allow the low side mosfet to operate even in light load conditions. The transistor is not disabled at
light loads. A zero crossing detection circuit will disable it when inductor current reverses. During the whole
process the body diode does not conduct but is used as blocking diode only.
During the skipping interval, the upper and lower transistors are turned off and the converter stays in idle mode.
The output capacitors are discharged by the load current until the moment when the output voltage drops to a
low threshold.
The choice of output filter will influence the performance of the low power circuit. The maximum ripple during low
power mode can be calculated as:
K T
VOUT _ RIPPLE = RIP S
COUT
(12)
Where KRIP is 1.4 for Buck1 and 0.7 for Buck2 and Buck3. TS can be calculated as:
0.35
TS =
éæ VIN - VOUT ö VOUT ù
êç
÷ V ú
L
ø IN û
ëè
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SLVSBX3 – MAY 2013
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USB Switches
The USB switches are enabled (active high) with the USB_ENx pin. The switches have a typical resistance of
135 mΩ. If a continuous short-circuit condition is applied to the USB switch output, the USB switch will shut-down
once its temperature reaches 130°C, allowing for the buck converters to operate unaffected. Once the USB
switch cools down it will restart automatically.
USB_VIN
0
USB_EN
USB_VO
OVERCURRENT DETECTED
USB_LOAD
ICS_USB
OVERCURRENT IS CLEARED
USB_I
Normal operation
Overcurrent at the out.put Alarm
Normal operation is restor. ed
Alarm is cleare.d
is asserted after 8.8 ms
USB_nFAULT
Tdeglitch
Tdeglitch
Figure 53. USB Switches
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The
thermal shutdown hysteresis is 20°C.
3.3-V and 6.5 LDO Regulators
The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:
• 4.7 µF to 10 µF for V7V pin 28
• 3.3 µF to 10 µF for V3V pin 29
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Layout Recommendation
Layout is a critical portion of PMIC designs.
• Place tracing for output voltage and LX on the top layer and an inner power plane for VIN.
• Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with
ground.
• The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass
capacitor, the output filter capacitor and directly under the TPS65288 device to provide a thermal path from
the PowerPad land to ground.
• For operation at full rated load, the top side ground area together with the internal ground plane, must provide
adequate heat dissipating area.
• There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching
node, the output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
• The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor.
Try to minimize this conductor length while maintaining adequate width.
• The compensation should be as close as possible to the CMPx pins. The CMPx and ROSC pins are sensitive
to noise so the components associated to these pins should be located as close as possible to the IC and
routed with minimal lengths of trace.
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27
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS65288RHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS
65288
TPS65288RHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS
65288
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS65288RHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
TPS65288RHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65288RHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
TPS65288RHAT
VQFN
RHA
40
250
210.0
185.0
35.0
Pack Materials-Page 2
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