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TPS65301-Q1
SLVSC10C – OCTOBER 2013 – REVISED APRIL 2016
TPS65301-Q1 3-MHz Step-Down Regulator and Triple Linear Regulators and Protected
Sensor Supply
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Input VIN Range 5.6 V to 40 V, With Transients
up to 45 V
5.45-V Switch-Mode Regulator With Integrated
High-Side Switch
– Recommended Switch-Mode Frequency
Range 2 MHz to 3 MHz
– Overcurrent Protection and 1.2-A Peak Switch
Current
One Linear Regulator 5 V ±2%
Two Linear Regulator Controllers With 3.3-V and
1.2 V ±2%
Status Indicator Output of IGN_EN Input
Soft Start on IGN_EN and EN
External Clock Input for Synchronization
Programmable Power-On-Reset Delay, ResetFunction Filter Timer for Fast Negative Transients
Voltage Supervisor for the Following Supplies
– VREG, 3.3 V, 1.2 V
Thermally Enhanced 24-Pin HTSSOP or 24-Pin
VQFN Package
Protected 5-V Sensor Supply Output, Which
Tracks 3.3-V Supply
The device has a voltage supervisor which monitors
the output of the switch-mode power supply, the 3.3V linear regulator, and the 1.2-V linear regulator. An
external timing capacitor is used to set the power-on
delay and the release of the reset output nRST. This
reset output is also used to indicate if the switchmode supply, the 3.3-V linear regulator supply, or the
1.2-V linear regulator supply is outside the set limits.
The protected sensor supply 5VS tracks the 3.3-V
linear regulator within the specified limits.
The TPS65301-Q1 device has a switching frequency
range from 2 MHz to 3 MHz, allowing the use of lowprofile inductors and low-value input and output
ceramic capacitors. External loop compensation gives
the user the flexibility to optimize the converter
response for the appropriate operating conditions.
This device has built-in protection features such as
soft start on IGN_EN ON or enables cycle, pulse-bypulse current limit, thermal sensing, and shutdown
due to excessive power dissipation.
Device Information(1)
PART NUMBER
PACKAGE
TPS65301-Q1
BODY SIZE (NOM)
HTSSOP (24)
7.80 mm × 4.40 mm
VQFN (24)
5.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
VIN_D
VI = 5.6 V to 40 V
VIN
Supply
EN
RT/CLK
SS
BOOT
3
1 PH
9
IGN_EN
2 Applications
2
4
22
5
14
8
5.45 V
VREG
COMP
15
20
VSENSE
TPS65301PWPR-Q1
•
•
•
Power Supply for TMS570 Microcontrollers
Power Supply for C28XXX DSP
General-Purpose Power Supply for Automotive
Applications
3 Description
The TPS65301-Q1 power supply is a combination of
a single switch-mode buck power supply and three
linear regulators. This is a monolithic high-voltage
switching regulator with an integrated 1.2-A peak
current switch, 45-V power MOSFET, one low-voltage
linear regulator, two voltage-regulator controllers and
a protected sensor supply.
BOOT_LDO
6
19
18
GND
DELAY
12
3.3 V
5V
21
7
17
PGND
3.3VSENSE
10
23
5VS
3.3VDRIVE
16
nRST
1.2VDRIVE
1.2VSENSE
1.2 V
24
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65301-Q1
SLVSC10C – OCTOBER 2013 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
5
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
DC Characteristics ....................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application .................................................. 16
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2013) to Revision C
Page
•
Changed the Features section .............................................................................................................................................. 1
•
Changed the minimum VIN value from 5.75 to 5.6 in the Features and Power Supply Recommendations sections .......... 1
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
•
Updated the pin types and descriptions in the Pin Functions table ....................................................................................... 4
•
Changed the maximum PH buck regulator voltage in the Absolute Maximum Ratings table ............................................... 4
•
Moved the TA value from the Recommended Operating Conditions table to the Absolute Maximum Ratings table ........... 4
•
Changed DC CHARACTERISTICS condition statement from TJ = –40°C to 150°C to TJ-Max = 150°C ................................. 5
Changes from Revision A (November 2013) to Revision B
Page
•
Changed the Operating Junction Temperature Range from –40°C to 150°C to up to 150°C in the FEATURES list............ 1
•
Changed DC CHARACTERISTICS condition statement from TJ = –40°C to 150°C to TJ-Max = 150°C ................................. 5
•
Added Output Voltage vs Output Current graph to TYPICAL CHARACTERISTICS section................................................. 8
•
Changed Y-axis name from Current (mA) to Efficiency in the EFFICIENCY vs OUTPUT CURRENT ON VREG
graph in the TYPICAL CHARACTERISTICS section ........................................................................................................... 24
Changes from Original (October 2013) to Revision A
Page
•
Changed document status from Product Preview to Production Data ................................................................................... 1
•
Changed min value for VIL in the DC CHARACTERISTICS table from 2 to 2.2 .................................................................... 5
•
Deleted the 5VS oft-start time, TSS, parameter from the DC CHARACTERISTICS table...................................................... 7
•
Changed the min, typ, and max values for the nRST parameter for VREG output from 0.87, 0.9, and 0.93 to 0.845,
0.875, and 0.905 respectively................................................................................................................................................. 7
2
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SLVSC10C – OCTOBER 2013 – REVISED APRIL 2016
5 Pin Configuration and Functions
PWP Package
24-Pin HTSSOP With Exposed Thermal Pad
Top View
BOOT_LDO
6
19
3.3VDRIVE
18
3.3VSENSE
17
1.2VDRIVE
VREG
20
SS
1
19
DELAY
VIN
2
18
SS
IGN_EN
3
17
3.3VDRIVE
16
3.3VSENSE
Thermal
Thermal
EN
9
16
1.2VSENSE
5V
10
15
VSENSE
IGN_ST
11
14
COMP
GND
12
13
Reserved
4
Pad
5VS
5
15
1.2VDRIVE
RT/CLK
6
14
1.2VSENSE
EN
7
13
VSENSE
9
8
BOOT_LDO
IGN_ST
RT/CLK
Pad
8
7
5V
5VS
12
20
BOOT
COMP
5
nRST
IGN_EN
PGND
DELAY
21
VREG
21
22
22
4
11
3
VIN
10
BOOT
GND
nRST
Reserved
PGND
23
PH
24
2
23
1
VIN_D
PH
VIN_D
24
RHF Package
24-Pin VQFN With Exposed Thermal Pad
Top View
Pin Functions
PIN
NAME
TYPE (1)
NO.
DESCRIPTION
HTSSOP
VQFN
1.2VDRIVE
17
15
PWR
1.2VSENSE
16
14
I
3.3VDRIVE
19
17
PWR
3.3VSENSE
18
16
I
Feedback node of 3.3-V supply
5V
10
8
O
Regulated output, external capacitor to ground for stability of regulated output
5VS
7
5
PWR
Regulated output, external capacitor to ground for stability of regulated output
BOOT
3
1
O
External bootstrap capacitor connected to PH (pin 1) to drive gate of internal switching FET
BOOT_LDO
6
4
O
External capacitor connected to ground for stability of internal regulator
COMP
14
12
O
Error amplifier output to connect external compensation components
DELAY
21
19
O
External capacitor to ground to program the power-on-reset delay
EN
9
7
I
A high logic-level input signal to enable and low signal to disable device. Internally pulled down to
ground
GND
12
10
GND
IGN_EN
5
3
I
Ignition input, (high-voltage tolerant) internally pulls to ground. Must be externally pulled up to
enable
IGN_ST
11
9
O
Active-low, open-drain ignition input indicator, output connected to external bias voltage through a
resistor. Asserted high after ignition input is high
Reserved
13
11
—
Should be grounded in the application
nRST
23
21
O
Active-low, open-drain reset output connected to external bias voltage through a resistor. This
output is floating and pulled high by an external resistor after the preregulator, 3.3-V, and 1.2-V
regulator outputs are regulating and the delay timer has expired. Also, output is asserted low if
any one of these three supplies is out of the set regulation, this threshold is internally set.
PGND
24
22
GND
Power ground pin, must be connected to the exposed copper pad on PCB for proper electrical
and thermal performance
PH
1
23
PWR
Source of internal switching FET
RT/CLK
8
6
I/O
(1)
Output current source to drive the base of an external bipolar transistor to regulate the 1.2-V
supply
Feedback node of 1.2-V supply
Output current source to drive the base of an external bipolar transistor to regulate the 3.3-V
supply
GND pin, must be electrically connected to the exposed copper pad on PCB
External resistor connected ground to program the internal oscillator. Alternative option is to feed
an external clock to provide reference for switching frequency.
PWR = power, I = input, O = output, I/O = input-output, GND = ground, — = not applicable
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Pin Functions (continued)
PIN
NAME
TYPE (1)
NO.
DESCRIPTION
HTSSOP
VQFN
SS
20
18
O
VIN
4
2
PWR
Unregulated input voltage supply. Pin 2 and pin 4 must be connected together externally.
VIN_D
2
24
PWR
Drain input for internal high side MOSFET. Pin 2 and pin 4 must be connected together externally.
VREG
22
20
I
Connect this pin to the buck converter output. Integrated internal low-side FET to load output
during start-up or limit voltage overshoot
VSENSE
15
13
I
Inverting node of error amplifier for voltage-mode control of preregulated supply
Thermal pad
—
External capacitor to ground to program soft-start time
Electrically connect to ground and solder to ground plane of PCB for thermal efficiency
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Buck regulator
Control
Output
Temperature
(1)
MIN
MAX
UNIT
VIN, VIN_D
–0.3
45
V
BOOT
–0.3
50
V
–1
–2 for 30 ns
45
V
VSENSE
–0.3
5.5
V
IGN_EN
–0.3
45
V
EN
–0.3
5.5
V
3.3VSENSE
–0.3
5.5
V
1.2VSENSE
–0.3
5.5
V
RT/CLK
–0.3
5.5
V
VREG
–0.3
8
V
3.3VDRIVE
–0.3
8
V
1.2VDRIVE
–0.3
8
V
nRST
–0.3
5.5
V
IGN_ST
–0.3
5.5
V
SS
–0.3
7
V
DELAY
–0.3
7
V
COMP
–0.3
7
V
BOOT_LDO
–0.3
9
V
5V
–0.3
7
V
5VS
–1
45
V
Operating junction, TJ
–40
150
°C
Operating ambient temperature, TA
–40
125
°C
Storage, TS
–55
165
°C
PH
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
4
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 12, 13, and 24)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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SLVSC10C – OCTOBER 2013 – REVISED APRIL 2016
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN, VIN_D
5.6
40
V
BOOT
5.6
48
V
PH
–1
40
V
IGN_EN
0
40
V
EN, VSENSE, 3.3VSENSE, 1.2VSENSE, RT/CLK, nRST, IGN_ST
0
5.25
V
VREG, 3.3VDRIVE, 1.2VDRIVE
0
7.5
V
SS, DELAY, COMP
0
6.5
V
BOOT_LDO
0
8.1
V
6.4 Thermal Information
TPS65301-Q1
THERMAL METRIC (1)
PWP (HTSSOP)
RHF (VQFN)
24 PINS
24 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
33.6
30.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.6
30.5
°C/W
RθJB
Junction-to-board thermal resistance
14.5
8.7
°C/W
ψJT
Junction-to-top characterization parameter
0.4
0.3
°C/W
ψJB
Junction-to-board characterization parameter
14.3
8.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.3
1.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 DC Characteristics
VIN = VIN_D = 6 V to 27 V, IGN_EN = VIN, TJ = –40°C to 150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
14
40
UNIT
VIN, VIN_D (Input Power Supply)
VIN, VIN_D
Supply voltage on VIN, line
Normal mode, after initial startup
Iq-Normal
Current normal mode
Open-loop test
ISD
VIN
ISD
VIND
Shut down
5.6
5.57
V
mA
IGN = 0 V, VIN = 12 V, TA = –40°C to 125°C
2.2
15
IGN = 0 V, VIN = 12 V, TA = –40°C to 125°C
2.2
15
µA
IGN_EN (Ignition Input)
VIGN_EN
Input voltage range
Input into IGN_EN pin
VIH
Input high
Enable device to be ON (rising signal)
VIL
Input low
Enable device to be OFF (falling signal)
IIH
Input high
2.2
14
40
V
3.16
3.6
V
3.03
V
Enable device to be ON, VIGN_EN = 18 V
23.7
50
Enable device to be ON, VIGN_EN = 3.7 V
4
7
1.7
2.3
µA
EN (Logic Level Enable)
VIH
Input high
Enable device to be ON (rising signal)
VIL
Input low
Enable device to be OFF (falling signal)
0.7
1.53
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DC Characteristics (continued)
VIN = VIN_D = 6 V to 27 V, IGN_EN = VIN, TJ = –40°C to 150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.45
5.70
V
Switch-Mode Output 5.45 V
VREG
Regulator output internal
resistor network
Fixed output based on internal resistor network
5.30
CO
Output capacitor for 5.45 V
ESR = 0.001 Ω to 100 mΩ; large output
capacitance may be required for load transients
10
rds(on)
Internal switch resistance
Measured across VIN_D and PH pins, IVREG = 1
A
IO-CL
Switch current limit
VIN = 12 V
tON-min
Minimum ON time
Dmax
Maximum duty cycle
µF
Ω
0.3
1.2
2
3
40
A
ns
97%
VSENSE (Internal Reference Voltage)
VREG ref
Internal reference voltage
1.954
2
2.046
V
40
50
60
µA
0.056
0.4
V
0.05
2
µA
SS (Soft-Start Timer for Switch-Mode Converter)
ISS
Soft-start source current
Css = 0.001 µF to 0.01 µF
IGN_ST (Ignition Input Status)
VOL
Output low
Output asserted low when IGN_EN < 2.2 V, IOL =
1 mA
IIH
Leakage test
IGN_ST = 5 V
5V (5-V Linear Regulator)
5VO
Output voltage
IO = 1 mA, VREG = 5.45 V
5
5.1
V
∆VO-Line
Line regulation
5.15 V < VREG < 5.45 V, IO = 1 mA, VIN = 12 V
4.9
10
20
mV
∆VO-Load
Load regulation
1 mA < IO < 200 mA, VREG = 5.45 V, VIN = 12 V
10
30
mV
VDO
Dropout voltage
IO = 150 mA, measure VREG when VO(nom) –
0.1 V, then VDO = VREG – (5VO – 0.1) V, VREG
>5V
0.15
0.26
I5V-CL
Current limit
5VO = 0.8 x 5VO (nom)
CO
Output capacitor
ESR = 0.001 Ω to 2 Ω. Larger output capacitance
may be required for load transients.
PSRR
Power-supply rejection ratio
f = 100 Hz, VREG = 5.45 V, IO = 100 mA, VIN =
12 V
Vsoft-start
Soft start on enable cycle
5VO = 0 V (initially) with fsw = 2.5 MHz
V
350
1080
mA
1
2.2
10
µF
45
60
75
dB
13
ms
3.3-V Linear Regulator Controller (3.3VSENSE)
3.3VO
Output voltage
IO = 5 mA, Vnpn_power input = 5.3 V
∆3.3VO-Line
Line regulation
3.8 V < Vnpn_power input < 7 V (with nRST not
triggered)
3.234
∆3.3VO-Load
Load regulation
5 mA < IO < 550 mA
CO
Output capacitor for 3.3 V
ESR = 0.001 Ω to 2 Ω. Large output capacitance
may be required for load transients.
PSRR
Power-supply rejection ratio
f = 100 Hz, VREG = 5.45 V, IO = 200 mA, VIN =
12 V
tss
Soft-start time
3.3VO = 0 V (initially) with fsw = 2.5 MHz
3.3
3.366
1
10
mV
7.5
30
mV
1
4.7
10
µF
45
60
75
dB
12.3
V
ms
3.3VDRIVE (Example: Switch Control Output)
IOH
Base drive current. NPN turn
ON
3.3VDRIVE – 3.3VSENSE = 1 V
10
28
IOL
NPN turn off
3.3VDRIVE – 3.3VSENSE at 0.2 V
0.1
0.412
1.176
50
mA
mA
1.2-V Linear Regulator Controller (1.2VSENSE)
1.2VO
Output voltage
IO = 5 mA, Vnpn_power input = 5.3 V
1.2
1.224
∆1.2VO-Line
Line regulation
3.25 V < Vnpn_power input < 7 V (with nRST not
triggered)
1
10
mV
∆1.2VO-Load
Load regulation
5 mA < IO < 350 mA
5
15
mV
6
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DC Characteristics (continued)
VIN = VIN_D = 6 V to 27 V, IGN_EN = VIN, TJ = –40°C to 150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
CO
Output capacitor for 1.2 V
ESR = 0.001 Ω to 100 mΩ. Large output
capacitance may be required for load transients.
PSRR
Power-supply rejection ratio
f = 100 Hz, VREG = 6 V, IO = 200 mA, VIN = 12 V
tss
Soft-start time
1.2VO = 0 V (initially) with fsw = 2.5 MHz
MIN
TYP
MAX
8
10
12
60
75
45
UNIT
µF
dB
8.5
ms
1.2VDRIVE (Example: Switch Control Output)
IOH
Base drive current. NPN turn
ON
1.2VDRIVE – 1.2VSENSE = 1 V
10
27
IOL
NPN turn off
1.2VDRIVE – 1.2VSENSE at 0.2 V
0.1
0.47
50
mA
mA
5VS (Protected Sensor Supply Linear Regulator)
VSENSOR
Output tolerant range
VSENSOR output shorted fault conditions
–1
VSENSOR
Output voltage
IO = 1 mA to 100 mA, VREG = 5.45 V
4.9
I5VS_SC
Short circuit current
5VS = 45 V
I5VS
Output current
VREG = 5.45 V
∆5VSLOAD
Load regulation
1 mA < I5VS < 75 mA, VREG = 5.45 V, VIN = 12 V
VDO
Drop out voltage
IO = 150 mA, Measure VREG when 5VS (nom) –
0.1 V
Then VDO = VREG – (5VS – 0.1) V, VREG > 5.1
V
CO
Output capacitor for protected ESR = 0.001 Ω to 2 Ω, Larger output capacitance
5-V supply
may be required for load transients
I5VS-CL
Current limit
5VS = 0.8 x 5VS (nom)
ILkg
Leakage current
EN_LIN_REG = 0 V with VIN = 14 V
Power-supply rejection ratio
f = 100 Hz, VREG = 6 V, I5VS = 75 mA, VIN = 12
V
PSRR
VIN
5
V
5.1
V
2.25
mA
150
mA
15
1
180
320
mV
0.4
V
10
µF
650
mA
5
µA
60
dB
DELAY (Power-On-Reset Delay)
VThreshold
Threshold voltage
ICharge
Capacitor charging current
Threshold to release nRST high
1.3
2.05
2.6
V
1.4
2
2.6
µA
0
0.16
0.4
V
nRST (Reset Indicator)
VOL
Output low
Reset asserted due to falling VREG or 3.3 VO or
1.2 VO output voltages, IOL = 1 mA
tnRSTdly
Filter time
Delay before nRST is asserted low
Trigger nRST for VREG
output
VREG ramp down
0.845
0.875
0.905
VREG
Trigger nRST for 3.3 VO
VREG ramp down
0.9
0.93
0.96
3.3 VO
Trigger nRST for 1.2 VO
VREG ramp down
0.9
0.93
0.96
1.2 VO
Leakage test
Reset = 5 V
0.07
2
VTH_VREG
IIH
11
µs
µA
RT/CLK (Oscillator Setting of External Clock Input)
fsw
Switching freq using RT
mode
2
3
Switching freq using CLK
mode
2
3
MHz
Minimum clock input pulse
duration
Internal oscillator frequency
External clock input
VIH
Input high
VIL
Input low
40
Switching frequency tolerance for clock
ns
–14%
14%
–20%
10%
2.3
0.6
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6.6 Typical Characteristics
5.50
2.10
TA = 25ƒC
Vin = 12 V
VREG (V)
Current Limit (A)
Vin = 6 V
5.45
5.40
Vin = 5.9 V
5.35
1.90
1.70
Vin = 5.8 V
Vin = 5.6 V
1.50
5.30
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0
1.4
I_VREG (A)
3
5
4
6
Temperature (°C)
7
8
9
10
G002
Figure 2. Buck Current Limit vs Temperature
1.994
7
1.993
6
Shutdown Current (µA)
1.992
VSNESE (V)
2
C002
Figure 1. Output Voltage vs Output Current
1.991
1.99
1.989
1.988
1.987
Isd_total
5
4
Isd_vind
3
2
Isd_vin
1
1.986
1.985
-50
1
0
50
Temperature (°C)
100
150
0
-40
-10
0
G003
Figure 3. VSENSE Reference Voltage vs Temperature
25
50
85
Temperature (°C)
100
125
150
G005
Figure 4. Current Consumption IIN vs Temperature
Iq (mA)
4.98
4.92
4.86
4.8
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
G004
Figure 5. Quiescent Current vs Temperature
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6.6.1 5-V Linear Regulator (5 VO)
250
5.015
230
5.01
190
5VLDO
Dropout (mV)
210
170
5.005
5
150
4.995
130
110
−60 −40 −20
0
20 40 60 80
Temperature (°C)
4.99
-50
100 120 140 160
0
50
100
Temperature (°C)
G006
Figure 6. Dropout Voltage vs Temperature
150
G007
Figure 7. Output Voltage 5VO vs Temperature
6.6.2 3.3-V Linear Regulator Controller (3.3 VO)
30
3.314
3.3VSENSE (V)
Base Drive Current (mA)
32
28
26
24
22
3.310
3.306
3.302
-40
-10
0
25
50
85
Temperature (°C)
100
125
3.298
150
-40
-10
0
G008
Figure 8. Output Base Drive vs Temperature
25
50
85
Temperature (°C)
100
125
150
G009
Figure 9. 3.3VSENSE vs Temperature
6.6.3 1.2-V Linear Regulator Controller (1.2 VO)
1.203
30
1.2VSENSE (V)
Base Drive Current (mA)
1.202
28
26
24
1.201
1.2
1.199
1.198
22
1.197
20
-40
-10
0
25
50
85
Temperature (°C)
100
125
1.196
150
-40
-10
G010
Figure 10. Output Base Drive vs Temperature
0
25
50
85
Temperature (°C)
100
125
150
G011
Figure 11. 1.2VSENSE vs Temperature
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7 Detailed Description
7.1 Overview
The device integrates an asynchronous switch-mode power-supply converter with a internal FET that converts
the input battery voltage to a 5.45-V preregulator output. This 5.45-V output supplies the other regulators. The
switching frequency range is from 2 MHz to 3 MHz, allowing the use of low-profile inductors and low value input
and output capacitors. External loop compensation provides flexibility which optimizes the converter response for
the appropriate operating condition.
A fixed 5-V linear regulator with an internal FET is integrated as an external peripheral supply. A fixed 3.3-V
linear regulator controller with external bi-polar transistor is used for an IO supply, for example. A fixed 1.2-V
linear regulator controller with external bi-polar transistor is used for a CPU Core supply, for example. The device
has a voltage supervisor which monitors the output of the switch-mode power supply, the 3.3-V linear regulator,
and the 1.2-V linear regulator.
An external timing capacitor sets the power-on delay and the release of the reset output nRST. This reset output
is also used to indicate if the switch-mode supply, the 3.3-V linear regulator supply, or the 1.2-V linear regulator
supply is outside the set limits. The 5-V regulator tracks the 3.3-V linear regulator within the specified limits.
7.2 Functional Block Diagram
VIN_D
2
VIN
4
EN
9
Buck Regulator
Control
24
PGND
3
BOOT
1
PH
14
COMP
22
VREG
15
VSENSE
19
3.3VDRIVE
18
3.3VSENSE
10
5V
17
1.2VDRIVE
16
1.2VSENSE
7
5VS
23
nRST
Wake Up
COMP
Network
OR
IGN_EN
5
+
RT/CLK
SS
Ref
Error
Amp
±
8
±
+
20
BG Ref
3.3-V Linear
Regulator
Control
BOOT_LDO
GND
6
±
+ 0.8 V
Internal Reg
Regulator
Control
12
±
+ 0.8 V
1.2-V Linear
Regulator
Control
0.8 V
DELAY
21
1.2 V
VREG
3.3 V
±
+
5-V Protected
Sensor Supply
Control
±
+ 0.8 V
Reverse Protected
Voltage Supervisor
with Reset Delay
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Pin numbers apply to the PWP package.
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7.3 Feature Description
7.3.1 Buck Converter
7.3.1.1 PWM Operation
The switch-mode power supply (SMPS) operates in a fixed-frequency pulse-width modulation (PWM) mode. The
switching frequency is set by an external resistor or synchronized with an external clock input. The internal Nchannel MOSFET is turned on at the beginning of each cycle. This MOSFET is turned off when the PWM
comparator resets the latch. Once the high external FET is turned off, the external Schottky diode recirculates
the energy stored in the inductor for the remainder of the switching period.
The external bootstrap capacitor acts as a voltage supply for the internal high-side MOSFET. This capacitor is
recharged on every recirculation cycle (when the internal high-side MOSFET is turned OFF). In case of a VIN
close to the desired output voltage, requiring a nearly 100% duty cycle for the internal high side MOSFET, the
device automatically revert to 87% to allow the bootstrap capacitor to recharge.
7.3.1.2 Voltage-Mode Control Loop
The voltage-mode control monitors the set output voltage and processes the signal to control the internal
MOSFET. A voltage feedback signal is compared to a constant ramp waveform, resulting in a PWM modulation
pulse. An input line-voltage feedforward technique is incorporated to compensate for changes in the input voltage
and ensures the output voltage is stable by adjusting the ramp waveform for the correct duty cycle. The internal
MOSFET is protected from excess power dissipation with a current limit and frequency foldback circuitry during
an output-to-ground short-circuit event.
A combination of internal and external components forms a compensation network to ensure error-amplifier gain
does not cause instability due to input voltage changes or load perturbations.
7.3.1.3 Output Voltage 5.45 V (VREG)
Output voltage VREG is generated by the converter supplied from the battery voltage VIN and the external
components (L, C). The output is sensed through an internal resistor divider and compared with an internal
reference voltage.
This output requires larger output capacitors (4.7-µF to 10-µF range) to ensure that during load transients the
output does not drop below the reset threshold for a period longer than the reset deglitch filter time.
An internal load is enabled for a short period whenever
• a start-up condition occurs, that is, during power up or when IGN_EN or EN is toggled.
• an overvoltage condition exists on this output.
7.3.1.4 Switching Frequency (RT/CLK)
The oscillator frequency of the buck regulator is selectable by means of a resistor placed at the RT/CLK pin to
ground. The switching frequency (fSW) can be set in the range 2 MHz to 3 MHz in this resistor mode.
Alternatively, if there is an external clock input signal, the internal oscillator synchronizes to this signal within 10
µs.
The following equation determines the value of resistor (RT) for the required switching frequency fSW.
RT =
98.4 ´ 109
fSW
(Ohms)
(1)
7.3.1.5 Boost Capacitor (BOOT)
This capacitor provides the gate-drive voltage for the internal MOSFET switch. X7R and X5R grade dielectrics
are recommended due to their stable values over temperature. Usually, a 0.1-µF capacitor is used for the boot
capacitor.
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Feature Description (continued)
7.3.1.6 Soft Start (SS)
To limit the start-up inrush current for the switch-mode supply, an internal soft-start circuit is used to ramp up the
reference voltage from 0 V to the final value of 0.8 V. The regulator uses the internal reference or the SS-pin
voltage as the power-supply reference voltage to regulate the output accordingly. The following equation
determines the soft-start timing.
C ´ 0.8 V
Time (t SS ) =
50 µA
where
•
C = Capacitor on SS pin, usually 0.1 µF or lower
(2)
7.3.1.7 Power-On Delay (DELAY)
The power-on delay function delays the release of the nRST line. The method of operation is to detect when all
VREG (5.45 V), 3.3-V and 1.2-V power-supply outputs are above 90% (typical) of the set value. This then
triggers a current source to charge the external capacitor on the DELAY pin. Once this capacitor is charged to
approximately 2 V, the nRST line is asserted high. The delay time is calculated using the following equation:
2 V´C
tDELAY =
2 mA
where
•
C = capacitor on DELAY pin
(3)
Example: For a 20-ms delay, C = 20 nf.
7.3.1.8 Reset (nRST)
The nRST pin is an open-drain output. The power-on reset signal is a voltage supervisor output to indicate the
output voltages on VREG (5.45 V), 3.3 V, and 1.2 V are within the specified tolerance of their set regulated
voltages. Additionally, whenever both the IGN_EN and EN pins are low or open, nRST is immediately asserted
low regardless of the output voltage. If a thermal shutdown occurs due to excessive thermal conditions, this pin is
asserted low.
Conversely on power down, once the VREG or 3.3V or 1.2V output voltage falls below 90% of its respective set
threshold, nRST is pulled low after a de-glitch filter delay of approximately 15 µs (max). This is implemented to
prevent nRST from being invoked due to noise on the output supplies.
7.3.1.9 Thermal Shutdown
This device has two independent thermal-sensing circuits for the VREG (5.45 V), 5-V regulators; if either one of
these circuits detects the power FET junction temperature to be greater than the set threshold, that particular
output-power switch is turned OFF. The appropriate FET turns back on once it is allowed to cool sufficiently.
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Feature Description (continued)
7.3.1.10 Reset Function
Vin
Vin
SS
SS
Approx 0.9 x 1.2 Vout
1.2 Vout
3.3 Vout
Approx 0.9 x 3.3 Vout
1.2 Vout
Approx 0.9 x 1.2 Vout
3.3 Vout
Approx 0.9 x 3.3 Vout
5.45 V (typ)
5.45 V (typ)
VREG
VREG
Approx 4.91 V
2V
DELAY
DELAY
t delay
nRST
nRST
15 µs ( max- deglitch time)
On power up, ALL three regulated supplies,
VREG, 3.3 V and 1.2 V have to be more than
90% of their respective value before the delay
timer capacitor on delay pin can start charging
On power down, if any one of the three regulated
supplies, VREG, 3.3 V and 1.2 V drops below the
90% RI LW¶V YDOXH Q567 LV DVVHUWHG ORZ DIWHU D VPDOO
deglitch filter time. Once nRST is asserted low, it can
only go high again after ALL three supplies are above
the 90% value and delay pin voltage higher than 2 V.
Figure 12. Reset Function
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Feature Description (continued)
7.3.2 Linear Regulators
7.3.2.1 Fixed Linear Regulator Output (5 V)
This is a fixed, regulated output of 5 V ±2% over temperature and input supply using a precision voltage-sense
resistor network. A low-ESR ceramic capacitor is required for loop stabilization; this capacitor must be placed
close to the pin of the IC. This output is protected against shorts to ground by a foldback current limit for safe
operating conditions, and a current limit for limiting inrush current due to depleted charge on the output capacitor.
Initial IGN_EN or EN initiates power cycle of the soft-start circuit on this regulator. The soft-start takes typically
13 ms. This output may require a larger output capacitor to ensure that during load transients the output does not
drop below the required regulated specifications.
7.3.2.2 Fixed Linear Regulator Controller (3.3 V)
The linear regulator controller requires an external NPN bipolar pass transistor of sufficient gain stage to support
the maximum load current required. The base-drive output current is protected by current limiting both the source
and sink drive circuitry. The 3.3VSENSE pin is the remote sense input of the output of the REG3 supply and
controls the 3.3VDRIVE output accordingly. This regulator is fixed 3.3 V with ±2% tolerance using a precision
voltage-sense resistor network. A low-ESR ceramic output capacitor is used for loop compensation of the
regulator. A voltage on this pin of less than approximately 50% of the regulated value initiates a current limit on
the 3.3VDRIVE output.
This output may require larger output capacitors to support load transients, so the output does not drop below
90% of 3.3 V.
7.3.2.3 Fixed Linear Regulator Controller (1.2 V)
The linear regulator controller requires an external NPN bipolar pass transistor of sufficient gain stage to support
the maximum load current required. The 1.2VSENSE pin is the remote sense input of the output of 1.2-V supply
and controls the 1.2VDRIVE output accordingly. This regulator output is 1.2 V with ±2% tolerance using a
precision voltage-sense resistor network. A low-ESR ceramic output capacitor is used for loop compensation of
the regulator. A voltage on this pin of less than approximately 50% of the regulated value initiates a current limit
on the 1.2VDRIVE output.
This output may require larger output capacitors to support load transients, so the output does not drop below
90% of 1.2 V.
7.3.2.4 Protected Sensor Supply Output (5VS)
This is a fixed regulated output of 5 V ±2% over temperature and input supply using precision voltage sense
resistor network. A low ESR ceramic capacitor is required for loop stabilization; this capacitor must be placed
close to the pin of the IC. This output is protected against shorts to ground by a fold back current limit for safe
operation conditions, and a current limit for limiting in-rush current due to depleted charge on the output
capacitance. This output is also protected against shorts to battery voltage by limiting the reverse current. This
supply can thus be used to power a sensor outside the electrical control unit ECU. On initial IGN_EN or EN
power cycle the soft start circuit on this regulator is initiated. The soft-start takes typically 10 ms. This output may
require larger output capacitor to ensure that during load transients the output does NOT drop below the required
regulated specifications.
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7.4 Device Functional Modes
7.4.1 Operational Mode
The purpose of the EN input is to keep the regulated supplies ON for a period for the microprocessor to log
information into the memory locations once the ignition input is disabled. The microprocessor disables the power
supplies by pulling EN low after this activity is complete (see Table 1).
Table 1. Enable Logic Table
(1)
IGN_EN
EN
nRST
OUTPUTS
H
H
H
ON
H
L
H
ON
L
H
L
L
H
(1)
L
ON (1)
OFF
If IGN_EN was high before.
7.4.2 Buck Converter Modes of Operation
7.4.2.1 Modes of Operation
The converter operates in different modes based on load current, input voltage, and component selection.
7.4.2.1.1 Continuous-Conduction Mode (CCM)
This mode of operation is typically when the inductor current is non-zero and the load current is greater than
IL CCM.
(1 - D) ´ VREG
IIND _ CCM ³
2 ´ fSW ´ L
where
•
•
•
•
•
IIND_CCM = Inductor current in continuous-conduction mode
D = duty cycle
VREG = output voltage
L = Inductor
fSW = switching frequency
(4)
In this mode, the duty cycle should always be greater than the minimum tON or the converter may go into burst
mode.
7.4.2.1.2 Discontinuous Mode (DCM)
IIND _ DCM ³
(1 - D) ´ VREG
2 ´ f SW ´ L
(5)
This mode of operation is typically when the inductor current goes to zero and the load current is less than
IIND DCM.
7.4.2.2 Tracking Mode
When the input voltage is low and the converter approaches approximately 100% duty cycle, the following
equation determines the output voltage.
t OFF _ MIN ö
æ
VREG = çç 1 ÷÷ ´ (VIN - I Load ´ R DS )
T
è
ø
where
•
•
•
T = Period
RDS = Internal FET resistance
ILOAD = Output load current
(6)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This section is a starting point and theoretical representation of the values to be used for the application, further
optimization of the components derived may be required to improve the performance of the device.
8.2 Typical Application
VIN_D
2
3
S1
Supply
VIN
4
1
10 µF
BOOT
0.1 µF
L
6.3 W
10 µH
VREG
5.45 V
PH
10 µF
S2
EN
R2
9
14
30 k
IGN_EN
Vign
6k
RT/CLK
1 nF
5
22
SS
C1
VREG
8
15
R1
COMP
C3
VSENSE
20
TPS65301PWPR-Q1
3k
IGN_ST
BOOT_LDO
PSS302NZ
11
19
6
18
1 µF
GND
10
12
0.5W
5VS
5 VS
1W
3. 3 V
3.3VSENSE
2.2 µF
1W
5V
5 V
2.2 µF
3k
7
23
2.2 µF
DELAY
3.3VDRIVE
17
21
16
C2
nRST
1.2VDRIVE
PSS302NZ
0.48W
1. 2 V
1.2VSENSE
2.2 µF
Copyright © 2016, Texas Instruments Incorporated
L: B82462G4103MOOO (EPCOS) or XFL4020 472MEB (Coilcraft)
S1: MBRS310T3 (ON Semiconductors) or SS3H10 (Vishay)
S2: B240A, SS16 (Vishay)
External BJT: PBSS302NZ (NXP)
Figure 13. Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Switching Regulator Requirements
PARAMETER
REQUIREMENT
Input voltage, VI
6.5 V to 27 V, typical 14 V
Output voltage, 5.45 V
5.45 VO ±2% at 6.3 W
Maximum output current I5.45V_max
1A
Minimum output current I5.45V_min
0.01 A
Transient response 0.01 A to 0.8 A
5%
Reset threshold
90% of output voltage
5V
5 VO at 1 W
3.3V
3.3 VO at 1 W
1.2V
1.2 VO at 0.5 W
5VS
5 VO at 0.5 W
Switching frequency fSW
2.5 MHz
Overvoltage threshold
106% of output voltage
Undervoltage threshold
95% of output voltage
8.2.2 Detailed Design Procedure
The following design procedure provides typical application procedures as well as the details of a switching
regulator design using the requirements listed in Table 2.
8.2.2.1 Duty Cycle
Use Equation 7 to calculate the duty cycle.
V
5.45
D= O =
= 0.389
VI
14
where
•
•
VO = Output voltage
VI = Input voltage
(7)
8.2.2.2 Output Inductor Selection (L)
The minimum inductor value is calculated using the coefficient KIND that represents the amount of inductor ripple
current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor, and
so the typical range of this ripple current is in the range of KIND = 0.2 to 0.3, depending on the ESR and the
ripple-current rating of the output capacitor.
For this design example, use Equation 8 to calculate the inductor ripple current.
IRipple = K IND ´ I O = 0.25 ´ 1 A = 0.25 A
where
•
IO = Output current
(8)
The benefits of a low inductor value include the following:
• Low inductor value gives high di/dt, which allows for fewer output capacitors for good load transient response.
• Gives higher saturation current for the core due to fewer turns
• Fewer turns yields low DCR and therefore less dc inductor losses in the windings.
• High di/dt provides faster response to load steps.
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The benefits of a high inductor value include the following:
• Low ripple current leads to lower conduction losses in MOSFETs
• Low ripple; means lower RMS ripple current for capacitors
• Low ripple; yields low ac inductor losses in the core (flux) and windings (skin effect)
• Low ripple; gives continuous inductor current flow over a wide load range
For this design example a value of 10 μH was selected because of variations in temperature and inductor
tolerance. Use Equation 9 to find the value of LMin.
(VI-Max - VO ) ´ VO
(27 V - 5.45 V) ´ 5.45 V
=
= 7 mH
LMin =
fSW ´ IRipple ´ VI-Max 2.5 MHz ´ 0.25 A ´ 27 V
where
•
•
fSW = the regulator switching frequency
IRipple = Allowable ripple current in the inductor, typically ±20% of maximum output load IO
For this design, use Equation 10 to calculate the inductor peak current.
IRipple
0.25 A
IL-Peak = I O +
=1A+
= 1.125 A
2
2
(9)
(10)
8.2.2.3 Output Capacitor Selection (CO)
The selection of the output capacitor determines several parameters in the operation of the converter, the
modulator pole, the voltage droop on the output capacitor, and the output ripple.
During a load step from no load to full load or changes in the input voltage, the output capacitor must hold up the
output voltage above a certain level for a specified time and not issue a reset until the main regulator control loop
responds to the change. The capacitance value determines the modulator pole and the rolloff frequency due to
the LC output-filter double pole—the output ripple voltage is a product of the output capacitor ESR and ripple
current.
Use Equation 11 to calculate the minimum capacitance required to maintain desired output voltage during a highto-low load transition and prevent overshoot.
CO =
(
2
2
L (IO -max ) - (IO -min )
(VO-max )2 - (VO-min )2
)= 10 mH((1 A ) - (0.01 A ) )= 3.06 µF
2
2
(5.6 V )2 - (5.3 V )2
where
•
•
Io-max is the maximum output current
Io-min is the minimum output current
The difference between the output current, maximum to minimum, is the worst-case load step in the
system.
•
•
Vo-max is maximum tolerance of regulated output voltage
Vo-min is the minimum tolerance of regulated output voltage
(11)
Use Equation 12 to calculate the output capacitor root-mean-square (RMS) ripple current IO_RMS. This is to
prevent excess heating or failure because of high ripple currents.
This parameter is sometimes specified by the manufacturer. Therefore, because of variations in temperature and
manufacture, use a 10-μF capacitor with a voltage rating greater than the maximum 10-V output.
VO ´ (VI-max - VO )
5.45 V ´ (27 V - 5.45 V )
IO _ RMS =
=
= 0.050 A
12 ´ VI-max ´ L ´ fSW
12 ´ 27 V ´ 10 mH ´ 2.5 MHz
(12)
(13)
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8.2.2.4 External Schottky Diode (D) Power Dissipation
The TPS65301-Q1 device requires an external ultrafast Schottky diode with fast reverse-recovery time
connected between the PH and power ground pins. The diode conducts the output current during the off-state of
the internal power switch. This diode must have a reverse breakdown higher than the maximum input voltage of
the application. A Schottky diode is selected for its lower forward voltage. The Schottky diode is selected based
on the appropriate power rating, which factors in the DC conduction losses and the AC losses because of the
high switching frequencies. The power dissipation PD is calculated with Equation 14.
PD = IO ´ VFD ´ (1 - D ) +
(VI - VFD )2 ´ fSW
2
´ CJ
= 1 A ´ 0.55 V ´ (1 - 0.389) +
(14 V - 0.55 V)2 ´ 2.5 MHz ´ 30 pF
= 0.34 W
2
where
•
•
VFD = forward conducting voltage of Schottky diode
CJ = junction capacitance of the Schottky diode
(14)
8.2.2.5 Input Capacitor (CI)
The TPS65301-Q1 requires an input ceramic decoupling capacitor type X5R or X7R and bulk capacitance to
minimize input ripple voltage. The dc voltage rating of this input capacitance must be greater than the maximum
input voltage. The capacitor must have an input ripple-current rating higher than the maximum input ripple
current of the converter for the application. The input capacitors for power regulators are chosen to have
reasonable capacitance-to-volume ratio and to be fairly stable over temperature. The value of the input
capacitance is based on the input voltage desired (∆VI).
Use Equation 15 to calculate the input capacitance.
IO _ max ´ 0.25
1 A ´ 0.25
=
= 0.33 mF
CI =
DVI ´ fSW
0.3 V ´ 2.5 MHz
(15)
Use Equation 16 to calculate the input-capacitor root-mean-square (RMS) ripple current II_RMS.
Because of variations in temperature and manufacture, use a 10-μF capacitor with a voltage rating greater than
the maximum 45-V transient.
II _ RMS = IO ´
VO
VI _ min
æ VI _ min - VO
´ç
ç VI _min
è
ö
5.45 V æ 6 V - 5.45 V ö
´ç
÷ =1A´
÷ = 0.29 A
÷
6V
6V
è
ø
ø
(16)
8.2.2.6 Loop Compensation
The double pole is due to the output-filter components inductor and capacitor. The calculations for the following
equations use values taken from Figure 14.
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8.2.2.6.1 Loop-Control Frequency Compensation
Internal
compensation
L
C2 = 20 pf
C4 = 140 pf
VO = VREG
R3 = 8k
x
C ESR
R4 = 163.36k
C3
R2
CO
C
x
VSENSE
Error
AMP
R5 = 94.7K
x
COMP
Vref = 2 V
Internal Resistor
Divider
Type 3 Compensation
Figure 14. Loop-Control Frequency Compensation
8.2.2.6.1.1 Type III Compensation
fCO = fSW × 0.1 (the cutoff frequency when the gain is 1 is called the unity-gain frequency).
fCO is typically 1/5 to 1/10 of the switching frequency double-pole frequency response due to the LC output filter.
The LC output filter gives a double pole, which has a –180° phase shift.
Make the two zeroes close to the double pole (LC), for example, fZ1 ≈ fZ2 ≈ ½π(LCOUT)½.
1. Make the first zero below the filter double pole (approximately 50% to 75% of fLC)
2. Make the second zero at the filter double pole (fLC)
Make the two poles above the crossover frequency fCO.
3. Make the first pole at the ESR frequency (fESR)
4. Make the second pole at 0.5 the switching frequency
The following compensation components are integrated in the device with the following typical values. Guidelines
for compensation components:
R3 = 8 kΩ, C4 = 140 pF, C2 = 20 pF
Use Equation 17 to calculate the double pole to calculate the output filter components LC.
1
1
fLC =
=
= 15.9 kHz
2p LCO 2p 10 mH ´ 10 mF
(17)
The ESR of the output capacitor C gives a zero that has a 90° phase shift. The ESR of the output capacitor
should be in the range of 1 mΩ to 100 mΩ. Use Equation 18 to calculate the value of fESR.
1
1
fESR =
=
= 3.2 MHz
2p ´ CO ´ ESR 2p ´ 10 mF ´ 0.005 W
(18)
20
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8.2.2.6.1.2 PWM Modulator Gain K
K=
VI
Vramp
where
•
Vramp = VI / 10, VI = Input operating voltage
(19)
8.2.2.6.1.3 Resistor Values
In this design example, select a value of 94.7 kΩ for R5 and use Equation 20 to calculate the value of R4.
R5 ´ (VO - Vref ) 94.7 kΩ ´ (5.45 V - 2 V)
R4 =
=
= 163.36 kΩ
Vref
2V
(20)
Use Equation 21 to calculate the value of R2 for this design example.
fCO ´ Vramp ´ R4 250 kHz ´ 1.4 V ´ 163.36 kΩ
=
= 256.9 kΩ
R2 =
fLC ´ VI
15.9 kHz ´ 14 V
(21)
Calculate C3 based on placing a zero at 50% to 75% of the output-filter double-pole frequency (below set at
50%).
For this design example, use Equation 22 to calculate the value of C3 as 786 pF.
1
1
C3 =
=
= 786 pF
p ´ R2 ´ fLC p ´ 256.9 kΩ ´ 15.9 kHz
(22)
8.2.2.6.1.4 Gain of Amplifier
AV =
R2 ´ (R4 + R3)
(R4 ´ R3)
(23)
8.2.2.6.1.5 Poles and Zero Frequencies
The following equations were used in this design example:
1
1
fP1 =
=
= 30.98 kHz
2p ´ R2 ´ C2 2p ´ 256.9 kΩ ´ 20 pF
1
1
fP2 =
=
= 142.1 kHz
2p ´ R3 ´ C4 2p ´ 8 kΩ ´ 140 pF
1
1
fZ1=
=
= 7.93 kHz
2p ´ R2 ´ C3 2p ´ 264.2 kΩ ´ 76 pF
1
1
=
= 6.77 kHz
fZ2 =
2p ´ R4 ´ C4 2p ´ 168 kΩ ´ 140 pF
(24)
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Open Loop Error
Amp Gain
fP1 fP2
Gain (dB)
fZ1 fZ2
Modulator Gain
Compensation
Gain
Closed Loop Gain
fLCo
fESR
Frequency
Figure 15. Typical Gain vs Frequency
8.2.2.7 Power Dissipation
8.2.2.7.1 Switch-Mode Power-Supply Losses
The power dissipation losses are applicable for continuous-conduction mode operation (CCM).
1. Conduction losses
P5.45V_CON = IO2 × Rds(on) × (VO/VI)
where
•
•
•
•
IO = Output current
VO = VREG = Output voltage
VI = Input voltage
fSW = Switching frequency
(25)
2. Switching losses
P5.45V_SW = ½ × VI × IO × (tr + tf) × fSW
where
•
•
tr = FET switching rise time (tr max = 20 ns)
tf = FET switching fall time (tf max = 20 ns)
(26)
3. Gate drive losses
P5.45V_Gate = Vdrive × Qg × fsw
where
•
•
Vdrive = FET gate-drive voltage (typically Vdrive = 6 V and Vdrive max = 8 V)
Qg = 1 × 10–9 (nC) (typical)
(27)
4. Supply losses
PIC = VI × Iq-normal
(28)
Therefore:
PTotal = PCON + PSW + PGate + P5V_Lin Reg + PIC
22
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8.2.2.7.2 Linear Regulator (5V) and Sensor Supply (5VS)
P5V_Lin Reg = (VREG – 5 V) × IO_5V
P5VS_Lin Reg = (VREG – 5 V) × IO_5VS
(30)
(31)
Therefore, for this design, the following equations were used:
2
P5.45V _ CON = IO2 ´ RdsON ´ (VO / VI ) = (1 A ) ´ 0.5 W ´ (5.45 V / 14 V) = 0.195 W
P5.45_SW = 1/ 2 ´ VI ´ IO ´ (tr + tf ) ´ fSW
= 1/ 2 ´ 14 V ´ 1 A ´ (20 ns + 20 ns) ´ 2.5 MHz = 0.7 W
P5.45V_Gate = Vdrive ´ Qg ´ fSW = 8 V ´ 1 nC ´ 2.5 MHz = 0.02 W
P5V _ Lin _ Re g = (VREG - 5 V) ´ IO = (5.45 V - 5 V) ´ 0.2 A = 0.09 W
P5VS _ Lin _ Re g = (VREG - 5 V) ´ IO = (5.45 V - 5 V) ´ 0.1 A = 0.045 W
PIC = VI ´ IIC = 14 V ´ 5.47 mA = 0.08 W
PTotal = P5.45V _ CON + P5.45V _ SW + P5.45V _ Gate + P5V _ LinRe g + P5VS _ LinRe g + PIC
= 0.195 W + 0.7 W + 0.02 W + 0.09 W + 0.045 W + 0.08 W = 1.13 W
(32)
8.2.2.7.3 Total Power Dissipation
For given operating ambient temperature, TA:
TJ = TA + Rth × PTotal
where
•
•
•
•
TJ = Junction temperature in °C
TA = Ambient temperature in °C
Rth = Thermal resistance of package in (°C/W)
PTotal = Total power dissipation (watts)
(33)
For a given max junction temperature TJ-Max = 150°C
TA-Max = TJ-Max – Rth × PTotal
where
•
•
TA-Max = Maximum ambient temperature in °C
TJ-Max = Maximum junction temperature in °C
(34)
Other factors not included in the foregoing information which affect the overall efficiency and power losses are
• Inductor AC and DC losses
• Trace resistance and losses associated with the copper trace routing connection
• Schottky diode
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JESD51-5
3.0
Power Dissipation (W)
www.ti.com
2.0
1.0
45
80
Ambient Temperature (°C)
115
150
Figure 16. Power Dissipation Derating Profile, 24-Pin PWP Package With Thermal Pad
8.2.3 Application Curves
1
Efficiency
0.8
0.6
Vin = 12 V
Vin = 7 V
0.4
Vreg=5
Fsw=2245 kHz
L=10 uH
Co=10 uF
0.2
0
0
200
600
400
800
Output Current (mA)
1000
A001
G001
Figure 17. Efficiency vs Output Current on VREG
24
1200
Figure 18. VREG Load Transient Response, 10 mA to 1 A
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A002
Figure 19. VREG Load Transient Response, 10 mA to 200
mA
A003
Figure 20. VREG Load Transient Response, 10 mA to 550
mA
A004
Figure 21. VREG Load Transient Response, 10 mA to 350 mA
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9 Power Supply Recommendations
The TPS65301-Q1 device is designed to operate using an input supply voltage range from 5.6 V to 40 V.
10 Layout
10.1 Layout Guidelines
The following guidelines are recommended for PCB layout of the TPS65301-Q1 device.
10.1.1 Inductor (L)
Use a low-EMI inductor with a ferrite-type shielded core. Other types of inductors may be used; however, they
must have low-EMI characteristics and be located away from the low-power traces and components in the circuit.
10.1.2 Input Filter Capacitors (CI)
Input ceramic filter capacitors should be located in close proximity to the VIN pin. Surface-mount capacitors are
recommended to minimize lead length and reduce noise coupling.
10.1.3 Feedback
Route the feedback trace such that there is minimum interaction with any noise sources associated with the
switching components. Recommended practice is to ensure placing the inductor away from the feedback trace to
prevent a source of EMI noise.
10.1.4 Traces and Ground Plane
All power (high-current) traces should be thick and as short as possible. The inductor and output capacitors
should be as close to each other as possible. This reduces EMI radiated by the power traces due to high
switching currents.
In a two-sided PCB it is recommended to have ground planes on both sides of the PCB to help reduce noise and
ground-loop errors. The ground connection for the input and output capacitors and IC ground should be
connected to this ground plane.
In a multi-layer PCB, the ground plane is used to separate the power plane (where high switching currents and
components are placed) from the signal plane (where the feedback trace and components are) for improved
performance.
Also arrange the components such that the switching-current loops curl in the same direction. Place the highcurrent components such that during conduction the current path is in the same direction. This prevents magnetic
field reversal caused by the traces between the two half-cycles, helping to reduce radiated EMI.
26
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10.2 Layout Example
10 µF
S2
L
nRST
VREG
5.45 V
TPS65301PWPRQ1
1
PH
2
VIN_D
nRST
3
BOOT
VREG 22
4
VIN
5
IGN_EN
6
Vign
5VS
PGND 24
3k
0.1 µF
S1
23
C2
Supply
DELAY
21
SS
20
BOOT_LDO
3.3VDRIVE
19
7
5VS
3.3VSENSE
18
8
RT/CLK
1.2VDRIVE
17
9
EN
1.2VSENSE
16
10 µF
1 nF
6k
30 k
1 µF
C1
2.2 µF
R1
2.2 µF
T1
Enable
2.2 µF
5V
3.3 V
T2
10
5V
11
IGN_ST
VSENSE
15
COMP
14
1.2 V
C3
2.2 µF
3k
IGN_ST
12
GND
Exposed Thermal Pad
Connected to Ground
Plane
R2
NC
13
Connection to backside of PCB through vias
Connection to topside of PCB through vias
Connection to ground plane of PCB through vias
Power bus
Voltage Output rails
T1, T2 are PSS302NZ, sufficent heat sink may be required for power
dissipation
Figure 22. PCB Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
TPS65301EVM User’s Guide, SLVU929
11.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65301QPWPRQ1
ACTIVE
HTSSOP
PWP
24
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS65301
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
