RGT
TPS65561
www.ti.com
SLVS691 – FEBRUARY 2007
INTEGRATED PHOTO FLASH CHARGER AND IGBT DRIVER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
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Highly Integrated Solution to Reduce
Components
Integrated Voltage Reference
Integrated 50-V Power Switch,
Integrated IGBT Driver
High Efficiency
Programmable Peak Current: 1.1 A to 2.2 A
Input Battery Voltage of 1.6 V to 12 V
Optimized Control Loop for Fast Charge Time
Output Voltage Feedback From Primary Side
16-Pin QFN Package
Protection
– MAX On Time
– MAX Off Time
– Overcurrent Shutdown to Monitor VDS at
the SW pin (OVDS)
– Thermal Monitor
Digital Still Cameras
Optical Film Cameras
DESCRIPTION
This device offers a complete solution for charging a
photo flash capacitor from a battery input, and
subsequently discharging the capacitor to a xenon
flash tube. The device has an integrated voltage
reference, power switch, IGBT driver, and control
logic blocks for capacitor charging applications and
driving IGBT applications. Compared with discrete
solutions, this device reduces the component count,
shrinks the solution size, and eases designs for
xenon tube applications. Additional advantages are a
fast charging time and high efficiency from an
optimized PWM control algorithm.
Other provisions of the device includes sensing the
output voltage from the primary side, programmable
peak current, thermal shutdown, an output pin for
charge completion, and input pins for charge enable
and flash enable.
D1
T1
VCC
VCC
VA
VO
C1
SW
VBAT
VI/F
VI/F
CHG
D Q
F1
Controller
0 Vds
XFULL
or
R1
D Q
F2
U1
ENA
V_FULL
D/A Conv
VCC
ENA
or
Analog
Circuit
U0
Max ON
U2
I_PEAK
LOGIC
TSD
I_PEAK
Ref.
Vref
SW
PGND
U3
or
VCC
F_ON
ENA
G_IGBT
U4
SW1
IGBT
NC
Figure 1. Typical Application Circuit
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPS65561
www.ti.com
SLVS691 – FEBRUARY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
TA
PACKAGE MARKING
PACKAGE (1)
PART NUMBER
-35°C to 70°C
BUO
16-pin QFN
TPS65561RGT
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
VCC
-0.6 V to 6 V
VBAT
-0.6 V to 13 V
VSS
Supply voltage
V(SW)
Switch terminal voltage
I(SW)
Switch current between SW and PGND
VI
Input voltage of CHG, I_PEAK, F_ON
Tstg
Storage temperature
TJ
Maximum junction temperature
ESD rating
(1)
-0.6 V to 50 V
3A
-0.3 V to VCC
-40°C to 150°C
125°C
HBM (Human Body Model) JEDEC JES22-A114
1kV
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Supply voltage, VCC
2.7
4
V
Supply voltage, VBAT
1.6
12
V
V(SW)
Switch terminal voltage
-0.3
45
V
I(SW)
Switch current between SW and PGND
VSS
Operating free-air temperature range
-35
VIH
High-level digital input voltage at CHG and F_ON
VIL
Low-level digital input voltage at CHG and F_ON
2.5
A
70
°C
2
V
0.5
DISSIPATION RATINGS
(1)
2
PACKAGE
RθJA (1)
POWER RATING
TA < 25°C
POWER RATING
TA = 70°C
QFN
47.4 °C/W
2.11 W
1.16 W
The thermal resistance, RθJA, is based on a soldered PowerPAD™ on a 2S2P JEDEC board using thermal vias.
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TPS65561
www.ti.com
SLVS691 – FEBRUARY 2007
ELECTRICAL CHARACTERISTICS
TA = 25°C, VBAT = 4.2 V, VCC = 3 V, V(SW) = 4.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.5
3
UNIT
R(ONL)
ON resistance of XFULL
I(XFULL) = -1 mA
V(PKH) (1)
Upper threshold voltage of
I_PEAK
VCC = 3 V
V(PKL) (1)
Lower threshold voltage of
I_PEAK
VCC = 3 V
ICC1
Supply current from VBAT
CHG = H, V(SW) = 0 V
(free run by tMAX)
ICC2
Supply current from VCC
CHG = H, V(SW) = 0 V
(free run by tMAX)
ICC3
Supply current from VCC and
VBAT
CHG = L
Ilkg1
Leakage current of SW terminal
Ilkg2
Leakage current of XFULL
terminal
I(sink)
Sink current at I_PEAK
R(ONSW)
SW ON resistance between
SW and PGND
I(SW) = 1 A, VCC = 3 V
R(IGBT1)
G_IGBT pullup resistance
V(G_IGBT) = 0 V, VCC = 3 V
R(IGBT2)
G_IGBT pulldown resistance
V(G_IGBT) = 3 V, VCC = 3 V
I(PEAK1)
Upper peak of I(SW)
V(I_IPEAK) = 3 V
I(PEAK2)
Lower peak of I(SW)
V(I_IPEAK) = 0 V
V(FULL)
Charge completion detect voltage
at V(SW)
VBAT = 1.6 V, VCC = 3 V
V(ZERO)
Zero current detection at V(SW)
1
20
60
mV
T(SD) (1)
Thermal shutdown temperature
150
160
170
°C
Over VDS detection at V(SW)
2.4
V
0.6
V
17
50
µA
1.3
3
mA
1
µA
2
µA
1
µA
V(XFULL) = 5 V
V(I_PEAK) = 3 V, CHG: High
2
V(I_PEAK) = 3 V, CHG: Low
0.1
VCC = 3 V
kΩ
µA
0.4
0.9
Ω
8
12
19.4
Ω
36
53
70
Ω
2
2.2
2.4
A
1
1.1
1.2
A
28
28.7
29.4
28.6
29
29.4
V
1.35
1.65
1.95
V
t MIN
MAX OFF time
25
50
80
µs
tMAX
MAX ON time
50
100
160
µs
R(INPD)
Pulldown resistance of CHG,
F_ON
(1)
VCHG = V(F_ON) = 4.2 V
100
kΩ
Specified by design.
SWITCHING CHARACTERISTICS
TA = 25°C, VBAT = 4.2 V, VCC = 3 V, V(SW) = 4.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
F_ON↑↓ - G_IGBT↑↓
tPD (1)
(1)
Propagation delay
MIN
TYP
MAX
UNIT
50
ns
SW ON after V(SW) dips from
V(ZERO)
500
ns
SW OFF after I(SW) exceeds I(PEAK)
270
ns
XFULL↓ after V(SW) exceeds V(FULL)
400
ns
SW ON after CHG↑
12
µs
SW OFF after CHG↓
20
ns
Specified by design.
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TPS65561
www.ti.com
SLVS691 – FEBRUARY 2007
PIN ASSIGNMENT
2
3
F_ON
4
TEST_GND
PGND
11
PGND
10
CHG
PowerPAD
5
NC
SW
VCC
16 15 14 13
12
6
7
8
9
XFULL
NC
1
I_PEAK
G_IGBT
SW
NC
NC
VBAT
RGT
(Top View)
NC − No internal connection
TERMINAL FUNCTIONS
PIN NUMBER
SW
3
VCC
4
F_ON
5, 8, 13, 16
I/O
DESCRIPTION
O
Primary side switch. Connect SW to the switched side of the transformer
I
Power supply input. Connect VCC to an input supply from 2.7 V to 4 V. Bypass VCC to
GND with a 1-µF ceramic capacitor as close as possible to the IC.
I
IGBT gate control input. A logic high on F_ON when CHG is low will drive the gate of the
IGBT high to initiate a flash. See the IGBT Driver Control section SubSec1 1 for details.
NC
No internal connection.
I
Primary side peak current control input. The voltage at I_PEAK sets the peak current into
SW. See the Programming Peak Current section for details on selecting V(I_PEAK).
G_IGBT
O
IGBT gate driver output. G_IGBT swings from PGND to VCC to drive external IGBT devices.
9
XFULL
O
Charge completion indicator output. XFULL is an open-drain output that pulls low once the
output is fully charged. XFULL is high impedance during charging and all fault conditions.
XFULL is reset when CHG turns Low from High. See the Indicating Charging Status section
for details.
10
CHG
I
6
I_PEAK
7
11, 12
4
SIGNAL
1, 2
Charge control input. Drive CHG high to initiate charging of the output. Drive CHG low to
terminate charging.
PGND
Power ground. Connect to the ground plane.
14
TEST_GND
Used by TI, should be connected to PGND and ground plane.
15
VBAT
I
Battery voltage monitor input. Connect VBAT to an input supply from 1.6 V to 12 V. Bypass
VBAT to GND with a 10-µF ceramic capacitor (C1 in Figure 1, as close as possible to the
battery) and a 1-µF ceramic capacitor (C2 in Figure 1, as close as possible to the IC). There
are no power sequencing requirements between VBAT and VCC.
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TPS65561
www.ti.com
SLVS691 – FEBRUARY 2007
FUNCTIONAL BLOCK DIAGRAM
VCC
VBAT
CHG
SW
D Q
F1
XFULL
0 Vds
D Q
F2
U1
ENA
V_FULL
VCC
ENA
Max ON
U2
U0
TSD
I_PEAK
Logic
I_PEAK
Ref.
Vref
PGND
SW
U3
VCC
F_ON
ENA
G_IGBT
U4
NC
Figure 2. Functional Block Diagram
I/O Equivalent Circuits
CHG, F_ON
SW
VCC
SW
CHG,
F_ON
PGND
PGND
I_PEAK
XFULL
VCC
XFULL
I_PEAK
PGND
PGND
G_IGBT
VBAT
VCC
VBAT
G_IGBT
PGND
PGND
Figure 3. I/O Equivalent Circuits
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TPS65561
www.ti.com
SLVS691 – FEBRUARY 2007
PRINCIPLES OF OPERATION
CHG
(VOUT)
XFULL
F_ON
G_IGBT
(ENA)
TimeA
TimeB
TimeC
TimeD
TimeE
TimeF
TimeH
TimeI
TimeJ
TimeG
Figure 4. Whole Operation Sequence Chart
Start/Stop Charging
TPS65561 has one internal enable latch, F1, that holds the charge enable (ON/OFF status) of the device. See
Figure 2.
The only way to start charging is to input CHG↑ (see time A/C/H in Figure 4). Each time CHG↑ is applied, the
TPS65561 starts charging.
There
1.
2.
3.
are three trigger events to stop charging:
Forced stop by inputting CHG = L from the controller (see timeB in Figure 4).
Automatic stop by detecting a full charge. VOUT reaches the target value (see TimeD in Figure 4).
Protected stop by detecting an over current function (OVDS) trigger at SW pin (see TimeI in Figure 4).
Indicating Charging Status
When the charging operation is complete, the TPS65561 drives the charge completion indicator pin, XFULL, to
GND. A controller can detect the status of the device as a logic signal when connected through a pullup resister,
R1 (see Figure 1).
The XFULL output enables the controller to detect the OVDS protection status. If OVDS protection occurs, XFULL
never goes L during CHG = H. Therefore, the controller detects OVDS protection by measuring the time from
CHG high to XFULL low. If the time to XFULL low is longer than the maximum designed charge time, then an
OVDS protection occurred.
The device starts charging at timeH, and OVDS protection occurs at TimeI (see Figure 4). At TimeI, XFULL stays
high. At TimeJ, the controller detects OVDS protection through the expiration of a timer and then sets CHG to low
to terminate the operation.
6
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TPS65561
www.ti.com
SLVS691 – FEBRUARY 2007
CHG
SW
LOGIC
OFF
ON
OFF
XFULL
V(SW)
V(ZERO)
SW
OFF
ON
OFF
OFF ON
OFF
V
V(SW)
V(BAT)
V(FULL)
V
0V
VA
VBAT
VOUT
0V
VBAT
V(SW)
VOUT
V
0V
VA
V
0V
I(SW)
I
VOUT
VA
I(PEAK)
0A
I
I
IOUT
I(PEAK)/N(TURN)
0A
Time 1
Time 2
T
Time 3
Time 5
Time 4
Figure 5. Timing Diagram at One Switching Cycle
I(SW)
0A
I
0A
I(PEAK)
IOUT
I(PEAK)/N(TURN)
I(SW)
IOUT
T
Figure 6. Timing Diagram at Beginning/Ending
Control Charging
The TPS65561 provides three comparators to control charging. Figure 2 shows the block diagram of TPS65561
and Figure 5 shows a timing diagram of one switch cycle. Note that emphasis is placed on Time1 and Time3 of
the waveform in Figure 5.
While SW is ON (Time1 to Time2 in Figure 5), U3 monitors current flow through the integrated power switch
from SW pin to GND. When I(SW) exceeds I(PEAK), SW turns OFF (Time2 in Figure 5).
When SW turns OFF (Time2 in Figure 5), the magnetic energy in the transformer starts discharging. Meanwhile,
U2 monitors the kickback voltage at the SW terminal. As the energy is discharging, the kickback voltage is
increasing according to the increase of VO (Time2 to Time3 in Figure 5). When almost all energy is discharged,
the system cannot continue rectification via the diode, and the charging current of IO goes to zero (Times3 in
Figure 5). After rectification stops, the small amount of energy left in the transformer is released via parasitic
paths, and the kickback voltage reaches zero (Time3 to Time4 in Figure 5). During this period, U2 makes SW
turn ON when (V(SW) - VBAT) dips from V(ZERO) (Time5 in Figure 5). In the actual circuit, the period between
Time4 and Time5 in Figure 5 is small or does not appear dependent on the delay time of the U2 detection to SW
ON.
U1 also monitors the kickback voltage. When (V(SW) - VBAT) exceeds V(FULL), the TPS65561 stops charging (see
Figure 6).
In Figure 5 and Figure 6, ON time is always the same period in every switch cycle. The ON time is calculated by
Equation 1. L and I(PEAK) are selected to ensure that tON does not exceed the MAX ON time (tMAX).
I
tON = L PEAK
VBAT
(1)
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TPS65561
www.ti.com
SLVS691 – FEBRUARY 2007
The OFF time is dependant on output voltage. As the output voltage gets higher, the OFF time gets shorter (see
Equation 2).
I
tOFF = NTURN x L PEAK
VOUT
(2)
Programming Peak Current
The TPS65561 provides a method to program the peak primary current with a voltage applied to the I_PEAK
pin. Figure 7 shows how to program I(PEAK).
The I_PEAK input is treated as a logic input below V(PKL) (0.6 V) and above V(PKH) (2.4 V). Between V(PKL) and
V(PKH), I_PEAK input is treated as an analog input. Using this characteristic, I(PEAK) can be set by a logic signal or
by an analog input.
Typical usages of this function are:
1. Setting the peak charging currents based on the battery voltage. Larger I(PEAK) for a fully charged battery
and lower I(PEAK) for a discharged battery.
2. Reducing I(PEAK) when powering a zooming lens motor. This avoids inadvertent shutdowns due to large
current from the battery.
In Figure 1, three optional connections to I_PEAK are shown.
1. Use the controller to treat I_PEAK as the logic input pin. This option is the easiest.
2. Use a D/A converter to force I(PEAK) to follow analog information, such as battery voltage.
3. Use an analog circuit to achieve the same results as the D/A converter.
Peak of I(SW)
I(PEAK1)
I(PEAK2)
V(PKL)
V(PKH)
Voltage of I(PEAK) - V
Figure 7. I_PEAK vs I(SW)
8
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TPS65561
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SLVS691 – FEBRUARY 2007
IGBT Driver Control
The IGBT driver is provided by the TPS65561. The driver voltage depends on VCC. TPS65561 has a mask filter
as shown in Figure 8. The mask does not have hysteresis; therefore, there is no wait time from CHG forcing Low
after FULL CHARGE to F_ON turning High.
CHG
XFULL
F_ON
G_IGBT
STANDBY
PREACTIVE
SW On
SW Off
etc
FULL CHARGE
STANDBY
Figure 8. IGBT Timing Diagram
Protections
TPS65561 provides four protection mechanisms: max on time, max off time, thermal disable, and overcurrent
shutdown.
MAX On Time
To prevent a condition such as pulling current from a poor power source (i.e., an almost empty battery), and
never reaching peak current, the TPS65561 provides a maximum ON time function. If the ON time exceeds tMAX,
the TPS65561 is forced OFF regardless of I(PEAK) detection.
MAX Off Time
To prevent a condition such as never increasing the voltage at the SW pin when the internal FET is OFF, the
TPS65561 provides a maximum OFF time function. If the OFF time exceeds tMIN, the TPS65561 is forced ON
regardless of V(ZERO) detection.
Thermal Disable
Once the TPS65561 die temperature reaches 160°C, all functions stop. Once the die cools below 160°C, the
TPS65561 restarts charging if CHG remains high during the entire overtemperature condition.
Overcurrent Shutdown to Monitor VDS at the SW Pin (OVDS)
The TPS65561 provides an overvoltage monitor function of the SW pin. The TPS65561 is latched off if the
voltage on the SW pin is above OVDS during the switch ON time (see Figure 4 and its descriptions).
This function protects against a shorted primary winding of the flyback transformer. A short-circuit on the primary
winding shorts the battery voltage to GND through the SW pin which could damage the device.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65561RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-35 to 85
BUO
TPS65561RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-30 to 85
BUO
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of