TPS65580
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SLVSC29B – SEPTEMBER 2013 – REVISED DECEMBER 2013
4.5V to 18V Input 1.5A, 2.5A, 1.5A Triple Synchronous Step-Down Converter
Check for Samples: TPS65580
FEATURES
APPLICATIONS
•
•
1
2
•
•
•
•
•
•
•
•
•
•
•
•
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•
Advanced D-CAP2™ Control Mode
– Fast Transient Response
– No External Parts Required For Loop
Compensation
– Compatible with Ceramic Output
Capacitors
Wide Input Voltage Range : 4.5 V to 18 V
Output Voltage Range : 0.76 V to 7.0 V
Highly Efficient Integrated FETs Optimized for
Low Duty Cycle Applications
– 160 mΩ (High Side) and 130 mΩ (Low Side)
for 2.5A
– 250mΩ (High Side) and 230mΩ (Low Side)
for 1.5A
High Initial Reference Accuracy
Low-Side RDS(on) Loss-Less Current Sensing
Fixed 1.2 ms Soft Start
Non-Sinking Pre-Biased Soft Start
700 kHz Switching Frequency
Cycle-by-Cycle Over-Current Limiting Control
OCL, OVP, UVP, UVLO, TSD Protections
Hiccup Timer for Over Load Protection
PowerGood
Adaptive Gate Drivers with Integrated Boost
PMOS Switch
OCP Constant Due To Thermally Compensated
rds(on) with 4000ppm/℃
℃
20-Pin HTSSOP
Point-of-Load Regulation in Low Power
Systems for Wide Range of Applications
– Digital TV Power Supply
– Networking Home Terminal
– Digital Set Top Box (STB)
– DVD Player/Recorder
– Gaming Consoles and Other
DESCRIPTION
The TPS65580 is a triple, advanced D-CAP2™ mode
synchronous buck converter. The TPS65580 enables
system designers to complete the suite of various
end equipment’s power bus regulators with a cost
effective, low component count, and low standby
current solution. The main control loops of the
TPS65580 uses the advanced D-CAP2™ mode
control which provides a fast transient response with
no external compensation components. The
TPS65580 is able to adapt to both low equivalent
series resistance (ESR) output capacitors such as
POSCAP or SP-CAP, and ultra-low ESR, ceramic
capacitors. The device provides convenient and
efficient operation with input voltages from 4.5V to
18V.
The TPS65580 is available in 4.4mm × 6.5mm 20 pin
TSSOP (PWP) package, and is specified from –40°C
to 85°C ambient temperature range.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP2, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS65580
SLVSC29B – SEPTEMBER 2013 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
HTSSOP APPLICATION DIAGRAM
Input Voltage
1 VIN
VBST2 20
2 VIN
SW2 19
C32
C11
3 VBST1
L11
VO1
L12
VO2
C22
PGND2 18
C31
4 SW1
PGND
EN2 17
C21
5 PGND1
TPS65580
PGND3 16
PGND
L13
C4
PGND
6 VREG5
PGND
HTSSOP20
(PowerPAD)
C23 VO3
SW3 15
C33
7 PG
VBST3 14
8 EN1
EN3 13
9 VFB1
VFB3 12
10 GND
VFB2 11
R13
R1１
R21
R12
R23
R22
SGND
SGND
SGND
SGND
ORDERING INFORMATION
TA
–40℃ to 85℃
(1)
2
PACKAGE
(1)
ORDERING PART NUMBER
PWP
TPS65580PWPR
TPS65580PWP
PINS
OUTPUT SUPPLY
ECO PLAN
Tape-and-Reel
Green (RoHS & no Sb/Br)
20
Tube
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1) (2)
VALUE
Input voltage range
MIN
MAX
VIN, EN1, EN2, EN3
–0.3
20
VBST1, VBST2, VBST3
–0.3
26
VBST1, VBST2, VBST3 (10ns transient)
–0.3
28
VBST1–SW1, VBST2–SW2, VBST3–SW3
–0.3
6.5
VFB1, VFB2, VFB3
–0.3
6.5
–2
20
SW1, SW2, SW3
SW1, SW2, SW3 (10ns transient)
Output voltage range
Electrostatic discharge
UNIT
–3
22
VREG5, PG
–0.3
6.5
PGND1, PGND2, PGND3
–0.3
0.3
Human Body Model (HBM)
V
V
2
Charged Device Model (CDM)
kV
500
V
TA
Operating ambient temperature range
–40
85
°C
TSTG
Storage temperature range
–55
150
°C
TJ
Junction temperature range
–40
150
°C
(1)
(2)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to IC GND terminal.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS65580
PWP (20) PINS
θJA
Junction-to-ambient thermal resistance
40.0
θJCtop
Junction-to-case (top) thermal resistance
24.8
θJB
Junction-to-board thermal resistance
21.3
ψJT
Junction-to-top characterization parameter
0.8
ψJB
Junction-to-board characterization parameter
21.1
θJCbot
Junction-to-case (bottom) thermal resistance
1.7
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VALUES
Supply input voltage range
Input voltage range
MIN
MAX
4.5
18
VBST1, VBST2, VBST3
–0.1
24
VBST1, VBST2, VBST3 (10ns transient)
–0.1
27
VBST1–SW1, VBST2–SW2, VBST3–SW3
–0.1
5.7
VFB1, VFB2, VFB3
–0.1
5.7
EN1, EN2, EN3
–0.1
18
SW1, SW2, SW3
–1.0
18
–3
21
VREG5, PG
–0.1
5.7
PGND1, PGND2, PGND3
–0.1
0.1
VIN
SW1, SW2, SW3 (10ns transient)
Output voltage range
UNIT
V
V
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating Junction Temperature
–40
150
°C
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TPS65580
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ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IIN
VIN supply current
TA = 25°C, EN1 = EN2 = EN3 = 5 V,
VFB1 = VFB2 = VFB3 = 1.0 V, Nonswitching
2.9
3.6
mA
IVINSDN
VIN shutdown current
TA = 25°C, EN1 = EN2 = EN3 = 0 V
1.8
3
µA
764
776
mV
180
ppm/℃
VFB VOLTAGE
VVFBTHLx
TCVFBx
VFBx threshold voltage (1)
Temperature coefficient
TA = 25°C, VO1=3.3V, VO2=1.2V,
VO3=1.5V
On the basis of 25°C
752
(2)
–180
VREG5 OUTPUT
VREG5 Rising
4.0
Hysteresis
0.3
VREG5 output voltage
TA = 25°C, VIN = 12 V, IVREG = 5 mA
5.5
Output current
VIN = 6 V, TA = 25°C
rDS(on)H2
High side switch resistance for 2.5A
TA = 25℃, VBST2-SW2 = 5.5 V
rDS(on)L2
Low side switch resistance for 2.5A
TA = 25℃
VUVREG5
VREG5 UVLO Threshold
VVREG5
IVREG5
20
V
V
mA
MOSFETs
(2)
, CH2
(2)
, CH2
rDS(on)Hx
High side switch resistance for 1.5A
TA = 25℃, VBSTx-SWx = 5.5 V
CH3
rDS(on)Lx
Low side switch resistance for 1.5A
TA = 25℃
(2)
, CH1,
(2)
, CH1, CH3
160
mΩ
130
mΩ
250
mΩ
230
mΩ
MIN ON/OFF TIME and SWfrequency
TONminx
Min On Time
TA = 25℃, VOUT = 0.8V (2)
TOFFminx
Min Off Time
TA = 25℃, VFBx = 0.7 V (2)
220
ns
Fsw
SW-frequency
TA = 25℃
700
kHz
Soft-start time
Internal soft-start time
1.2
ms
80
ns
SOFT START
TSS
(1)
(2)
4
x means either 1 or 2 or 3, that is, VFBx means VFB1, VFB2 or VFB3.
Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
130
Ω
POWER GOOD
VPGTH
PGx threshold
RPG
PGx pull-down resistance
TPGDLY
PGx delay time
TPGCOMPSS
PGOOD comparator start-up delay
PG from lower VOx (going high)
84%
PG from higher VOx (going low)
116%
VPGx = 0.5 V
50
Delay for PGx going high
85
1.5
Delay for PGx going low
PGx comparator wake-up delay
ms
2
µs
2.8
ms
LOGIC THRESHOLD
VENH
ENx H-level threshold voltage
VENL
ENx L-level threshold voltage
RENx_IN
ENx input resistance
2.0
V
0.4
V
ENx = 12 V
225
400
900
kΩ
Lout = 3.3 µH (3), VOUT = 3.3 V
1.7
2.0
3.4
A
Lout = 2.2 µH (3) VOUT = 1.2 V
2.9
3.5
4.9
A
(3)
1.8
2.2
3.6
A
CURRENT LIMIT
IOCL1
IOCL2
Current limit
IOCL3
Lout = 2.2 µH
VOUT = 1.5 V
OVER / UNDER VOLTAGE PROTECTION
VOVP
Output OVP trip threshold
measured on VFBx
VUVP
Output UVP trip threshold
measured on VFBx
TUVPDEL
Output UVP delay time
TUVPEN
Output UVP enable delay
120%
63%
68%
73%
0.5
ms
UVP Enable Delay
2.8
ms
Shutdown temperature (3)
155
THERMAL SHUTDOWN
TSD
(3)
Thermal shutdown threshold
Hysteresis (3)
30
°C
Specified by design. Not production tested.
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TPS65580
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DEVICE INFORMATION
HTSSOP PACKAGE
(TOP VIEW)
1 VIN
VBST2 20
2 VIN
SW2 19
3 VBST1
PGND2 18
4 SW1
EN2 17
5 PGND1
TPS65580
6 VREG5
PGND3 16
HTSSOP20
(PowerPAD)
7 PG
SW3 15
VBST3 14
8 EN1
EN3 13
9 VFB1
VFB3 12
10 GND
VFB2 11
PIN FUNCTIONS (1)
PIN
I/O
DESCRIPTION
1,2
I
Power input and connects to both high side NFET drains. Supply Input for 5.5V linear regulator.
3, 14, 20
I
Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between
VBSTx and SWx pins. An internal diode is connected between VREG5 and VBSTx
SW1, SW2,
SW3
4,15,19
I/O
Switch node connections for both the high-side NFETs and low–side NFETs. Input of current
comparator.
PGND1,
PGND2,
PGND3
5,16,18
I/O
Ground returns for low-side MOSFETs. Input of current comparator.
VREG5
6
O
Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least
1.0µF. VREG5 is active when ENx is high level.
PG
7
O
Open drain power good output. Low means the output voltage is out of regulation.
EN1, EN2, EN3
8,13,17
I
Enable. Pull High to according converter.
VFB1, VFB2,
VFB3
9,11,12
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
10
I/O
Signal GND. Connect sensitive VFBx returns to GND at a single point.
Back side
I/O
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be
connected to GND.
NAME
TSSOP20
VIN
VBST1, VBST2,
VBST3
GND
Exposed
Thermal Pad
(1)
6
x means either 1, 2 or 3, VFBx means VFB1, VFB2 or VFB3.
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FUNCTIONAL BLOCK DIAGRAM
VIN
Circuitry for single channel, x = 1,2 or 3
VIN
-32
UVx
VBSTx
.
OVx
+20
VOx
SWx
Refx
SSx
Err
Comp
PGND
VFBx
PGNDx
+16%
PGx
/
Ref_OCL
-16%
SWx
OCPx
CHx Min-off timer
ENx
EN
Logic
GND
Fixed
SoftStart
SSx
Common Circuitry
Control
and
Protection
Logic
ENSSx
PG
PG1
PG2
PG3
ENintx
VIN
ENSSx
OVx
UVx
UVLO
TSD
VREG5
VREG5
.
VBG
Refx
UVLO
TSD
Bandgap
UVLO
TSD
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TPS65580
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OVERVIEW
The TPS65580 is a 1.5A/2.5A/1.5A triple synchronous step-down (buck) converter with two integrated N-channel
MOSFETs for each channel. It operates using Advanced D-CAP2™ control mode. The fast transient response of
Advanced D-CAP2™ control reduces the required output capacitance to meet a specific level of performance.
Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer
types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS65580 is a fixed switching frequency pulse width modulation (PWM) controller
that supports a proprietary advanced D-CAP2™ mode control. Advanced D-CAP2™ mode control combines
constant switching frequency with an internal compensation circuit and low external component count
configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the
output.
PWM Frequency and Adaptive On-Time Control
TPS65580 uses a advanced D-CAP2 mode control scheme and have a dedicated on board oscillator. The
TPS65580 runs with fixed frequency of 700 kHz.
Soft Start and Pre-Biased Soft Start
The TPS65580 has an internal, 1.2ms, soft-start for each channel. When the ENx pin becomes high, an internal
DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is
maintained during start up.
The TPS65580 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than internal feedback voltage VFB), the controller slowly activates synchronous rectification by
starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx)
starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.
Overvoltage Protection
TPS65580 detects overvoltage conditions by monitoring the feedback voltage (VFB). When the feedback voltage
becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit drives as
the high-side MOSFET driver turns off and the low-side MOSFET turns off.
This is a non-latch function.
Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit and
using HICCUP mode over current protection. The switch current is monitored by measuring the low-side FET
switch voltage between the SWx pin and PGNDx. This voltage is proportional to the switch current and the onresistance of the FET. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iox. If the sensed voltage on the
low side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on
until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle
begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is
monitored in the same manner.
8
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Following are some important considerations for this type of over-current protection. The load current one half of
the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited,
the output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. When the over current condition is removed, the output voltage returns to the regulated value. This
protection is non-latching.
Load current less than 1.5 A for CH1 and CH3 is required at VOUT setting in high on-duty because overcurrent
limit function causes degradation of load transient response.
Hiccup Mode
Hiccup mode of operation protects the power supply from being damaged during an over-current fault condition.
The operation of hiccup is as follows. If the OCL comparator circuit detects an over-current event the output
voltage falls. When the feedback voltage falls below 68% of the reference voltage, the UVP comparator output
goes high and an internal UVP delay counter begins counting. After counting UVP delay time, the TPS65580
shuts off the power supply for a given time (7x UVP Enable Delay Time) and then tries to re-start the power
supply. If the over-load condition has been removed, the power supply starts and operates normally; otherwise,
the TPS65580 detects another over-current event and shuts off the power supply again, repeating the previous
cycle. Excess heat due to overload lasts for only a short duration in the hiccup cycle, therefore the junction
temperature of the power devices is much lower.
POWERGOOD
The TPS65580 has power-good output that are measured on VFBx. The power-good function is activated after
the soft-start has finished. If the all output voltages of 3 channels are within 16% of the target voltage, the
internal comparator detects the power good state and the power good signal becomes high after 1.5ms delay.
During start-up, this internal delay starts after 1.5ms of the UVP Enable delay time to avoid a glitch of powergood signal. Even if at least one of the feedback voltages of 3 channels goes outside of ±16% of target value,
the power-good signal becomes low after 2µs.
Figure 1. Start up
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Figure 2. VOUT Transient
Figure 3. Power Down
UVLO Protection
Under voltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS65580 is shut down. As soon as the voltage increases above the
UVLO threshold, the converter starts again.
Thermal Shutdown
TPS65580 monitors its temperature of itself. If the temperature exceeds the threshold value (typically 155°C), the
device is shut down. When the temperature falls below the threshold, the IC starts again. When VIN starts up
and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is lower than 155℃. As
long as VIN and VREG5 rise, TJ must be kept below 110℃.
10
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TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted)
30
5.0
VIN = 12 V
4.5
IIN - VIN Supply Current (mA)
IIN - VIN Supply Current (mA)
VIN = 12 V
25
20
15
10
5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.0
0
±50
50
100
150
TJ Junction Temperature (C)
150
C019
50
VIN = 12 V
45
4
40
EN Input Current (uA)
Ivinsdn - VIN Shutdown Current ( A)
100
Figure 5. VIN Current vs Junction Temperature
(VIN Current at ALL Channels Non-switching EN = H)
5
3.5
3
2.5
2
1.5
35
30
25
20
15
1
10
0.5
5
0
EN1
EN2
EN3
0
0
±50
50
100
150
TJ Junction Temperature (C)
0
1.25
1.24
VOUT - Output Voltage (V)
VIN = 12 V
VIN = 18 V
3.32
3.3
3.28
3.26
3.24
VIN = 6 V
3.22
15
20
C003
Figure 7. EN Current vs EN Voltage
3.4
3.36
10
EN Input Voltage (V)
3.38
3.34
5
C002
Figure 6. VIN Shutdown Current vs Junction Temperature
VOUT - Output Voltage (V)
50
TJ Junction Temperature (C)
Figure 4. VIN Current vs Junction Temperature
(VIN Current at ALL Channels Switching with IO = 0A)
4.5
0
±50
C001
1.23
VIN = 18 V
1.22
1.21
1.2
VIN = 5 V
1.19
VIN = 12 V
1.18
1.17
1.16
3.2
1.15
0
0.2
0.4
0.6
0.8
1
IOUT - Output Current (A)
1.2
1.4
1.6
0
Figure 8. VOUT1 = 3.3V Output Voltage vs Output Current
0.5
1
1.5
2
IOUT - Output Current (A)
C004
2.5
C005
Figure 9. VOUT2 = 1.2V Output Voltage vs Output Current
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TYPICAL CHARACTERISTICS (continued)
1.55
3.4
1.54
3.38
1.53
VIN = 18 V
1.52
VOUT - Output Voltage (V)
VOUT - Output Voltage (V)
VIN = 12 V, TA = 25°C (unless otherwise noted)
VIN = 5 V
1.51
1.5
VIN = 12 V
1.49
1.48
1.47
3.34
3.32
3.3
3.28
3.26
3.24
1.46
3.22
1.45
3.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
IOUT - Output Current (A)
1.6
1.53
VOUT - Output Voltage (V)
1.54
1.23
1.22
1.21
1.2
1.19
1.18
1.17
IOUT
=0A
Io=0A
4
6
8
10
12
14
VIN - Input Voltage (V)
16
18
10
12
14
20
16
18
20
C007
1.52
1.51
1.5
1.49
1.48
1.47
IOUT
=0A
Io=0A
IOUT
=1A
Io=1A
0
2
4
6
8
10
12
14
VIN - Input Voltage (V)
C008
16
18
20
C009
Figure 13. VOUT3 = 1.5V Output Voltage vs Input Voltage
VOUT(50mV/div)
Vo=1.2V
Vout(50mV/div)
Iout2(1A/div)
IOUT1(1A/div)
100us/div
100us/div
Figure 14. VOUT1 = 3.3V, 0A to 1.5A Load Transient
Response
12
8
1.45
Figure 12. VOUT2 = 1.2V Output Voltage vs Input Voltage
Vo=3.3V
6
1.46
IOUT
=1A
Io=1A
2
4
Figure 11. VOUT1 = 3.3V Output Voltage vs Input Voltage
1.55
0
2
VIN - Input Voltage (V)
1.24
1.15
IOUT
=1A
Io=1A
0
1.25
1.16
IOUT
=0A
Io=0A
C006
Figure 10. VOUT3 = 1.5V Output Voltage vs Output Voltage
VOUT - Output Voltage (V)
3.36
Figure 15. VOUT2 = 1 .2V, 0A to 2.5A Load Transient
Response
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
100
Vo=1.5V
VOUT(50mV/div)
Efficiency (%)
90
IOUT3(1A/div)
80
70
60
VVIN=6V
IN = 6 V
50
100us/div
VVIN=12V
IN = 12 V
VVIN=18V
IN = 18 V
40
0
0.2
0.4
0.6
0.8
1
1.2
1.4
IOUT - Output Current (A)
100
100
90
90
80
80
70
60
VVIN=6V
IN = 5 V
50
VVIN=18V
IN = 18 V
0
0.5
1
1.5
2
VVIN=12V
IN = 12 V
VVIN=18V
IN = 18 V
0
0.2
0.4
0.6
0.8
1
1.2
900
750
700
650
600
550
500
450
400
1.6
C012
Figure 19. VOUT3=1.5V, Light Load Efficiency vs Output
Current
IOUT = 1 A
800
1.4
IOUT - Output Current (A)
C011
fsw - Switching Frequency (kHz)
fsw - Switching Frequency (kHz)
VVIN=6V
IN = 5 V
40
Figure 18. VOUT2 = 1.2V Light Load Efficiency vs Output
Current
850
60
2.5
IOUT - Output Current (A)
900
70
50
VVIN=12V
IN = 12 V
40
C010
Figure 17. VOUT1 = 3.3V Light Load Efficiency vs Output
Current
Efficiency (%)
Efficiency (%)
Figure 16. VOUT3 = 1.5V, 0A to 1.5A Load Transient
Response
1.6
IOUT = 1 A
850
800
750
700
650
600
550
500
450
400
0
2
4
6
8
10
12
14
VIN - Input Voltage (V)
16
18
20
0
Figure 20. VOUT1 = 3.3V Switching Frequency vs Input
Voltage
2
4
6
8
10
12
14
16
18
VIN - Input Voltage (V)
C013
20
C014
Figure 21. VOUT2 = 1.2V Switching Frequency vs Input
Voltage
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
900
IOUT = 1 A
850
fsw - Switching Frequency (kHz)
fsw - Switching Frequency (kHz)
900
800
750
700
650
600
550
500
450
800
750
700
650
600
550
500
450
400
400
0
2
4
6
8
10
12
14
16
VIN - Input Voltage (V)
18
20
0
0.6
0.8
1
1.2
fsw - Switching Frequency (kHz)
750
700
650
600
550
500
450
1.6
C016
900
800
1.4
Figure 23. VOUT1 = 3.3V Switching Frequency vs Output
current
VIN = 12 V
400
VIN = 12 V
850
800
750
700
650
600
550
500
450
400
0
0.5
1
1.5
2
2.5
IO - Output Current (A)
VO1 (10mV/div)
VO = 3.3V
0
0.2
0.4
SW1 (5V/div)
0.6
0.8
1
1.2
1.4
IO - Output Current (A)
C005
Figure 24. VOUT2 = 1.2V, Switching Frequency vs Output
Current
1.6
C018
Figure 25. VOUT3 = 1.5V, Switching Frequency vs Output
Current
VO2 (10mV/div)
VO = 1.2V
SW2 (5V/div)
400 ns/div
400 ns/div
Figure 26. VOUT1 = 3.3V, VO1 Ripple Voltage at IOUT1 =
1.5A
14
0.4
IO - Output Current (A)
900
850
0.2
C015
Figure 22. VOUT3 = 1.5V Switching Frequency vs Input
Voltage
fsw - Switching Frequency (kHz)
VIN = 12 V
850
Figure 27. VOUT2 = 1.2V, Ripple Voltage at IOUT2 = 2.5A
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
VO3 (10mV/div)
VO = 1.5V
SW3 (5V/div)
VIN(50mV/div)
VO = 3.3V
SW1(5V/div)
400ns/div
400 ns/div
Figure 28. VOUT3 = 1.2V, Ripple Voltage at IOUT3 = 1.5A
VIN(50mV/div)
VO = 1.2V
Figure 29. VOUT1 = 3.3V, VIN Ripple Voltage at IOUT1 =
1.5A
VIN (50mV/div)
VO = 1.5V
SW3(5V/div)
SW2(5V/div)
400ns/div
400ns/div
Figure 30. VOUT2 = 1.2V VIN Ripple at IOUT2 = 2.5A
Figure 31. VOUT3 = 1.5V VIN Ripple at IOUT3 = 1.5A
EN2 (10V/div)
EN1 (10V/div)
VREG5 (5V/div)
VREG5 (5V/div)
VOUT2 (0.5V/div)
VOUT1 (1V/div)
PG (5V/div)
PG (5V/div)
1 ms/div
1 ms/div
Figure 32. VOUT1 = 3.3V Soft-Start IOUT1 = 1.5A
Figure 33. VOUT2 = 1.2V Soft-Start IOUT2 = 2.5A
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
EN3 (10V/div)
VREG5 (5V/div)
VOUT3 (0.5V/div)
PG (5V/div)
1 ms/div
Figure 34. VOUT3 = 1.5V Soft-Start IOUT3 = 1.5A
16
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SLVSC29B – SEPTEMBER 2013 – REVISED DECEMBER 2013
DESIGN GUIDE
Step By Step Design Procedure
To
•
•
•
begin the design process, you must know a few application parameters:
Input voltage range
Output voltage
Output current
Input Voltage
1 VIN
VBST2 20
2 VIN
SW2 19
C32
C11
VO2
C22
PGND2 18
3 VBST1
L11
VO1
L12
C31
4 SW1
PGND
EN2 17
C21
5 PGND1
TPS65580
PGND3 16
PGND
L13
C4
PGND
6 VREG5
PGND
7 PG
HTSSOP20
(PowerPAD)
C23 VO3
SW3 15
C33
VBST3 14
8 EN1
EN3 13
9 VFB1
VFB3 12
10 GND
VFB2 11
R13
R1１
R21
R12
R23
R22
SGND
SGND
SGND
SGND
Figure 35. Schematic Diagram for the Design Example at Vin=12V
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 1 to calculate VOx.
To improve efficiency at very light loads consider using larger value resistors; although, resistance values too
high cause more susceptibility to noise and voltage errors due to the VFBx input current being more noticeable.
R1x ö
æ
VOX = 0.764 ´ ç 1 +
÷
è R2x ø
(1)
Output Filter Selection
The output filter used with the TPS65580 is an LC circuit. This LC filter has double pole at:
1
FP =
2p L1X ´ C2X
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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS65580. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. Advanced D-CAP2™ introduces a high frequency
zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade
above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the
double pole of Equation 2 is located below the high frequency zero but close enough that the phase boost
provided by the high frequency zero provides adequate phase margin for a stable circuit. To meet this
requirement use the values recommended in Table 1.
Table 1. Recommended Component Values
OUTPUT VOLTAGE (V)
R1x (kΩ)
R2x (kΩ)
L1x (µH)
C2x (µF)
1
0.68
2.2
1.5 to 3.3
22 - 68
1.05
0.82
2.2
1.5 to 3.3
22 - 68
1.2
1.27
2.2
1.5 to 3.3
22 - 68
1.5
2.15
2.2
1.5 to 3.3
22 - 68
1.8
3.00
2.2
1.5 to 3.3
22 - 68
2.5
4.98
2.2
2.2 to 4.7
22 - 68
3.3
7.36
2.2
2.2 to 4.7
22 - 68
5
12.4
2.2
2.2 to 4.7
22 - 68
6.5
16.5
2.2
2.2 to 4.7
22 - 68
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 3,
Equation 4 and Equation 5. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
For the calculations, use 700 kHz as the switching frequency, fSW. Make sure the chosen inductor is rated for the
peak current of Equation 4 and the RMS current of Equation 5.
VIN(MAX) - VOX
VOX
DIL1X =
´
VIN(MAX)
L1x ´ ƒSW
(3)
DIL1X
IL1XPEAK = IOX +
(4)
2
IL1X(RMS) = IOX2 +
1
DIL1X2
12
(5)
For the above design example, the calculated peak current is 2.46 A and the calculated RMS current is 2.02 A.
for Vo1. The inductor used is a TDK CLF7045-1R5N with a rated current of 7.3 A based on the inductance
change and of 4.9A based on the temperature rise.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS65580 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 6 to
determine the required RMS current rating for the output capacitor(s).
IC2X(RMS) =
VOX ´ (VIN - VOX )
12 ´ VIN ´ LIX ´ ƒSW
(6)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.19A and each output capacitor is rated for 4A.
Input Capacitor Selection
The TPS65580 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10µF × 2 is recommended for the decoupling capacitor. Accordingly, 0.1 µF
ceramic capacitors from pin 1 to ground is recommended to improve the stability and reduce the SWx node
overshoots. The capacitor voltage rating needs to be greater than the maximum input voltage.
18
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SLVSC29B – SEPTEMBER 2013 – REVISED DECEMBER 2013
Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is
recommended to use ceramic capacitors with a dielectric of X5R or better.
VREG5 Capacitor Selection
A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is
recommended to use a ceramic capacitor with a dielectric of X5R or better.
Thermal Information
This 20-pin PWP package incorporates an exposed thermal pad that is designed to be directly to an external
heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to the Technical Brief, PowerPAD™Thermally Enhanced Package, Texas Instruments Literature
No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
Figure 36. Thermal Pad Dimensions
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Layout Considerations
1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal
pad.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching currents to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected to PGND.
9. Output capacitors should be connected with a broad pattern to the PGND.
10. Voltage feedback loops should be as short as possible, and preferably with ground shield.
11. Kelvin connections should be brought from the output to the feedback pin of the device.
12. Providing sufficient vias is preferable for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
VIN INPUT
BYPASS
CAPACITOR
10µFx2
VIN
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
～0.1µF
VO1
OUTPUT
FILTER
CAPACITOR
BOOST
CAPACITOR
VIN
Recommend to keep
distance more than 3-4mm.
(to avoid noise scattering,
especially GND plane.)
Break Line * Flow of
switching noise.
Switching noise
flows through IC
and Cin.
1
20
VBST2
19
SW2
VIN
2
VBST1
3
18
PGND2
SW1
4
17
EN2
PGND1
5
16
PGND3
VREG5
6
15
SW3
PG
7
14
VBST3
EN1
8
13
EN3
VFB1
9
12
VFB3
GND
10
11
VFB2
OUTPUT
FILTER
CAPACITOR
VO2
OUTPUT
INDUCTOR
GND PLANE
OUTPUT
INDUCTOR
Feedback
resisters
TO ENABLE
CONTROL
GND PLANE
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
VO3
TO ENABLE
CONTROL
Feedback
resisters
Feedback
resisters
VO3
GND
PLANE
2,3 or bottom
layer
Keep
distance more
than 1 inch
VO2
VO1
Figure 37. TPS65580 Layout
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SLVSC29B – SEPTEMBER 2013 – REVISED DECEMBER 2013
REVISION HISTORY
Page numbers of current version may differ from previous versions.
Changes from Original (September 2013) to Revision A
Page
•
Added text to Current Protection section for clarification. ..................................................................................................... 9
•
Added text to Output Voltage Resistors Selection for clarification. .................................................................................... 17
•
Corrected resistor R1x (kΩ) values in Table 1. .................................................................................................................. 18
Changes from Revision A (September 2013) to Revision B
Page
•
Added VOVP specification to ELEC CHARA, OVER / UNDER VOLTAGE PROTECTION ................................................... 5
•
Added Overvoltage Protection description. .......................................................................................................................... 8
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65580PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS65580
TPS65580PWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS65580
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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