TI INFORMATION – SELECTIVE DISCLOSURE
TPS65640
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SLVSCE2 – NOVEMBER 2013
LCD Bias With Digital VCOM Buffer for Notebook PCs and Tablet PCs
Check for Samples: TPS65640
FEATURES
DESCRIPTION
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The TPS65640 is a compact LCD bias solution
primarily intended for use in notebook and tablet PCs.
The device comprises two boost converters to supply
the LCD panel’s source driver and gate driver or level
shifter; one buck converters or a LDO regulator
alternatively to supply the time controller logic
voltages; a linear negative voltage regulator to supply
gate off voltage or provide negative voltage for
source driver; a programmable VCOM generator with
one high-speed amplifier; a gate voltage shaping
function and two high speed operational amplifiers.
1
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•
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•
•
•
•
•
•
•
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•
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2.5-V to 5.5-V Input Voltage Range
3.6 to 12.7 V Boost Converter (AVDD)
15 to 37 V Boost Converter with Temperature
Compensation (VGH)
–8 V to –3.8 V Linear Negative Voltage
Regulator (VGL or NAVDD)
1.5-V to 3-V Alternative Buck Converter or Low
Dropout Regulator (V25)
7 bits Programmable VCOM Calibrator With One
Integrated Buffer Amplifiers
0.8 V to 5.1 V Programmable VCOM Voltage
Output for Full AVDD Application
–4.1 V to 0.2 V Programmable VCOM Voltage
Output for Positive and Negative AVDD
Application
Two Operational Amplifiers
Gate Voltage Shaping
Programmable VGH and VCOM Temperature
Compensation
TCON Reset Signal Generator With
Programmable Delay
I2C Interface for E2PROM Programming
Thermal Shutdown
Supports GIP and Non-GIP Displays
28 Pins, 5.5-mm × 3.5-mm 0.5-mm Pitch QFN
All the regulators and VCOM voltage outputs are
programmed through I2C interface and stored in the
TPS65640 integrated E2PROM. The TPS65640 is
available in 5.5-mm × 3.5-mm, 28-lead QFN package.
VIN
Notebook PCs
Tablet PCs
AVDD
Negative Charge
Pump Regulator
VGL
Buck Converter
V25
LDO Regulator
V25
Reset Generator
RST
AVDD
Boost Converter2
VGH
Operational Amplifier1
VOUTA
Operational Amplifier2
VOUTB
Programmable
VCOM + Buffers
APPLICATIONS
•
•
Boost Converter1
VGH
2
I C
7
Gate Voltage Shaping
VCOM
VGHM
2
I C Interface
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TI INFORMATION – SELECTIVE DISCLOSURE
TPS65640
SLVSCE2 – NOVEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TA
ORDERING
PACKAGE
PACKAGE MARKING
–40°C to 85°C
TPS65640
5.5-mm x 3.5-mm 28-pin QFN
PZXI
(1)
The device is supplied taped and reeled, with 3000 devices per reel.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
Pin Voltage (2)
ESD Rating (3)
UNIT
MIN
MAX
VIN, V25, V25_LX, RESET, COMP, SCL, SDA, VFLK, VT
–0.3
7
V
VIN (100ms) Pulse
–0.3
12
V
AVDD, LX
–0.3
20
V
–5
5
V
VCOM_OUT, INA+, INA–, OUTA, INB+, INB–, OUTB
VGH_LX, VGH, VGHM, RE
–0.3
40
V
DRVN, VGL, NAVDD
–12
0.3
V
Human Body Model
2000
V
Machine Model
200
V
700
V
TA
Charged Device Model
Ambient temperature
–40
85
°C
TJ
Junction temperature
–40
150
°C
TSTG
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
TPS65640
THERMAL METRIC (1)
RHR
UNITS
28 PINS
θJA
Junction-to-ambient thermal resistance (2)
37.4
θJCtop
Junction-to-case (top) thermal resistance (3)
26.3
θJB
Junction-to-board thermal resistance (4)
8.3
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (6)
8.1
θJCbot
Junction-to-case (bottom) thermal resistance (7)
1.2
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2
0.2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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SLVSCE2 – NOVEMBER 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage range
TYP
2.5
MAX
UNIT
5.5
V
BOOST CONVERTER 1
AVDD
Boost converter 1 output voltage range
IAVDD
Boost converter 1 output current when 5.5 V ≥ VIN ≥ 2.5 V
3.6
L1
Boost converter #1 inductor range
4.7
COUT1
Boost converter #1 output capacitance
10
11
V
400
mA
10
µH
µF
BOOST CONVERTER 2
AVDD
Input voltage range
3.6
11 (1)
VGH
Output voltage range
15
37
V
IGH
Output current
15
40
mA
L4
Inductor
4.7
10
10
µH
COUT4
Output capacitance
1
2.2
µF
RNTC
Thermistor resistance at 25 °C
10
kΩ
V
BUCK CONVERTER (V25)
V25
Output voltage
I25
Output current
1.5
L2
Inductor
2.2
COUT2
Output capacitance
4.7
3
V
600
mA
4.7
10
µH
10
22
µF
3
V
350
mA
LDO Regulator (V25)
V25
Output voltage
I25
Output current
COUT2
Output capacitance
(1)
1.5
1
4.7
µF
VGH – AVDD must be greater than 6 volts.
ELECTRICAL CHARACTERISTICS
VIN = 3.3 V; V25 = 2.5 V, AVDD = 8.5 V, VGH = 23 V, VGL = –6 V, RCAMP=200kΩ, CCAMP=1 nF, NAVDD = AGND = PGND = 0V,
TA = –40 °C to 85 °C. Typical values are at 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
IIN
Supply current into VIN
Converters not switching
2
3
mA
Supply current into AVDD
No load on op-amp outputs
5
8.5
mA
Supply current into VGH
No load on VGHM
0.1
1
mA
2.35
2.4
2.2
2.25
UNDER VOLTAGE LOCKOUT
VUVLO
Undervoltage lockout threshold
Hysteresis
VIN rising
2.3
VIN falling TA = 25°C
2.05
VIN rising – VIN falling
V
0.15
BOOST CONVERTER 1 (AVDD)
AVDD
VUVP1
Output voltage range
Tolerance
3.6
11
–2%
2%
AVDD falling
75
VSCP1
Short circuit threshold
AVDD falling
25
30
35
VOVP1
Over Voltage threshold
AVDD rising
14.5
15
16
V
ILK1
Switch leakage current
AVDD = 13.5 V
10
20
µA
rDS(ON)1
Switch ON resistance
ILX = 1 A
Ω
ILIM1
85
% of
AVDD
Undervoltage threshold
TDLY_UVP1
80
V
160
AVDD switch current limit
ms
0.2
0.3
AVDD ILIM = 0, TA = 25 °C
0.8
1
1.2
AVDD ILIM = 1, TA = 25 °C
1.6
2
2.4
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V; V25 = 2.5 V, AVDD = 8.5 V, VGH = 23 V, VGL = –6 V, RCAMP=200kΩ, CCAMP=1 nF, NAVDD = AGND = PGND = 0V,
TA = –40 °C to 85 °C. Typical values are at 25°C (unless otherwise noted).
PARAMETER
DMAX1
Maximum Duty Cycle
fSW1
Oscillator frequency
VLIR1
Line regulation,
VLIR=ΔAVDD/(AVDD×ΔVIN)
Load regulation,
VLOR=(AVDD_20mA–AVDD_200mA)/AVDD_
VLOR1
TEST CONDITIONS
MIN
TYP
MAX
480
600
720
600
750
900
FREQ1 = 10, TA = 25°C
720
900
1080
FREQ1 = 11, TA = 25°C
800
1000
1200
±0.1
±0.15
FREQ1 = 01
80%
FREQ1 = 00, TA = 25°C
FREQ1 = 01, TA = 25°C
VIN = 2.5 V to 5.5 V, AVDD = 8.5 V, TA = 25 °C
VIN = 3.3 V, AVDD = 8.5 V, IAVDD = 20 mA to 200 mA
1
SS1 = 00
20
SS1 = 01
40
SS1 = 10
60
UNIT
kHz
%/V
%/A
20mA
VSS1
AVDD soft stat duration
Tf1
AVDD switch ON voltage slew rate
SS1 = 11
80
LX1TS = 00
0.5
LX1TS = 01
0.7
LX1TS = 10
0.9
LX1TS = 11
1.1
ms
V/ns
BUCK CONVERTER (V25Buck)
Output voltage
V25Buck
Tolerance
(V25-V25_setting)/V25_seeting
Undervoltage threshold
V25 falling
Hysteresis
V25 rising
ILIM2
Switch current limit
ISW2A ramps from 0 A to 2 A
TSS2
Soft start duration
VUVP2
1.5
3
–2%
2%
0.8
TDLY_UVP2
rDS(ON)2A
1.2
160
Switch ON resistance
rDS(ON)2B
1
0.1
1
1.2
V
V
ms
1.4
4
A
ms
High-side, ISW2A = ILIM2
250
450
Low-side, ISW2B = 1 A
100
200
1250
1500
kHz
±0.15
%/V
fSW2
Switching frequency
VIN = 3.3 V; V25 = 2.5 V, I25 = 200 mA
VLIR2
Line regulation, VLIR = ΔV25 /
(AV25×ΔVIN)
1000
VIN = 2.5 V to 5.5 V
±0.1
VLOR2
Load regulation
VIN = 3.3 V, I25 = 1 mA to 400 mA
1%
mΩ
LINEAR REGULATOR (V25LDO)
Output voltage
V25LDO
Tolerance
1.5
3.0
–2.5%
2.5%
Undervoltage threshold
V25 falling
Hysteresis
V25 rising
VDO3
Dropout voltage
I25 = 350 mA, V25 = –3%
300
500
mV
VLIR3
Line regulation, VLIR = ΔV25 /
(V25×ΔVIN)
VIN = 2.8 V to 5.5 V, I25 = 100 mA
0.1
±0.15
%/V
VLOR3
Load regulation
VIN = 3.3 V, I25 = 1 mA to 300 mA
1
VUVP3
0.8
1
1.2
V
0.1
TDLY_UVP3
160
V
ms
%/A
BOOST CONVERTER 2 (VGH)
Output voltage range
VGH
Tolerance
15
37
–3%
3%
V
VOVP4
Overvoltage threshold
TA = 25 °C
38
39
40
V
VUVP4
Undervoltage threshold
VGH falling
75
80
85
% of VGH
TDLY_UVP4
Undervoltage protection shutdown
delay
ILK4
Switch leakage current
4
160
Switching off VVGH_LX = 38 V
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10
ms
20
µA
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TPS65640
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SLVSCE2 – NOVEMBER 2013
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V; V25 = 2.5 V, AVDD = 8.5 V, VGH = 23 V, VGL = –6 V, RCAMP=200kΩ, CCAMP=1 nF, NAVDD = AGND = PGND = 0V,
TA = –40 °C to 85 °C. Typical values are at 25°C (unless otherwise noted).
PARAMETER
fSW4
VGH swithching frequency
rDS(ON)4
VGH switch ON resistance
ILIM4
VGH switch current limit
MIN
TYP
MAX
FREQ4 = 0
TEST CONDITIONS
300
400
500
FREQ4 = 1
600
800
1000
IVGH_LX = 1 A
0.9
SS4 = 00
TSS4
VGH soft start duration
UNIT
kHz
0.5
1
Ω
1.2
1.5
A
4
SS4 = 01
8
SS4 = 10
12
SS4 = 11
ms
16
DMAX4
88%
90%
IVT
Thermistor reference current
VVT = 1 V
VLIR4
Line regulation
AVDD = 3.6 V to 11 V
±0.1
40
VLOR4
Load regulation
IGH = 5 mA to 40 mA
1
µA
±0.15
%/V
%/A
PROGRAMMABLE VCOM CALIBRATOR
VS+ – VS–
VCOM buffer supply voltage
VCOM
VCOM voltage accuracy,
VCOM–VCOM_setting
Load regulation
ISC2
Short circuit current
IOUT = 0 mA
–6
15
V
6
LSB
AVDD = 8.5 V, NAVDD = 0 V, VCOM_OUT = AVDD / 2,
ISOURCE = 1mA to 20mA
1
2
AVDD = 5 V, NAVDD = –5 V, VCOM_OUT = 0 V,
ISOURCE = 1 mA to 20 mA
1
2
AVDD = 8.5 V, NAVDD = 0 V, VCOM_OUT = AVDD / 2,
ISINK = –1 mA to –20 mA
1
2
AVDD = 5 V, NAVDD = –5 V, VCOM_OUT = 0 V,
ISINK = –1 mA to –20 mA
1
2
V/A
AVDD = 5 V, VCOM_OUT = AVDD,
NAVDD = –5 V
–200
AVDD = 5 V,
VCOM_OUT = NAVDD = –5 V
200
mA
SR2
Slew rate
VCOM_OUT = AVDD / 2 + 1 V
12
V/µs
BW2
Small signal 3dB bandwidth
VCOM_OUT = AVDD / 2, VSIGNAL = 60 mVPP, no load
12
MHz
OPERATIONAL AMPLIFIER 1 and 2 (AVDD = 5 V, NAVDD = –5 V, RL = 10 kΩ, CL = 10 pF, TA = 25°C)
VIO1
Input offset voltage
VCM = (AVDD + NAVDD) / 2
–15
15
ΔVIO/ΔT
Average offset voltage drift
TA = –40°C to 85°C
5
μV/°C
RIN1
Input impedance
1
GΩ
CIN1
Input capacitance
1.35
VCM1
Input common mode voltage range
AVDD = 5 V, NAVDD = –5 V
–4
AVOL1
Open loop gain
VCM = (AVDD + NAVDD) / 2
75
95
dB
PSRR1
Power supply rejection ratio
VCM = (AVDD + NAVDD) / 2
60
70
dB
CMRR1
Common mode rejection ration
VCM = (AVDD + NAVDD) / 2
50
80
VOL1
Output swing low
IL = 5 mA
VOH1
Output swing High
IL = –5 mA
IOC1
Continuous output current
IPK1
Peak output current
VIN+ = (AVDD + NAVDD) / 2, VIN– = (AVDD + NAVDD) / 2 ±1 V,
open-loop
tS
Setting to ±0.1%
AV = –1, VIN– = (AVDD + NAVDD) / 2 ±1 V
500
ns
SR1
Slew rate
AV = –1, VIN– = (AVDD + NAVDD) / 2 ±1 V
12
V/µs
BW1
Small signal 3 dB bandwidth
AV = –1, VCM = (AVDD + NAVDD) / 2, VSIGNAL = 60 mVPP
PM
Phase margin
CS
Channel Separation
–4.92
AV = –1, VCM = (AVDD + NAVDD) / 2, VSIGNAL = 60 mVPP, f =
5 MHz
pF
3
4.85
mV
V
dB
4.92
V
–485
V
±35
mA
±120
mA
5
MHz
50
Degree
75
dB
GATE OFF REGULATION CONTROLLER (VGL)
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V; V25 = 2.5 V, AVDD = 8.5 V, VGH = 23 V, VGL = –6 V, RCAMP=200kΩ, CCAMP=1 nF, NAVDD = AGND = PGND = 0V,
TA = –40 °C to 85 °C. Typical values are at 25°C (unless otherwise noted).
PARAMETER
VGL
VGL voltage regulate accuracy
IDRVN
DRVN source current
VLIR5
Line regulation
TEST CONDITIONS
MIN
TYP
MAX
Output voltage
–3.8
-8
Tolerance
–3%
3%
1
UNIT
V
4
6
mA
IDRVN = 1 mA, VIN = 2.5 V to 5.5 V
1
6
mV
GATE VOLTAGE SHAPING
rDS(ON)H
VGH to VGHM ON resistance
VGH = 24 V, IGHM = 10 mA, VFLK = 2.5 V
13
25
Ω
rDS(ON)L
VGHM to RE ON resistance
VGHM = 24 V, IGHM = 10 mA, VFLK = 0 V
13
25
Ω
VIH
High-level input voltage
VFLK rising
VIL
Low-level input voltage
VFLK falling
tPLH
Propagation delay
tPHL
Gate voltage shaping / LCD bias
ready delay range
tDLY
1.5
V
0.6
VGHM rising, 2.5 V, 50% thresholds, COUT = 150 pF, RE = 0
mΩ
100
200
VGHM falling, 2.5 V, 50% thresholds, COUT = 150 pF, RE = 0
mΩ
100
200
V
ns
DLY = 00
0
DLY = 01
20
DLY = 10
40
DLY = 11
60
ms
TCON RESET GENERATOR
VDIV
Detecting voltage falling threshold
VDIV = 000
1.08
1.2
1.32
VDIV = 001
1.26
1.4
1.54
VDIV = 010
1.44
1.6
1.76
VDIV = 011
1.62
1.8
1.98
VDIV = 100
1.8
2
2.2
VDIV = 101
1.98
2.2
2.42
VDIV = 110
2.16
2.4
2.64
VDIV = 111
2.34
2.6
2.86
Hysteresis
150
VOL(RST)
Output voltage
IRST = 1 mA (sinking)
ILK(RST)
Leakage current
VRST = 2.5 V
tRESET (1)
Reset delay time
RESET = 0000
0
…
…
RESET = 1111
30
TJ rising
150
V
mV
0.5
V
1
µA
ms
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature
°C
2
I C INTERFACE
ADDR
Configuration parameters slave
address
E8
Programmable VCOM slave address
9E
VIL
Low level input voltage
Supply = 2.5 V, VIN falling, standard and fast modes
VIH
High level input voltage
Supply = 2.5 V, VIN rising, standard and fast4 modes
VHYS
Hysteresis
Supply = 2.5 V, applicable to fast mode only
VOL
Low level output voltage
Sinking 3 mA
CI
Input capacitance
fSCL
Clock frequency
tLOW
Clock low period
tHIGH
Clock high period
(1)
6
0.3 × V25
V
125
mV
500
mV
10
pF
Standard mode
100
Fast mode
400
Standard mode
4.7
Fast mode
1.3
Standard mode
Fast mode
V
0.7 × V25
4
0.6
kHz
µs
µs
Refer to Table 12 for RESET time delay break down.
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V; V25 = 2.5 V, AVDD = 8.5 V, VGH = 23 V, VGL = –6 V, RCAMP=200kΩ, CCAMP=1 nF, NAVDD = AGND = PGND = 0V,
TA = –40 °C to 85 °C. Typical values are at 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tBUF
Bus free time between a STOP and a
START condition
Standard mode
4.7
Fast mode
1.3
thd:STA
Hold time for a repeated START
condition
Standard mode
tsu:STA
Set-up time for a repeated START
condition
Standard mode
Fast mode
0.6
tsu:DAT
Data set-up time
Standard mode
250
Fast mode
100
Standard mode
0.05
3.45
Fast mode
0.05
0.9
Standard mode
20 +
0.1CB
1000
Fast mode
20 +
0.1CB
1000
Standard mode
20 +
0.1CB
1000
Fast mode
20 +
0.1CB
300
Standard mode
20 +
0.1CB
300
Fast mode
20 +
0.1CB
300
Standard mode
20 +
0.1CB
1000
Fast mode
20 +
0.1CB
300
Standard mode
20 +
0.1CB
300
Fast mode
20 +
0.1CB
300
thd:DAT
Data hold time
tRCL1
Rise time of SCL after a repeated
START condition and after an ACK
bit
tRCL
tFCL
tRDA
tFDA
Fast mode
Rise time of SCL
Fall time of SCL
Rise time of SDA
Fall time of SDA
tsu:STO
Set-up time for STOP condition
CB
Capacitive load on SDA and SCL
Standard mode
Fast mode
UNIT
µs
4
µs
0.6
4
µs
ns
µs
ns
ns
ns
ns
ns
4
µs
0.6
Standard mode
400
Fast mode
400
pF
E2PROM
NWRITE
Number of write cycles
tWRITE
Write time
Data retention
1000
100
Storage temperature = 150°C
100000
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DEVICE INFORMATION
LX
AVDD
AGND
COMP
VT
V25
VIN
V25_LX
PGND2
VINA+
PIN ASSIGNMENT
28 PIN 5.5mm × 3.5mm RHR PACKAGE
TOP VIEW
24
23
22
21
20
19
18
17
16
15
PGND1 25
14 VINA–
VGH_LX 26
13 OUTA
PGND3
VGH 27
12 OUTB
VGHM 28
11 VINB–
8
9
10
VINB+
7
VCOM_OUT
SDA
6
NAVDD
FLK
5
VGL
RE
4
DRVN
3
RESET
2
SCL
1
PIN FUNCTIONS
PIN
TYPE
DESCRIPTION
NAME
NO.
AGND
22
P
Ground
AVDD
23
I
AVDD sense pin
COMP
21
O
Boost converter 1 compensation. Connect a suitable compensation network (typically a series R-C
combination) between this pin and ground
DRVN
6
O
Drive output for negative linear regulator
FLK
2
I
Gate voltage shaping flicker clock input
LX
24
P
Boost convert 1 switch node
NAVDD
8
I
Negative AVDD voltage input
OUTA
13
O
Operational amplifier A output
OUTB
12
O
Operational amplifier B output
PGND1
25
P
Power Ground 1 for boost converter 2
PGND2
16
P
Power Ground 2 for buck converter
PGND3
29
P
Power Ground 3 for boost converter 1
RE
1
O
Gate voltage shaping discharge resistor connection
RESET
5
O
T-CON reset output
SCL
4
I
I2C Interface serial clock
SDA
3
I/O
I2C Interface serial data
VCOM_OUT
9
O
VCOM amplifier output
VGH
27
P
Gate voltage shaping input and boost converter 2 output sense
VGH_LX
26
P
Boost converter 2 switch node
VGHM
28
O
Gate voltage shaping output
VGL
7
I
Negative linear regulator sense pin
VIN
18
P
Supply voltage
8
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PIN FUNCTIONS (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
VINA+
15
I
Operational amplifier B non-inverting input
VINA–
14
I
Operational amplifier A inverting input
VINB+
10
I
Operational amplifier B non-inverting input
VINB–
11
I
Operational amplifier B inverting input
VT
20
I
Boost converter 2 and VCOM reference external thermistor network connection
V25
19
O
Buck converter or LDO regulator output sense
V25_LX
17
P
Buck converter switch node or LDO regulator output
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
PARAMETER
CONDITIONS
FIGURE
BOOSTER CONVERTER 1
Efficiency vs. Load Current
VIN = 3.3 V, AVDD = 5.5 V and 8.5V, L = 10 µH, fSW = 1 MHz
Figure 1
Output Voltage Ripple
VIN = 3.3 V, AVDD = 5.5 V, IAVDD = 200 mA, fSW = 1 MHz
Figure 2
Load Transient Response
VIN = 3.3 V, AVDD = 5.5 V, IAVDD = 20 mA to 200 mA
Figure 3
Startup
VIN = 3.3 V, AVDD = 5.5 V, fSW = 1 MHz, ILOAD = 55 Ω
Figure 4
Over Voltage Protection
VIN = 3.3 V, AVDD = 5.5 V, fSW = 1 MHz
Figure 5
Under Voltage Protection
VIN = 3.3 V, AVDD = 5.5 V, fSW = 1 MHz
Figure 6
Efficiency vs. Load Current
VIN = 3.3 V, V25 = 1.8 V and 2.5 V
Figure 7
Output Voltage Ripple
VIN = 3.3 V, V25 = 2.5 V, IV25 = 600 mA
Figure 8
Load Transient Response
VIN = 3.3 V, V25 = 2.5 V, IV25 = 20 to 200 mA
Figure 9
Startup
VIN = 3.3 V, V25 = 2.5 V, ILOAD = 12.5 Ω
Figure 10
Undervoltage Protection
VIN = 3.3 V, V25 = 2.5 V
Figure 11
Load Transient Response
VIN = 3.3 V, V25 = 2.5 V, IV25 = 20 to 200 mA
Figure 12
Startup
VIN = 3.3 V, V25 = 2.5 V, ILOAD = 12.5 Ω
Figure 13
Undervoltage Protection
VIN = 3.3 V, V25 = 2.5 V
Figure 14
Efficiency vs. Load Current
VIN = 3.3 V, AVDD = 5.5 V, VGH = 16 V, L = 10 µH, fSW = 800 kHz
Figure 15
Efficiency vs. Load Current
VIN = 3.3 V, AVDD = 8.5 V, VGH = 25 V, L = 10 µH, fSW = 800 kHz
Figure 16
Output Voltage Ripple
VIN = 3.3 V, AVDD = 5.5 V, VGH = 16 V, L = 10 µH, IVGH = 50 mA, fSW = 800 kHz
Figure 17
Load Transient Response
VIN = 3.3 V, AVDD = 5.5 V, VGH = 16 V, L = 10 µH, IVGH = 10 to 50 mA
Figure 18
Startup
VIN = 3.3 V, AVDD = 5.5 V, VGH = 16 V, L = 10 µH, fSW = 800 kHz
Figure 19
Under Voltage Protection
VIN = 3.3 V, AVDD = 5.5 V, VGH = 16 V, L = 10 µH, fSW = 800 kHz
Figure 20
BUCK CONVERTER
LDO VOLTAGE REGULATOR
BOOST CONVERTER 2
NEGATIVE CHARGE PUMP REGULATOR CONTROL
Output Voltage Ripple
VIN = 3.3 V, AVDD = 5.5 V, VGL = –4.5 V, IGL = 50 mA
Figure 21
Load Transient Response
VIN = 3.3 V, AVDD = 5.5 V, VGL = –4.5 V, IGL = 10 to 50 mA
Figure 22
GATE VOLTAGE SHAPING
VIN = 3.3 V, AVDD = 5 V, AVDD = 5 V,
Figure 23
OPERATIONAL AMPLIFIER
SLEW RATE
VIN = 3.3 V, VGH = 16 V, NAVDD = –5 V, INA+ = –1 V to 1 V
Figure 24
POWER ON SEQUENCY
VIN = 3.3 V, AVDD = 5.5 V, VGH = 16 V, VGL = –4.5 V
Figure 25
POWER OFF SEQUENCY
VIN = 3.3 V, AVDD = 5.5 V, VGH = 16 V, VGL = –4.5 V
Figure 26
10
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EFFICIENCY
vs
LOAD CURRENT
OUTPUT VOLTAGE RIPPLE
100
AVDD Voltage 20mV/div
90
80
Efficiency (%)
70
60
50
40
LX Voltage 2V/div
30
20
Inductor Current 300mA/div
AVDD
5.5V
AV
V
DD ==5.5
10
AV
V
AVDD
8.5V
DD ==8.5
0
1
10
100
1k
Load Current (mA)
C001
Time (1 µs/div)
Figure 1. Boost Converter 1 Efficiency
Figure 2. Boost Converter 1 Output Ripple
LOAD TRANSIENT RESPONSE
STARTUP
VIN Voltage 2V/div
AVDD Voltage 200mV/div
AVDD Voltage 2V/div
LX Voltage 2V/div
Inductor Current 200mA/div
Load Current 50mA/div
Time (10 ms/div)
Time (2 ms/div)
Figure 3. Boost Converter 1 Load Transient Response
Figure 4. Boost Converter 1 Startup
OVERVOLTAGE PROTECTION
UNDERVOLTAGE PROTECTION
AVDD Voltage 5V/div
AVDD Voltage 2V/div
LX Voltage 5V/div
LX Voltage 2V/div
V25 Voltage 1V/div
V25 Voltage 2V/div
Time (5 ms/div)
Time (50 ms/div)
Figure 5. Boost Converter 1 Overvoltage Protection
Figure 6. Boost Converter 1 Undervoltage Protection
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EFFICIENCY
vs
LOAD CURRENT
OUTPUT VOLTAGE RIPPLE
100
V25 Voltage 10mV/div
90
80
Efficiency (%)
70
60
50
V25_LX Voltage 2V/div
40
30
Inductor Current 300mA/div
20
V25
= 1.8V
V
25 = 1.8 V
10
V25
2.5V
V
V
25 ==2.5
0
1
10
100
1k
Load Current (mA)
C002
Time (2 µs/div)
Figure 7. Buck Converter Efficiency
Figure 8. Buck Converter Output Ripple
LOAD TRANSIENT RESPONSE
STARTUP
VIN Voltage 2V/div
V25 Voltage 100mV/div
V25 Voltage 1V/div
V25_LX Voltage 2V/div
Inductor Current 200mA/div
Load Current 50mA/div
Time (2 ms/div)
Time (10 ms/div)
Figure 9. Buck Converter Load Transient Response
Figure 10. Buck Converter Startup
UNDERVOLTAGE PROTECTION
LOAD TRANSIENT RESPONSE
V25 Voltage 200mV/div
V25 Voltage 1V/div
V25_LX Voltage 2V/div
AVDD Voltage 5V/div
VGH Voltage 10V/div
Load Current 50mA/div
Time (2 ms/div)
Time (50 ms/div)
Figure 11. Buck Converter Undervoltage Protection
12
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Figure 12. LDO Load Transient Response
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STARTUP
UNDERVOLTAGE PROTECTION
VIN Voltage 2V/div
V25 Voltage 1V/div
V25 Voltage 1V/div
AVDD Voltage 3V/div
AVDD Voltage 2V/div
VGH Voltage 10V/div
IIN Current 100mA/div
VGL Voltage 4V/div
Time (50 ms/div)
Figure 14. LDO Undervoltage Protection
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
Time (10 ms/div)
Figure 13. LDO Startup
70
60
50
40
70
60
50
40
AVDD = 5.5 V
AVDD = 5.5V
V
1616V
V
VGH
GH = =
30
20
AVDD = 8.5 V
AVDD = 8.5V
V
2525V
V
VGH
GH = =
30
20
0
10
20
30
40
Load Current (mA)
50
0
10
20
30
40
Load Current (mA)
C003
Figure 15. Boost Converter 2 Efficiency
Figure 16. Boost Converter 2 Efficiency
OUTPUT VOLTAGE RIPPLE
LOAD TRANSIENT RESPONSE
VGH Voltage 10mV/div
50
C004
VGH Voltage 200mV/div
VGH_LX Voltage 6V/div
Load Current 20mA/div
Inductor Current 300mA/div
Time (2 ms/div)
Time (1 µs/div)
Figure 17. Boost Converter 2 Output Ripple
Figure 18. Boost Converter 2 Load Transient Response
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STARTUP
UNDERVOLTAGE PROTECTION
AVDD Voltage 3V/div
VGH Voltage 2V/div
VGH Voltage 8V/div
VGH_LX Voltage 3V/div
VGH_LX Voltage 8V/div
AVDD Voltage 3V/div
Inductor Current 300mA/div
Time (50 ms/div)
Time (10 ms/div)
Figure 19. Boost Converter 2 Startup
Figure 20. Boost Converter 2 Undervoltage Protection
OUTPUT VOTLAGE RIPPLE
LOAD TRANSIENT RESPONSE
VGL Voltage 20mV/div
VGL Voltage 50mV/div
Load Current 20mA/div
LX Voltage 2V/div
Inductor Current 100mA/div
Time (1 µs/div)
Time (2 ms/div)
Figure 21. Negative Charge Pump Output Ripple
Figure 22. Negative Charge Pump Load Transient Response
GATE VOLTAGE SHAPING
SLEW RATE
INA+ Voltage 500mV/div
VGH Voltage 8V/div
VOUTA Voltage 500mV/div
VGHM Voltage 8V/div
FLK Voltage 2V/div
Time (10 µs/div)
Time (20 ns/div)
Figure 23. Gate Voltage Shaping
14
Figure 24. Operational Amplifier Slew Rate
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POWER ON SEQUENCY
POWER OFF SEQUENCY
VIN
VIN
V25
V25
RESET
RESET
AVDD
AVDD
VGH
VGH
VGL
VGL
VGPM
VGPM
VCOM
VCOM
Time (10 ms/div)
Time (10 ms/div)
Figure 25. Power Off Sequency
Figure 26. Power Off Sequency
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DETAILED DESCRIPTION
An internal block diagram of the TPS65640 is shown in Figure 27.
COMP
LX
Current
Limit
AVDD
DAC
Gm
VREF
Gate
Driver
VIN
PGND3
V25_LX
VREF
LDO Mode
V25
R
DAC
VREF
Gate
Driver
Latch
Off-Time
Control
RESET
S
PGND2
DAC
AGND
VCOM_OUT
DAC
1.25 V
VT
VGH_LX
6
40 µA
ADC
0.5 V
R
DAC
Latch
VGH
Off-Time
Control
Gate
Driver
PGND1
S
VGHM
FLK
Logic
Control
AVDD
RE
VINA+
VINA-
DRVN
VIN
OUTA
VCC
VREF
VINB+
VINBOUTB
NAVDD
DAC
VGL
SDA
EEprom
DAC
Register
SCL
Figure 27. Internal Block Diagram
16
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BOOST CONVERTER 1 (AVDD)
VIN
L1
D1
AV DD
VIN
AVDD
LX
COUT1
R1
Current
Limit
DAC
Gate
Driver
Gm
VREF
Q1
R2
COMP
PGND3
200 kΩ
1 nF
Figure 28. Boost Converter 1 Internal Block Diagram
Switching Frequency (Boost Converter 1)
Boost Converter 1 can be configured to operate at 600 kHz, 800 kHz, 1000 kHz, or 1200 kHz. In general, the
higher switching frequency offers better transient performance at the expense of slightly reduced efficiency. In
some applications, it may be necessary to select a particular switching frequency to minimize EMI problems. The
switching frequency is determined by the state of the FREQ1 configuration bit in the AVDDCONFIG register.
Compensation (Boost Converter 1)
Boost Converter 1 uses an external compensation network connected to its COMP pin to stabilize its feedback
loop. A simple series R-C network connected between this pin and ground is sufficient to achieve good
performance (that is, stable and with good transient response) in most applications. Good starting values, which
will work for many applications, are 200 kΩ and 1 nF.
In some applications (for example, those using electrolytic output capacitors), it may be necessary to include a
second compensation capacitor between the COMP pin and ground. This has the effect of adding an additional
pole in the feedback loop's frequency response, which can be used to cancel the zero introduced by the
electrolytic output capacitor's ESR.
Output Voltage (Boost Converter 1)
Boost converter 1's output voltage can be programmed from 3.6 V to 11 V with 100-mV increment using the
AVDD register. Because changing the output voltage in big steps can temporarily demand switch currents
greater than the switch's current limit, it is recommended that AVDD be changed in 100-mV steps, for example,
first change AVDD from 7 V to 7.1 V, then to 7.2 V, then to 7.3 V, and so on until the desired output voltage has
been achieved.
Start-Up (Boost Converter 1)
Boost converter 1 starts immediately after the V25 voltage raming to its programmed voltage.
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To minimize inrush current during start-up, boost converter 1 ramps its output voltage in tSS1 milliseconds. The
value of tSS1 can be programmed from 20ms to 80ms using the SS1 bits in AVDDCONFIG register.
Boost converter 1's internal power good signal is asserted when two conditions are met:
• the converter's soft-start ramp has reached its final value
• the converter's output voltage is greater than its UVP threshold.
The power good signal is latched and will only be reset when the supply voltage is cycled.
Current limit (Boost Converter 1)
The boost converter 1 has built-in cycle-by-cycle current limit for the power MOSFET. When the inducotr current
or the power MOSFET current reaches ILIM, the power MOSFET will be tuned off immediately until the next
switching cycle. The ILIM can be programmed from 1 A to 2 A using the AVDD ILIM bit in AVDDCONFIG register.
Design Procedure (Boost Converter 1)
The first step in the design procedure is to verify whether the maximum possible output current of the boost
converter 1 supports the specific application requirements.
1. Converter Duty Cycle:
V ´h
D = 1 - IN
VAVDD
(1)
2. Inductor Ripple Current:
V ´D
DIL = IN
fs ´ L
3. Maximum Output Current:
DI
æ
IOUT _ max = ç ILIM _ min - L
2
è
(2)
ö
÷ ´ (1 - D )
ø
(3)
4. Peak Switching Current:
I
DI
ISWPEAK = OUT + L
1- D
2
(4)
η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.9 as an estimation)
fS = Switching frequency
L = Selected inductor value (typ. 10 µH)
ILIM_min: Minimum current limit
ISWPEAK = Peak switch current for the used output current
ΔIL = Inductor peak-to-peak ripple current
The peak switch current ISWPEAK is the current that the integrated switch, the inductor and the external Schottky
diode have to be able to handle. The calculation must be done for the minimum input voltage where the peak
switch current is the highest.
Inducotr Selection (Boost Converter 1)
Inductor Value:
Saturation Current:
DC Resistance:
18
Higher the inductor value the lower the inductor current ripple and the output
voltage ripple but the slower the transient response.
4.7 µH ≤ L ≤ 10 µH
ISAT ≥ ISWPEAK or ISAT ≥ ILIM_max
The inductor saturation current must be higher than the switch peak current for
the max. peak output current or as a more conservative approach higher than
the max. switch current limit.
The lower the inductors resistance the lower the losses and the higher the efficiency.
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Rectifier Diode Selection (Boost Converter 1)
Diode type: Schottky or super barrier rectifier (SBR) for better efficiency.
Forward voltage: The lower the forward voltage VF the higher the efficiency and the lower the diode temperature.
Reverse voltage: VR must be higher than the output voltage and should be higher than the OVP voltage typically
15 V.
Thermal characteristics: The diode must be able to handle the dissipated power of PD = VF x IOUT.
Output Capacitor Selection (Boost Converter 1)
For best output voltage filtering, TI recommends low-ESR ceramic capacitors. Two 4.7 µF (or four 2.2-µF)
ceramic capacitors work for most applications. To improve the load transient response more capacitance can be
added between the rectifier diode.
To calculate the output voltage ripple the following equations can be used:
- VIN IOUT
V
DVC _ RIPPLE = AVDD
+ DVC _ ESR
x
VAVDD ´ fs COUT
(5)
DVC _ ESR = ISWPEAK ´ RC _ ESR
(6)
BUCK CONVERTER (V25)
The buck converter uses a current mode, quasi-constant off-time topology that offers high efficiency, fast
transient response, and constant ripple current amplitude under all operating conditions (see Figure 29). The
converter's off time is inversely proportional V25 and therefore constant when the converter is in regulation. Thus
for a given VIN the converter operates at a constant frequency that changes temporarily when the converter
reacts to load changes.
When the latch is set, transistor Q1 is turned on and transistor Q2 is turned off. As inductor L2 charges, the
current flowing through Q1 ramps up at a rate determined by the difference between VIN and VCORE and the value
of L2. The ramping current is sensed across Q1, and when it reaches the level demanded by error amplifier A1
the output of comparator A2 goes high, resetting the latch. The reset latch turns off Q1 and turns on Q2. Inductor
L2 now discharges through Q2 for a fixed off time. At the end of the off time, the latch is set, turning on Q1 and
turning off Q2, and the cycle repeats.
The sensed output voltage is divided down by a multiplying DAC and used as negative feedback to amplifier A1.
The output of A1 is the error signal required to regulate V25 at the desired voltage.
VIN
Q1
VREF
A2
R
A1
L2
DAC
Latch
Off-Time
Control
S
V25
Gate
Driver
V25_LX
COUT2
Q2
V25
PGND2
Figure 29. Buck Converter 1 Block Diagram
Output Voltage (Buck Converter)
Buck converter's output voltage can be programmed from 1.5 V to 3.0 V using the V25 register.
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Start-Up (Buck Converter)
Buck converter starts as soon as the supply voltage exceeds the under-voltage lockout threshold (the same time
as the linear regulator starts).
To minimize inrush current during start-up, buck converter ramps V25 from 0 V to programmed voltage in tSS2
milliseconds. The value of tSS2 is around 0.5 ms to 4.0 ms.
The same ramp rate is used for both buck converter and the linear regulator (LDO).
Current limit (Buck Converter)
The buck converter has built-in cycle-by-cycle current limit for the high side power MOSFET, Q1 in Figure 29.
When the inductor current or the MOSFET Q1 current reaches ILIM, the Q1 is tuned off immediately until the next
switching cycle. The ILIM is typically 1.2 A.
Design Procedure (Buck Converter)
The first step in the design procedure is to verify whether the maximum possible output current of the buck
converter supports the specific application requirements.
1. Switching Frequency:
V ´ h - V25
fs = IN
VIN ´ h ´ Toff
(7)
2. Converter Duty Cycle
V25
D=
VIN ´ h
(8)
3. Inductor Ripple Current:
DIL =
(VIN - V25 )´ D
fs ´ L
(9)
4. Maximum Output Current:
DI
IOUT _ max = ILIM _ min - L
2
5. Peak Switching Current:
DI
ISWPEAK = IOUT + L
2
(10)
(11)
Toff = Buck boost switch duty off time (typ. 200 ns)
η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.8 as an estimation)
fS = Switching frequency
L = Selected inductor value (typ. 10 µH)
ILIM_min: Minimum current limit
ISWPEAK = Peak switch current for the used output current
ΔIL = Inductor peak-to-peak ripple current
The peak switch current ISWPEAK is the current that the integrated switch, the inductor and the external Schottky
diode have to be able to handle. The calculation must be done for the minimum input voltage where the peak
switch current is the highest.
Inducotr Selection (Buck Converter)
Inductor Value:
20
4.7 µH ≤ L ≤ 10 µH
Higher the inductor value the lower the inductor current ripple and the output
voltage ripple but the slower the transient response.
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Saturation Current:
DC Resistance:
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ISAT ≥ ISWPEAK or ISAT ≥ ILIM_max
The inductor saturation current must be higher than the switch peak current for
the max. peak output current or as a more conservative approach higher than
the max. switch current limit.
The lower the inductors resistance the lower the losses and the higher the efficiency.
Output Capacitor Selection (Buck Converter)
For best output voltage filtering, TI recommends low-ESR ceramic capacitors. Two 4.7-µF (or four 2.2-µF)
ceramic capacitors work for most applications. To improve the load transient response more capacitance can be
added between the rectifier diode.
To calculate the output voltage ripple the following equations can be used:
V25
I
DVC _ RIPPLE =
´ OUT + DVC _ ESR
VIN ´ fs COUT
(12)
DVC _ ESR = ISWPEAK ´ RC _ ESR
(13)
LDO REGULATOR (V25)
A low-dropout (LDO) linear regulator generates V25 (see Figure 30). The linear regulator is supplied from VIN and
it’s an alternative option to buck converter. The V25 voltage could be supplied either by Buck converter or LDO
determined by the state of the BUCK/LDO configuration bit in the CONFIG register.
VIN
Q1
Q2
Body
diode
V25
V25_LX
COUT3
VREF
Q3
A1
DAC
V25
R1
AGND
AGND
Figure 30. Linear Regulator Block Diagram
Amplifier A1 regulates the current through Q3 by comparing a reduced version of the output voltage with a
bandgap voltage reference VREF. The output of Q3 is mirrored by Q1 and Q2 to generate the desired output
voltage. In practice, Q2 is made much bigger than Q1. This means that the current flowing through Q1 and Q3 is
smaller than the output current by the same ratio as the transistor areas.
The maximum output current is inherently limited by the maximum output voltage of A1, the value of resistor R1,
and the characteristics of transistor Q3.
Output Voltage (LDO Regulator)
LDO's output voltage can be programmed from 1.5 V to 3.0 V using the V25 register. Because the V25_LX pin
alternates for LDO regulator's output voltage and buck converter's switch node, select buck converter with LDO
circuit configuration can make the permanent damage. The LDO regulator mode is factory default setup.
Start-Up (Low Dropout Regulator)
LDO starts as soon as the supply voltage exceeds the under-voltage lockout threshold (the same time as the
buck converter starts).
To minimize inrush current during start-up, LDO regulator ramps V25 from 0V to programmed voltage in tSS2
milliseconds. The value of tSS2 is around 0.5 ms to 4.0 ms.
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The same ramp rate is used for both buck converter and the linear regulator.
BOOST CONVERTER 2 (VGH)
Boost converter 2 is a low-power boost converter that can be used to generate the LCD panel's gate ON voltage
VGH. Operating the converter in DCM removes the right-half-plane zero from its transfer function, simplifying its
stabilization and allowing the use of small chip inductors. To simplify its application and to minimize the external
parts required, boost converter 2 features internal compensation and soft-start circuitry.
A simplified block diagram of boost converter 2 is shown in Figure 31.
D4
L4
AV DD
VGH
VGH_LX
DAC
COUT4
R
A2
A1
Latch
Off-Time
Control
Q1
Gate
Driver
S
VGH
PGND1
Figure 31. Boost Converter 2 Block Diagram
Switching Frequency (Boost Converter 2)
Boost Converter 2 can be configured to operate at 400 kHz or 800 kHz. The switching frequency is determined
by the state of the FREQ4 configuration bit in the VGHCONFIG register.
Output Voltage Temperature Compensation (Boost Converter 2)
Boost converter 2 can be temperature compensated, allowing its output voltage to transition from a higher
voltage at low temperatures VGH(COLD) to a lower voltage at high temperatures VGH(HOT) (see Figure 32 and
Figure 33).
VGH
VGHCOLD
VGHHOT
TCOLD
THOT
Temperature
Figure 32. Boost Converter 2 Temperature Compensation Characteristic
22
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1.25 V
VT
40 µA
6
ADC
A1
R1
R2
0.5 V
VGHHOT
5 Bits
PWM
Controller
DAC
VGH
RT
VGHCOLD
5 Bits
Figure 33. Boost Converter 2 Temperature Compensation Block Diagram
Referring to Figure 33, The thermistor network formed by R1, R2, and RT (1) generates a voltage at the VT pin
whose value decreases with increasing temperature. With proper selection (2) of the external components RT, R1
and R2, temperatures THOT and TCOLD can be configured to suit each display's characteristics. A spreadsheet
allowing easy calculation of component values is available from Texas Instruments free of charge.
Output Voltage (Boost Converter 2)
The output voltage of boost converter 2 at cold temperatures can be programmed from 15 V to 37 V using the
VGHCOLD register.
The output voltage of boost converter 2 at hot temperatures can be programmed from 15 V to 37 V using the
VGHHOT register.
In applications that do not require temperature compensation, the VGHT bit in CONFIG register should be set to
1 and the VGHHOT register used to set the voltage of VGH.
Because changing the output voltage in big steps can temporarily demand switch currents greater than the
switch's current limit, it is recommended that VGH be changed in 1 V steps, i.e. first change VGH from 15 V to 16
V, then to 16 V, then to 17 V, and so on until the desired output voltage has been achieved.
Start-Up (Boost Converter 2)
Boost converter 2 is enabled when AVDD has finished ramping to its programmed voltage.
To minimize inrush current during start-up, boost converter 2 ramps VGH to its programmed value in tSS4
seconds. The value of tSS4 can be programmed from 4 ms to 16 ms using the SS4 bits in VGHCONFIG register.
The same ramp rate is used for both boost converter 2 and the negative charge pump regulator.
Boost converter 2's internal power good signal is asserted when two conditions are met:
• the converter's soft-start ramp has reached its final value
• the converter's output voltage is greater than its UVP threshold.
The power good signal is latched and will only be reset when the supply voltage is cycled.
Current limit (Boost Converter 2)
The boost converter 2 has built-in cycle-by-cycle current limit for the power MOSFET. When the inducotr current
or the power MOSFET current reaches ILIM, the power MOSFET will be tuned off immediately until the next
switching cycle. The ILIM is typically 1.2 A for boost converter 2.
Design Procedure (Boost Converter 2)
The first step in the design procedure is to verify whether the maximum possible output current of the boost
converter supports the specific application requirements.
1. Converter Duty Cycle:
(1)
(2)
RT should be a negative temperature coefficient (NTC) type whose resistance at 25°C is 10kΩ.
Texas Instruments can provide a spreadsheet that calculates suitable component values automatically.
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V
´h
D = 1 - AVDD
VGH
2. Inductor Ripple Current:
´D
V
DIL = AVDD
fs ´ L
(14)
(15)
3. Maximum Output Current:
DI ö
æ
IOUT _ max = ç ILIM _ min - L ÷ ´ (1 - D )
2 ø
è
4. Peak Switching Current:
I
DI
ISWPEAK = OUT + L
1- D
2
(16)
(17)
η = Estimated boost converter efficiency (use the number from the efficiency plots or 0.9 as an estimation)
fS = Switching frequency
L = Selected inductor value (typ. 10 µH)
ILIM_min: Minimum current limit
ISWPEAK = Peak switch current for the used output current
ΔIL = Inductor peak-to-peak ripple current
The peak switch current ISWPEAK is the current that the integrated switch, the inductor and the external Schottky
diode have to be able to handle. The calculation must be done for the minimum input voltage where the peak
switch current is the highest.
Inducotr Selection (Boost Converter 2)
Inductor Value:
Saturation Current:
DC Resistance:
Higher the inductor value the lower the inductor current ripple and the output
voltage ripple but the slower the transient response.
4.7 µH ≤ L ≤ 10 µH
ISAT ≥ ISWPEAK or ISAT ≥ ILIM_max
The inductor saturation current must be higher than the switch peak current for
the max. peak output current or as a more conservative approach higher than
the max. switch current limit.
The lower the inductors resistance the lower the losses and the higher the efficiency.
Rectifier Diode Selection (Boost Converter 2)
Diode type: Schottky or super barrier rectifier (SBR) for better efficiency.
Forward voltage: The lower the forward voltage VF the higher the efficiency and the lower the diode temperature.
Reverse voltage: VR must be higher than the output voltage and should be higher than the OVP voltage 39 V.
Thermal characteristics: The diode must be able to handle the dissipated power of PD = VF x IOUT.
Output Capacitor Selection
For best output voltage filtering, TI recommends low-ESR ceramic capacitors. Two 4.7-µF (or four 2.2-µF)
ceramic capacitors work for most applications. To improve the load transient response more capacitance can be
added between the rectifier diode.
To calculate the output voltage ripple the following equations can be used:
V - VAVDD IOUT
DVC _ RIPPLE = GH
´
+ DVC _ ESR
VGH ´ fs
COUT
DVC _ ESR = ISWPEAK ´ RC _ ESR
24
(18)
(19)
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NEGATIVE CHARGE PUMP VOLTAGE REGULATOR CONTROL (VGL)
The negative charge pump voltage regulator control an external NPN transistor to regulate the VGL output. As
typical application circuit Figure 34 illustrated, a one time negative voltage charge pump based on the AVDD
boost switching provides the source voltage to the emitter of NPN transistor. Depending on the feedback voltage
applied on the VGL pin, A1 error amplifier regulates the current through Q3. The proportional current mirrored by
Q1 to Q2 sends to the base of NPN transistor from DRVN pin. Therefore, the regulation is achieved by controlled
voltage drop between collector and emitter of NPN transition.
Normally the negative charge pump regulator is to provide gate OFF voltage to the gate driver or level shift. In
additional, for positive and negative AVDD application, it can also be used for negative AVDD regulating. Because
of charge bump voltage loss, it is recommended to leave enough voltage guard band (for example, 1 V for 50mA load) between positive AVDD to negative AVDD.
R1
LX
VGL
COUT5
VIN
Q1
Q2
DRVN
VCC
VREF
Q3
A1
DAC
VGL
AGND
Figure 34. Negative Charge Pump Block Diagram
Output Voltage (Negative Charge Pump)
Negative charge pump's output voltage can be programmed from –8 V to –3.8 V using the VGL register.
Start-Up (Negative Charge Pump)
Negative charge pump is enabled together with booster converter 2 when AVDD has finished ramping to its
programmed voltage.
The same ramp rate is shared for both boost converter 2 and negative charge pump regulator. The negative
charge pump regulator ramps VGL to its programmed value from 0V in tSS4 seconds. The value of tSS4 can be
programmed from 4 ms to 16 ms using the SS4 bits in VGHCONFIG register.
NPN Transistor Selection (Negative Charge Pump)
The NPN transistor used to regulator VGL or Negtive AVDD should have a DC gain (hFE) of at least 100 when its
collector current is equal to the charge pump's output current. The transistor should also be able withstand
voltages up to VIN across its collector-emitter (VCE).
The power dissipated in the transistor is given by Equation 20. The transistor must be able to dissipate this
power without its junction becoming too hot. Note that the ability to dissipate power depends on adequate PCB
thermal design.
PQ = [VIN -(2 ´ VF )- | VGL |] ´ IGL
(20)
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Where IGL is the mean (not RMS) output current drawn from the charge pump.
Diode Selection (Negative Charge Pump)
Small-signal diodes can be used for most low current applications ( 160 ms
VGH boost converter is disabled.
Error condition is removed and VIN is
cycled (POR).
PROTECT BEHAVIOR
RECOVERY CONDITION
RESET GENERATOR
The RESET pin generates an active-low reset signal for the T-CON (see Figure 35). During power-up the reset
timer (tRESET) starts when V25 has finished ramping. The reset pulse duration can be programmed from 0 ms to
30 ms using the RESET register.
The RESET output is an open-drain type that requires an external pull-up resistor. Pull-up resistor values in the
range 10 kΩ to 100 kΩ are recommended for most applications.
26
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RESET
V25
OSC
VREF
CLK
H
Reset
EN Timer Q
DAC
≥
D
RST
RST
Figure 35. Reset Internal Block Diagram
GATE VOLTAGE SHAPING
The gate voltage shaping function can be used to reduce image sticking in LCD panels by modulating the LCD
panel's gate ON voltage (VGH). Figure 36 shows a block diagram of the gate voltage shaping function and
Figure 37 shows the typical waveforms during operation.
VGH
VGH
Q1
VGHM
FLK
Control
Logic
CVGHM
4.7 nF
VGHM
Q2
RE
RE
Figure 36. Gate Voltage Shaping Block Diagram
VGHPG
FLK
Don’t Care
tDLY
VGHM
Figure 37. Gate Voltage Shaping Waveforms
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Gate voltage shaping is controlled by the FLK input. When FLK is high, Q1 is on, Q2 is off, and VGHM is equal to
VGH. On the falling edge of FLK, Q1 is turned off, Q2 is turned on, and the LCD panel load connected to the
VGHM pin discharges through the external resistor connected to the RE pin.
During power-up Q2 is held permanently on and Q1 permanently off, regardless of the state of the FLK signal,
until tDLY milliseconds after boost converter 2 (VGH) has finished ramping. The value of tDLY can be programmed
from 0ms to 60ms using the DLY register.
During power-down Q2 is held permanently on and Q1 permanently off, regardless of the state of the FLK signal.
PROGRAMMABLE VCOM CALIBRATOR (VCOM)
The programmable VCOM calibrator uses a DAC to generate an offset Voltage for LCD panel common voltage
reference.
AVDD
1.25 V
6
VT
ADC
R1
40 µA
VCOM
Temp
0.5 V
VCOM_OUT
RT
I2C Interface
R2
VCOMHOT
10-Bits
VCOMHOT
10-Bits RAM
VCOMCOLD
10-Bits
VCOMCOLD
10-Bits RAM
DAC
VCOM
7-Bits RAM
NAVDD
Figure 38. Programmable VCOM Calibrator Block Diagram
The VCOM voltage calibration needs two steps for adjustment.
First step is to set the central value of VCOM voltage according to the AVDD, VGH and LCD panel characteristic.
The VCOM voltage is programmable from 1.5 V to 5.0 V or –4 V to 0.8 V by VCOMHOT register. The first step is
normally done by PCB assembly manufacturer.
Second step is to calibrate the VCOM voltage on the LCD panel assembly line by VCOM RAM register through I2C
digital interface. The VCOM register value indicates the voltage increment or decrement of VCOM_OUT which is
preset by VCOMHOT. Once the proper value is identified, the VCOM_OUT voltage value can be renewed with
VCOM register value added. The default value for VCOM register is 1000000. If 1000001 is written into VCOM
register, the VCOM_OUT voltage will increase with one DAC step, 10mV. In the other hand if 0111111 is written
to VCOM register, the VCOM_OUT voltage will decrease with one DAC step, 10 mV.
The VCOM voltage also supports temperature compensation and allows its output voltage to transition from a
lower voltage at low temperatures VCOMCOLD to a higher voltage at high temperatures VCOMHOT (see Figure 39).
The temperature compensation for VCOM could be turn on/off by bit VCOMT in register CONFIG. If temperature
compensation for VCOM is ON state, both VCOMHOT and VCOMCOLD need to be input. Otherwise only
VCOMHOT is active for VCOM voltage setting without temperature compensation.
28
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VCOM
VCOMHOT
VCOMCOLD
TCOLD
THOT
Temperature
Figure 39. VCOM Temperature Compensation Characteristic
OPERATIONAL AMPLIFIERS
Like most operational amplifiers, the VCOM amplifiers are not designed to drive purely capacitive loads, so it is not
recommended to connect a capacitor directly to their outputs in an attempt to increase performance; however,
the amplifiers are capable of delivering high peak currents that make such capacitors unnecessary.
To optimize performance, the VCOM amplifiers' positive supplies are connected internally to the AVDD pin and
negative supplies are connected internally to NAVDD pin (See Figure 40 for operational amplifier internal block
diagram).
AVDD
VINA+
OUTA
VINA-
VINB+
OUTB
VINB-
NAVDD
Figure 40. Operational Amplifier Block Diagram
The two integrated operational amplifiers are able to be disabled for non-used application to minimize the power
consumption. Setting the OPA_A bit or OPA_B bit in CONFIG register can turn on/off operational amplifier A or
B individually.
To minimize the addtional power dissipated when operational amplifier is turned off, it is recommanded to short
the both inverter input and non-inverter input to same voltage bias or leave them floating.
CONFIGURATION PARAMETERS
The TPS65640 divides the configuration parameters into two categories:
• VCOM calibration
• All other configuration parameters
In typical applications, all configuration parameters except VCOM are programmed by the subcontractor during
PCB assembly, and VCOM is programmed by the display manufacturer during display calibration.
RAM and E2PROM
Configuration parameters can be changed by writing the desired values to the appropriate RAM register or
registers. The RAM registers are volatile and their contents are lost when power is removed from the device. By
writing to the Control Register, it is possible to store the active configuration in non-volatile E2PROM so that it will
subsequently be used as the default setting upon when the device is powered up.
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Configuration Parameters (Excluding VCOM Calibration)
Table 2 shows the memory map of the configuration parameters.
Table 2. Configuration Memory Map
30
Register
Address
Register
Name
Factory
Default
Description
00h
CONFIG
FAh
Sets function control bits
01h
AVDD
3Ah
Sets the output voltage of AVDD boost converter
02h
AVDDCONFIG
0Ah
Sets miscellaneous configuration bits for AVDD boost converter
03h
VGHHOT
09h
Sets the output voltage of VGH boost converter at high temperatures (VGHT = 0) or
VGH boost converter (VGHT=1)
04h
VGHCOLD
09h
Sets the output voltage of VGH boost converter at low temperatures (VGHT=0)
05h
VGHCONFIG
02h
Sets miscellaneous configuration bits for VGH boost converter
06h
VGL
1Fh
Sets the output voltage of VGL linear regulator
07h
V25
0Ah
Sets the output voltage of buck converter.
08h
VDIV
01h
Sets the threshold of the /RST signals
09h
RESET
06h
Sets the reset pulse duration
0Ah
DLY
01h
Sets the gate voltage shaping delay
0Bh
VCOMHOT
5Fh
Presets the output voltage of VCOM reference at high temperatures (VCOMT = 0) or
VCOM reference (VCOMT=1)
0Ch
VCOMCOLD
5Fh
Presets the output voltage of VCOM reference at low temperatures (VCOMT=0)
FFh
Control
00h
Controls whether read and write operations access RAM or E2PROM registers
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CONFIG (00h)
The CONFIG register can be written to and read from.
Table 3. CONFIG Register Bit Allocation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCOMR
VCOMT
OPA_B
OPA_A
BUCK/LDO
VGL
VGHT
VGH
VGH
Bit
0
This bit enables/disables the boost converter for VGH voltage regulator.
0
Enables the VGH boot converter
1
Disables the VGH boost converter
VGHT
Bit
1
This bit enables/disables the temperature compensation for VGH regulator.
0
Enables the temperature compensation for VGH voltage regulator
1
Disables the temperature compensation for VGH voltage regulator
VGL
Bit
2
This bit enables/disables the VGL linear voltage regulator.
0
Enables the VGL linear voltage regulator
1
Disables the VGL linear voltage regulator
BUCK/LDO
Bit
3
This bit selects the operation mode for V25 voltage regulator.
0
Selects the Buck converter for V25 voltage regulator
1
Selects the LDO for V25 voltage regulator
OPA_A
Bit
4
This bit enables/disables the OPA_A operational amplifier.
0
Enables the OPA_A operational amplifier
1
Disables the OPA_A operational amplifier
OPA_B
Bit
5
This bit enables/disables the OPA_B operational amplifier.
0
Enables the OPA_B operational amplifier
1
Disables the OPA_B operational amplifier
VCOMT
Bit
6
This bit enables/disables the temperature compensation for VCOM voltage
0
Enables the temperature compensation for VCOM voltage
1
Disables the temperature compensation for VCOM voltage
VCOMR
Bit
7
This bit sets the VCOM voltage output range
0
VCOM = 0.8 V ~ 5 V for full AVDD Application
1
VCOM = –4.1 V ~ 0.2 V for PN AVDD Application
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AVDD (01h)
The AVDD register can be written to and read from.
Table 4. AVDD Register Bit Allocation
Bit 7
Bit 6
Bit 5
Reserved
AVDD
32
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AVDD
Bits
6-0
These bits select boost converter 1's output voltage (AVDD)
0000000
N.A.
1000010
AVDD = 6.6 V
……
N.A.
1000011
AVDD = 6.7 V
0100100
AVDD = 3.6 V
1000100
AVDD = 6.8 V
0100101
AVDD = 3.7 V
1000101
AVDD = 6.9 V
0100110
AVDD = 3.8 V
1000110
AVDD = 7.0 V
0100111
AVDD = 3.9 V
1000111
AVDD = 7.1 V
0101000
AVDD = 4.0 V
1001000
AVDD = 7.2 V
0101001
AVDD = 4.1 V
1001001
AVDD = 7.3 V
0101010
AVDD = 4.2 V
1001010
AVDD = 7.4 V
0101011
AVDD = 4.3 V
1001011
AVDD = 7.5 V
0101100
AVDD = 4.4 V
1001100
AVDD = 7.6 V
0101101
AVDD = 4.5 V
1001101
AVDD = 7.7 V
0101110
AVDD = 4.6 V
1001110
AVDD = 7.8 V
0101111
AVDD = 4.7 V
1001111
AVDD = 7.9 V
0110000
AVDD = 4.8 V
1010000
AVDD = 8.0 V
0110001
AVDD = 4.9 V
1010001
AVDD = 8.1 V
0110010
AVDD = 5.0 V
1010010
AVDD = 8.2 V
0110011
AVDD = 5.1 V
1010011
AVDD = 8.3 V
0110100
AVDD = 5.2 V
1010100
AVDD = 8.4 V
0110101
AVDD = 5.3 V
1010101
AVDD = 8.5 V
0110110
AVDD = 5.4 V
1010110
AVDD = 8.6 V
0110111
AVDD = 5.5 V
1010111
AVDD = 8.7 V
0111000
AVDD = 5.6 V
1011000
AVDD = 8.8 V
0111001
AVDD = 5.7 V
1011001
AVDD = 8.9 V
0111010
AVDD = 5.8 V
1011010
AVDD = 9.0 V
0111011
AVDD = 5.9 V
1011011
AVDD = 9.1 V
0111100
AVDD = 6.0 V
1011100
AVDD = 9.2 V
0111101
AVDD = 6.1 V
1011101
AVDD = 9.3 V
0111110
AVDD = 6.2 V
1011110
AVDD = 9.4 V
0111111
AVDD = 6.3 V
1011111
AVDD = 9.5 V
1000000
AVDD = 6.4 V
1100000
AVDD = 9.6 V
1000001
AVDD = 6.5 V
1100001
AVDD = 9.7 V
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1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
AVDD = 9.8 V
AVDD = 9.9 V
AVDD = 10.0 V
AVDD = 10.1 V
AVDD = 10.2 V
AVDD = 10.3 V
AVDD = 10.4 V
AVDD = 10.5 V
AVDD = 10.6 V
AVDD = 10.7 V
AVDD = 10.8 V
AVDD = 10.9 V
AVDD = 11.0 V
AVDD = 11.1 V
AVDD = 11.2 V
AVDD = 11.3 V
AVDD = 11.4 V
AVDD = 11.5 V
AVDD = 11.6 V
AVDD = 11.7 V
AVDD = 11.8 V
AVDD = 11.9 V
AVDD = 12.0 V
AVDD = 12.1 V
AVDD = 12.2 V
AVDD = 12.3 V
AVDD = 12.4 V
AVDD = 12.5 V
AVDD = 12.6 V
AVDD = 12.7 V
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AVDDCONFIG (02h)
The AVDDCONFIG register can be written to and read from.
Table 5. AVDDCONFIG Register Bit Allocation
Bit 7
Bit 6
Bit 5
Reserved
AVDD ILIM
Bit 4
Bit 3
SSI
Bit 2
FREQ1
Bit 1
Bit 0
LX1TS
LX1TS
Bit
1-0
These bits configure the falling speed of AVDD boost switch.
00
Tf = 0.5 V/ns
01
Tf = 0.7 V/ns
10
Tf = 0.9 V/ns
11
Tf = 1.1 V/ns
FREQ1
Bit
3-2
These bits configure the switching frequency of AVDD boost.
00
fLX = 600 kHz
01
fLX = 800 kHz
10
fLX = 1000 kHz
11
fLX = 1200 kHz
SSI
Bit
5-4
These bits configure the soft start duration for AVDD boost regulator
00
tSS1 = 20 ms
01
tSS1 = 40 ms
10
tSS1 = 60 ms
11
tSS1 = 80 ms
AVDD ILIM
Bit
6
This bit select the AVDD boost current limite value
0
ILIM = 1 A
1
ILIM = 2 A
Reserved
Bits
7
This bit is reserved for future use. During write operations data intended for these bits is ignored, and during
read operations 0 is returned.
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VGHHOT (03h)
The VGHHOT register can be written to and read from.
Table 6. VGHHOT Register Bit Allocation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Reserved
Bit 2
Bit 1
Bit 0
VGHHOT
VGHHOT
Bits
4-0
These bits select VGH output voltage at hot temperatures (VGHT=0) or all temperature range (VGHT=1).
00000
N.A.
10000
VGHHOT = 22 V
00001
N.A.
10001
VGHHOT = 23 V
00010
N.A.
10010
VGHHOT = 24 V
00011
N.A.
10011
VGHHOT = 25 V
00100
N.A.
10100
VGHHOT = 26 V
00101
N.A.
10101
VGHHOT = 27 V
00110
N.A.
10110
VGHHOT = 28 V
00111
N.A.
10111
VGHHOT = 29 V
01000
N.A.
11000
VGHHOT = 30 V
01001
VGHHOT = 15 V
11001
VGHHOT = 31 V
01010
VGHHOT = 16 V
11010
VGHHOT = 32 V
01011
VGHHOT = 17 V
11011
VGHHOT = 33 V
01100
VGHHOT = 18 V
11100
VGHHOT = 34 V
01101
VGHHOT = 19 V
11101
VGHHOT = 35 V
01110
VGHHOT = 20 V
11110
VGHHOT = 36 V
01111
VGHHOT = 21 V
11111
VGHHOT = 37 V
Reserved
Bits
7-5
These bits are reserved for future use. During write operations data intended for these bits is ignored, and
during read operations 0 is returned.
VGHCOLD (04h)
The VGHCOLD register can be written to and read from.
Table 7. VGHCOLD Register Bit Allocation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Reserved
Bit 2
Bit 1
Bit 0
VGHCOLD
VGHCOLD
Bits
4-0
These bits select VGH output voltage at cold temperatures (VGHT=0)
00000
N.A.
10000
VGHCOLD = 22 V
00001
N.A.
10001
VGHCOLD = 23 V
00010
N.A.
10010
VGHCOLD = 24 V
00011
N.A.
10011
VGHCOLD = 25 V
00100
N.A.
10100
VGHCOLD = 26 V
00101
N.A.
10101
VGHCOLD = 27 V
00110
N.A.
10110
VGHCOLD = 28 V
00111
N.A.
10111
VGHCOLD = 29 V
01000
N.A.
11000
VGHCOLD = 30 V
01001
VGHCOLD = 15 V
11001
VGHCOLD = 31 V
01010
VGHCOLD = 16 V
11010
VGHCOLD= 32 V
01011
VGHCOLD = 17 V
11011
VGHCOLD = 33 V
01100
VGHCOLD = 18 V
11100
VGHCOLD = 34 V
01101
VGHCOLD = 19 V
11101
VGHCOLD = 35 V
01110
VGHCOLD = 20 V
11110
VGHCOLD= 36 V
01111
VGHCOLD = 21 V
11111
VGHCOLD = 37 V
Reserved
Bits
7-5
These bits are reserved for future use. During write operations data intended for these bits is ignored, and
during read operations 0 is returned.
34
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VGHCONFIG (05h)
The VGHMISC register can be written to and read from.
Table 8. VGHCONFIG Register Bit Allocation
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
FREQ4
Bit 3
Bit 2
SS4
Bit 1
Bit 0
LX4TS
LX4TS
Bit
1-0
These bits configure the falling speed of VGH boost switch.
00
Tf = 2.2 V/ns
01
Tf = 3.5 V/ns
10
Tf = 4.8 V/ns
11
Tf = 6 V/ns
SS4
Bit
3-2
These bits configure the soft start duration for VGH boost regulator
00
tSS4 = 4 ms
01
tSS4 = 8 ms
10
tSS4 = 12 ms
11
tSS4 = 16 ms
FREQ4
Bit
4
This bit configures the switching frequency of VGH boost regulator
0
FVGH_LX = 400 kHz
1
FVGH_LX = 800 kHz
Reserved
Bits
7-5
These bits are reserved for future use. During write operations data intended for these bits is ignored, and
during read operations 0 is returned.
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VGL (06h)
The VGL register can be written to and read from.
Table 9. VGL Register Bit Allocation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Reserved
VGL
Reserved
36
Bit 2
Bit 1
Bit 0
VGL
Bits
5-0
These bits select VGL output voltage
000000
N.A.
000001
N.A.
000010
N.A.
000011
N.A.
000100
N.A.
000101
N.A.
000110
N.A.
000111
N.A.
001000
N.A.
001001
N.A.
001010
N.A.
001011
N.A.
001100
N.A.
001101
N.A.
001110
N.A.
001111
N.A.
010000
N.A.
010001
N.A.
010010
N.A.
010011
N.A.
010100
N.A.
010101
VGL = –3.8 V
Bits
7-6
These bits are reserved for future use. During write operations data intended for these bits is ignored, and
during read operations 0 is returned.
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
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= –3.9 V
= –4.0 V
= –4.1 V
= –4.2 V
= –4.3 V
= –4.4 V
= –4.5 V
= –4.6 V
= –4.7 V
= –4.8 V
= –4.9 V
= –5.0 V
= –5.1 V
= –5.2 V
= –5.3 V
= –5.4 V
= –5.5 V
= –5.6 V
= –5.7 V
= –5.8 V
= –5.9 V
= –6.0 V
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
= –6.1 V
= –6.2 V
= –6.3 V
= –6.4 V
= –6.5 V
= –6.6 V
= –6.7 V
= –6.8 V
= –6.9 V
= –7.0 V
= –7.1 V
= –7.2 V
= –7.3 V
= –7.4 V
= –7.5 V
= –7.6 V
= –7.7 V
= –7.8 V
= –7.9 V
= –8.0 V
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V25 (07h)
The V25 register can be written to and read from.
Table 10. V25 Register Bit Allocation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
V25
Reserved
Bit 1
Bit 0
V25
Bits
3-0
These bits select V25 buck converter’s output voltage
0000
V25 = 1.5 V
1000
0001
V25 = 1.6 V
1001
0010
V25 = 1.7 V
1010
0011
V25 = 1.8 V
1011
0100
V25 = 1.9 V
1100
0101
V25 = 2.0 V
1101
0110
V25 = 2.1 V
1110
0111
V25 = 2.2 V
1111
Bits
7-4
These bits are reserved for future use. During write operations data intended for these bits is ignored, and
during read operations 0 is returned.
V25 = 2.3 V
V25 = 2.4 V
V25 = 2.5 V
V25 = 2.6 V
V25 = 2.7 V
V25 = 2.8 V
V25 = 2.9 V
V25 = 3.0 V
VDIV (08h)
The VDIV register can be written to and read from.
Table 11. VDIV Register Bit Allocation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Reserved
Bit 2
Bit 1
Bit 0
VDIV
VDIV
Bits
3-0
These bits select the threshold voltage of the RESET signal
000
VDIV = 1.2 V
001
VDIV = 1.4 V
010
VDIV = 1.6 V
011
VDIV = 1.8 V
100
VDIV = 2.0 V
101
VDIV = 2.2 V
110
VDIV = 2.4 V
111
VDIV = 2.6 V
Reserved
Bits
7-4
These bits are reserved for future use. During write operations data intended for these bits is ignored, and
during read operations 0 is returned.
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RESET (09h)
The RESET register can be written to and read from.
Table 12. RESET Register Bit Allocation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
RESET
Reserved
Bit 1
Bit 0
RESET
Bits
3-0
These bits select the RESET generate delay time period
0000
TRESET = 0 ms
1000
TRESET
0001
TRESET = 2 ms
1001
TRESET
0010
TRESET = 4 ms
1010
TRESET
0011
TRESET = 6 ms
1011
TRESET
0100
TRESET = 8 ms
1100
TRESET
0101
TRESET = 10 ms
1101
TRESET
0110
TRESET = 12 ms
1110
TRESET
0111
TRESET = 14 ms
1111
TRESET
Bits
7-4
These bits are reserved for future use. During write operations data intended for these bits is ignored, and
during read operations 0 is returned.
= 16 ms
= 18 ms
= 20 ms
= 22 ms
= 24 ms
= 26 ms
= 28 ms
= 30 ms
DLY (0Ah)
The DLY register can be written to and read from.
Table 13. DLY Register Bit Allocation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Reserved
Bit 2
Bit 1
Bit 0
DLY
DLY
Bits
1-0
These bits configure the gate voltage shaping delay time period
00
VDLY = 0 ms
01
VDLY = 20 ms
10
VDLY = 40 ms
11
VDLY = 60 ms
Reserved
Bits
7-2
These bits are reserved for future use. During write operations data intended for these bits is ignored, and
during read operations 0 is returned.
38
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VCOMHOT (0Bh)
The VCOMHOT1 register can be written to and read from.
Table 14. VCOMHOT Register Bit Allocation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCOMHOT
VCOMHOT
Bits
These bits select VCOM output voltage at hot temperatures (VCOMT = 0) or all temperature range (VCOMT =
1).
VCOMR = 0
VCOMR = 1
00000000
VCOMHOT = N.A
VCOMHOT = N.A
00000001
VCOMHOT = N.A
VCOMHOT = N.A
00000010
VCOMHOT = N.A
VCOMHOT = N.A
…..
VCOMHOT = N.A
VCOMHOT = N.A
00100111
VCOMHOT = N.A
VCOMHOT = N.A
00101000
VCOMHOT = 0.80 V VCOMHOT = 0.20 V
00101001
VCOMHOT = 0.82 V VCOMHOT = 0.18 V
00101010
VCOMHOT = 0.84 V VCOMHOT = 0.16 V
00101011
VCOMHOT = 0.86 V VCOMHOT = 0.14 V
10111100
VCOMHOT = 0.86 V VCOMHOT = 0.12 V
…..
…..
…..
11111101
VCOMHOT = 5.06 V VCOMHOT = –4.06 V
11111110
VCOMHOT = 5.08 V VCOMHOT = –4.08 V
11111111
VCOMHOT = 5.10 V VCOMHOT = –4.10 V
VCOMCOLD (0Ch)
The VCOMCOLD register can be written to and read from.
Table 15. VCOMCOLD Register Bit Allocation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCOMCOLD
VCOMCOLD
Bits
These bits select VCOM output voltage at cold temperatures (VCOMT=0)
VCOMR = 0
VCOMR = 1
00000000
VCOMCOLD = N.A
VCOMCOLD = N.A
00000001
VCOMCOLD = N.A
VCOMCOLD = N.A
00000010
VCOMCOLD = N.A
VCOMCOLD = N.A
…..
VCOMCOLD = N.A
VCOMCOLD = N.A
00100111
VCOMCOLD = N.A
VCOMCOLD = N.A
00101000
VCOMCOLD = 0.80 V VCOMCOLD = 0.20 V
00101001
VCOMCOLD = 0.82 V VCOMCOLD = 0.18 V
00101010
VCOMCOLD = 0.84 V VCOMCOLD = 0.16 V
00101011
VCOMCOLD = 0.86 V VCOMCOLD = 0.14 V
10111100
VCOMCOLD = 0.86 V VCOMCOLD = 0.12 V
…..
…..
…..
11111101
VCOMCOLD = 5.06 V VCOMCOLD = –4.06 V
11111110
VCOMCOLD = 5.08 V VCOMCOLD = –4.08 V
11111111
VCOMCOLD = 5.10 V VCOMCOLD = –4.10 V
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Control (FFh)
Table 16. Control Register Bit Allocation
Bit 7
Bit 6
Bit 5
WED
RED
Bit 4
Bit 3
Reserved
Bit
0
Bit 2
Bit 1
Bit 0
RED
The state of this bit determines whether read operations return the contents of the DAC registers or the
contents of the E2PROM
0
Read operations return the contents of the DAC registers
1
Read operations return the contents of the E2PROM
Reserved
Bits
6-1
These bits are reserved for future use. During write operations data intended for these bits is ignored, and
during read operations 0 is returned.
WED
Bit
7
Setting this bit forces the contents of all DAC registers to be copied into E2PROM, thereby making them the
default values during power-up.
When the contents of all the DAC registers have been written to the E2PROM, the TPS65640 automatically
resets this bit.
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Example – Writing to a Single RAM Register
1. Bus master sends START condition.
2. Bus master sends 7-bit slave address plus low R/W bit (E8h).
3. TPS65640 acknowledges.
4. Bus master sends address of RAM register (00h).
5. TPS65640 acknowledges.
6. Bus master sends data to be written.
7. TPS65640 acknowledges.
8. Bus master sends STOP condition.
E8h
S
DATA
00h
7-Bit Slave Address
0 A
RAM Register Address
A
A P
RAM Register Data
Figure 41. Writing to a Single RAM Register
Example – Writing to Multiple RAM Registers
1. Bus master sends START condition.
2. Bus master sends 7-bit slave address plus low R/W bit (E8h).
3. TPS65640 acknowledges.
4. Bus master sends address of first RAM register to be written to (00h).
5. TPS65640 acknowledges.
6. Bus master sends data to be written to first RAM register.
7. TPS65640 acknowledges.
8. Bus master sends data to be written to RAM register at next higher address (auto-increment).
9. TPS65640 acknowledges.
10. Steps (8) and (9) repeated until data for final RAM register has been sent.
11. TPS65640 acknowledges.
12. Bus master sends STOP condition.
E8h
S
7-Bit Slave Address
DATA
00h
0 A
RAM Register Address (n)
A
RAM Register Data (n)
DATA
A
RAM Register Data (n+1)
A
DATA
RAM Register Data (Last)
A P
Figure 42. Writing to Multiple RAM Registers
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Example – Saving Contents of all RAM Registers to E2PROM
1. Bus master sends START condition.
2. Bus master sends 7-bit slave address plus low R/W bit (E8h).
3. TPS65640 acknowledges.
4. Bus master sends address of Control Register (FFh).
5. TPS65640 acknowledges.
6. Bus master sends data to be written to the Control Register (80h).
7. TPS65640 acknowledges.
8. Bus master sends STOP condition.
E8h
S
7-Bit Slave Address
80h
FFh
0 A
Control Register Address
A
Control Register Data
A P
Figure 43. Saving Contents of all RAM Registers to E2PROM
The TPS65640 needs 50ms time period after TPS65640 receiving STOP condition for saving all RAM registers
data to E2PROM. If bus master send 7-bit slave address to call TPS65640 again within 50ms period, the
TPS65640 will pull down the SCL line to LOW until the all RAM registers data saving to E2PROM is completed.
42
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Example – Reading from a Single RAM Register
1. Bus master sends START condition.
2. Bus master sends 7-bit slave address plus low R/W bit (E8h).
3. TPS65640 acknowledges.
4. Bus master sends address of Control Register (FFh).
5. TPS65640 acknowledges.
6. Bus master sends data for Control Register (00h).
7. TPS65640 acknowledges.
8. Bus master sends STOP condition.
9. Bus master sends START condition.
10. Bus master sends 7-bit slave address plus low R/W bit (E8h).
11. TPS65640 acknowledges.
12. Bus master sends address of RAM register (00h).
13. TPS65640 acknowledges.
14. Bus master sends REPEATED START condition.
15. Bus master sends 7-bit slave address plus high R/W bit (E9h).
16. TPS65640 acknowledges.
17. TPS65640 sends RAM register data.
18. Bus master does not acknowledge.
19. Bus master sends STOP condition.
E8h
S
7-Bit Slave Address
S
7-Bit Slave Address
00h
FFh
0 A
Control Register Address
0 A
RAM Register Address
E8h
A
Control Register Data
A P
DATA
E9h
00h
A Sr
7-Bit Slave Address
1 A
RAM Register Data
A P
Figure 44. Reading from a Single RAM Register
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Example – Reading from a Single E2PROM Register
1. Bus master sends START condition.
2. Bus master sends 7-bit slave address plus low R/W bit (E8h).
3. TPS65640 acknowledges.
4. Bus master sends address of Control Register (FFh).
5. TPS65640 acknowledges.
6. Bus master sends data for Control Register (01h).
7. TPS65640 acknowledges.
8. Bus master sends STOP condition.
9. Bus master sends START condition.
10. Bus master sends 7-bit slave address plus low R/W bit (E8h).
11. TPS65640 acknowledges.
12. Bus master sends address of E2PROM register (00h).
13. TPS65640 acknowledges.
14. Bus master sends REPEATED START condition.
15. Bus master sends 7-bit slave address plus high R/W bit (E9h).
16. TPS65640 acknowledges.
17. TPS65640 sends E2PROM register data.
18. Bus master does not acknowledge.
19. Bus master sends STOP condition.
E8h
S
7-Bit Slave Address
S
7-Bit Slave Address
01h
FFh
0 A
Control Register Address
0 A
E2PROM Register Address
E8h
A
Control Register Data
A P
DATA
E9h
00h
A Sr
7-Bit Slave Address
1 A
E2PROM Register Data
A P
Figure 45. Reading from a Single E2PROM Register
44
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Example – Reading from Multiple RAM Registers
1. Bus master sends START condition.
2. Bus master sends 7-bit slave address plus low R/W bit (E8h).
3. TPS65640 acknowledges.
4. Bus master sends address of Control Register (FFh).
5. TPS65640 acknowledges.
6. Bus master sends data for Control Register (00h).
7. TPS65640 acknowledges.
8. Bus master sends STOP condition.
9. Bus master sends START condition.
10. Bus master sends 7-bit slave address plus low R/W bit (E8h).
11. TPS65640 acknowledges.
12. Bus master sends address of first register to be read (00h).
13. TPS65640 acknowledges.
14. Bus master sends REPEATED START condition.
15. Bus master sends 7-bit slave address plus high R/W bit (E9h).
16. TPS65640 acknowledges.
17. TPS65640 sends contents of first RAM register to be read.
18. Bus master acknowledges.
19. Bus master sends contents of second RAM register to be read.
20. Bus master acknowledges.
21. TPS65640 sends contents of third (last) RAM register to be read.
22. Bus master does not acknowledge.
23. Bus master sends STOP condition.
E8h
S
7-Bit Slave Address
S
7-Bit Slave Address
FFh
0 A
Control Register Address
0 A
RAM Register Address (n)
E8h
00h
A
Control Register Data
A P
DATA
E9h
00h
A Sr
7-Bit Slave Address
1 A
DATA
RAM Register Data (n+1)
A
RAM Register Data (n)
DATA
A
RAM Register Data (Last)
A P
Figure 46. Reading from Multiple RAM Registers
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Example – Reading from Multiple E2PROM Registers
1. Bus master sends START condition.
2. Bus master sends 7-bit slave address plus low R/W bit (E8h).
3. TPS65640 acknowledges.
4. Bus master sends address of Control Register (FFh).
5. TPS65640 acknowledges.
6. Bus master sends data for Control Register (01h).
7. TPS65640 acknowledges.
8. Bus master sends STOP condition.
9. Bus master sends START condition.
10. Bus master sends 7-bit slave address plus low R/W bit (E8h).
11. TPS65640 acknowledges.
12. Bus master sends address of first E2PROM register to be read (00h).
13. TPS65640 acknowledges.
14. Bus master sends REPEATED START condition.
15. Bus master sends 7-bit slave address plus high R/W bit (E9h).
16. TPS65640 acknowledges.
17. TPS65640 sends contents of first E2PROM register to be read.
18. Bus master acknowledges.
19. Bus master sends contents of second E2PROM register to be read.
20. Bus master acknowledges.
21. TPS65640 sends contents of third (last) E2PROM register to be read.
22. Bus master does not acknowledge.
23. Bus master sends STOP condition.
E8h
S
7-Bit Slave Address
S
7-Bit Slave Address
FFh
0 A
E8h
Control Register Address
01h
A
Control Register Data
A P
DATA
E9h
00h
0 A E2PROM Register Address (n) A Sr
7-Bit Slave Address
1 A
DATA
E2PROM Register Data (n)
A
DATA
E2PROM Register Data (n+1) A E2PROM Register Data (Last) A
P
Figure 47. Reading from Multiple E2PROM Registers
46
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Configuration Parameter VCOM
The VCOM register can be written to and read from.
Table 17. VCOM Register Bit Allocation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
VCOM
Bit 2
Bit 1
Bit 0
P
P
Bit
0
During write operations, this bit determines the target for the data:
0 = Data written to E2PROM and RAM register
1 = Data written to RAM register only
During read operations this bit indicates whether the contents of the E2PROM and RAM register are the same
0 = E2PROM and RAM register contents are the same
1 = E2PROM and RAM register contents are different
VCOM
Bits
7-1
During write operations, these bits contain the data to be written.
During read operations, these bits return the contents of the RAM.
The factory default setting is 1000000.
Where VCOM is a 7-bit integer between 0 and 127 decimal.
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Example – Writing a VCOM Value of 77h to VCOM Register Only
1. The bus master sends a START condition.
2. The bus Master sends (9E hexadecimal (7-bit slave address plus low R/W bit).
3. TPS65640 slave acknowledges.
4. The bus master sends EF hexadecimal (data to be written plus LSB = '1').
5. The TPS65640 slave acknowledges.
6. The bus master sends a STOP condition.
9Eh
S
EFh
7-Bit Slave Address
0 A
Data to be Written
1 A P
Figure 48. Writing a VCOM Value of 77h to RAM Only
Example – Writing a VCOM Value of 77h to E2PROM and RAM
1. The bus master sends a START condition.
2. The bus Master sends 9E hexadecimal (7-bit slave address plus low R/W bit).
3. TPS65640 slave acknowledges.
4. The bus master sends EE hexadecimal (data to be written plus LSB = '0').
5. The TPS65640 slave acknowledges.
6. The bus master sends a STOP condition.
9Eh
S
EEh
7-Bit Slave Address
0 A
Data to be Written
0 A P
Figure 49. Writing a VCOM Value of 77h to E2PROM and RAM
48
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Example – Reading a VCOM Value of 77h from RAM when E2PROM Contents are Identical
1. The bus master sends a START condition.
2. The bus Master sends 9F hexadecimal (7-bit slave address plus low R/W bit).
3. TPS65640 slave acknowledges.
4. The bus master sends EE hexadecimal from E2PROM (data to be read plus LSB = '0').
5. The bus master does not acknowledge.
6. The bus master sends a STOP condition.
9Fh
S
EEh
7-Bit Slave Address
1 A
Data to be Read
0 A P
Figure 50. Reading 77h from RAM when E2PROM Contents are Identical
Example – Reading a VCOM Value of 77h from RAM when E2PROM Contents are Different
1. The bus master sends a START condition.
2. The bus Master sends 9F hexadecimal (7-bit slave address plus low R/W bit).
3. TPS65640 slave acknowledges.
4. The bus master sends EF hexadecimal from RAM (data to be read plus LSB = '1').
5. The bus master does not acknowledge.
6. The bus master sends a STOP condition.
9Fh
S
EFh
7-Bit Slave Address
1 A
Data to be Read
1 A P
Figure 51. Reading 77h from E2PROM when RAM Contents are Different
I2C INTERFACE
Configuration parameters and the VCOM voltage setting are programmed via an industry standard I2C serial
interface. The TPS65640 always works as a slave device and supports standard (100kbps) and fast (400kbps)
modes of operation.
During write operations, all further attempts to access its slave addresses are ignored until the current write
operation has completed.
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POWER SEQUENCY
Buck converter (V25Buck) or the linear regulator (V25LDO) start as soon as VIN > VUVLO.
The reset generator holds RST low until tRESET seconds after V25 has reached power good status.
Boost converter 1 starts after V25 reached power good status.
Boost converter 2 starts as soon as AVDD has reached power good status.
Figure 52 show the typical power-up/down characteristic of the TPS65640.
VIN
VIN > VUVLO
V25 < VUVLO
tSS2
V25 > VDIV
V25
V25 < VDIV
tRESET
RST
tSS1
AVDD
tSS4
VGH
VGL
tDLY
VGHM
Figure 52. Power-Up and Power-Down Sequencing
50
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UNDERVOLTAGE LOCKOUT
An undervoltage lockout function disables the IC when the supply voltage is too low for proper operation. A lowpass filter at the input of the UVLO comparator ensures that short transients on VIN do not cause premature
shutdown of the IC.
VIN
Low Pass
Filter
UVLO
VUVLO
Figure 53. Undervoltage Lockout Comparator with Low-Pass Filter
THERMAL SHUTDOWN
A thermal shutdown function automatically disables all functions if the device’s junction temperature exceeds the
safe maximum. The device automatically starts operating again once it has cooled down and operation may
safely continue. A restart after a thermal shutdown event follows the same sequence as following a normal
power-up condition (see Figure 52).
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APPLICATION INFORMATION
10 µH
VIN 2.5 V~5.5 V
AV DD
10 µF
10 µF
AVDD
LX
VIN
200 kΩ 1 nF
BOOST
CONVERTER 1
10 µF
COMP
AV DD
10 µH
BOOST
CONVERTER 2
10 kΩ @ 25°C
VT
VGH
VGH_LX
R1
4.7 µF
R2
FLK
VGH
GATE
VOLTAGE SHAPING
VGHM
VGHM
RE
RE
4.7 µH
LX
V25
V25_LX
BUCK/LDO
CONVERTER
10µF
V25
V25
220 nF
10 kΩ
RESET
GENERATOR
RESET
To T CON
100 kΩ
1µF
DRVN
VGL
VGL
NEGATIVE
LINEAR REGULATOR
1µF
SDA
I2C INTERFACE
SCL
PROGRAMMABLE
VCOM
BUFFER
VCOM_OUT
VINA+
VINAVOUTA
VINB+
OPERATIONAL
AMPLIFIER
PGND
VINBVOUTB
AGND
Figure 54. Typical Application Circuit
52
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LAYOUT RECOMMENDATION
As for all switching power supplies, especially those providing high current and using high switching frequencies,
layout is an important design step. If layout is not carefully done, the regulator could show instability as well as
EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor in the typical
application circuit, should also be placed close to the VIN pin, but also to the GND in order to reduce the input
ripple seen by the IC. The LX pin carries high current with fast rising and falling edges. Therefore, the connection
between the pin to the inductor and schottky diode should be kept as short and wide as possible. It is also
beneficial to have the ground of the output capacitor for both Boost converter 1, Boost converter 2 and Buck
converter close to the PGND pin since there is a large ground return current flowing between them. When laying
out signal grounds, it is recommended to use short traces separated from power ground traces, and connect
them together at a single point, for example on the thermal pad. The thermal pad needs to be soldered on to the
PCB and connected to the GND pin of the IC. An additional thermal via can significantly improve power
dissipation of the IC.
VIN
PGND
PGND
VIN
V25
PGND
AVDD
0 18 17 16 15
24 23 22 21 20 19
PGND
25
14
26
13
PGND
27
12
28
1
11
2
3
4
5
5
6
7
8
9 10
VGH
PGND
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PACKAGE OPTION ADDENDUM
www.ti.com
6-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS65640RHRR
PREVIEW
Package Type Package Pins Package
Drawing
Qty
WQFN
RHR
28
3000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
Level-2-260C-1 YEAR
(4)
-40 to 85
PZXI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65640RHRR
ACTIVE
WQFN
RHR
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PZXI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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