TPS6590377ZWST

Product Folder Order Now Technical Documents Tools & Software Support & Community Reference Design TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 TPS659037 Power management unit (PMU) for processor 1 Device Overview 1.1 Features 1 • Seven Step-Down Switched-Mode Power Supply (SMPS) Regulators: – One 0.7 to 1.65 V at 6 A (10-mV Steps) – Dual-Phase Configuration With Digital Voltage Scaling (DVS) Control – One 0.7 to 1.65 V at 4 A (10-mV Steps) – Dual-Phase Configuration With DVS Control – One 0.7 to 3.3 V at 3 A (10 or 20-mV Steps) – Single-Phase Configuration – This Regulator can be Combined With the 6 A Resulting in a 9-A Triple-Phase Regulator (DVS Controlled) – Two 0.7 to 3.3 V at 2 A (10 or 20-mV Steps) – Single-Phase Configuration – One Regulator With DVS Control That can also be Configured as a 3-A Regulator – Two 0.7 to 3.3 V at 1 A (10 or 20-mV Steps) – Single-Phase Configuration – One Regulator With DVS Control – Output Current Measurement in All Except 1-A SMPS Regulators – Differential Remote Sensing (Output and Ground) in Dual-Phase and Triple-Phase Regulators – Hardware and Software-Controlled Eco-mode™ up to 5 mA with 15-µA Quiescent Current – Short-Circuit Protection – Powergood Indication (Voltage and Overcurrent Indication) – Internal Soft-Start for In-Rush Current Limitation – Ability to synchronize SMPS to External Clock or Internal Fallback Clock With Phase Synchronization • Seven General-Purpose Low Dropout Regulators (LDOs) with 50-mV Steps: – Two 0.9 to 3.3-V LDOs at 300 mA With Preregulated Supply – Two 0.9 to 3.3-V LDOs at 200 mA With Preregulated Supply 1.2 • • • • • • • • • • – One 0.9 to 3.3-V LDOs at 50 mA With Preregulated Supply – One 100-mA USB LDO – One 0.9 to 3.3-V, Low-Noise LDO up to 100 mA (Low-Noise Performance up to 50 mA) – Two Additional LDOs for PMU Internal Use – Short-Circuit Protection Clock Management 16-MHz Crystal Oscillator and 32-kHz RC Oscillator – One Buffered 32-kHz Output Real-Time Clock (RTC) With Alarm Wake-Up Mechanism 12-bit Sigma-Delta General-Purpose Analog-toDigital-Converter (GPADC) With Three External Input Channels and Six Internal Channels for Self Monitoring Thermal Monitoring – High Temperature Warning – Thermal Shutdown Control – Configurable Power-Up and Power-Down Sequences (One-Time Programmable [OTP]) – Configurable Sequences Between the SLEEP and ACTIVE States (OTP Programmable) – One Dedicated Digital Output Signal (REGEN) that can be Included in the Start-Up Sequence – Three Digital Output Signals MUXed With GPIO that can be Included in the Start-Up Sequence – Selectable Control Interface – One Serial Peripheral Interface (SPI) for Resource Configurations and DVS Control – Two I2C Interfaces. One Dedicated for DVS Control, and a General Purpose I2C Interface for Resource Configuration and DVS Control Undervoltage Lockout System Voltage Range from 3.135 to 5.25 V Package Options – 12-mm × 12-mm 169-pin nFBGA with 0,8-mm Pin Pitch Applications Factory Automation Programmable Logic Controllers • • System-on-Module Human-Machine Interface 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 1.3 www.ti.com Description The TPS659037 device is an integrated power-management IC (PMIC). The device provides seven configurable step-down converters with up to 6 A of output current for memory, processor core, inputoutput (I/O), or preregulation of LDOs. One of these configurable step-down converters can be combined with another 3-A regulator to allow up to 9 A of output current. All of the step-down converters can synchronize to an external clock source between 1.7 MHz and 2.7 MHz, or an internal fallback clock at 2.2 MHz. The TPS659037 device contains seven LDO regulators for external use. These LDO regulators can be supplied from either a system supply or a preregulated supply. The power-up and power-down controller is configurable and supports any power-up and power-down sequences (OTP based). The TPS659037 device includes a 32-kHz RC oscillator to sequence all resources during power up and power down. In cases where a fast start up is needed, a 16-MHz crystal oscillator is also included to quickly generate a stable 32-kHz for the system. All LDOs and SMPS converters can be controlled by the SPI or I2C interface, or by power request signals. In addition, voltage scaling registers allow transitioning the SMPS to different voltages by SPI, I2C, or roof and floor control. One dedicated pin in each package can be configured as part of the power-up sequence to control external resources. General-purpose input-output (GPIO) functionality is available and two GPIOs can be configured as part of the power-up sequence to control external resources. Power request signals enable power mode control for power optimization. The device includes a general-purpose sigma-delta analog-todigital converter (GPADC) with three external input channels. The TPS659037 device is available in a 13-pin × 13-pin nFBGA package with a 0,8-mm pitch. Device Information (1) PART NUMBER TPS659037 (1) 2 PACKAGE ZWS (169) BODY SIZE (NOM) 12.00 mm × 12.00 mm For all available packages, see the orderable addendum at the end of the datasheet. Device Overview Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com 1.4 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Simplified Block Diagram Reference and Bias PLL for external Sync Clock 16MHz Crystal RTC 12-Bit GPADC with 3 External Channels TPS659037 Programmable Power Sequencer Controller ECO PWM DVS Switch On or Off LDO9 50 mA LDOLN 50 mA LDOUSB 100 mA SMPS45 0.7 to 1.6 V, 10-mV step, 4 A Registers Dual Phase or Triple Phase SMPS7 0.7 to 1.6 V, 10-mV step 1 to 3.3 V, 20-mV step, 2 A Watchdog Thermal Monitoring and Shutdown Power Good Monitor 2 SMPS6 0.7 to 1.6 V, 10-mV step 1 to 3.3 V, 20-mV step, 2 or 3 A VSYS Monitor SMPS8 0.7 to 1.6 V, 10-mV step 1 to 3.3-V, 20-mV step, 1 A 8x GPIO SMPS9 0.7 to 1.6 V, 10-mV step 1 to 3.3 V, 20-mV step, 1 A LDOVRTC 20 mA 2x I C or 1x SPI SMPS3 0.7 to 1.6 V, 10-mV step 1 to 3.3 V, 20-mV step, 3 A OTP Registers LDO2 300 mA LDO4 200 mA Dual Phase or Triple Phase OTP Controller LDO1 300 mA LDO3 200 mA SMPS12 0.7 to 1.6 V, 10-mV step, 6 A Copyright © 2016, Texas Instruments Incorporated Device Overview Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 3 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Table of Contents 1 Device Overview ......................................... 1 4.17 Parameters .......................................... 24 Electrical Characteristics: Digital Output Signal Parameters .......................................... 24 Description ............................................ 2 4.18 Electrical Characteristics: I/O Pullup and Pulldown . 26 Simplified Block Diagram ............................. 3 4.19 I2C Interface Timing Requirements ................. 26 Revision History ......................................... 4 Pin Configuration and Functions ..................... 6 Specifications ........................................... 13 4.20 SPI Timing Requirements ........................... 28 4.21 Typical Characteristics .............................. 30 1.1 Features .............................................. 1 1.2 Applications ........................................... 1 1.3 1.4 2 3 4 4.1 Absolute Maximum Ratings ......................... 13 4.2 ESD Ratings ........................................ Recommended Operating Conditions ............... Thermal Information ................................. Electrical Characteristics: Latch Up Rating ......... Electrical Characteristics: LDO Regulator .......... 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators .............................. Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9) .. Electrical Characteristics: Reference Generator (Bandgap) ........................................... Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers .......... 14 14 14 7 8 18 20 20 Electrical Characteristics: DC-DC Clock Sync ...... 21 4.12 4.13 Electrical Characteristics: 12-Bit Sigma-Delta ADC. 21 Electrical Characteristics: Thermal Monitoring and Shutdown ............................................ 23 Electrical Characteristics: System Control Threshold ............................................ 23 4.15 4.16 6 15 17 Electrical Characteristics: Current Consumption .... 23 Electrical Characteristics: Digital Input Signal Detailed Description ................................... 32 ............................................ 5.2 Functional Block Diagram ........................... 5.3 Feature Description ................................. 5.4 Device Functional Modes ........................... Application and Implementation .................... 6.1 Application Information .............................. 6.2 Typical Application .................................. Power Supply Recommendations .................. Layout .................................................... 8.1 Layout Guidelines ................................... 8.2 Layout Example ..................................... Device and Documentation Support ............... 9.1 Device Support ...................................... 9.2 Documentation Support ............................. 9.3 Receiving Notification of Documentation Updates .. 9.4 Community Resources .............................. 9.5 Trademarks.......................................... 9.6 Electrostatic Discharge Caution ..................... 9.7 Glossary ............................................. 5.1 13 4.11 4.14 5 9 Overview 32 33 34 61 77 77 77 88 88 88 91 94 94 94 94 94 94 94 94 10 Mechanical, Packaging, and Orderable Information .............................................. 95 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (January 2018) to Revision G • • • • • • • • • • • • • • • • • • 4 Page Updated the LDOVRTC_OUT pulldown resistor recommendation to only include applicable silicon revisions. ........ 7 Changed ESD Ratings for charge device model on 6 pins ................................................................... 13 Clarified that LDO1 and LDO2 input pins are not included in this minimum recommended operating voltage. See Electrical Characteristics: LDO Regulators for more information. ............................................................ 14 Changed minimum recommended operating condition of OSC16MIN from 0V to -0.7V ................................. 14 Added LDO and SMPS output capacitance footnote .......................................................................... 15 Changed VSYS_LO hysteresis from 95mV to 75mV .......................................................................... 23 Updated Caution statement to only include applicable silicon revisions. ................................................... 32 Changed discharge resistance to match electrical characteristics table .................................................... 35 Added information about shutdown timing during short circuit detection ................................................... 38 Updated POWERGOOD description to clarify multi-phase operation. ...................................................... 38 Updated LDOVRTC note to only include applicable silicon revisions. ...................................................... 43 Added details on identifying device version. .................................................................................... 61 Added typical debounce time from POWERHOLD to the enable of the first rail in the power sequence. .............. 63 Added VSYS_LO note for applicable silicon revisions. ........................................................................ 74 Updated POR requirements to only include applicable silicon revisions. ................................................... 75 SMPS and LDO output capacitance specification further explained ......................................................... 82 Added design considerations for VCC1 capacitance to support loss of power ............................................. 82 Corrected 9-Vpp with 7V absolute maximum specification in the Layout Guidelines section ............................. 88 Revision History Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com • • SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Updated requirements relating to measurement of high-side and low-side FETs in the Layout Guidelines section ... 90 Updated images and description on differential measurements across high-side and low-side FETs .................. 90 Changes from Revision E (July 2017) to Revision F • • • • • • • • • Page Deleted pullup and pulldown from BOOT0 pin description ................................................................... Deleted the voltage mode to the I/O digital supply voltage, VIO_IN parameter from the Recommended Operating Conditions table ......................................................................................................... Added 2-A mode for SMPS6 in the test conditions for high-side and low-side MOSFET forward current limit and low-side MOSFET negative current limit in the Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9) table ................................................................................... Added the number of active SMPS phases (K) to the equation for the temperature compensated result in the Current Monitoring and Short Circuit Detection section ........................................................................ Added additional description of SMPS short detection and recovery behavior ............................................ Added equation to convert GPADC code to internal die temperature........................................................ Added description of VIO power-up timing, and updated start up timing diagram ......................................... Added additional description of VSYS_LO functionality........................................................................ Changed the Electrostatic Discharge Caution statement ...................................................................... Changes from Revision D (April 2016) to Revision E • • • • • • • • • • Deleted CLK32KGO from the Startup Timing Diagram ........................................................................ Added OTP note to the Application Schematic.................................................................................. Changed the VIO_GND connection to C6 in the Typical Application Schematic ........................................... Updated part numbers and settings for released devices in the Design Parameters table .............................. Added the Receiving Notification of Documentation Updates section ....................................................... 38 38 48 68 73 94 68 78 79 80 94 Changed the LDOVRTC_OUT pin description in the Pin Functions table ................................................... 7 Changed the typical value for the channel 11 SMPS output current measurement gain factor parameter in the 12-Bit Sigma-Delta ADC Characteristics table .................................................................................. 22 Changed the typical value for the channel 11 SMPS output current measurement current offset parameter in the 12-Bit Sigma-Delta ADC Characteristics table .................................................................................. 22 Added maximum current of LDOVRTC in BACKUP and OFF states ........................................................ 43 Added a note to the LDOVRTC section ......................................................................................... 43 Added additional description of POR in System Voltage Monitoring section ................................................ 76 Updated part numbers and settings for released devices in the Design Parameters table .............................. 80 Page Added statement to the Current Monitoring and Short Circuit Detection section that the SMPS_SHORT_REGISTER bit will keep a resource off until it is cleared .................................................. 38 Changes from Revision A (September 2015) to Revision B • 19 Page Changes from Revision B (November 2015) to Revision C • 14 Page Changes from Revision C (November 2015) to Revision D • • 11 Changed device status from Advanced Information to Production Data Page ..................................................... Revision History Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 2 5 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com 3 Pin Configuration and Functions 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H PBKG SMPS1_2_FDBK GPIO_1 SMPS1_IN SMPS1_SW SMPS2_SW SMPS2_IN SMPS3_IN GPIO_2 GPIO_0 SMPS1_IN SMPS1_SW SMPS2_SW SMPS2_IN SMPS1_2_FDBK J K L M N SMPS3_SW SMPS3_FDBK LDO34_IN GND_ANA PBKG SMPS3_IN SMPS3_SW LDO4_OUT LDO34_IN GND_DIG VPROG _GND VCC_SENSE2 PBKG RPWRON SMPS1_IN SMPS1_SW SMPS2_SW SMPS2_IN SMPS3_IN SMPS3_SW LDO3_OUT SMPS8_FDBK CLK32KGO GPIO_6 LDOUSB_IN1 PBKG GPIO_5 SMPS1_GND SMPS1_GND SMPS2_GND SMPS2_GND SMPS3_GND SMPS3_GND GPIO_4 SMPS8_GND SMPS8_SW SMPS8_SW LDOUSB_IN2 LDOUSB_OUT NC VIO_IN SMPS1_GND SMPS2_GND GPIO_7 GPIO_3 SMPS3_GND RESET_IN SMPS8_GND SMPS8_IN SMPS8_IN LDOVRTC_OUT SYNCDCDC LDOVANA_OUT VBUS PBKG REGEN1 PWRON I2C2_SDA_SDO SMPS9_FDBK PWRDOWN SMPS9_GND SMPS9_IN SMPS9_IN GND_ANA VBG VCC1 PBKG GND_ANA PBKG PBKG PBKG POWERGOOD BOOT1 SMPS9_GND SMPS9_SW SMPS9_SW LDO12_IN LDO2_OUT LDO1_OUT PBKG NRESWARM PBKG RESET_OUT PBKG PBKG SMPS6_FDBK SMPS6_GND SMPS6_IN SMPS6_IN LDO9_OUT LDOLN_OUT LDOLN_IN SMPS7_GND NSLEEP GND_ANA SMPS4_GND SMPS5_GND ENABLE1 NC SMPS6_GND SMPS6_SW SMPS6_SW REFGND1 GPADC_VREF LDO9_IN SMPS7_GND SMPS7_GND SMPS4_GND SMPS4_GND SMPS5_GND SMPS5_GND NC NC LDO_SUPPLY LDO_SUPPLY OSC16MIN VCC_SENSE GPADC_IN2 SMPS7_SW SMPS7_IN SMPS4_IN SMPS4_SW SMPS5_SW SMPS5_IN BOOT0 I2C2_SCL_SCE LDO_SUPPLY SMPS4_5_FDBK _GND OSC16MOUT GPADC_IN0 GPADC_IN1 SMPS7_SW SMPS7_IN SMPS4_IN SMPS4_SW SMPS5_SW SMPS5_IN SMPS4_5_FDBK I2C1_SDA_SDI PBKG VIO_GND PBKG SMPS7_FDBK OSC16MCAP SMPS7_SW SMPS7_IN SMPS4_IN SMPS4_SW SMPS5_SW SMPS5_IN INT I2C1_SCL_SCK PBKG PBKG Figure 3-1. 169-Pin ZWS New Fine Pitch Ball Grid Array (NFBGA) With 0,8-mm Pitch Top View 6 Pin Configuration and Functions Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Pin Functions PIN NO. I/O PU OR PD (1) NAME CONNECTION IF NOT USED OR NOT AVAILABLE DESCRIPTION A1 PBKG — — Ground Substrate ground A2 OSC16MOUT O — Floating 16-MHz crystal oscillator output or floating in case of digital clock A3 OSC16MIN I — Floating or ground in bypass mode A4 REFGND1 — — Ground System reference ground A5 LDO9_OUT O — Floating LDO9 output voltage A6 LDO12_IN I — System supply A7 GND_ANA — — Ground A8 LDOVRTC_OUT O — — A9 LDOUSB_IN2 I — System supply Power input voltage 2 for LDOUSB regulator A10 LDOUSB_IN1 I — System supply Power input voltage 1 for LDOUSB regulator A11 VCC_SENSE2 I — System supply System-supply sense line PPU Power input voltage for LDO1 and LDO2 regulators Analog power ground Internal LDOVRTC output voltage. For silicon revisions 1.3 or earlier, rapid power off and on requires a pulldown resistor on the LDOVRTC_OUT pin. See Section 5.4.11 for more details. Primary function: General-purpose input (2) or output I/O PPD 16-MHz crystal oscillator input or digital clock input A12 GPIO_2 Floating O — A13 PBKG — — Ground Substrate ground B1 SMPS7_FDBK I — Floating Output voltage-sense (feedback) input for step-down converter, SMPS7 B2 GPADC_IN0 I — Ground Sigma-delta GPADC input 0 B3 VCC_SENSE I — System supply B4 GPADC_VREF O — Floating Sigma-delta GPADC output reference voltage B5 LDOLN_OUT O — Floating Output voltage for the low-noise dropout regulator, LDOLN B6 LDO2_OUT O — Floating LDO2 output voltage B7 VBG O — — B8 SYNCDCDC I — Ground Sync pin to sync DC-DCs with external clock B9 LDOUSB_OUT O — Floating LDOUSB output voltage PBKG — — Ground Substrate ground B12 GPIO_0 I/O PPD B13 SMPS1_2_FDBK I — Ground Output voltage-sense (feedback) input for step-down converters, SMPS1 and SMPS2 C1 OSC16MCAP O — Floating Filtering capacitor for the 16-MHz crystal oscillator C2 GPADC_IN1 I — Ground Sigma-delta GPADC input 1 C3 GPADC_IN2 I — Ground Sigma-delta GPADC input 2 C4 LDO9_IN I — System supply Power input voltage for LDO9 regulator C5 LDOLN_IN I — System supply Power input voltage for the low-noise dropout regulator, LDOLN C6 LDO1_OUT O — Floating C7 VCC1 I — System supply C8 LDOVANA_OUT O — — Internal LDOVANA output voltage C9 NC — — — Not connected Secondary function: REGEN2 — External regulator enable output 2 System-supply sense line Bandgap reference voltage B10 B11 Ground or VSYS (VCC1) General-purpose input (2) or output PPU I/O C10 GPIO_5 PPD (2) LDO1 output voltage Analog input voltage supply Ground Primary function: General-purpose input (2) or output O — Floating Secondary function: CLK32KGO1V8 — 32-kHz digital-gated output clock available when VRTC is present C11 RPWRON I PU Floating External remote switch-on event C12 SMPS1_2_FDBK_GND I — Ground Ground-sense (feedback) input for step-down converters, SMPS1 and SMPS2 I/O PPU C13 GPIO_1 O (1) (2) Primary function: General-purpose input (2) or output Floating PPD Secondary function: VBUSDET - VBUS detection The PU/PD column shows the pullup and pulldown resistors on the digital input lines. The pullup and pulldown resistors are defined as follows: PU pullup PD pulldown PPU software-programmable pullup PPD software-programmable pulldown Default option Pin Configuration and Functions Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 7 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Pin Functions (continued) PIN I/O PU OR PD (1) CONNECTION IF NOT USED OR NOT AVAILABLE SMPS7_SW O — Floating Switch node of step-down converter, SMPS7. Connect the output to an inductor. SMPS7_GND — — Ground Power ground connection for step-down converter, SMPS7 PBKG — — Ground Substrate ground D8 VBUS I — Ground VBUS Detection Voltage D9 VIO_IN I — System supply D10 SMPS1_GND — — Ground SMPS1_IN I — System supply Power input for step-down converter, SMPS1 SMPS7_IN I — System supply Power input for step-down converter, SMPS7 SMPS7_GND — — Ground Power ground connection for step-down converter, SMPS7 Floating NSLEEP request signal NO. NAME DESCRIPTION D1 D2 D3 D4 D5 D6 D7 Digital supply input for GPIOs and I/O supply voltage Power ground connection for step-down converter, SMPS1 D11 D12 D13 E1 E2 E3 E4 PPU (2) E5 NSLEEP I PPD E6 NRESWARM I PPU (2) Floating Warm reset input E7 GND_ANA — — Ground Analog power ground E8 PBKG — — Ground Substrate ground SMPS1_GND — — Ground Power ground connection for step-down converter, SMPS1 SMPS1_SW O — Floating Switch node of step-down converter, SMPS1. Connect the output to an inductor. SMPS4_IN I — System supply F4 SMPS4_GND — — Ground Power ground connection for step-down converter, SMPS4 F5 GND_ANA — — Ground Analog power ground PBKG — — Ground Substrate ground REGEN1 O — Floating External regulator enable output 1 SMPS2_GND — — Ground Power ground connection for step-down converter, SMPS2 SMPS2_SW O — Floating Switch node of step-down converter, SMPS2. Connect the output to an inductor. SMPS4_SW O – Floating Switch node of step-down converter, SMPS4. Connect the output to an inductor. SMPS4_GND — — Ground Power ground connection for step-down converter, SMPS4 E9 E10 E11 E12 E13 F1 F2 Power input for step-down converter, SMPS4 F3 F6 F7 F8 F9 F10 F11 F12 F13 G1 G2 G3 G4 G5 G6 RESET_OUT O — Floating System reset and power on output (Low → Reset, High → Active or Sleep) G7 PBKG — — Ground Substrate ground G8 PWRON I PU Floating External power-on event (on-button switch-on event) I/O PPD I PPD (2) SMPS2_GND — — Ground SMPS2_IN I — System supply G9 G10 GPIO_7 Primary function: General-purpose input (2) or output Ground or VRTC Secondary function: POWERHOLD input Power ground connection for step-down converter, SMPS2 G11 G12 Power input for step-down converter, SMPS2 G13 8 Pin Configuration and Functions Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Pin Functions (continued) PIN NO. I/O PU OR PD (1) CONNECTION IF NOT USED OR NOT AVAILABLE SMPS5_SW O — Floating Switch node of step-down converter, SMPS5. Connect the output to an inductor. SMPS5_GND — — Ground Power ground connection for step-down converter, SMPS5 PBKG — — Ground Substrate ground I2C2_SDA_SDO I/O — Floating DVS I2C serial bidirectional data (external pullup) and SPI data read signal or I2C serial bidirectional data (external pullup) NAME DESCRIPTION H1 H2 H3 H4 H5 H6 H7 H8 H9 GPIO_3 I PPD Ground General-purpose input (2) or output H10 SMPS3_GND — — Ground Power ground connection for step-down converter, SMPS3 SMPS3_IN I — System supply Power input for step-down converter, SMPS3 SMPS5_IN I — System supply Power input for step-down converter, SMPS5 SMPS5_GND — — Ground Power ground connection for step-down converter, SMPS5 Floating Peripheral power request input 1 H11 H12 H13 J1 J2 J3 J4 PPU J5 ENABLE1 I J6 PBKG — — Ground Substrate ground J7 POWERGOOD O — Floating Indication signal for valid regulator output voltages J8 SMPS9_FDBK I — Ground Output voltage-sense (feedback) input for step-down converter, SMPS9 SMPS3_GND — — Ground Power ground connection for step-down converter, SMPS3 SMPS3_SW O — Floating Switch node of step-down converter, SMPS3. Connect the output to an inductor. K1 INT O — — K2 SMPS4_5_FDBK I — Ground Output voltage-sense (feedback) input for step-down converters, SMPS4 and SMPS5 K3 SMPS4_5_FDBK_GND I — Ground Ground-sense (feedback) input for step-down converters, SMPS4 and SMPS5 NC — — — K6 SMPS6_FDBK I — Ground K7 BOOT1 I — Ground or VRTC K8 PWRDOWN I PPD Floating Power-down signal K9 RESET_IN I PPD Floating Reset input PPD (2) J9 J10 J11 J12 J13 Maskable interrupt output request to the host processor K4 Not connected K5 PPU I/O Output voltage sense (feedback) input for step-down converter, SMPS6 Boot pin 1 for power-up sequence selection Primary function: General-purpose input (2) or output PPD (2) Floating O — Floating LDO3 output voltage LDO4_OUT O — Floating LDO4 output voltage K13 SMPS3_FDBK I — Floating Output voltage-sense (feedback) input for step-down converter, SMPS3 L1 I2C1_SCL_SCK I/O — Floating Control I2C serial clock (external pullup) and SPI clock signal L2 I2C1_SDA_SDI I/O — Floating Control I2C serial bidirectional data (external pullup) and SPI data signal L3 BOOT0 I — Ground or VRTC L4 NC — — — SMPS6_GND — — Ground Power ground connection for step-down converter, SMPS6 SMPS9_GND — — Ground Power ground connection for step-down converter, SMPS9 SMPS8_GND — — Ground Power ground connection for step-down converter, SMPS8 SMPS8_FDBK I — Ground Output voltage-sense (feedback) input for step-down converter, SMPS8 K10 GPIO_4 K11 LDO3_OUT K12 O Secondary function: SYSEN1 — External system enable Boot pin 0 for power-up sequence selection Not connected L5 L6 L7 L8 L9 L10 L11 Pin Configuration and Functions Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 9 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Pin Functions (continued) PIN I/O PU OR PD (1) CONNECTION IF NOT USED OR NOT AVAILABLE LDO34_IN I — System supply PBKG — — Ground Substrate ground M3 I2C2_SCL_SCE I/O — Floating DVS I2C serial clock (external pullup) and SPI enable signal or I2C serial clock (external pullup) M4 LDO_SUPPLY I — System supply M5 SMPS6_SW O — Floating M6 SMPS6_IN I — System supply M7 SMPS9_SW O — Floating M8 SMPS9_IN I — System supply Power input for step-down converter, SMPS9 M9 SMPS8_IN I — System supply Power input for step-down converter, SMPS8 M10 SMPS8_SW O — Floating Switch node of step-down converter, SMPS8 Connect the output to an inductor. M11 CLK32KGO O — Floating 32-kHz digital-gated output clock available when VIO_IN input supply is present M12 GND_DIG — — Ground Digital power ground M13 GND_ANA — — Ground Analog power ground N1 PBKG — — Ground Substrate ground N2 VIO_GND — — Ground Digital ground connection N3 LDO_SUPPLY I — System supply Power input voltage for internal LDO N4 LDO_SUPPLY I — System supply Power input voltage for internal LDO N5 SMPS6_SW O — Floating N6 SMPS6_IN I — System supply N7 SMPS9_SW O — Floating N8 SMPS9_IN I — System supply Power input for step-down converter, SMPS9 N9 SMPS8_IN I — System supply Power input for step-down converter, SMPS8 N10 SMPS8_SW O — Floating Switch node of step-down converter, SMPS8 Connect the output to an inductor. Ground Primary function: General-purpose input (2) or output Secondary function: SYSEN2 — External system enable NO. NAME DESCRIPTION L12 Power input voltage for LDO3 and LDO4 regulators L13 M1 M2 PPU I/O N11 N12 N13 10 GPIO_6 PPD (2) Power input voltage for internal LDO Switch node of step-down converter, SMPS6. Connect the output to an inductor. Power input for step-down converter, SMPS6 Switch node of step-down converter, SMPS9 Connect the output to an inductor. Switch node of step-down converter, SMPS6. Connect the output to an inductor. Power input for step-down converter, SMPS6 Switch node of step-down converter, SMPS9 Connect the output to an inductor. O — Floating I — Ground or floating O — Floating Secondary function: TESTV — — Ground Substrate ground Primary function: OTP programming voltage VPROG PBKG Pin Configuration and Functions Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Table 3-1. Summary of Digital Signals and Some Dedicated Analog Signals POWER DOMAIN AND TOLERANCE LEVEL I/O PWRON VSYS (VCC1) Input RPWRON VSYS (VCC1) Input Input PPD (2) (Optional External PU) SIGNAL NAME PWRDOWN VRTC, fail-safe (5.25-V tolerance) OTP PU/PD SELECTION OUTPUT TYPE SELECTION ACTIVE HIGH OR LOW OTP POLARITY SELECTION PU fixed N/A (fixed) N/A (input) Low No PU fixed N/A (fixed) N/A (input) Low INPUT PU/PD (1) Yes N/A (input) No Low or high (2) Yes (2) Yes POWERGOOD VRTC Output N/A (output) N/A (output) Open-drain Low or high BOOT0 VRTC Input No No N/A (input) Boot conf. No BOOT1 VRTC Tri-level input PPU or PPD (2) No N/A (input) Boot conf. No GPIO_0 VRTC, fail-safe (5.25-V tolerance) Yes Open-drain Low or high No GPIO_1 (primary function) GPIO_2 (primary function) VRTC, fail-safe (5.25-V tolerance) GPIO_4 (primary function) Input (2) or output PPU/PPD (2) Yes Push-pull (2) or open- drain Low or high Output N/A (output) N/A (output) Push-pull (2) or open- drain High Input (2) or output PPU or PPD (2) Yes Push-pull (2) or open- drain Low or high Output N/A (output) N/A (output) Push-pull (2) or open- drain High Input (2) or output PPD (2) Yes Open-drain Low or high (2) Input (2) or output PPU/PPD (2) No Output N/A (output) N/A (output) Input (2) or output PPU/PPD (2) No Push-pull (2) or open- drain Low or high No Output N/A (output) N/A (output) Push-pull Toggling No No No VIO (VIO_IN) GPIO_4 secondary function: SYSEN1 GPIO_5 (primary function) GPIO_5 secondary function: CLK32KGO1V8 or SYNCCLKOUT (2) PPD VSYS GPIO_2 secondary function: REGEN2 (1) or output (2) VSYS GPIO_1 secondary function: VBUSDET GPIO_3 Input (2) Yes Low or high Push-pull No High VRTC The pullup and pulldown resistors are defined as follows: PU pullup PD pulldown PPU software-programmable pullup PPD software-programmable pulldown Default option. Pin Configuration and Functions Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 11 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Table 3-1. Summary of Digital Signals and Some Dedicated Analog Signals (continued) SIGNAL NAME POWER DOMAIN AND TOLERANCE LEVEL GPIO_6 (primary function) GPIO_6 secondary function: SYSEN2 GPIO_7 (primary function) GPIO_7 secondary function: POWERHOLD I/O INPUT PU/PD (1) OTP PU/PD SELECTION ACTIVE HIGH OR LOW Input (2) or output PPU/PPD (2) No Output N/A (output) N/A (output) Input (2) or output PPD (2) Yes Open-drain Low or high Input PD fixed No N/A (input) High VIO (VIO_IN) VRTC, fail-safe (5.25-V tolerance) OUTPUT TYPE SELECTION OTP POLARITY SELECTION Low or high Push-pull No High No NSLEEP VRTC Input PPU (2) or PPD No N/A (input) Low (2) or high No but software possible ENABLE1 VIO (VIO_IN) Input PPU or PPD (2) No N/A (input) Low or high (2) No but software possible REGEN1 VSYS (VCC1) Output N/A (output) N/A (output) Push-pull or open- drain (OTP selection) High No VRTC, fail-safe (5.25-V tolerance) Input PPD (2) Yes N/A (input) Low (2) or high Yes RESET_OUT VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull Low No NRESWARM VRTC Input PPU (2) No N/A (input) Low No INT VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull (2) or open- drain Low (2) or high No but software possible CLK32KGO VIO (VIO_IN) Output N/A (output) N/A (output) Push-pull Toggling No I2C1_SDA_SDI VIO (VIO_IN) Input or output No No Open-drain High (I2C) Yes (I2C/SPI) I2C1_SCL_SCK VIO (VIO_IN) Input No No N/A (input) High (I2C) Yes (I2C/SPI) RESET_IN I2C2_SCL_SCE VIO (VIO_IN) Input No No 2 N/A (input) 2 High (I C) Yes (I2C/SPI) VIO (VIO_IN) Input or output No No Open-drain (I C) or Pushpull (SPI) High (I2C) Yes (I2C/SPI) GPADC_IN0 VRTC Input No No N/A (analog) Analog No GPADC_IN1 VANA Input No No N/A (analog) Analog No GPADC_IN2 VANA Input No No N/A (analog) Analog No GPADC_VREF VANA Output No No N/A (analog) Analog No OSC16MIN VRTC Input No No N/A (analog) Analog No OSC16MOUT VRTC Output No No N/A (analog) Analog No VCC_SENSE2 VSYS (VCC1) Input No No N/A (analog) Analog No VCC_SENSE VSYS (VCC1) Input No No N/A (analog) Analog No I2C2_SDA_SD0 12 Pin Configuration and Functions Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 4 Specifications 4.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT VCC1 pins –0.3 6 V VCC_SENSE, VCC_SENSE2 pins –0.3 7 V All LDOs and SMPS supply voltage input pins (except LDOUSB_IN2) –0.3 6 V –2 7 V All SMPS-related input pins, SMPSx_FDBK –0.3 3.6 V LDOUSB regulator LDOUSB_IN2 input voltage –0.3 20 V VIOmax + 0.3 V SMPSx_SW pins, 10 ns transient –0.3 I/O digital supply voltage (3) Voltage VIOmax + 0.3 VBUS –2 20 V GPADC pins: GPADC_IN0, GPADC_IN1 –0.3 5.25 V GPADC pins: GPADC_IN2 –0.3 2.5 V V OTP supply voltage VPROG –0.3 20 Without fail-safe –0.3 2.15 With fail-safe –0.3 5.25 VIO digital input pins (VIO_IN pin reference) –0.3 VIOmax + 0.3 V VSYS digital input pins (VCC1 pin reference) –0.3 6 V –5 VRTC digital input pins Peak output current on all pins other than power resources Current V 5 mA Power pins, nFBGA 1 A Buck SMPS, SMPSx_IN, SMPSx_SW, and SMPSx_OUT total per phase 4 A LDOs 1 A Junction temperature range, TJ –45 150 °C Storage temperature range, Tstg –65 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability. When operating the TPS659037 device without an external crystal, each SMPS regulating an output voltage greater than 1.8 V must be disabled before VCC is removed. Lowering VCC below the programmed VSYS_LO level while any SMPS is regulating an output voltage above 1.8 V may cause damage to the device. VIO_IN with respect to VIO_GND. 4.2 ESD Ratings Human body model (HBM), per ANSI/ESDA/JEDEC JS–001 (1) V(ESD) (1) (2) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101 (2) VALUE UNIT ±2000 V Pins B4, B7, H8, L1, L2, M3 ±450 All other pins ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 13 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 4.3 www.ti.com Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) MIN NOM All system voltage input pins VCC1 (named VSYS in the specification) 3.135 3.8 VCC_SENSE and VCC_SENSE2, HIGH_VCC_SENSE = 0 (1) 3.135 VCC_SENSE and VCC_SENSE2, HIGH_VCC_SENSE = 1 (1) 3.135 VVCC1 – 1 V 5.25 V All LDO-related input pins _IN (except LDOUSB) (2) 1.75 3.8 MAX UNIT 5.25 V VVCC1 V LDOUSB_IN1 3.6 5.25 V LDOUSB_IN2 4.3 5.25 V 5.25 V All SMPS-related input pin _IN 3.135 All SMPS-related input pins _FDBK 3.8 0 VOmax + 0.3 V All SMPS-related input pins _FDBK_GND –0.3 0.3 V I/O digital supply voltage VIO_IN, for 1.8-V Mode 1.71 1.8 1.89 V I/O digital supply voltage VIO_IN, for 3.3-V Mode 3.135 3.3 3.465 V Voltage on the GPADC pins GPADC_IN0, GPADC_IN1 pins 0 1.25 V Voltage on the GPADC pins GPADC_IN2 pin 0 2.5 V 1.85 V Voltage on the crystal oscillator OSC16MIN pin -0.7 VLDOVRTC OTP supply voltage VPROG 0 8 10 V Voltage on VRTC digital input pins 0 VLDOVRTC 1.85 V Voltage on VIO digital input pins (VIO_IN pin reference) 0 VIO VIOmax V Voltage on VSYS digital input pins (VCC1 pin reference) 0 3.8 5.25 V Operating free-air temperature range (3) –40 27 85 °C Operating Junction temperature –40 27 125 °C (1) (2) (3) If measured with GPADC, see Table 5-3. Does not include LDO1 and LDO2 minimum input voltages. Additional cooling strategies may be necessary to maintain junction temperature at recommended limits. 4.4 Thermal Information TPS659037 THERMAL METRIC (1) ZWS (NFBGA) UNIT 169 PINS RθJA Junction-to-ambient thermal resistance 36.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 6.6 °C/W RθJB Junction-to-board thermal resistance 18.6 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 18.2 °C/W (1) 4.5 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics: Latch Up Rating Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN I2C and SPI pins ILU Latch up current, Class 2 LDOVANA_OUT pin All other pins 14 Specifications TYP MAX UNIT 90 –60 mA 100 Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com 4.6 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Electrical Characteristics: LDO Regulator Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) MIN TYP Input filtering capacitance (C29, C30, C31, C32, C33, C34) PARAMETER Connected from LDOx_IN to GND. Shared input tank capacitance (depending on platform requirements) 0.6 2.2 Output filtering capacitance (C35, C36, C37, C38, C45, C46, C47) (1) Connected from LDOx_OUT to GND (Except LDO9) 0.6 2.2 2.7 Connected from LDO9_OUT to GND 0.6 2.2 2.7 Connected from LDO9_OUT to GND. LDO9 configured in BYPASS MODE (LDO9_CTRL.LDO_PYPASS_EN = 1) 0.6 1 1.2 < 100 kHz 20 100 600 mΩ 1 10 20 mΩ LDO9 Output filtering capacitance (C44) (1) CESR Filtering capacitor ESR TEST CONDITIONS 1 MHz ≤ f ≤ 10 MHz LDO1, LDO2 LDOLN, LDO3, LDO4 VLDOx Input voltage, LDOx LDO9 VLDOUSB1 Input voltage, LDOUSB1 VLDOUSB2 Input voltage, LDOUSB2 VI(VCC1) Input voltage, VCC1 VCC1 – Used for internal power supply VO(LDOx) LDO output voltage programmable (2) (except LDOVRTC and LDOVANA) VO(LDOx) < VLDOx – VDROPOUT(LDOx) TDCOV(LDOx) VDROPOUT(LDOx) VDROPOUT(LDOx) IO(LDOx) Total DC output voltage accuracy, including voltage references, DC load/line regulations, process and temperature Dropout voltage (3) Dropout voltage, internal LDOs LDOUSB – From LDOUSB_IN1 LDOUSB – From LDOUSB_IN2 0.9 V ≤ VO ≤ 2.15 V (1) (2) (3) 1.2 VVCC1 1.2 5.25 1.75 VVCC1 2.2 V ≤ VO ≤ 3.3 V 1.75 5.25 0.9 V ≤ VO ≤ 1.75 V 1.75 VVCC1 1.8 V ≤ VO ≤ 3.3 V 1.75 5.25 Bypass Mode 1.75 3.6 0.9 V ≤ VO ≤ 2.15 V 3.6 VVCC1 2.2 V ≤ VO ≤ 3.3 V 3.6 5.25 0.9 V ≤ VO ≤ 2.15 V 4.3 VVCC1 2.2 V ≤ VO ≤ 3.3 V 4.3 5.25 3.135 3.8 0.9 Step size 5.25 3.3 50 V V V V V mV All LDOs except LDO3, LDO4, LDOVANA, and LDOVRTC 0.99 × VO(LDOx) –0.014 1.006 × VO(LDOx) + 0.014 LDO3, LDO4: IO = 200 mA 0.99 × VO(LDOx) –0.014 1.006 × VO(LDOx) + 0.014 0.99 × VOUT(LDOx) – 0.018 1.006 × VOUT(LDOx) + 0.018 LDOVRTC_OUT 1.726 1.8 1.85 LDOVANA_OUT 2.002 2.093 2.119 LDO1, LDO2: IO = IOmax 150 LDO3, LDO4: IO = 200 mA 290 LDO3, LDO4: IO = IOmax 550 LDO9: IO = IOmax 230 LDOLN: IO = IOmax 150 LDOLN: IO = 100 mA (Functional, not low-noise performance) 290 LDOUSB – From LDOUSB_IN1: IO = IOmax 200 LDOUSB – From LDOUSB_IN2: IO = IOmax 900 LDOVRTC, LDOVANA: IO = IOmax 150 LDO1, LDO2 300 LDO3, LDO4 300 V mV Output current mV mA LDO9, LDOLN 50 100 LDOVANA 10 LDOVRTC 25 Output current, internal LDOs LDO inrush current µF µF 0.9 V ≤ VO ≤ 2.15 V LDO3, LDO4: 200 mA < IO ≤ 300 mA UNIT µF 2.2 V ≤ VO ≤ 3.3 V LDOUSB IO(LDOx_int) MAX mA LDO1, LDO2 500 mA Additional information about how this parameter is specified is located in Section 6.2.2. LDO output voltages are programmed separately. VDROPOUT(LDOx) = VI – VO, where VO = VOnom – 2% Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 15 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Electrical Characteristics: LDO Regulator (continued) Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER IL(LDOx) LDO current limitation ΔVO(ΔVI)(DC) DC load regulation, ΔVO MIN TYP MAX LDO1, LDO2 TEST CONDITIONS 380 600 1800 LDO3, LDO4 400 650 1300 LDO9 120 200 400 LDOUSB 120 250 600 LDOLN 150 325 740 LDOVANA 100 250 400 LDOVRTC 55 250 400 LDO1, LDO2: IO = 0 to IOmax at pin 4 16 LDO3, LDO4: 0 to 200 mA at pin 4 14 LDO3, LDO4: IO = 0 to IOmax at pin 4 18 DC line regulation, except VRTC, ΔVO / VO mA mV All other LDOs: IO = 0 to IOmax at pin ΔVO(DVI)(DC) UNIT 4 14 VI = VImin to VImax, IO = IOmax 0.1% 0.2% VSYS = VSYSmin to VSYSmax, IO = IOmax. VI constant (LDO preregulated), VO ≤ 2.2 V 0.3% 0.75% DC line regulation on LDOVRTC, ΔVO/VO VSYS = VSYSmin to VSYSmax, IO = IOmax 1% Bypass resistance of LDO9 VI ≥ 2.7 V, programmed to BYPASS 4.2 Ω ton Turnon time IO = 0, VO = 0.1 V up to VOmin 100 500 µs toff Turnoff time (except VRTC ) IO = 0, VO down to 10% × VO 250 500 μs RDIS Pulldown discharge resistance at LDO output, except LDOVRTC OFF mode, pull down enabled and LDO disabled. Also applies to bypass mode 30 125 Ω ƒ = 217 Hz, IO = IOmax 55 90 ƒ = 50 kHz, IO = IOmax 28 45 ƒ = 1 MHz, IO = IOmax 25 35 LDO9, LDOUSB: ƒ = 217 Hz, IO = IOmax 55 90 LDO3, LDO4: ƒ = 217 Hz, IO = IOmax 50 60 LDO3, LDO4: ƒ = 217 Hz, IO = 200 mA 55 90 All other LDOs: ƒ = 50 kHz, IO = IOmax 20 45 All other LDOs: ƒ = 1 MHz, IO = IOmax 20 35 ƒ = 217 Hz, IO = IOmax 55 90 ƒ = 50 kHz, IO = IOmax 25 45 ƒ = 1 MHz, IO = IOmax 25 35 Power-supply ripple rejection, LDO1, LDO2 Power-supply ripple rejection, LDO3, LDO4,LDO9, LDOUSB Power-supply ripple rejection, LDOLN IQ(off) Quiescent-current off mode IQ(on) Quiescent-current LDO ON mode Quiescent current coefficient, LDO ON mode (4) αQ ΔVO(ΔIO)(T) Transient load regulation ΔVO For all LDOs, T = 27°C 0.1 For all LDOs, T ≥ 85°C 0.2 IL = 0 mA (LDO1, LDO2), 0.9 V ≤ VO ≤ 3.3 V, VO(LDOx) < VLDOx – VDROPOUT(LDOx) 39 Transient line regulation, ΔVO / VO (4) IQO = IQ(on) + αQ × IO 16 Specifications dB dB µA 70 IL = 0 mA (LDO3, LDO4, LDO9), VO(LDOx) < VLDOx – VDROPOUT(LDOx) 36 47 IL = 0 mA (LDOLN) , VO ≤ 1.8 V, VO(LDOx) < VLDOx – VDROPOUT(LDOx) 140 190 IL = 0 mA (LDOLN) , VO > 1.8 V, VO(LDOx) < VLDOx – VDROPOUT(LDOx) 180 210 IL = 0 mA (LDOUSB) – IN1, VO(LDOx) < VLDOx – VDROPOUT(LDOx) 45 65 IL = 0 mA (LDOUSB) – IN2, VO(LDOx) < VLDOx – DV(LDOx) 18 25 IO < 100 µA 4% 100 µA ≤ IO < 1 mA 2% IO ≥ 1 mA 1% All LDOs except LDO3, LDO4, LDO9, LDOLN: ON mode, IO = 10 mA to IOmax / 2, tr = tf = 1 µs –25 25 LDO9, LDOLN: ON mode, IO = 1 mA to IOmax /2, tr = tf = 1 µs –25 25 LDO3, LDO4: ON mode, IO = 10 mA to 100 mA, tr = tf = 1 µs –25 25 LDO3, LDO4: ON mode, IO = 10 mA to IOmax / 2, tr = tf = 1 µs –40 25 ON mode, IO = 100 µA to IOmax / 2, tr = tf = 1 µs –50 VI step = 600 mVPP, tr = tf = 10 µs ΔVO(ΔVI)(T) dB VSYS step = 600 mVPP, tr = tf = 10 µs. VI constant (LDO preregulated), VO ≤ 2.2 V µA mV 33 0.25% 0.5% 0.8% 1.6% Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Electrical Characteristics: LDO Regulator (continued) Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER TEST CONDITIONS Noise (except LDOLN) Noise (LDOLN) Ripple 4.7 TYP MAX 100 Hz < ƒ ≤ 10 kHz MIN 5000 8000 10 kHz < ƒ ≤ 100 kHz 1250 2500 100 kHz < ƒ ≤ 1 MHz 150 300 ƒ > 1 MHz 250 500 100 Hz < ƒ ≤ 5 kHz, IO = 50 mA, VO ≤ 1.8 V 400 500 5 kHz < ƒ ≤ 400 kHz, IO = 50 mA, VO ≤ 1.8 V 62 400 kHz < ƒ ≤ 10 MHz, IO = 50 mA, VO ≤ 1.8 V 25 UNIT nV/√Hz 125 nV/√Hz 50 LDO1, LDO2, ripple (from internal charge pump) 5 mVPP MAX UNIT Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Input capacitance (C9, C10, C11, C12, C13) Output capacitance (C18, C19, C21, C22) (1) Output capacitance, (C20, C24) CESR 4.7 33 47 57 SMPS3 and SMPS7 (triple phase operation) 33 47 57 µF 2 10 mΩ 1 MHz ≤ f ≤ 10 MHz Output filter inductance (L1, L2, L3, L4, L5) SMPSx_SW Filter inductor DC resistance VSMPSx Input voltage range, SMPSx_IN Output voltage, programmable, SMPSx Connected to VSYS (VCC1) RANGE = 0 (value for RANGE must not be changed when SMPS is active). In Eco-mode the output voltage values are fixed (defined before Eco-mode is enabled). RANGE = 1 is not supported for Multiphase regulators. 0.7 µF 1 1.3 µH 50 100 mΩ 3.135 5.25 V 0.7 1.65 V Step size, 0.7 V ≤ VO ≤ 1.65 V (RANGE = 0) DC output voltage accuracy, includes voltage references, DC load/line regulation, process and temperature µF SMPS12 or SMPS45 dual phase operation, per phase Filtering capacitor ESR DCRL VOSMPSx (1) TYP 10 mV Eco-mode –3% 4% Forced PWM mode –1% 2% Ripple, dual phase Maximum load, VI = 3.8 V, VO = 1.2 V, ESRCO = 2 mΩ, measure with 20-MHz LPF 4 mVPP Ripple, triple phase Maximum load, VI = 3.8 V, VO = 1.2 V, ESRCO = 2 mΩ, measure with 20-MHz LPF 1 mVPP ΔVO(ΔVI) DC line regulation 0.1 %/V ΔVO(ΔIO) DC load regulation 0.1 %/A IOmax Transient load step response, dual phase IO = 0.8 to 2 A, tr = tf = 400 ns, CO = 47 µF , L= 1 µH 3% Transient load step response, triple phase IO = 0.8 to 2 A, tr = tf = 400 ns, CO = 47 µF , L= 1 µH 3% Transient load step response, dual or triple phase IO = 0.5 to 500 mA, tr = tf = 100 ns, CO = 47 µF , L= 1 µH 3% Rated output current, SMPS12 Advance thermal design is required to avoid thermal shutdown 6 Rated output current, SMPS123 Advance thermal design is required to avoid thermal shutdown 9 Rated output current, SMPS45 Advance thermal design is required to avoid thermal shutdown 4 Maximum output current, Eco-mode I(LIM_HS_FET) High-side MOSFET forward current-limit I(LIM_LS_FET) Low-side MOSFET forward current-limit 5 SMPS123, each phase 3.7 4 SMPS45, each phase 2.7 3 mA A SMPS123, each phase 3.7 SMPS45, each phase 2.7 SMPS123, phase 1 0.6 SMPS45, phase 4 0.6 SMPS123, each phase 115 SMPS45, each phase 115 A Low-side MOSFET negative current-limit A rDS(on_HS_FET) N-channel MOSFET on-resistance, high-side FET rDS(on_LS_FET) N-channel MOSFET on-resistance, low- SMPS123, each phase side FET SMPS45, each phase t(start) Time from enable to start of the ramp (1) A mΩ 30 mΩ 30 150 µs Additional information about how this parameter is specified is located in Section 6.2.2. Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 17 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators (continued) Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER t(ramp) Time from enable to 80% of VO TEST CONDITIONS MIN CO < 57 µF per phase, no load TYP MAX UNIT 400 1000 µs Overshoot during turnon Output voltage slew rate 5% Fixed TSTEP 2.5 SMPS turned off 300 R(DIS) Pulldown discharge resistance at SMPS2, SMPS4 output R(SENSE) Between SMPS1_2_FDBK, SMPS1_2_FDBK_GND Input resistance for remote sense/sense Between SMPS4_5_FDBK, SMPS4_5_FDBK_GND line SMPS3_FDBK input resistance IQ(off) Quiescent current – OFF mode Quiescent current -ON mode, dual or triple phase IQ(on) VSMPSPG Powergood threshold IL_AVG_COMP Powergood: GPADC monitoring SMPS Ω SMPSx_SW, SMPS turned off. Pulldown is at the master phase output. 9 22 380 1300 380 1300 380 1300 IL = 0 mA 0.1 1 Eco-mode, device not switching, VO < 1.8 V 13.5 19 Eco-mode, device not switching, VO ≥ 1.8 V 15 21 FORCED_PWM mode, IL= 0 mA, VI = 3.8 V, device switching, 1phase operation 11 kΩ µA µA SMPS output voltage rising, referenced to programmed output voltage –7.5% SMPS output voltage falling, referenced to programmed output voltage –12.5% IL_AVG_COMP_rising 4.8 mV/μs IOmax – 20% IOmax mA IOmax + 20% IL_AVG_COMP_falling, 3-A phase IL_AVG_COMP_rising – 5% IL_AVG_COMP_falling, 2-A phase IL_AVG_COMP_rising – 8% Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9) Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Input capacitance (C11, C14, C15, C16, C17) CESR SMPSx operation Filtering capacitor DC ESR 1 MHz ≤ f ≤ 10 MHz Output filter inductance (L3, L6, L7, L8, L9) SMPSx_SW Filter inductor DC resistance VSMPSx Input voltage range, SMPSx_IN MAX 4.7 Output capacitance (C20, C23, C24, C25, C26) (1) LR(DC) TYP 33 0.7 UNIT µF 47 57 µF 2 10 mΩ 1 1.3 µH 100 mΩ 3.135 50 5.25 V RANGE = 0 (value for RANGE must not be changed when SMPS is active). In Eco-mode the output voltage value is fixed (defined before Eco-mode is enabled). 0.7 1.65 RANGE = 1 (value for RANGE must not be changed when SMPS is active). In Eco-mode the output voltage value is fixed (defined before Eco-mode is enabled). 1 3.3 Connected to VSYS (VCC1) V VOSMPSx Output voltage, programmable, SMPSx DC output voltage accuracy, includes voltage references, DC load/line regulation, process and temperature Step size, 0.7 V ≤ VO ≤ 1.65 V 10 Step size, 1 V ≤ VO ≤ 3.3 V 20 mV Eco-mode –3% 4% PWM mode –1% 2% Ripple Max load, VI = 3.8 V, VO = 1.2 V, ESRCO = 2 mΩ, measure with 20-MHz LPF 8 mVPP DCLNR DC line regulation TA = –40°C to 85°C 0.1 %/V DCLDR DC load regulation TA = –40°C to 85°C 0.1 %/A TLDSR Transient load step response SMPS3, SMPS6, SMPS7 , IOUT = 0.5 to 500 mA, tr = tf = 100 ns, CO = 47 µF , L = 1 µH 3% TLDSR Transient load step response SMPS8, SMPS9, IO = 0.5 to 500 mA, TR = TF = 1 µs, CO = 47 µF , L = 1 µH 3% VI ≥ 3 V, Advance thermal design is required to avoid thermal shutdown 3 VI < 3 V, Advance thermal design is required to avoid thermal shutdown 2 Rated output current, SMPS3 (1) 18 A Additional information about how this parameter is specified is located in Section 6.2.2. Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9) (continued) Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2 When OTP programmed with BOOST_CURRENT = 1 Advance thermal design is required to avoid thermal shutdown 3 Rated output current, SMPS7 Advance thermal design is required to avoid thermal shutdown 2 Rated output current, SMPS8, SMPS9 Advance thermal design is required to avoid thermal shutdown 1 A 5 mA Rated output current, SMPS6 A Maximum output current, Eco-mode SMPS3, and SMPS6 in 3-A mode ILIM HS FET High-side MOSFET forward current limit SMPS6 in 2-A mode, SMPS7 SMPS8, SMPS9 3.7 4 2.7 3 1.7 2 SMPS3, and SMPS6 in 3-A mode ILIM LS FET rDS(on_LS_FET) 1.7 SMPS3, and SMPS6 in 3-A mode 0.6 SMPS3 115 SMPS6, SMPS7 115 SMPS8, SMPS9 180 SMPS3 N-channel MOSFET on-resistance (lowSMPS6, SMPS7 side FET) SMPS8, SMPS9 30 Time from enable to start of the ramp t(ramp) Time from enable to 80% of VO A 0.6 0.6 t(start) A 2.7 SMPS8, SMPS9 SMPS8, SMPS9 N-channel MOSFET on-resistance (high-side FET) A mΩ 30 mΩ 79 150 CO < 57 µF, no load µs 400 1000 Overshoot during turnon Fixed TSTEP, only available on SMPS6, SMPS8 2.5 SMPSx_FDBK, SMPS turned off 300 R(DIS) Pulldown discharge resistance at SMPSx output IQ(off) Quiescent current – OFF mode IL = 0 mA 0.1 1 Eco-mode, device not switching, VO < 1.8 V 12 15 13.5 23 9 22 µA µA Quiescent current – ON mode - SMPS3, Eco-mode, device not switching, VO ≥ 1.8 V SMPS6, SMPS7 FORCED_PWM mode, IL = 0 mA, VI = 3.8 V, device switching 11 mA 10.5 15 12 23 µA Quiescent current – ON mode - SMPS8, Eco-mode, device not switching, VO ≥ 1.8 V SMPS9 FORCED_PWM mode, IL = 0 mA, VI = 3.8 V, device switching 7 SMPS output voltage rising, referenced to programmed output voltage VSMPSPG mV/μs Ω SMPSx_SW, SMPS turned off Eco-mode, device not switching, VO < 1.8 V IQ(on_SMPS8,9) µs 5% Output voltage slew rate IQ(on_SMPS3,6,7) A 3.7 Low-side MOSFET forward current limit SMPS6 in 2-A mode, SMPS7 Low-side MOSFET negative current limit SMPS6 in 2-A mode, SMPS7 rDS(on_HS_FET) UNIT When OTP programmed with BOOST_CURRENT = 0 Advance thermal design is required to avoid thermal shutdown mA –7.5% Powergood threshold SMPS output voltage falling, referenced to programmed output voltage IL_AVG_COMP_rising Powergood: GPADC monitoring SMPS –12.5% IOmax – 20% IOmax IOmax + 20% IL_AVG_COMP_falling, 3-A phase IL_AVG_COMP_rising – 5% IL_AVG_COMP_falling, 2-A phase IL_AVG_COMP_rising – 8% Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 19 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 4.9 www.ti.com Electrical Characteristics: Reference Generator (Bandgap) Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER Filtering capacitor VI TEST CONDITIONS Connected from VBG to REFGND Input voltage MIN TYP MAX UNIT 30 100 150 nF 2.1 3.8 5.25 V Output voltage 0.85 Ground current 20 40 µA 1 3 ms Start-up time V 4.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CRYSTAL CHARACTERISTICS Crystal frequency Typical with specified load capacitors Crystal frequency tolerance Parameter of crystal; TA 27°C 16.384 Crystal motional inductance Parameter of crystal Crystal series resistance At fundamental frequency Oscillator drive power The power dissipated in the crystal during oscillator operation Load capacitance Corresponding to crystal frequency, including parasitic capacitances Crystal shunt capacitance Parameter of crystal 0.5 Oscillator frequency drift TJ from –40°C to 125°C, VCC1 from 3.15 V to 5.25 V Excluding crystal tolerance –50 Oscillator startup time Time from VCC1 > 3.15 V until 32-kHz clock output is available from crystal oscillator –30 23 8 MHz 30 ppm 33 43 mH 90 Ω 15 120 μW 10 12 pF 4 pF 50 ppm 10 ms 32-kHz RC OSCILLATOR Output frequency low-level output voltage Output frequency accuracy 32768 After trimming, TA 27°C –10% 0 40% 50% Cycle jitter (RMS) Hz 10% 10% Output duty cycle Settling time Active current consumption 4 Power-down current 60% 150 μs 8 μA 30 nA 50 pF ns CLK32KGO OUTPUT BUFFER Logic output external load 5 Rise and fall time CL = 35 pF, 10% to 90% Duty cycle Logic output signal 35 5 50 100 40% 50% 60% 25 50 μs 7 10 μA 30 nA CLK32KGO1 V8 OUTPUT BUFFER Settling time Active current consumption 5 Power-down current Duty cycle degradation contribution –2% External output load 5 Output delay time Output load = 10 pF Output rise and fall time Output load = 10 pF 2% 10 50 pF 15 30 ns 20 ns 7.5 SYNCCLKOUT OUTPUT BUFFER Logic output external load Rise and fall time 20 CL = 35 pF, 10% to 90% Specifications 5 35 50 pF 5 50 100 ns Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers (continued) Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER Duty cycle TEST CONDITIONS Logic output signal MIN TYP MAX UNIT 40% 50% 60% MIN TYP MAX UNIT 1.7 2.2 2.7 MHz 4.11 Electrical Characteristics: DC-DC Clock Sync Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER TEST CONDITIONS SYNC CLOCK SPECIFICATION AND DITHER PARAMETERS ƒ(SYNC) The allowed range of the external sync clock input A(DITHER) Dither amplitude 128 Dither slope kHz/ 1.35 µs M(DITHER) kHz SYNC DC-DC DIGITAL CLOCK INPUT VIL Low-level input on SYNCDCDC pin –0.3 0 0.3 × VVRTC V VIH High-level input on SYNCDCDC pin 0.7 × VVRTC VVRTC 5.25 V Duty cycle of SYNCDCDC input signal 20% 80% 0.1 × VVRTC Hysteresis of input buffer V SYNC CLOCK AND FREQUENCY FALLBACK ƒ(FALLBACK) Fall-back frequency ƒ(SAT_LO) The low saturation frequency output of the PLL ƒ(SAT_HI) The high saturation frequency output of the PLL ƒ(SETTLE) Time from initial application or removal of sync clock until PLL output has settled to 1% of its final value ƒ(ERROR) The steady-state percent difference between fSYNC and the switching frequency td Time delay between corresponding staggered phases 1.98 2.2 2.42 MHz 1.65 MHz 2.8 MHz 100 –1% 15 µs 1% 30 45 ns 4.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1500 1600 IQ(on) Current consumption During conversion IQ(off) OFF mode current GPADC is not enabled (no conversion) ƒ Running frequency 2.5 MHz Resolution 12 Bit 1 Number of available external inputs 3 Number of available internal inputs 5 Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 μA μA 21 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Electrical Characteristics: 12-Bit Sigma-Delta ADC (continued) Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER Turnon time TEST CONDITIONS MIN Active or sleep with VANA ON and RC15MHZ_ON_IN_SLEEP = 1 or sleep with GPADC_FORCE = 1 TYP MAX UNIT 0 μs Sleep or OFF 794 μs Sleep with VANA enabled 282 Gain error (without scaler) μs –3.5% 3.5% Gain error of the scaler –1% 1% Offset before trimming –50 50 LSB Temperature and supply –2 2 LSB Gain error drift (after trimming, including reference Temperature and supply voltage) –0.6% 0.2% –3.5 3.5 LSB 3.5 LSB 20 kΩ Offset drift after trimming INL Integral nonlinearity DNL Differential nonlinearity Input capacitance Source input impedance Best fitting –1 GPADC_IN0–GPADC_IN2 0.5 Source resistance without capacitance Source capacitance with > 20-kΩ source resistance GPADC_VREF voltage reference 100 1.237 nF 1.25 Load current for GPADC_VREF Input range (sigma-delta ADC) Conversion time Typical range Assured range without saturation 1.263 V 200 µA 0 1.250 0.01 1.215 1 channel, EXTEND_DELAY = 0 113 1 channel, EXTEND_DELAY = 1 563 2 channels 223 CURRENT_SRC_CH0[1:0] = 00 (default) GPADC_IN0 current source pF V μs 0 CURRENT_SRC_CH0[1:0] = 01 4.5 5.13 5.75 CURRENT_SRC_CH0[1:0] = 10 14.45 15.55 16.65 CURRENT_SRC_CH0[1:0] = 11 19.2 20.7 22.1 SMPS current monitoring (GPADC Channel 11) μA See Equation 1 and Equation 2 IFS0 Channel 11 SMPS output current measurement gain factor 3.958 A IOS0 Channel 11 SMPS output current measurement current offset 0.652 A TC_R0 Channel 11 SMPS output current measurement temperature coefficient –1090 ppm/ C SMPS output current measurement Accuracy, I(ERROR) (%), GPADC trimmed 22 SMPS3, SMPS6, SMPS7 IL(error) (%) = IL(meas) / IL × 100 at 1 A, 25°C –13% 13% SMPS6, SMPS7 IL(error) (%) = IL(meas) / IL × 100 at 2 A, 25°C –9% 9% SMPS3 IL(error) (%) = IL(meas) / IL × 100 at 3 A, 25°C –8% 8% SMPS45 IL(error) (%) = IL(meas) / IL × 100 at 4 A, 25°C –7% 7% SMPS12 IL(error) (%) = IL(meas) / IL × 100 at 6 A, 25°C, –7% 7% SMPS123 IL(error) (%) = IL(meas) / IL × 100 at 9 A, 25°C –7% 7% Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 4.13 Electrical Characteristics: Thermal Monitoring and Shutdown Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER TEST CONDITIONS Hot-die temperature threshold Thermal shutdown threshold MIN TYP MAX UNIT Rising threshold, THERM_HD_SEL[1:0] = 00 104 117 129 Falling threshold, THERM_HD_SEL[1:0] = 00 95 108 119 Rising threshold, THERM_HD_SEL[1:0] = 01 109 121 133 Falling threshold, THERM_HD_SEL[1:0] = 01 99 112 124 Rising threshold, THERM_HD_SEL[1:0] = 10 113 125 136 Falling threshold, THERM_HD_SEL[1:0] = 10 104 116 128 Rising threshold, THERM_HD_SEL[1:0] = 11 117 130 143 Falling threshold, THERM_HD_SEL[1:0] = 11 108 120 132 Rising threshold 133 148 163 Falling threshold 111 123 135 Off ground current (two sensors on the die, specification for one sensor) Device in OFF state, VVCC1 = 3.8 V, T = 25°C 0.1 IQ(off) Device in OFF state 0.5 On ground current (two sensors on the die, specification for one sensor) Device in ACTIVE state, VVCC1 = 3.8 V, T = 25°C IQ(on) Device in ACTIVE state, GPADC measurement 7 15 25 40 °C °C µA µA 4.14 Electrical Characteristics: System Control Threshold Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2 2.15 2.50 1.90 2 2.10 V 40 300 mV Voltage range, 50-mV steps 2.75 3.10 Voltage accuracy –50 95 mV 75 460 mV Voltage range, 50-mV steps 2.9 3.85 V Voltage accuracy –55 105 mV VSYS_MON, measured on VCC_SENSE pin Voltage range, 50-mV steps 2.75 4.6 V Voltage accuracy –70 140 mV VBUS detection (VBUS wake-up comparator threshold) Rising threshold 2.9 3.6 V Falling threshold 2.8 3.3 V POR (power-on reset) rising-edge threshold Measured on VCC1 pin POR falling-edge threshold Measured on VCC1 pin POR hysteresis Rising edge to falling edge VSYS_LO, measured on VCC1 pin VSYS_LO hysteresis Falling edge to rising edge VSYS_HI, measured on VCC_SENSE pin V V 4.15 Electrical Characteristics: Current Consumption Over operating free-air temperature range, typical values are at TA = 27°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 20 45 VSYS (VCC1) = 3.8 V 120 180 VSYS (VCC1) = 5.25 V 150 225 VSYS (VCC1) = 3.8 V 2.64 2.81 VSYS (VCC1) = 5.25 V 3.3 3.5 UNIT OFF MODE Current consumption in OFF mode VSYS (VCC1) = 3.8 V µA SLEEP MODE Current consumption in SLEEP mode LDO2 and LDO9 enabled without load, 16-MHz oscillator completely disabled with system clock coming solely on internal 32-KHz RC oscillator LDO2 and LDO9 enabled without load, 16-MHz oscillator enabled µA mA Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 23 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com 4.16 Electrical Characteristics: Digital Input Signal Parameters Over operating free-air temperature range, typical values are at TA = 27°C VIO refers to the VIO_IN pin, VSYS to the VCC1 pin (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWRON, RPWRON VIL Low-level input voltage related to VSYS (VCC1 pin reference) –0.3 0 0.35 × VVSYS V VIH High-level input voltage related to VSYS (VCC1 pin reference) 0.65 × VVSYS VVSYS VVSYS + 0.3 ≤ 5.25 V Hysteresis 0.05 × VVSYS V ENABLE1, GPIO_4, GPIO_6, I2C1_SCL_SCK, I2C1_SDA_SDI, I2C2_SCL_SCE, I2C2_SDA_SDO VIL Low-level input voltage related to VIO (VIO_IN pin reference) –0.3 0 0.3 × VIO V VIH High-level input voltage related to VIO (VIO_IN pin reference) 0.7 × VIO VIO VIO + 0.3 V 0.05 × VIO Hysteresis V BOOT0, PWRDOWN, RESET_IN, NSLEEP, NRESWARM, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_5, GPIO_7 OR POWERHOLD VIL Low-level input voltage related to VRTC –0.3 0 0.3 × VVRTC V VIH High-level input voltage related to VRTC 0.7 × VVRTC VVRTC VVRTC + 0.3 V Hysteresis 0.05 × VVRTC V Input voltage maximum for RESET_IN and GPIO_7 5.25 V BOOT1 VIL Low-level input voltage related to VRTC –0.3 0 0.3 × VVRTC V VIH High-level input voltage related to VRTC 0.95 × VVRTC VVRTC VVRTC + 0.3 V 4.17 Electrical Characteristics: Digital Output Signal Parameters Over operating free-air temperature range, typical values are at TA = 27°C, VIO refers to the VIO_IN pin, VSYS to the VCC1 pin (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REGEN1, REGEN2 VOL Low-level output voltage, push-pull IOL = 2 mA and open-drain IOL = 100 µA 0 0.45 V 0 0.2 V VOH High-level output voltage, pushpull IOH = 2 mA VVSYS – 0.45 VVSYS V IOH = 100 µA VVSYS – 0.2 VVSYS V VVSYS V 0 0.4 V IOH = 2 mA VVSYS – 0.45 VVSYS V IOH = 100 µA VVSYS – 0.2 VVSYS V VVSYS V Supply for external pullup resistor, open-drain GPIO_1 or VBUSDET, GPIO_2 VOL Low-level output voltage, push-pull IOL = 10 mA and open-drain VOH High-level output voltage, pushpull Supply for external pullup resistor, open-drain 24 Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Electrical Characteristics: Digital Output Signal Parameters (continued) Over operating free-air temperature range, typical values are at TA = 27°C, VIO refers to the VIO_IN pin, VSYS to the VCC1 pin (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INT VOL Low-level output voltage, push-pull IOL = 2 mA and open-drain IOL = 100 µA VOH High-level output voltage, pushpull (VIO_IN pin reference) IOH = 2 mA IOH = 100 µA 0 0.45 V 0 0.2 V VIO – 0.45 VIO V VIO – 0.2 VIO V VIO V 0 0.45 V Supply for external pullup resistor, open-drain GPIO_4 or SYSEN1, GPIO_6 or SYSEN2, RESET_OUT VOL VOH Low-level output voltage, push-pull High-level output voltage, pushpull (VIO_IN pin reference) IOL = 2 mA IOL = 100 µA 0 0.2 V VIO – 0.45 VIO V VIO – 0.2 VIO V IOL = 2 mA 0 0.45 V IOL = 100 µA 0 0.2 V VVRTC V IOH = 2 mA IOH = 100 µA POWERGOOD VOL Low-level output voltage, opendrain Supply for external pullup resistor, open-drain GPIO5 VOL VOL VOH Low-level output voltage, opendrain Low-level output voltage, push-pull High-level output voltage, pushpull IOL = 2 mA 0 0.45 V IOL = 100 µA 0 0.2 V IOL = 2 mA 0 0.45 V IOL = 100 µA 0 0.2 V IOH = 2 mA VVRTC – 0.45 VVRTC V IOH = 100 µA VVRTC – 0.2 VVRTC V VVRTC V Supply for external pullup resistor, open-drain CLK32KGO1 V8, SYNCCLKOUT VOL VOH Low-level output voltage, push-pull High-level output voltage, pushpull IOL = 1 mA 0 0.45 V IOL = 100 µA 0 0.2 V IOH = 1 mA VVRTC – 0.45 VVRTC V IOH = 100 µA VVRTC – 0.2 VVRTC V IOL = 1 mA 0 0.45 V IOL = 100 µA 0 0.2 V VIO – 0.45 VIO V VIO – 0.2 VIO V External pullup to VRTC, IOL = 2 mA 0 0.45 V External pullup to VRTCIOL = 100 μA 0 0.2 V 5.25 V CLK32KGO VOL VOH Low-level output voltage, push-pull High-level output voltage, pushpull (VIO_IN pin reference) IOH = 1 mA IOH = 100 µA GPIO_0, GPIO_3, GPIO_7 VOL Low-level output voltage, opendrain Maximum supply for external pullup resistor, open-drain I2C1_SDA_SDI, I2C2_SDA_SDO Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 25 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Electrical Characteristics: Digital Output Signal Parameters (continued) Over operating free-air temperature range, typical values are at TA = 27°C, VIO refers to the VIO_IN pin, VSYS to the VCC1 pin (unless otherwise noted) PARAMETER Low-level output voltage VOL related to VIO (VIO_IN pin reference) TEST CONDITIONS MIN 3-mA sink current TYP 0 0.1 × VIO 0.2 × VIO V 20 pF Capacitive load for I2C2_SDA_SDO in SPI mode CB MAX UNIT 4.18 Electrical Characteristics: I/O Pullup and Pulldown Over operating free-air temperature range, VIO refers to the VIO_IN pin, VSYS to the VCC1 pin (unless otherwise noted) PARAMETER TEST CONDITIONS PWRON, RPWRON pullup resistance, fixed pullup PWRDOWN pulldown resistance BOOT1 pullup resistance PULLUP SUPPLY MIN TYP MAX UNIT VSYS 55 120 370 kΩ — 180 400 VRTC BOOT1 pulldown resistance — GPIO_0 pulldown resistance GPIO_1, GPIO_2 pullup resistance GPIO_1, GPIO_2 pulldown resistance GPIO_3, RESET_IN pulldown resistance GPIO_4, GPIO_6 pullup resistance GPIO_4, GPIO_6 pulldown resistance GPIO_5 pullup resistance 900 kΩ 13.5 kΩ 14 kΩ — 180 400 900 kΩ VSYS 170 400 950 kΩ — 170 400 950 kΩ — 180 400 900 kΩ VIO 170 400 950 kΩ — 170 400 950 kΩ VRTC 170 400 950 kΩ GPIO_5 pulldown resistance — 170 400 950 kΩ GPIO_7 or POWERHOLD pulldown resistance — 180 400 900 kΩ VRTC 170 400 950 kΩ — 170 400 950 kΩ VRTC 78 120 225 kΩ NSLEEP, ENABLE1 pullup resistance NSLEEP, ENABLE1 pulldown resistance NRESWARM pullup resistance 4.19 I2C Interface Timing Requirements Over operating free-air temperature range (1) (2) (3) (4). For the timing diagram for fast and standard (F/S) modes, see Figure 4-1. For the timing diagram for high-speed (HS) mode, see Figure 4-2. MIN ƒ(SCL) t(BUF) (1) (2) (3) (4) 26 SCL clock frequency Bus free time between a STOP and START condition MAX UNIT Standard mode 100 kHz Fast mode 400 kHz High-speed mode (write operation), CB – 100 pF max 3.4 MHz High-speed mode (read operation), CB – 100 pF max 3.4 MHz High-speed mode (write operation), CB – 400 pF max 1.7 MHz High-speed mode (read operation), CB – 400 pF max 1.7 MHz Standard mode 4.7 µs Fast mode 1.3 µs Specified by design. Not tested in production. All values referred to VIHmin and VIHmax levels. For bus line loads CB between 100 and 400 pF, the timing parameters must be linearly interpolated. A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time. Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 I2C Interface Timing Requirements (continued) Over operating free-air temperature range(1)(2)(3)(4). For the timing diagram for fast and standard (F/S) modes, see Figure 4-1. For the timing diagram for high-speed (HS) mode, see Figure 4-2. MIN Standard mode th(STA) t(LOW) µs ns 160 ns Standard mode 4.7 µs Fast mode 1.3 µs High-speed mode, CB – 100 pF maximum 160 ns High-speed mode, CB – 400 pF maximum 320 ns 4 µs 600 ns High-speed mode, CB – 100 pF maximum 60 ns High-speed mode, CB – 400 pF maximum 120 ns Standard mode 4.7 µs Fast mode 600 ns High-speed mode 160 ns Standard mode 250 ns Fast mode 100 ns Standard mode t(HIGH) tsu(STA) tsu(DAT) High period of the SCL clock Setup time for a REPEATED START condition Data setup time Fast mode High-speed mode th(DAT) tr(CL) Data hold time Rise time of the SCL signal tf(CL) tr(DA) Fall time of the SCL signal Rise time of the SDA signal ns 0 3.45 µs Fast mode 0 0.9 µs High-speed mode, CB – 100 pF maximum 0 70 ns High-speed mode, CB – 400 pF maximum 0 150 ns Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns 10 40 ns High-speed mode, CB – 400 pF maximum tr(CL1) 10 Standard mode High-speed mode, CB – 100 pF maximum Rise time of the SCL signal after a REPEATED START condition and after an Acknowledge bit UNIT 600 Hold time (REPEATED) START Fast mode condition High-speed mode Low period of the SCL clock MAX 4 20 80 ns Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns High-speed mode, CB – 100 pF maximum 10 80 ns High-speed mode, CB – 400 pF maximum 20 160 ns Standard mode 20 + 0.1 CB 300 ns Fast mode 20 + 0.1 CB 300 ns High-speed mode, CB – 100 pF maximum 10 40 ns High-speed mode, CB – 400 pF maximum 20 80 ns Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns High-speed mode, CB – 100 pF maximum 10 80 ns High-speed mode, CB – 400 pF maximum 20 160 ns Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 27 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com I2C Interface Timing Requirements (continued) Over operating free-air temperature range(1)(2)(3)(4). For the timing diagram for fast and standard (F/S) modes, see Figure 4-1. For the timing diagram for high-speed (HS) mode, see Figure 4-2. tf(DA) Fall time of the SDA signal MIN MAX UNIT Standard mode 20 + 0.1 CB 300 ns Fast mode 20 + 0.1 CB 300 ns High-speed mode, CB – 100 pF maximum 10 80 ns High-speed mode, CB – 400 pF maximum 20 160 ns Standard mode Setup time for a STOP condition tsu(STOP) 4 µs Fast mode 600 ns High-speed mode 160 ns 4.20 SPI Timing Requirements For the SPI timing diagram, see Figure 4-3 MIN MAX UNIT tsu(ce) Chip-select setup time 30 ns th(ce) Chip-select hold time 30 ns tc(clk) Clock cycle time 67 tp(HIGH_ck) Clock high typical pulse duration 20 ns tp(LOW_ck) Clock low typical pulse duration 20 ns tsu(si) Input data set up time, before clock active edge 5 ns th(si) Input data hold time, after clock active edge 5 tdr Data retention time t(CE) Time from CE going low to CE going high 100 ns ns 15 ns 67 ns SDA tf t(LOW) tr tsu(DAT) tf t(buf) tr th(STA) SCL th(STA) S tsu(STO) tsu(STA) th(DAT) t(HIGH) Sr P S Figure 4-1. Serial Interface Timing Diagram for F/S Mode 28 Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Sr Sr tf(DA) P tr(DA) SDA (HS) th(DAT) tsu(STA) tsu(STO) tsu(DAT) th(STA) SCL (HS) tf(CL1) tr(CL1) See note A. tr(CL1) tr(CL1) t(LOW) t(HIGH) t(LOW) See note A. t(HIGH) = MCS Current Source Pullup = R(P) Resistor Pullup A. The first rising edge of the SCL (HS) signal after the repeated START condition (Sr) and after each acknowledge bit. Figure 4-2. Serial Interface Timing Diagram For HS Mode SPI chip select tc(clk) tp(HIGH_ck) th(ce) tp(LOW_ck) tsu(ce) SPI clock enable tsu(si) th(si) SPI data input R/W Address Data Unused tdr 'RQ¶W FDUH SPI data output Figure 4-3. SPI Timing Diagram Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 29 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) 4.21 Typical Characteristics 60 50 40 30 60 50 40 30 20 20 VO = 0.7 V VO = 1.2 V 10 0 0 0.4 0.8 1.2 1.6 VI = 3.8 V 2 2.4 2.8 3.2 3.6 Load Current (mA) 4 4.4 4.8 0 ƒS = 2.2 MHz 1.2 1.6 2 2.4 Load Current (A) 2.8 3.2 3.6 4 D009 ƒS = 2.2 MHz Figure 4-5. SMPS Efficiency for 4-A Multi-Phase PWM Mode 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) 0.8 VI = 3.8 V 60 50 40 30 60 50 40 30 20 20 VO = 1.05 V VO = 1.2 V 10 VO = 1.05 V VO = 1.2 V 10 0 0 0 0.6 1.2 1.8 VI = 3.8 V 2.4 3 3.6 Load Current (A) 4.2 4.8 5.4 6 0 0.8 1.6 D008 ƒS = 2.2 MHz VI = 3.8 V Figure 4-6. SMPS Efficiency for 6-A Multi-Phase PWM Mode 100 100 90 90 80 80 70 70 60 50 40 30 VO VO VO VO VO 20 10 = = = = = 0.7 1.2 1.8 2.5 3.3 2.4 3.2 4 4.8 5.6 Load Current (A) 6.4 7.2 8 8.8 D007 ƒS = 2.2 MHz Figure 4-7. SMPS Efficiency for 9-A Multi-Phase PWM Mode Efficiency (%) Efficiency (%) 0.4 D010 Figure 4-4. SMPS Efficiency for Multi-Phase Eco-mode 60 50 40 30 V V V V V VO VO VO VO VO 20 10 0 = = = = = 1.05 V 1.2 V 1.8 V 2.5 V 3.3 V 0 0 0.4 0.8 1.2 1.6 VI = 3.8 V 2 2.4 2.8 3.2 3.6 Load Current (mA) 4 4.4 4.8 0 0.2 0.4 0.6 Load Current (A) VI = 3.8 V ƒS = 2.2 MHz D006 ƒS = 2.2 MHz Figure 4-8. SMPS Efficiency for 1-A Single-Phase Eco-mode 30 VO = 1.05 V VO = 1.2 V 10 0 0.8 1 D005 Figure 4-9. SMPS Efficiency for 1-A Single-Phase PWM Mode Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Typical Characteristics (continued) 60 50 40 30 VO VO VO VO VO 20 10 = = = = = 0.7 1.2 1.8 2.5 3.3 60 50 40 30 V V V V V 10 0 = = = = = 1.05 V 1.2 V 1.8 V 2.5 V 3.3 V 0 0 0.4 0.8 1.2 1.6 VI = 3.8 V 2 2.4 2.8 3.2 3.6 Load Current (mA) 4 4.4 4.8 0 0.2 0.4 0.6 D004 ƒS = 2.2 MHz VI = 3.8 V Figure 4-10. SMPS Efficiency for 2-A Single-Phase Eco-ode 100 100 90 90 80 80 70 70 60 50 40 30 VO VO VO VO VO 20 10 = = = = = 0.7 1.2 1.8 2.5 3.3 0.8 1 1.2 Load Current (A) 1.4 1.6 1.8 2 D003 ƒS = 2.2 MHz Figure 4-11. SMPS Efficiency for 2-A Single-Phase PWM Mode Efficiency (%) Efficiency (%) VO VO VO VO VO 20 60 50 40 30 V V V V V VO VO VO VO VO 20 10 0 = = = = = 1.05 V 1.2 V 1.8 V 2.5 V 3.3 V 0 0 0.4 0.8 1.2 1.6 VI = 3.8 V 2 2.4 2.8 3.2 3.6 Load Current (mA) 4 4.4 4.8 0 0.4 D002 ƒS = 2.2 MHz VI = 3.8 V Figure 4-12. SMPS Efficiency for 3-A Single-Phase Eco-mode 0.8 1.2 1.6 Load Set (A) 2 2.4 2.8 D001 ƒS = 2.2 MHz Figure 4-13. SMPS Efficiency for 3-A Single-Phase PWM Mode Specifications Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 31 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com 5 Detailed Description 5.1 Overview The TPS659037 device is a power-management integrated circuit (PMIC), available in a 169-pin, 0.8-mm pitch, 12-mm × 12-mm nFBGA package. The TPS659037 device provides seven configurable step-down converter rails, with the ability to combine power rails and supply up to 9 A of output current in multi-phase mode. The TPS659037 device has seven LDOs. The device also has a 12-bit GPADC with three external channels, eight configurable GPIOs, two I2C interface channels or one SPI channel, real-time clock module with calendar function, PLL for external clock sync and phase delay capability, and programmable power sequencer and control for supporting different processors and applications. The seven step-down converter rails are consisting of nine high frequency switch mode converters with integrated FETs. The step-down converter rails are capable of synchronizing to an external clock input and supports switching frequency between 1.7 MHz and 2.7 MHz. The SMPS12 and SMPS45 are dualphase step-down converters that can combine with the SMPS3 or SMPS7 respectively and become triplephase converters. In addition, the SMPS12, SMPS45, SMPS6, and SMPS8 support dynamic voltage scaling by a dedicated I2C interface for optimum power savings. All of the LDOs support a 0.9 to 3.3-V output with 50-mV step. The regulators are fully controllable by the I2C interface and can be supplied from either a system supply or a preregulated supply. All LDOs and step-down converters can be controlled by the SPI or I2C interface, or by power request signals. In addition, voltage scaling registers allow transitioning the SMPS to different voltages by SPI, I2C, or roof-and-floor control. The power-up and power-down controller is configurable and programmable through OTP. The TPS659037 device includes a 32-kHz RC oscillator to sequence all resources during power up and power down. In cases where a fast start-up is required, a 16-MHz crystal oscillator is also included to quickly generate a stable 32-kHz for the system. The TPS659037 device also includes an RTC module which provides date, time, calendar, and alarm capability, which is best used when a 16-MHz crystal or an external and high accuracy 32-kHz clock is present. The TPS659037 device also has eight configurable GPIOs with a multiplexed feature. Three of the GPIOs, together with the REGEN1 pin can be configured and used as enable signals for external resources, which can be included into the power-up and power-down sequence. The TPS659037 device also includes a general-purpose (GP) sigma-delta analog-to-digital converter (ADC) with three external input channels, which can be used as thermal or voltage and current monitors. CAUTION When operating the TPS659037 device using silicon revision 1.3 or earlier, without an external crystal, each SMPS regulating an output voltage greater than 1.8 V must be disabled before VCC is removed. Lowering VCC below the programmed VSYS_LO level while any SMPS is regulating an output voltage above 1.8 V may cause damage to the device. See Section 5.3.10 to identify the silicon version in the device. 32 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com LDOVANA LDOVRTC VPROG VBUS VIO_IN VIO_GND Test and program VCC internal supply Triple-Phases GPIO_6 SYSEN2 GPIO_7 VSYS_MON VBUS_SENSE VBUS_WKUP_UP SMPS5_GND Thermal shutdown Triple-Phases Hot die detection SMPS7 2A [Multi Or Stand-alone] EN VSEL CLK32KGO1V8 EN VSEL RAMP 16-MHz Oscillator Internal RC Oscillator RC 32 kHz OSC16MOUT OSC16MCAP Output Buffers EN VSEL RAMP 12-bit SDADC SMPS7_IN SMPS7_SW SMPS7_FDBK SMPS7_GND SMPS6_IN SMPS6 2A (DVS) SMPS6_SW SMPS6_FDBK SMPS6_GND SMPS8_IN SMPS8 1A (DVS) SMPS8_FDBK SMPS9 1A SMPS8_SW SMPS8_FDBK SMPS8_GND SMPS8_SW SMPS8_GND SMPS8_IN VSEL EN VSEL EN VBG Reference and bias LDOUSB 100 mA REFGND1 Grounds 2 LDO9_OUT VSEL LDO9_OUT Bypass LDO9 50 mA LDO9_IN LDO4_OUT LDO4 200 mA EN MUX VSEL EN VSEL EN LDO3 200 mA (LDO34_IN ) LDO2_OUT LDO2 300 mA LDO3_OUT VSEL EN EN VSEL (LDO12_IN ) LDOLN_OUT LDOLN_IN LDO1_OUT VSEL EN GPADC_IN0 GPADC_IN1 GPADC_IN2 GPADC_VREF LDOUSB_IN 1 LDOUSB_IN CLK32KGO SYNCDCDC GND_DIG OSC16MIN LDO_SUPPLY SMPS4_5_FDBK SMPS4_5_FDBK_GND RTC GPIO_5 LDO1 300 mA SMPS5_IN SMPS5_SW SMPS5 2A (DVS) [Master] EN VSEL RAMP POWERHOLD LDOLN 50 mA SMPS4_GND Dual-Phases WDT Thermal monitoring SMPS4_SW PBKG SYSEN1 ECO PWM DVS Switch ON and OFF VCC_SENSE Interrupt Handler (24 channels) GPIO_4 GPIO GPIO_3 SMPS3_GND SMPS4 2A (DVS) [Slave] Programmable power sequencer controller POR VBUSDET GPIO_2 SMPS3_FDBK SMPS4_IN VCC1 VCC1 VSYS_LO REGEN2 SMPS3_SW Registers GPIO_0 GPIO_1 SMPS3_IN SMPS3 3A [Multi Or Stand-alone] EN VSEL OTP controller OTP memory Control outputs Internal Interrupt events POWERGOOD SMPS2_GND JTAG RESET_OUT REGEN1 SMPS1_2_FDBK_GND TPS659037 DFT INT SMPS1_2_FDBK GND_ANA I2C2_SDA_SDO SMPS2_IN SMPS2_SW GND_ANA I2C2_SCL_SCE I C CNTL, I2C DVS, or SPI GND_ANA I2C1_SDA_SDI 2 SMPS1_GND SMPS2 3A (DVS) [Master] EN VSEL RAMP I2C1_SCL_CLK SMPS1_SW Dual-Phases GND_ANA ENABLE1 NSLEEP NRESWARM Power Management GND_ANA PWRON SMPS1_IN SMPS1 3A (DVS) [Slave] VPROG PWRDOWN TESTV Control inputs VCC_SENSE RESET_IN LDOVRTC_OUT PWRON VCC1 VCC1 BOOT0 BOOT1 SCC_SENSE2 Functional Block Diagram LDOVANA_OUT 5.2 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Copyright © 2016, Texas Instruments Incorporated Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 33 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 5.3 www.ti.com Feature Description 5.3.1 Power Management The TPS659037 device integrates an embedded power controller (EPC) that fully manages the state of the device during power transitions. According to four defined types of requests (ON, OFF, WAKE, and SLEEP), the EPC executes one of the five predefined power sequences (OFF2ACT, ACT2OFF, SLP2OFF, ACT2SLP, and SLP2ACT) to control the state of the device resources. Any resource can be included in any power sequence. When a resource is not controlled or configured through a power sequence, the resource remains in the default state of the resource (from OTP). Each resource is configured only through register bits. Therefore, a resource can be controlled statically by the user through the control interfaces (I2C or SPI) or controlled automatically by the EPC during power transitions (predefined sequences of registers accesses). The EPC is powered by an internal LDO that is automatically enabled when VSYS is available to the device. Ensuring that the VSYS pin (which is connected to VCC1, VCC_SENSE, SMPSx_In and LDOx_IN as suggested in Section 5.2) is the first supply available to the device is important to ensure proper operation of all the power resources provided by the TPS659037 device. Ensuring that the VSYS pin is stable prior to the VIO supply becoming available is important to ensure proper operation of the control interface and device IOs. 5.3.2 Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs) The power resources provided by the TPS659037 device includes inductor-based SMPSs and linear lowdropout voltage regulators (LDOs). These supply resources provide the required power to the external processor cores, external components, and to modules embedded in the device. Table 5-1 lists the power sources provided by the TPS659037 device. Table 5-1. Power Sources RESOURCE 34 TYPE VOLTAGE CURRENT COMMENTS SMPS1, SMPS2, and SMPS3 SMPS 0.5 to 1.65 V, 10-mV steps 1 to 3.3 V, 20-mV steps 9A Can be used as one triple-phase regulator (9 A) or one dual-phase (6 A) and single-phase (3 A) regulators SMPS4, SMPS5, and SMPS7 SMPS 0.5 to 1.65 V, 10-mV steps 1 to 3.3 V, 20-mV steps 6A Can be used as one triple-phase regulator (6 A) or one dual-phase (4 A) and single-phase (2 A) regulators SMPS6 SMPS 0.5 to 1.65 V, 10-mV steps 1 to 3.3 V, 20-mV steps 2 A or 3 A Can be configured as 2-A or 3-A SMPS through OTP programming SMPS8 SMPS 0.5 to 1.65 V, 10-mV steps 1 to 3.3 V, 20-mV steps 1A SMPS9 SMPS 0.5 to 1.65 V, 10-mV steps 1 to 3.3 V, 20-mV steps 1A LDO1 LDO 0.9 to 3.3 V, 50-mV steps 300 mA LDO2 LDO 0.9 to 3.3 V, 50-mV steps 300 mA LDO3 LDO 0.9 to 3.3 V, 50-mV steps 200 mA LDO4 LDO 0.9 to 3.3 V, 50-mV steps 200 mA LDO9 LDO 0.9 to 3.3 V, 50-mV steps 50 mA LDOLN LDO 0.9 to 3.3 V, 50-mV steps 50 mA LDOUSB LDO 0.9 to 3.3 V, 50-mV steps 100 mA Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com 5.3.2.1 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Step-Down Regulators The synchronous step-down converter used in the power-management core has high efficiency while enabling operation with small and cost-competitive external components. The SMPSx_IN supply pins of all the converters must be individually connected to the VSYS supply (VCC1 pin). Four of these configurable step-down converters are multi-phased to create up to 4-A and 6-A rails, while another converter can be combined to these two rails to create two rails up to 9 A and 6 A of output current. All of the step-down converters can synchronize to an external clock source between 1.7 MHz and 2.7 MHz, or an internal fall back clock at 2.2 MHz. The step-down converter supports two operating modes, which can be selected independently: Forced PWM mode: In forced PWM mode, the TPS659037 device avoids pulse skipping and allows easy filtering of the switch noise by external filter components. The drawback is the higher IDDQ at low output current levels. Eco-mode (lowest quiescent current mode): Each step-down converter can be individually controlled to enter a low quiescent current mode. In Eco-mode, the quiescent current is reduced and the output voltage is supervised by a comparator while most parts of the control are disabled to save power. The regulators should not be enabled under Eco-mode in order to ensure the stability of the output. Eco-mode should be enabled only when a converter has less than 5 mA of load current and VO can remain constant. In addition, Eco-mode should be disabled before a load transient step to let the converter respond in a timely manner to the excess current draw. To ensure proper operation of the converter while it is in Eco-mode, the output voltage level must be less then 70% of the input supply voltage level. If the VO of the converter is greater than 2.8 V, the TPS659037 device will monitor the supply voltage of the converter, and automatically shut down the converter if the input voltage falls below 4 V which prevents damage to the converter due to design limitation while the converter is in ECO mode. In addition to the operating modes, the following parameters can be selected for the regulators: Power good: The POWERGOOD signal high indicates that all SMPS outputs are within 10% (typical case) of the programmed value. The individual power good signal of a switching regulator is blanked when the regulator is disabled or when the regulator voltage transitions from one set point to another. Output discharge: Each switching regulator is equipped with an output discharge enable bit. When this bit is set to 1, the output of the regulator is discharged to ground with the equivalent of a 9-Ω resistor when the regulator is disabled. If the regulator enable bit is set, the discharge bit of the regulator is ignored. Output current monitoring: GPADC can monitor the SMPS output current. One SMPS at a time can be selected for measurement from the following: SMPS12, SMPS3, SMPS123, SMPS45, SMPS457, SMPS6 and SMPS7. Selection is controlled through the GPADC_SMPS_ILMONITOR_EN register. Step-down converter ENABLE: The step-down converter enable and disable is part of the flexible power-up and power-down state-machine. Each converter can be programmed so that it is powered up automatically to a preselected voltage in one of the time slots after a power-on condition occurs. Alternatively, each SMPS can be controlled by a dedicated pin. Pins NSLEEP and ENABLE1 can be mapped to any resource (LDOs, SMPS converter, 32-kHz clock output or GPIO) to enable or disable it. Each SMPS can also be enabled and disabled through I2C register access. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 35 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com 5.3.2.1.1 Sync Clock Functionality The TPS659037 device contains a SYNCDCDC input to sync DC-DCs with the external clock. In forced PWM mode, SMPSs are synchronized on an external input clock (SYNCDCDC) whereas in Ecomode or if the SYNCDCDC pin is grounded, the switching frequency is based on an internal RC oscillator. The clock generated from the internal RC oscillator can be output through GPIO5 to provide synchronization clock to external SMPSs. For PWM mode, a PLL is present to buffer the external input clock to create nine clock signals for the nine SMPSs with different phases. The sync clock dither specification parameters are based on a triangular dither pattern, but other patterns that comply with the minimum and maximum sync frequency range and the maximum dither slope can also be used. ¦(SYNC) M(DITHER) t(DITHER) ¦(SYNCmax) A(DITHER) ¦(SYNCmin) t Figure 5-1. Sync Clock Range and Dither The ollowing figure shows ƒ(SYNC), the frequency of SYNCDCDC input clock and ƒSW, the frequency of PLL output signal. When there is no clock present on SYNCDCDC pin, the PLL generates a clock with a frequency equal to ƒ(FALLBACK). If a clock is present on SYNCDCDC pin with a frequency between ƒ(SAT_LO) and ƒ(SAT_HI), then the PLL is synchronised on SYNCDCDC clock and generates a clock with frequency equal to ƒ(SYNC). If ƒ(SYNC) is higher than ƒ(SAT_HI), then the PLL generates a clock with a frequency equal to ƒ(SAT_HI). If ƒ(SYNC) is smaller than ƒ(SAT_LO), then the PLL generates a clock with a frequency equal to ƒ(SAT_LO). 36 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 ts ¦(SAT_HI) ¦(A) ¦SW ¦(FALLBACK) ¦(SAT_LO) ts ¦(SAT_HI) ¦(A) ¦(SYNC) ¦(SAT_LO) No Clock Figure 5-2. Sync Clock Saturation and Frequency Fallback 5.3.2.1.2 Output Voltage and Mode Selection The default output voltage and enabling of the regulator during startup sequence is defined by OTP bits. After start-up the software can change the output voltage with the RANGE and VSEL bits in the SMPSx_VOLTAGE register. The value 0x0 disables the SMPS (OFF). The operating mode of an SMPSx when the TPS659037 device is in ACTIVE mode can be selected in SMPSx_CTRL register with MODE_ACTIVE[1:0]. The operating mode of an SMPSx when the TPS659037 device is in SLEEP mode is controlled by MODE_SLEEP[1:0] bit depending on SMPS assignment to NSLEEP and ENABLE1, see Table 5-13. Soft-start slew rate is fixed (t(ramp)). The pulldown discharge resistance for OFF mode is enabled and disabled in the SMPS_PD_CTRL register. By default, discharge is enabled. SMPS behavior for warm reset (reload default values or keep current values) is defined by the SMPSx_CTRL.WR_S bit. 5.3.2.1.3 Current Monitoring and Short Circuit Detection The step-down converters include several other features. The SMPS sink current limitation is controlled with the SMPS_NEGATIVE_CURRENT_LIMIT_EN register. The limitation is enabled by default. Channel 11 of the GPADC can be used to monitor the output current of SMPS12, SMPS3, SMPS123, SMPS45, SMPS457, SMPS6, or SMPS7. Load current monitoring is enabled for a given SMPS in the SMPS_ILMONITOR_EN register. SMPS output power monitoring is intended to be used during the steady state of the output voltage, and is supported in PWM mode only. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 37 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Use Equation 1 as the basic equation for the SMPS output current result. I u GPADC code IL FS IOS 212 1 where • • IFS = IFS0 × K (K is the number of active SMPS phases) IOS = IOS0 × K (K is the number of active SMPS phases) Use Equation 2 to calculate the temperature compensated result. IFS u GPADC code IL IOS 12 ª2 1º u ª¬1 TC _ R0 u Temperature 25 º¼ ¬ ¼ (1) (2) For values of IFS0 and IOS0, see Section 4.12. The SMPS thermal monitoring is enabled (default) and disabled with the SMPS_THERMAL_EN register. When enabled, the SMPS thermal status is available in the SMPS_THERMAL_STATUS register. SMPS12 and SMPS3 have shared thermal protection, in effect, if SMPS12 triggers the thermal protection, then SMPS3 operating in stand-alone mode is disabled. There is no dedicated thermal protection in SMPS8 or SMPS9. Each SMPS has a detection for load current above ILIM, indicating overcurrent or shorted SMPS output. A register SMPS_SHORT_STATUS indicates any SMPS short condition. Depending on the interrupt short line mask bit register (INT2_MASK.SHORT), an interrupt is generated upon any shorted SMPS. If a short situation occurs on any enabled SMPSs, the corresponding short status bit is set in the SMPS_SHORT_STATUS register. A switch-off signal is then sent to the corresponding SMPS, and remains off until the corresponding bit in the SMPS_SHORT_STATUS register is cleared. This register is cleared on a read, or by issuing a POR. The SMPS_SHORT_STATUS register is cleared when read, or by issuing a POR. The same behavior applies to LDO shorts using the SDO_SHORT_STATUS registers. This same behavior applies to LDO shorts using the LDO_SHORT_STATUS registers. A short must occur on any enabled SMPS or LDO for at least 155 us to 185 us for the short detection to shut off the rail. During startup of the device, there is a 2 ms counter that masks any short-circuit shutdown. This counter starts when the device is enabled and the counter is reset when any SMPSx or LDOx rail becomes ACTIVE. When no rail has been enabled for 2 ms, the counter reaches its threshold and the short-circuit shutdown is no longer masked for the enabled SMPSs and LDOs. 5.3.2.1.4 POWERGOOD The external POWERGOOD pin indicates if the outputs of the SMPS are correct or not (Figure 5-3). Either voltage and current monitoring or a current monitoring only can be selected for POWERGOOD indication. This selection is common for all SMPSs in the SMPS_POWERGOOD_MASK2.POWERGOOD_TYPE_SELECT bit register. When both voltage and current are monitored, POWERGOOD signal active (polarity is programmable) indicates that all SMPS outputs are within certain percentage, VSMPSPG , of the programmed value and that load current is below ILIM. All POWERGOOD sources can be masked in the SMPS_POWERGOOD_MASK1 and SMPS_POWERGOOD_MASK2 registers. By default, only the SMPS12 rail (or SMPS123 rail if in triple phase) is monitored. When an SMPS is disabled, it should be masked to prevent it forcing POWERGOOD inactive. When SMPS voltage is transitioning from one target voltage to another due to DVS command, voltage monitoring is internally masked and POWERGOOD is not impacted. Including POWERGOOD in the GPADC result is possible for SMPS output current monitoring by setting SMPS_COMPMODE = 1. Only one SMPS can be monitored by the GPADC channel at the time. The POWERGOOD function can also be used for monitoring an external SMPS is at the correct output level and the load is lower than the current limit; indication is through the GPIO_7 pin. 38 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 All POWERGOOD sources can SMPS_POWERGOOD_MASK2 registers. be masked in SMPS_POWERGOOD_MASK1 and CAUTION The current monitor on multi-phase rails (such as SMPS12, SMPS123, or SMPS45) may cause POWERGOOD to change to a low level (with default polarity) when transitioning from multi-phase operation to single phase operation. TI recommends masking the multi-phase rails as a POWERGOOD source, using SMPS_POWERGOOD_MASK1, or debouncing the POWERGOOD signal if this POWERGOOD toggle is not desired in the application design. OVER_TEMP INT SMPS_SHORT_STATUS SMPS_THERMAL_STATUS INT2_MASK[6] ILIM SMPS12 POWERGOOD SMPS_POWERGOOD_MASK1[0] SMPS3 SMPS_POWERGOOD_MASK1[1] POWERGOOD SMPS_POWERGOOD_MASK1[7] External SMPS (through GPIO7) SMPS_POWERGOOD_MASK2[2] Figure 5-3. POWERGOOD Block Diagram 5.3.2.1.5 DVS-Capable Regulators The step-down converters SMPS12 or SMPS123, SMPS45 or SMPS457, SMPS6, and SMPS8 are DVScapable and have some additional parameters for control. The slew rate of the output voltage during a change in the voltage level is fixed at 2.5 mV/μs. The control for the two different voltage levels (ROOF and FLOOR) with the NSLEEP and ENABLE1 signals is available. The control bits for the output voltage slew rate control the following additional control bits. When the ROOF_FLOOR control is not used, two different voltage levels can be selected with the CMD bit in the SMPSx_FORCE register. • The output voltage slew rate for achieving new output voltage value is fixed at 2.5 mV/μs. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 39 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 • www.ti.com The NSLEEP and ENABLE1 pins can be used for roof-floor control of SMPS. For roof-floor operation sets the SMPSx_CTRL.ROOF_FLOOR_EN register, and assign SMPS to NSLEEP and ENABLE1 in the NSLEEP_SMPS_ASSIGN and ENABLE1_SMPS_ASSIGN registers. When the controlling pin is active, the SMPS output value is defined by the SMPSx_VOLTAGE register. When the controlling pin is not active, the SMPS output value is defined by the SMPSx_FORCE register. Set the second value for the output voltage with the SMPSx_FORCE.VSEL register. A value of 0x0 disables the SMPS (OFF). Select which register, SMPSx_VOLTAGE or SMPSx_FORCE, to use with the SMPSx_FORCE.CMD bit. The default is the voltage setting of SMPSx_VOLTAGE. For the CMD bit to work, ensure that SMPSx_CTRL.ROOF_FLOOR_EN = 0. • • Figure 5-5 and Figure 5-4 show the SMPS controls for DVS. SMPSx_VOLTAGE.VSEL (active mode) SMPSx_FORCE.VSEL (sleep mode) SMPSx_VOLTAGE.VSEL SMPSx_OUT Discharge control (pulldown) SMPS_PD_CTRL.SMPSx (disabled or enabled) t(start) 2 I C VSEL[6:0] (voltage selection): OFF, 0.5 to 1.65 V in 10-mV steps if SMPSx_VOLTAGE.RANGE = 1 1 to 3.3 V in 20-mV steps if SMPSx_VOLTAGE.RANGE = 1 2 I C: Control through access to SMPSx_VOLTAGE, SMPSx_FORCE registers Figure 5-4. DVS - SMPS Controls Voltage Control Through I2C (SMPSx_CTRL.ROOF_FLOOR_EN = 0) SMPSx_VOLTAGE.VSEL (active mode) SMPSx_FORCE.VSEL (sleep mode) SMPSx_VOLTAGE.VSEL SMPSx_OUT Discharge control (pulldown) SMPS_PD_CTRL.SMPSx (disabled or enabled) t(start) EN (1) EN: Control through NSLEEP or ENABLE1 (1) See Table 5-13. Figure 5-5. DVS - SMPS Controls Voltage Control Through External Pin (SMPSx_CTRL.ROOF_FLOOR_EN = 1) 5.3.2.1.6 Non DVS-Capable Regulators SMPS3 and SMPS7, when they are not part of the multi-phase configuration, will work as single phase step down converters. Together with SMPS9, these are non-DVS-Capable regulators. The output voltage slew rate is not controlled internally, and the converter will achieve the new output voltage in JUMP mode. When changes to the output voltage are necessary while SMPS3, SMPS7, or SMPS9 are configured as single phase converters, programming the changes to the output voltages at a rate which is slower than 2.5 mV/μs is recommended to avoid voltage overshoot or undershoot. 40 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 5.3.2.1.7 Step-Down Converters SMPS12 and SMPS123 The step-down converters SMPS1, SMPS2, and SMPS3 can be used in two different configurations: • SMPS12 in dual-phase configuration supporting 6-A load current and SMPS3 in single-phase configuration supporting 3-A load current • SMPS123 in triple-phase configuration supporting 9-A load current SMPS1 and SMPS2 cannot interleaved synchronous buck triple-phase configuration the sharing operate 120° out of operation. be used as separate converters. In dual-phase configuration the two regulator phases with built-in current sharing operate in opposite phase. In three interleaved synchronous buck regulator phases with built-in current phase. For light loads, the converter automatically changes to 1-phase Figure 5-6 shows the connections for dual-phase and triple-phase configurations. a. Dual-Phase SMPS and Stand-Alone SMPS b. Triple Phase SMPS C10 (C23) C10 (C23) VSYS VSYS SMPS1_IN (SMPS5_IN) SMPS1_IN (SMPS5_IN) SMPS1_SW SMPS1_SW L2 (L7) (SMPS5_SW) SMPS1 (SMPS5) [Slave] (SMPS5_SW) SMPS1 (SMPS5) SMPS1_GND (SMPS5_GND) C11, C13 (C20, C24) Vapps1 [Slave] L2 (L7) SMPS1_GND (SMPS5_GND) C12 (C19) C12 (C19) VSYS VSYS SMPS2_IN (SMPS4_IN) SMPS2_IN (SMPS4_IN) SMPS2_SW SMPS2_SW L3 (L6) (SMPS4_SW) SMPS2 (SMPS4) C11, C13, C16 (C20, C24, C28) Vapps1 L3 (L6) (SMPS4_SW) SMPS2 (SMPS4) SMPS2_GND (SMPS4_GND) SMPS2_GND (SMPS4_GND) [Master] [Master] SMPS1_2_FDBK (SMPS4_5_FDBK) SMPS1_2_FDBK (SMPS4_5_FDBK) SMPS1_2_FDBK_GND (SMPS4_5_FDBK_GND) SMPS1_2_FDBK_GND (SMPS4_5_FDBK_GND) C14 (C27) C14 (C27) VSYS VSYS SMPS3_IN (SMPS7_IN) SMPS3_IN (SMPS7_IN) Vapps2 C16 (C28) SMPS3_SW SMPS3_SW L4 (L9) SMPS3 (SMPS7) (SMPS7_SW) SMPS3 (SMPS7) SMPS3_GND (SMPS7_GND) [Standalone] L4 (L9) (SMPS7_SW) SMPS3_GND (SMPS7_GND) [Multi] SMPS3_FDBK (SMPS7_FDBK) SMPS3_FDBK (SMPS7_FDBK) (floating) Figure 5-6. Multi-Phase SMPS Connectivity To use the SMPS123 or SMPS12 and SMPS3 in the system: • OTP defines dual-phase (SMPS12) operation, single-phase (SMPS3) operation, or triple-phase (SMPS123) operation. If SMPS123 mode is selected, the SMPS12 registers control SMPS123. • By default SMPS123 and SMPS12 operate in multiphase mode for higher load currents and switch automatically to single-phase mode for low load currents. Forcing multiphase operation or single-phase operation by setting the SMPS_CTRL.SMPS123_PHASE_CTRL[1:0] bits when the SMPS123 or SMPS12 are loaded is also possible. Under no-load condition, do not force the multiphase operation, as this causes the SMPS to exhibit instability. 5.3.2.1.8 Step-Down Converter SMPS45 and SMPS457 The step-down converters SMPS4, SMPS5 and SMPS7 can be used in two different configurations: • SMPS45 in dual-phase configuration supporting 4-A load current and SMPS7 in single-phase configuration supporting 2-A load current • SMPS457 in triple-phase configuration supporting 6-A load current Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 41 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com SMPS4 and SMPS5 cannot be used as separate converters. In dual-phase configuration the two interleaved synchronous buck regulator phases with built-in current sharing operate in opposite phase. In triple-phase configuration the three interleaved synchronous buck regulator phases with built-in current sharing operate 120 degrees out of phase. For light loads, the converter automatically changes to 1-phase operation. To use SMPS457 or SMPS45 and SMPS7 in the system: • OTP defines dual-phase (SMPS45) operation, single-phase (SMPS7) operation, or triple-phase (SMPS457) operation. If SMPS457 mode is selected, the SMPS45 registers control SMPS457. • By default SMPS457 and SMPS45 operate in multiphase mode for higher load currents and switch automatically to single-phase mode for low load currents. Forcing multiphase operation or single-phase operation by setting the SMPS_CTRL.SMPS457_PHASE_CTRL[1:0] bits when the SMPS457 or SMPS45 are loaded is also possible. Under no-load condition, do not force the multiphase operation, as this causes the SMPS to exhibit instability. 5.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9 The SMPS3 is a buck converter supporting up to a 3-A load current, SMPS6 and SMPS7 are buck converters supporting up to a 2-A load current. The SMPS6 can support up to 3A if programmed in OTP for boosted current mode. Using extended current mode increases SMPS6 current limits so to protect external coil from damage, coil should be selected according to the higher current rating. SMPS8 and SMPS9 are buck converters supporting up to a 1-A load current. SMPS6 and SMPS8 are DVS-capable. 5.3.2.2 LDOs – Low Dropout Regulators All LDOs are integrated so that they can be connected to a system supply, to an external buck boost SMPS, or to another preregulated voltage source. The output voltages of all LDOs can be selected, regardless of the LDO input voltage level VI. There is no hardware protection to prevent software from selecting an improper output voltage if the VI minimum level is lower than TDCOV (total DC output voltage) + DV (dropout voltage). In such conditions, the output voltage would be lower and nearly equal to the input supply. The regulator output voltage cannot be modified on the fly from one (0.9–2.1 V) voltage range to the other (2.2–3.3 V) voltage range and vice versa. The regulator must be restarted in these cases. If an LDO is not needed, the external components can be unplaced. The TPS659037 device is not damaged by such configuration, and the other functions do not depend on the unused LDOs and work properly. 5.3.2.2.1 LDOVANA The VANA voltage regulator is dedicated to supply the analog functions of the TPS659037 device, such as the GPADC and other analog circuits. VANA is automatically enabled and disabled when it is needed. The automatic control optimizes the overall SLEEP state current consumption. 5.3.2.2.2 LDOVRTC The VRTC regulator supplies always-on functions, such as real-time clock (RTC) and wake-up functions. This power resource is active as soon as a valid energy source is present. This resource has two modes: • Normal mode is able to supply all digital parts of the TPS659037 device • Backup mode is able to supply only always-on parts 42 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 VRTC supplies the digital part of the TPS659037 device. In the BACKUP state, the VRTC regulator is in low-power mode and the digital activity is reduced to the RTC parts only and maintained in retention registers of the backup domain. The rest of the digital is under reset and the clocks are gated. In the OFF state, the turn-on events and detection mechanism are also added to the previous RTC current load. In BACKUP and OFF states, the external load on VRTC should not exceed 0.5 mA. In the ACTIVE state, VRTC switches automatically into ACTIVE mode. The reset is released and the clocks are available. In SLEEP state, VRTC is kept active. The reset is released and only the 32-kHz clock is available. To reduce power consumption, low-power mode can be selected by software. NOTE For silicon revision 1.3 or earlier, if VCC is discharged rapidly and then resupplied, a POR may not be reliably generated. In this case a pulldown resistor can be added on the LDOVRTC output. See Section 5.4.11 for details. See Section 5.3.10 to identify the silicon version in the device. 5.3.2.2.3 LDO Bypass (LDO9) LDO9 has a bypass capability to connect the input voltage to the output. It allows switching between 1.8 V and the preregulated supply. 5.3.2.2.4 LDOUSB This LDOUSB has two inputs, LDOUSB_IN1 and LDOUSB_IN2. The input selection occurs by the LDOUSB_ON_VBUS_VSYS bit in the LDO_CTRL register. 5.3.2.2.5 Other LDOs All the other LDOs have the same output voltage capability, from 0.9 to 3.3 V in 50-mV steps. All the LDO inputs can be independently connected into system voltage or into preregulated supply. The preregulated supply can be higher or lower than the system supply. 5.3.3 Long-Press Key Detection The TPS659037 device can detect a long press on the PWRON pin. Upon detection, the device generates a LONG_PRESS_KEY interrupt and then switches the system off. The key-press duration is configured through the LONG_PRESS_KEY.LPK_TIME bits. The interrupt clear has two behaviors based on the configuration of the LONG_PRESS_KEY .LPK_INT_CLR bit: • LONG_PRESS_KEY.LPK_INT_CLR = 0: If PWRON remains low and the interrupt is cleared, the switch-off sequence is cancelled. If PWRON remains low and the interrupt is not cleared, the switch-off sequence is executed. • LONG_PRESS_KEY.LPK_INT_CLR = 1: Switch off cannot be cancelled as long as PWRON remains low (default). 5.3.4 RTC 5.3.4.1 General Description The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions. The main functions of the RTC block are: • Time information (seconds, minutes, hours) in binary-coded decimal (BCD) code • Calendar information (day, month, year, day of the week) in BCD code up to year 2099 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 43 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 • • www.ti.com Programmable interrupts generation; the RTC can generate two interrupts: – Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods), which can be masked during the SLEEP state to prevent the host processor from waking up – Alarm interrupt at a precise time of the day (alarm function) Oscillator frequency calibration and time correction with 1/32768 resolution Figure 5-7 shows the RTC block diagram. 32-kHz clock input 32-kHz counter Seconds Week days Frequency compensation Hours Minutes Days Interrupt Control Months Alarm Years INT_ALARM INT_TIMER Figure 5-7. RTC Block Diagram 5.3.4.2 Time Calendar Registers All the time and calendar information is available in the time calendar (TC) dedicated registers: SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and YEARS_REG. The TC register values are written in BCD code. • Year data ranges from 00 to 99. – Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on) – Common Year = Other years • Month data ranges from 01 to 12. • Day value ranges: – 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12 – 1 to 30 when months are 4, 6, 9, 11 – 1 to 29 when month is 2 and year is a leap year – 1 to 28 when month is 2 and year is a common year • Week value ranges from 0 to 6. • Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode. • Minutes value ranges from 0 to 59. • Seconds value ranges from 0 to 59. Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are listed in Table 5-2: 44 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Table 5-2. RTC Time Calendar Registers Example REGISTER CONTENT SECONDS_REG 0x36 MINTURES_REG 0x54 HOURS_REG 0x10 DAYS_REG 0x05 MONTHS_REG 0x09 YEARS_REG 0x08 The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is performed. Example: • If current time is 10H59M45S, round operation changes time to 11H00M00S • If current time is 10H59M29S, round operation changes time to 10H59M00S 5.3.4.2.1 TC Registers Read Access TC registers read accesses can be done in two ways: • A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and the real time because the RTC keeps running because some of the registers can toggle in between register accesses. Software must manage the register change during the reading. • Read access to shadowed TC registers. These registers are at the same addresses as the normal TC registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit is set, the content of all TC registers is transferred into shadow registers so they represent a coherent timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of register access. 5.3.4.2.2 TC Registers Write Access TC registers write accesses can be done in two ways: • Direct write into the TC registers. In this case, because the RTC keeps running, there can be a discrepancy between the final time written and the target time to be written because some of the registers can toggle in between register accesses. Software must manage the register change during the writing. • Write access while RTC is stopped. Software can stop the RTC by the clearing STOP_RTC bit of the control register and checking the RUN bit of the status to be sure that RTC is frozen. It then updates the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final written values are aligned with the targeted values. 5.3.4.3 RTC Alarm RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG, ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm time or date to the corresponding generated IT_ALARM interrupts. This interrupt is enabled through the IT_ALARM bit in the RTC_INTERRUPTS_REG register. These register values are written in BCD code, with the same data range as described for the TC registers (see Section 5.3.4.2). 5.3.4.4 RTC Interrupts The RTC supports two types of interrupts: • IT_ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM registers is reached. This interrupt is enable by the IT_ALARM bit in the RTC_INTERRUPT_REG register. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 45 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 • 5.3.4.5 www.ti.com IT_TIMER interrupt. This interrupt is generated when the periodic time set in the EVERY bits of the RTC_INTERRUPT_REG register is reached. This interrupt is enabled by the IT_TIMER bit in the RTC_INTERRUPT_REG register. During the SLEEP state, the IT_TIMER interrupt can either be masked (stored and generated as soon as the TPS659037 device exists the SLEEP state) or unmasked using the IT_SLEEP_MASK_EN bit of the RTC_INTERRUPT_REG register. RTC 32-kHz Oscillator Drift Compensation The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for inaccuracy of the 32-kHz clock output from the 16.384-MHz crystal oscillator. To compensate for inaccuracy, software must perform an external calibration of the oscillator frequency, calculate the compensation needed versus one time hour period, and load the compensation registers with the compensation value. any any drift drift The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register. The process happens after the first second of each hour. The time between second 1 to second 2 (T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. These two registers form a 16-bit, 2s complement value COMP_REG (from –32767 to 32767) that is subtracted from the 32-kHz counter as shown in Equation 3 to adjust the length of T_ADJ: § 32768 COMP_REG · ¨ ¸ 32768 © ¹ (3) Therefore, adjusting the compensation with a 1/32768-second time unit accuracy per hour and up to 1 s per hour is possible. Software must ensure that these registers are updated before each compensation process (there is no hardware protection). For example, software can load the compensation value into these registers after each hour event, during second 0 to second 1, just before the compensation period, happening from second 1 to second 2. Preloading the internal 32-kHz counter with the content of the RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers possible when setting the SET_32_COUNTER bit in the RTC_CTRL_REG register. This setting must occur when the RTC is stopped. Figure 5-8 shows the RTC compensation scheduling. SECONDS_REG 4 3 HOURS_REG 0 1 ... RTC_COMP_xxx_REG 59 0 1 ... 58 59 0 1 58 6 ... 3 HOURS_REG SECONDS_REG 58 5 58 59 0 1 ... 58 59 4 0 59 New COMP Value 1 2 3 COMP Value Frozen Register Updated Compensation Event Figure 5-8. RTC Compensation Scheduling 46 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com 5.3.5 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 GPADC – 12-Bit Sigma-Delta ADC The GPADC consists of a 12-bit sigma-delta ADC combined with an analog input multiplexer. The GPADC allows the host processor to monitor a variety of analog signals using analog-to-digital conversion on the input source. After the conversion completes, an interrupt is generated for the host processor and it can read the result of the conversion through the I2C interface. The GPADC on this PMIC supports 16 analog inputs. However only a total of 9 inputs are available for the application use. Three of these inputs are available on external pins, and the remaining six are dedicated to internal resource monitoring. One of the three external inputs is associated with a current source allowing measurements of resistive elements (thermal sensor). To improve the measurement accuracy, the reference voltages GPADC_VREF can be used with an external resistor for the NTC resistor measurement. The reference voltage GPADC_VREF is always present when the GPADC is enabled. GPADC_IN0 is associated with three selectable current sources. The selectable current levels are 5, 15, and 20 μA. GPADC_IN1 is intended to measure temperature with an NTC sensor connected to ground. Two resistors, one in parallel with the NTC resistor and the other one between GPADC_IN1 and GPADC_VREF, can be used to modify the exponential function of the NTC resistor. Figure 5-9 shows the block diagram of the GPADC. ADC voltage reference GPADC_VREF GPADC_IN0 GPADC_IN1 Software conversion result GPADC_IN2 Input Scalar 12-bit sigma delta ADC AUTO conversion result AUTO conversion result Internal Channels (Supply Voltage, DCDC Current, and Die Temperature Monitoring) AUTO conversion request ADC control Software conversion request Interrupt Figure 5-9. Block Diagram of the GPADC For all the measurements performed by the monitoring GPADC, voltage dividers, current to voltage converters, and current source are integrated in the TPS659037 device to scale the signal to be measured to the GPADC input range. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 47 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com The conversion requests are initiated by the host processor either by software through the I2C. This mode is useful when real-time conversion is required. Two kinds of conversion requests are available with the following priority: 1. Asynchronous conversion request (SW) 2. Periodic conversion (AUTO) The EXTEND_DELAY bit in the GPADC_RT_CTRL register can extend by 400 μs the delay from the channel selection or triggering to the sampling. Use Equation 4 to convert from the GPADC code to the internal die temperature using GPADC channels 12 and 13. § ª GPADC Code º · ¨« » u 1.25 ¸ 0.753 V 12 2 ¬ ¼ ¹ Die Temperature (qC) © 2.64 mV (4) Table 5-3. GPADC Channel Assignments TYPE INPUT VOLTAGE FULL RANGE (1) INPUT VOLTAGE PERFORMANCE RANGE (2) SCALER 0 (GPADC_IN0) External (3) 0 to 1.25 V 0.01 to 1.215 V No Resistor value or general purpose. Select source current 0, 5, 15, or 20 μA 1 (GPADC_IN1) External (3) 0 to 1.25 V 0.01 to 1.215 V No Platform temperature, NTC resistor value and general purpose 2 (GPADC_IN2) External (3) 0 to 2.5 V 0.02 to 2.43 V 2 Audio accessory or general purpose 7 (VCC_SENSE) Internal 2.5 to 5 V when HIGH_VCC_SENSE = 0 2.3 V to (VCC1–1 V) when HIGH_VCC_SENSE = 1 2.5 to 4.86 V when HIGH_VCC_SENSE = 0 2.3 V to (VCC1–1 V) when HIGH_VCC_SENSE = 1 4 System supply voltage (VCC_SENSE) 10 (VBUS) Internal 0 to 6.875V 0.055 to 5.25 V 5.5 VBUS Voltage 11 Internal 0 to 1.25 V No DC-DC current probe 12 Internal 0 to 1.25 V 0 to 1.215 V No PMIC internal die temperature 13 Internal 0 to 1.25 V 0 to 1.215 V No PMIC internal die temperature 15 Internal 0 to VCC1 V 0.055 to VCC1 V 5 CHANNEL (1) (2) (3) OPERATION Test network The minimum and maximum voltage full range corresponds to typical minimum and maximum output codes (0 and 4095). The performance voltage is a range where gain error drift, offset drift, INL and DNL parameters are specified. If VANA LDO is OFF, maximum current to draw from GPADC_INx is 1 mA for reliability. For current higher than 1 mA, VANA must be set to SLEEP or ACTIVE mode. 5.3.5.1 Asynchronous Conversion Request (SW) Software can also request conversion asynchronously. This conversion is not critical in terms of start-ofconversion positioning. Software must select the channel to be converted, and then requests the conversion with the GPADC_SW_SELECT register. An INT interrupt is generated when the conversion result is ready, and the result is stored in the GPADC_SW_CONV0_LSB and GPADC_SW_CONV0_MSB registers. CAUTION A defect in the digital controller of TPS659037 device may cause an unreliable result from the first asynchronous conversion request after the device exit from a warm reset. TI recommends that user rely on subsequent requests to obtain accurate result from the asynchronous conversion after a device warm reset. In addition, a cold reset event which happens during a GPADC conversion will cause the GPADC controller to lock up. A software workaround for these issues are described in detail in the Guide to Using the GPADC in TPS65903x and TPS6591x Devices. 48 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com 5.3.5.2 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Periodic Conversion Request (AUTO) Software can enable periodic conversions to compare one or two channels with a predefined threshold level. Software must select one or two channels with the GPADC_AUTO_SELECT register and thresholds and polarity with the GPADC_THRES_CONV0_LSB, GPADC_THRES_CONV0_MSB, GPADC_THRES_CONV1_LSB, and GPADC_THRES_CONV1_MSB registers. In addition, software must select the conversion interval with the GPADC_AUTO_CTRL register and enable the periodic conversion with the AUTO_CONV0_EN and AUTO_CONV1_EN bits. There is no need to enable the GPADC separately. The control logic enables and disables the GPADC automatically to save power. When AUTO mode is the only conversion enabled, do not use the AUTO_CONV0_EN and AUTO_CONV1_EN bits to disabled the conversion. Instead, force the state machine of the GPADC on by setting the GPADC_CTRL1. GPADC_FORCE bit = 1, then shutdown the GPADC AUTO conversion using GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0. Wait 100 µs before disabling the GPADC state machine by setting GPADC_CTRL1. GPADC_FORCE bit = 0. The latest conversion result is always stored in the GPADC_AUTO_CONV0_LSB, GPADC_AUTO_CONV0_MSB, GPADC_AUTO_CONV1_LSB, and GPADC_AUTO_CONV1_MSB registers. All selected channels are queued and converted from channel 0 to 7. The first (lower) converted channel results is placed in the GPADC_AUTO_CONV0 register and the second one is placed in the GPADC_AUTO_CONV1 register. Therefore, TI recommends putting the lower channel to convert in AUTO_CONV0_SEL and the higher channel to convert in AUTO_CONV1_SEL. If the conversion result triggers the threshold level, an INT interrupt is generated and the conversion result is stored. If the interrupt is not cleared or the results are not read before another auto-conversion is completed, then the registers store only the latest results, discarding the previous ones. The auto conversion is never stopped by an uncleared interrupt or unread registers. Programming the triggering of the threshold level can also generate shutdown. This is available for CONV0 and CONV1 channels independently and is enabled with the SHUTDOWN bits in the GPADC_AUTO_CTRL register. During SLEEP and OFF modes, only channels from 0 to 10 can be converted. For channels 12 and 13, conversion is possible in sleep if thermal sensor is not disabled. 5.3.5.3 Calibration The GPADC channels are calibrated in the production line using a two-point calibration method. The channels are measured with two known values (X1 and X2) and the difference (D1 and D2) to the ideal values (Y1 and Y2) are stored in OTP memory. The principle of the calibration is shown in Figure 5-10. D2 = Y2 ± Y2 Ideal curve Measured curve Y1 D1 = Y1 ± X1 Offset Ideal code X1 X2 Calibration points Measured points Figure 5-10. ADC Calibration Scheme Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 49 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Some of the GPADC channels can use the same calibration data and the corrected result can be calculated using the equations: § (D2 D1) · k 1 ¨ ¸ © (X2 X1) ¹ Gain: (5) b D1 k 1 u X1 Offset: (6) If the measured code is a, the corrected code a' is: a b a' k (7) Table 5-4 lists the parameters X1 and X2, and the register of D1 and D2 required in the calculation for all the channels. Table 5-4. GPADC Calibration Parameters X1 X2 D1 D2 0,1 CHANNEL 2064 (0.63 V) 3112 (0.95 V) GPADC_TRIM1 GPADC_TRIM2 2 2064 (1.26 V) 3112 (1.9 V) GPADC_TRIM3 GPADC_TRIM4 7 2064 (2.52 V) 3112 (3.8 V) GPADC_TRIM7 GPADC_TRIM8 5.3.6 COMMENTS Channel 1 trimming is used General-Purpose I/Os (GPIO Pins) The TPS659037 device integrates eight configurable general-purpose I/Os that are multiplexed with alternative features as described in Table 5-5. Table 5-5. General Purpose I/Os Multiplexed Functions PIN PRIMARY FUNCTION SECONDARY FUNCTION GPIO_1 General-purpose I/O Output: VBUSDET (VBUS detection) GPIO_2 General-purpose I/O Output: REGEN2 GPIO_4 General-purpose I/O Output: SYSEN1 (external system enable) GPIO_5 General-purpose I/O Output: CLK32KGO1V8 (32-kHz digital-fated output clock in VRTC domain) or SYNCCLKOUT (Fallback synchronization clock for SMPS, 2.2MHz) GPIO_6 General-purpose I/O Output: SYSEN2 (external system enable) GPIO_7 General-purpose I/O Input: POWERHOLD For GPIO characteristics, refer to: • Pin description (see Section 3) • Electrical characteristics (see Section 4.16, and Section 4.17) • Pullup and pulldown characteristics (see Section 4.18) Each GPIO event can generate an interrupt on either rising and/or falling edge and each line is individually maskable (as described in Section 5.3.8) All GPIOs can be used as wake-up events. NOTE GPIO_4 and GPIO_6 are in the VIO domain and need the I/O supply to be available. When configured in OTP as SYSEN1 and SYSEN2, GPIO_4 and GPIO_6 can be programmed to be part of power-up sequence. Selection between primary and secondary functions is controlled through the registers PRIMARY_SECONDARY_PAD1 and PRIMARY_SECONDARY_PAD2. When configured as primary functions, all GPIOs are controlled through the following set of registers: 50 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com • • • • • • • • • SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 GPIO_DAT_DIR: Configure each GPIO direction individually (Read or Write) GPIO_DATA_IN: Data line-in when configured as an input (Read Only) GPIO_DATA_OUT: Data line-out when configured as an output (Read or Write) GPIO_DEBOUNCE_EN: Enable each GPIO debouncing individually (Read or Write) GPIO_CTRL: Global GPIO control to enable or disable all GPIOs (Read or Write) GPIO_CLEAR_DATA_OUT: Clear each GPIO data out individually (Write Only) GPIO_SET_DATA_OUT: Set each GPIO data out individually (Write Only) PU_PD_GPIO_CTRL1, PU_PD_GPIO_CTRL2: Configure each line pull up and pull down (Read or Write) OD_OUTPUT_GPIO_CTRL: Enable individual open-drain output (Read or Write) When configured as secondary functions, none of the GPIO control registers (see Table 5-5) affect GPIO lines. Line configuration (pullup, pulldown, open-drain) for secondary functions is held in a separate register set, as well as specific function settings. 5.3.6.1 REGEN Output Dedicated REGEN signal REGEN1 can be programmed to be part of power sequences to enable external devices like external SMPS. The REGEN2 signal is MUXed in GPIO_2, and when REGEN2 mode is selected it can also be programmed to be part of power sequences. All REGEN signals are at VSYS level. 5.3.7 Thermal Monitoring The TPS659037 device includes several thermal monitoring functions: • Thermal protection module internal to the TPS659037 device, placed close to the SMPS and LDO modules • Platform temperature monitoring with an external NTC resistor • Platform temperature monitoring with an external diode The TPS659037 device integrates two thermal detection modules to monitor the temperature of the die. These modules are placed on opposite sides of the chip and close to the LDO and SMPS modules. Overtemperature at either module generates a warning to the system; if the temperature continues to rise, the TPS659037 device shuts down before damage to the die can occur. Thus, two protection levels are available: • A hot-die (HD) function sends an interrupt to software. Software is expected to close any noncritical running tasks to reduce power. • A thermal shutdown (TS) function immediately begins the TPS659037 device switch-off. By default, thermal protection is always enabled except in the BACKUP or OFF state. Disabling thermal protection in SLEEP mode for minimum power consumption is possible. To use thermal monitoring in the system: • Set the value for the HD temperature threshold with the OSC_THERM_CTRL.THERM_HD_SEL[1:0] register. • TS can be disabled in SLEEP mode by setting the THERM_OFF_IN_SLEEP bit to 1 in the OSC_THERM_CTRL register. • During operation, if the die temperature increases above HD_THR_SEL, an interrupt (INT1.HOTDIE) is sent to the host processor. Immediate action to reduce the TPS659037 device power dissipation must be taken by shutting down some function. • If the die temperature of the TPS659037 device rises further (above 148°C) an immediate shutdown occurs. A TS event indication is written to the status register, INT1_STATUS_HOTDIE. The system cannot restart until the temperature falls below HD_THR_SEL. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 51 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 5.3.7.1 www.ti.com Hot-Die Function (HD) The HD detector monitors the temperature of the die and provides a warning to the host processor through the interrupt system when temperature reaches a critical value. The threshold value must be set below the thermal shutdown threshold. Hysteresis is added to the HD detection to avoid the generation of multiple interrupts. The integrated HD function provides the host PM software with an early warning overtemperature condition. This monitoring system is connected to the interrupt controller and can send an interrupt when the temperature is higher than the programmed threshold. The TPS659037 device allows the programming of four junction-temperature thresholds to increase the flexibility of the system: in nominal conditions, the threshold triggering of the interrupt can be set from 117°C to 130°C. The HD hysteresis is 10°C in typical conditions. When an interrupt is triggered by the power-management software, immediate action must be taken to reduce the amount of power drawn from the TPS659037 device (for example, noncritical applications must be closed). 5.3.7.2 Thermal Shutdown (TS) The TS detector monitors the temperature on the die. If the junction reaches a temperature at which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status register. The system cannot be restarted until the die temperature falls below the HD threshold. 5.3.7.3 Temperature Monitoring With External NTC Resistor or Diode The GPADC_IN1 channel can be used to measure a temperature with an external NTC resistor. External pullup and pulldown resistors can be connected to the input to linearize the characteristics of the NTC resistor. The temperature limits are set by external resistors. 5.3.8 Interrupts Table 5-6 lists the TPS659037 device interrupts. These interrupts are split into four register groups (INT1, INT2, INT3, INT4) and each group has three associated control registers: • INTx_STATUS: Reflects which interrupt source has triggered an interrupt event • INTx_MASK: Used to mask any source of interrupt, to avoid generating an interrupt on a specified source • INTx_LINE_STATE: Reflects the real-time state of each line associated to each source of interrupt The INT4 register group has two additional registers, INT4_EDGE_DETECT1 and INT4_EDGE_DETECT2, to independently configure rising and falling edge detection. All interrupts are logically combined on a single output line INT (default active low). This line is used as an external interrupt line to warn the host processor of any interrupt event that has occurred within the TPS659037 device. The host processor has to read the interrupt status registers (INTx_STATUS) through the control interface (I2C or SPI) to identify the interrupt sources. Any interrupt source can be masked by programming the corresponding mask register (INTx_MASK). When an interrupt is masked, its associated event detection mechanism is disabled. Therefore the corresponding STATUS bit is not updated and the INT line is not triggered if the masked event occurs. Any event happening while its corresponding interrupt is masked is lost. If an interrupt is masked after it has been triggered (event has occurred and has not yet been cleared), then the STATUS bit reflects the event until it is cleared and it does not trigger again if a new event occurs (because it is now masked). 52 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Because some interrupts are sources of ON requests (see Table 5-6), source masking can be used to mask a specific device switch-on event. Because an active interrupt line INT is treated as an ON request, any interrupt not masked must be cleared to allow the execution of a SLEEP sequence of the TPS659037 device when requested. The INT line polarity and interrupts clearing method can be configured using the INT_CTRL register. An INT line event can be provided to the host in either SLEEP or ACTIVE mode, depending on the setting of the OSC_THERM_CTRL.INT_MASK_IN_SLEEP bit. When a new interrupt occurs while the interrupt line INT is still active (not all interrupts have been cleared), then: • If the new interrupt source is the same as the one that has already triggered the INT line, it can be discarded or stored as a pending interrupt depending on the setting of the INT_CTRL.INT_PENDING bit. – When the INT_CTRL.INT_PENDING bit is active (default), then any new interrupt event occurring on the same source (while the INT line is still active) is stored as a pending interrupt. Because only one level of pending interrupt can be stored for a given source, when several events (more than two) occur on the same source, only the last one is stored. While an interrupt is pending, two accesses are needed (either read or write) to clear the STATUS bit: one access for the actual interrupt and another for the pending interrupt. Note: two consecutive read or write operations to the same register clear only one interrupt. Another register must be accessed between the two read or write clear operations. Example for clear-on-read: when INT signal is active, read all four INTx_STATUS registers in sequence to collect status of all potential interrupt sources. Read access clears the full register for an active or actual interrupt. If the INT line is still active, repeat read sequence to check and clear pending interrupts. – When the INT_CTRL.INT_PENDING bit is inactive, then any new interrupt event occurring on the same source (while the INT line is still active) is discarded. Note: two consecutive read or write operations to the same register clear only one interrupt. Another register must be accessed between the two read or write clear operations. • If the new interrupt source is different from the one that already triggered the INT line, then it is stored immediately into its corresponding STATUS bit. To clear the interrupt line, all status registers must be cleared. The clearing of all status registers is achieved by using a clear-on-read or a clear-on-write method. The clearing method is selectable though the INT_CTRL.INT_CLEAR bit. When set, the clearing method applies to all bits for all interrupts. • Clear-on-read – Read access to a single status register clears all the bits for only this specific register (8 bits). Therefore, clearing all interrupts requests to read the four status registers. If the INT line is still active when the four read accesses complete, then another interrupt event has occurred during the read process; therefore the read sequence must be repeated. • Clear-on-write – This method is bit-based; setting a specific bit to 1 clears only the written bit. Therefore, to clear a complete status register, 0xFF must be written. Clearing all interrupts requests to write 0xFF into the four status registers. If the INT line is still active when the four write accesses are complete, then another interrupt event has occurred during the write process; therefore the write sequence must be repeated. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 53 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Table 5-6. Interrupt Sources INTERRUPT ASSOCIATED EVENT EDGES DETECTION ON REQUEST REGISTER GROUP REGISTER BIT DESCRIPTION VSYS_MON Internal event Rising and falling Never 6 System voltage monitoring interrupt: Triggered when system voltage has crossed the configured threshold in VSYS_MON register. HOTDIE Internal event Rising and falling Never 5 Hot-die temperature interrupt: The embedded thermal monitoring module has detected a die temperature above the hot-die detection threshold. Interrupt is generated in ACTIVE and SLEEP state, not in OFF state. PWRDOWN (pin) Rising and falling Never 4 Power-down interrupt: Triggered when the event is detected on the PWRDOWN pin. PWRDOWN INT1 RPWRON (pin) Falling Always (INT mask don't care) 3 Remote power-on interrupt: Triggered when a signal change is detected. Interrupt is generated in ACTIVE and SLEEP state, not in OFF state. LONG_PRESS_KEY PWRON (pin) Falling Never 2 Power-on long key-press interrupt. Triggered when PWRON is low during more than the long-press delay LONG_PRESS_KEY.LPK_TIME. PWRON PWRON (pin) Falling Always (INT mask don't care) 1 Power-on interrupt: Triggered when PWRON button is pressed (low) while the TPS659037 device is on. Interrupt is generated in ACTIVE and SLEEP state, not in OFF state. SHORT Internal event Rising Yes (if INT not masked) 6 Short interrupt: Triggered when at least one of the power resources (SMPS or LDO) has its output shorted. RESET_IN (pin) Rising Never 4 RESET_IN interrupt: Triggered when event is detected on RESET_IN pin. WDT Internal event Rising Never 2 Watchdog time-out interrupt: Triggered when watchdog time-out has expired. RTC_TIMER Internal event Rising Yes (if INT not masked) 1 Real-time clock timer interrupt: Triggered at programmed regular period of time (every second or minute). Running in ACTIVE, OFF, and SLEEP state, default inactive. RTC_ALARM Internal event Rising Yes (if INT not masked) 0 Real-time clock alarm interrupt: Triggered at programmed determinate date and time. VBUS (pin) Rising and falling Yes (if INT not masked) 7 VBUS wake-up comparator interrupt. Active in OFF state. Triggered when VBUS present. GPADC_EOC_SW Internal event N/A Yes (if INT not masked) 2 GPADC software end of conversion interrupt: Triggered when conversion result is available. GPADC_AUTO_1 Internal event N/A Yes (if INT not masked) 1 GPADC automatic periodic conversion 1: Triggered when result of conversion is either above or below (depending on configuration) reference threshold GPADC_AUTO_CONV1_LSB and GPADC_AUTO_CONV1_MSB. GPADC_AUTO_0 Internal event N/A Yes (if INT not masked) 0 GPADC automatic periodic conversion 0: Triggered when result of conversion is either above or below (depending on configuration) reference threshold GPADC_AUTO_CONV0_LSB and GPADC_AUTO_CONV0_MSB. GPIO_7 GPIO_7 (pin) Rising and/or falling Yes (if INT not masked) 7 GPIO_7 rising- or falling-edge detection interrupt 6 GPIO_6 rising- or falling-edge detection interrupt 5 GPIO_5 rising- or falling-edge detection interrupt 4 GPIO_4 rising- or falling-edge detection interrupt RPWRON RESET_IN VBUS GPIO_6 GPIO_6 (pin) Rising and/or falling Yes (if INT not masked) GPIO_5 GPIO_5 (pin) Rising and/or falling Yes (if INT not masked) Rising and/or falling Yes (if INT not masked) GPIO_4 GPIO_4 (pin) INT2 INT3 INT4 GPIO_3 GPIO_3 (pin) Rising and/or falling Yes (if INT not masked) 3 GPIO_3 rising- or falling-edge detection interrupt 2 GPIO_2 rising- or falling-edge detection interrupt GPIO_2 GPIO_2 (pin) Rising and/or falling Yes (if INT not masked) GPIO_1 GPIO_1 (pin) Rising and/or falling Yes (if INT not masked) 1 GPIO_1 rising- or falling-edge detection interrupt GPIO_0 GPIO_0 (pin) Rising and/or falling Yes (if INT not masked) 0 GPIO_0 rising- or falling-edge detection interrupt 54 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com 5.3.9 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Control Interfaces The TPS659037 device has two exclusive selectable (from factory settings) interfaces; two high-speed I2C interfaces (I2C1_SCL_SCK or I2C1_SDA_SDI and I2C2_SCL_SCE or I2C2_SDA_SDO) or one SPI (I2C1_SCL_SCK, I2C1_SDA_SDI, I2C2_SDA_SDO, or I2C2_SCL_SCE). Both are used to fully control and configure the TPS659037 device and have access to all the registers. When the I2C configuration is selected the I2C1_SCL_SCK or I2C1_SDA_SDI, a general purpose control (GPC) interface is dedicated to configure the TPS659037 device and the I2C2_SCL_SCE or I2C2_SDA_SDO interface dynamic voltage scaling (DVS) is dedicated to dynamically change the output voltage of the SMPS converters. The DVS I2C interface has access only to the voltage scaling registers of the SMPS converters (read and write mode). 5.3.9.1 I2C Interfaces The GPC I2C interface (I2C1_SCL_SCK and I2C1_SDA_SDI) is dedicated to access the configuration registers of all the resources of the system. The DVS I2C interface (I2C2_SCL_SCE and I2C_SDA_SDO) is dedicated to access the DVS registers independently from the GPC I2C. The control interfaces comply with the HS-I2C specification and support the following features: • Mode: Slave only (receiver and transmitter) • Speed: – Standard mode (100 kbps) – Fast mode (400 kbps) – High-speed mode (3.4 Mbps) • Addressing: 7-bit mode addressing device The following features are not supported: • 10-bit addressing • General call • Master mode (bus arbitration and clock generation) I2C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I2C-Bus Specification and user manual, Rev 03, June 2007). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, the SDA and SCL lines are pulled high. All the I2Ccompatible devices connect to the I2C bus through open-drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the start and stop of data transfers. A slave device receives and/or transmits data on the bus under control of the master device. The data transfer protocol for standard and fast modes is exactly the same, and they are referred to as F/S mode in this document. The protocol for high-speed mode is different from F/S mode, and it is referred to as HS mode. 5.3.9.1.1 I2C Implementation The standard I2C 7-bit slave device address is set to 010010xx (binary) where the two least-significant bits are used for page selection. The TPS659037 device is organized in five internal pages of 256 bytes (registers) as follows: • Slave device address 0x48: Power registers • Slave device address 0x49: Interfaces and auxiliaries • Slave device address 0x4A: Trimming and test • Slave device address 0x4B: OTP • Slave device address 0x12: DVS The device address for the DVS I2C interface is set to 0x12. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 55 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com If one of the addresses conflicts with another device I2C address, it is possible to remap each address to a fixed alternative one as described in Table 5-7. I2C for DVS is fixed because it is dedicated interface. Table 5-7. I2C Address Configuration REGISTER I2C_SPI BIT PAGE ID_I2C1[0] Power registers ID_I2C1[1] Interfaces and auxiliaries ID_I2C1[2] Trimming and test ID_I2C1[3] OTP ID_IDC2 DVS ADDRESSES ID_I2C1[0] = 0: 0x48 ID_I2C1[0] = 1: 0x58 ID_I2C1[1] = 0: 0x49 ID_I2C1[1] = 1: 0x59 ID_I2C1[2] = 0: 0x4A ID_I2C1[2] = 1: 0x5A ID_I2C1[3] = 0: 0x4B ID_I2C1[3] = 1: 0x5B ID_I2C2 = 0: 0x12 5.3.9.1.2 F/S Mode Protocol The master initiates data transfer by generating a START condition. The START condition is when a highto-low transition occurs on the SDA line while SCL is high (see Figure 5-11). All I2C-compatible devices should recognize a START condition. The master then generates the SCL pulses and transmits the 7-bit address and the read or write direction bit (R/W) on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 512). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 5-13) by pulling the SDA line low during the entire high period of the ninth SCL cycle. When this acknowledge is detected, the master knows that the communication link with a slave has been established. The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. An acknowledge signal can be generated by the master or the slave, depending on which one is the receiver. Nine-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a STOP condition by pulling the SDA line from low to high while the SCL line is high (see Figure 5-11). This releases the bus and stops the communication link with the addressed slave. All I2C-compatible devices must recognize the STOP condition. Upon the receipt of a STOP condition, all devices know that the bus is released, and they wait for a START condition followed by a matching address. Attempting to read data from register addresses not listed in this section results in 0xFF being read out. 5.3.9.1.3 HS Mode Protocol When the bus is idle, the SDA and SCL lines are pulled high by the pullup devices. The master generates a START condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S mode at no more than 400 kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation. The master then generates a REPEATED START condition (a REPEATED START condition has the same timing as the START condition). After the REPEATED START condition, the protocol is the same as F/S mode, except transmission speeds up to 3.4 Mbps are allowed. A STOP condition ends the HS mode and switches all the internal settings of the slave devices to support F/S mode. Instead of using a STOP condition, REPEATED START conditions are used to secure the bus in HS mode. 56 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Attempting to read data from register addresses not listed in this section results in 0xFF being read out. DATA CLK S P START Condition STOP Condition Figure 5-11. START and STOP Conditions CLK Data line stable; data valid Change of data allowed Figure 5-12. Bit Transfer on the Serial Interface Data output by transmitter Not acknowledge Data output by receiver Acknowledge SCL by master 1 2 8 9 S Clock pulse for acknowledgement START condition Figure 5-13. Acknowledge on the I2C Bus Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 57 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Recognizes SROP or repeated START condition Recognizes START or repeated STOP condition Generates ACKNOWLEDGE signal P SDA MSB Acknowledgement from slave Sr Address R/W 1 SCL S or Sr START or repeated STOP condition 2 7 8 9 1 ACK The clock line is held low while the interrupts are serviced 2 3-8 9 ACK S or Sr STOP or repeated START condition Figure 5-14. Bus Protocol 58 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com 5.3.9.2 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Serial-Peripheral Interface (SPI) The SPI is a 4-wire slave interface used to access and configure the TPS659037 device. The SPI allows read-and-write access to the configuration registers of all resources of the system. The SPI uses the following signals: • SCE (I2C2_SCL_SCE): Chip enable – Input driven by host master, used to initiate and terminate a transaction • SCK (I2C1_SCL_SCK): Clock – Input driven by host master, used as master clock for data transaction • SDI (I2C1_SDA_SDI): Data input – Input driven by host master, used as data line from master to slave • SDO (I2C2_SDA_SDO): Data output – Output driven by the TPS659037 device, used as data line from slave to master and defaults to high impedance 5.3.9.2.1 SPI Modes The SPI does not have access to the OTP and DVS registers (slave device address 0x4B & 0x12) of the device. The SPI_PAGE_CTRL.SPI_PAGE_ACCESS regsiter can be configured to access all other registers (slave device address 0x48, 0x49, & 0x4A) by: • SPI_PAGE_CTRL.SPI_PAGE_ACCESS = 0: Page1 = 0x48, Page2 = 0x49 • SPI_PAGE_CTRL.SPI_PAGE_ACCESS = 1: Page1 = 0x48, Page3 = 0x4A This SPI supports two access modes (Note: all shifts are done MSB first (Data, Address, Page): • Single access (read or write) – This consists of fetching and storing one single data location. The protocol is depicted in Figure 515. – The R/W bit is always provided first, followed by page address and register address fields. When R/W = 0, a read access is performed. When R/W = 1, a write access is performed. – 1 burst bit indicates if following transfer is a single access (BURST = 0) or a burst access (BURST = 1). – 4 unused bits follow the burst bit and finally the 8-bit data is either shifted in (write) or out (read). – For a write access, the data output line SDO is invalid (useless) during the whole transaction. – For a read access, the data output line SDO is invalid during the unused bits (time slot used for data fetch) and then becomes active or valid after the unused bits. • Burst access (read or write) – This consists of fetching and storing several data at contiguous locations. The protocol is depicted in Figure 5-16. – The R/W bit is always provided first, followed by page address and register address fields. When R/W = 0, a read access is performed. When R/W = 1, a write access is performed. – 1 burst bit indicates if following transfer is a single access (BURST = 0) or a burst access (BURST = 1). – 4 unused bits follow the burst bit and finally packets of 8-bit data are either shifted in (write) or out (read). – The transaction remains active as long as the SCE signal is maintained high by the host. – The address is automatically incremented internally for each new 8-bit packet received. – The host must pull the SCE signal low after a complete 8-bit data is transferred, otherwise the last transaction is discarded. – For a write access, the data output line SDO is invalid (useless) during the whole transaction. – For a read access, the data output line SDO is invalid during the unused bits (time slot used for data fetch) and then becomes active or valid after the unused bits. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 59 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com 5.3.9.2.2 SPI Protocol SPI Write SCE SCK SDI RW Page (SDI) Register address (8) Burst Unused bits (5) Data (8) Burst Unused bits (5) Unused bits (8) TPS659037 samples SDI on SCK rising edge : 0DVWHU WR DVVHUW GDWD RQ IDOOLQJ HGJH SPI Read SCE SCK SDI RW Page (SDI) Register address (8) SDO Data (8) (SDO) PMIC asserts SDO so that it is available on SCK rising edge TPS659037 samples SDI on SCK rising edge : 0DVWHU WR DVVHUW GDWD RQ IDOOLQJ HGJH : Master must sample data on rising edge Figure 5-15. SPI Single Read and Write Access SPI Write SCE SCK SDI (SDI) RW Page Register address (8) Burst Unused bits (5) Data (8) Data (8) Data (8) Unused bits (8) Unused bits (8) Data (8) Data (8) TPS659037 samples SDI on SCK rising edge : 0DVWHU WR DVVHUW GDWD RQ IDOOLQJ HGJH SPI Read SCE SCK SDI (SDI) RW Page Register address (8) Burst Unused bits (5) Unused bits (8) SDO (SDO) Unused bits Data (8) TPS659037 samples SDI on SCK rising edge : 0DVWHU WR DVVHUW GDWD RQ IDOOLQJ HGJH PMIC asserts SDO so that it is available on SCK rising edge : Master must sample data on rising edge Figure 5-16. SPI Burst Read and Write Access 60 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 5.3.10 Device Identification The following registers can differentiate the TPS659037 device being used. Table 5-8. TPS65903x-Q1 Device ID REGISTER NAME REGISTER DESCRIPTION VALUE PRODUCT_ID_MSB For all TPS659037 devices, this register will have the same value. 0x90 PRODUCT_ID_LSB For all TPS659037 devices, this register will have the same value. 0x39 DESIGNREV SW_REVISION 5.4 This register distinguishes which silicon version is used. Revision 1.0 0x0 Revision 1.1 0x1 Revision 1.2 0x2 Revision 1.3 0x3 Revision 1.4 0x4 This register will be representative of the OTP version programmed on the device. OTP dependent Device Functional Modes 5.4.1 Embedded Power Controller The EPC is composed of three main modules: • An event arbitration module used to prioritize ON, OFF, WAKE, and SLEEP requests. • A power state-machine used to determine which power sequence to execute, based on the system state (supplies, temperature, and so forth) and requested transition (from the event arbitration module). • A power sequencer that fetches the selected power sequence from OTP and executes it. The power sequencer sets up and controls all resources accordingly, based on the definition of each sequence. Figure 5-17 shows the EPC block diagram. ON Requests OFF Requests SLEEP Requests WAKE Requests Events Arbitration Event Power State Machine Power Sequence Pointer Power Sequencer Resources Resources System State (Supplies, Temperature, ...) Power Sequences OFF2ACT ACT2OFF SLP2OFF ACT2SLP SLP2ACT Resources Figure 5-17. EPC Block Diagram The power state-machine is defined through the following states: NO SUPPLY The TPS659037 device is not powered by any energy source on the system power rail (VCC1 < POR). BACKUP The TPS659037 device is not powered by a valid supply on the system power rail (VCC1 < VSYS_LO) (VCC > POR). OFF The TPS659037 device is powered by a valid supply on the system power rail (VCC1 > VSYS_LO) and it is waiting for a start-up event or condition. All device resources are in the OFF state. The approximate time for the TPS659037 device to arrive the OFF state from the NO SUPPLY state, without considering the rise time of VSYS and the settling time of the VSYS_LO comparator, is approximately 5.5 ms. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 61 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com ACTIVE The TPS659037 device is powered by a valid supply on the system power rail (VCC1 > VSYS_LO) and has received a start-up event. It has switched to the ACTIVE state, having full capacity to supply the processor and other platform modules. SLEEP The TPS659037 device is powered by a valid supply on the system power rail (VCC1 > VSYS_LO) and is in low-power mode. All configured resources are set to their low-power mode, which can be ON, SLEEP, or OFF depending on the specific resource setting. If a given resource is maintained active (ON) during low-power mode, then all its linked subsystems are automatically maintained active. Figure 5-18 shows the state diagram for the power control state-machine. No Supply VCC > POR_threshold VCC < POR BACKUP VCC > POR and VCC < VSYS_LO VCC > VSYS_LO VCC < VSYS_LO VCC < POR VCC < VSYS_LO OFF VCC < POR ON Request and VCC_SENSE > VSYS_HI OFF Request VCC < VSYS_LO ACTIVE OFF Request SLEEP Request WAKE Request SLEEP Figure 5-18. State Diagram for the Power Control State-Machine 62 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Power sequences define how a resource state switches between the OFF, ACTIVE, and SLEEP states, but they have no effect during the NO SUPPLY or BACKUP states. The EPC supervises the system according to these power sequences when the TPS659037 device is brought into the OFF state from a NO SUPPLY or BACKUP state. This supervision is achieved automatically by internal hardware controlling the device before handing it over to the EPC. The allowed power transitions are: • OFF to ACTIVE (OFF2ACT) • ACTIVE to OFF (ACT2OFF) • ACTIVE to SLEEP (ACT2SLP) • SLEEP to ACTIVE (SLP2ACT) • SLEEP to OFF (SLP2OFF) Each power transition consists of a sequence of one or several register accesses that controls the resources according to the EPC supervision. Because these sequences are stored in nonvolatile memory (OTP), they cannot be altered. 5.4.2 State Transition Requests 5.4.2.1 ON Requests ON requests are used to switch on the TPS659037 device, which transitions the device from the OFF to the ACTIVE state. Table 5-9 lists the ON requests. Table 5-9. ON Requests EVENT MASKABLE POLARITY COMMENT DEBOUNCE RPWRON (pin) No Low Level sensitive 16 ms ± 1 ms PWRON (pin) No Low Level sensitive N/A Part of interrupts (event) Yes (INTx_MASK register. Default: Masked) Event Edge sensitive N/A POWERHOLD (pin) No High Level sensitive 3 - 5 ms typical If one of the events listed in Table 5-9 occurs, it powers on the device, unless one of the gating conditions listed in Table 5-10 is present. For interrupt sources that can be configured as ON requests, see Table 56. Table 5-10. ON Requests Gating Conditions EVENT MASKABLE POLARITY VSYS_HI (event) No Low VCC_SENSE < VSYS_HI Device temperature exceeds HOTDIE level HOTDIE (event) No High PWRDOWN (pin) No OTP configurable RESET_IN (pin) No OTP configurable 5.4.2.2 COMMENT OFF Requests OFF requests are used to switch off the TPS659037 device, and transition the device from the SLEEP or the ACTIVE to the OFF state. Table 5-11 lists the OFF requests. OFF requests have the highest priority, and no gating conditions exist. Any OFF request is executed even though a valid SLEEP or ON request is present and force the device to go to the OFF state. When the OFF request is cleared it reacts to an ON request, if any is present. Table 5-11. OFF Requests EVENT MASKABLE POLARITY DEBOUNCE SWITCH OFF DELAY RESET LEVEL RESET SEQUENCE PWRON (pin) (long press key) No Low N/A SWOFF_DLY HWRST SD Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 63 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Table 5-11. OFF Requests (continued) EVENT MASKABLE POLARITY PWRDOWN (pin) No OTP configurable WATCHDOG TIMEOUT (internal event) N/A. WDT is disabled by default but software can enable it. NA THERMAL SHUTDOWN (internal event) No RESET_IN (pin) SW_RST (register bit) DEV_ON (register bit) VSYS_LO (internal event) DEBOUNCE SWITCH OFF DELAY RESET LEVEL RESET SEQUENCE SWOFF_DLY OTP Configurable OTP Configurable N/A SWOFF_DLY OTP Configurable OTP Configurable NA N/A 0 OTP Configurable OTP Configurable No OTP configurable N/A SWOFF_DLY OTP Configurable OTP Configurable No NA N/A 0 OTP Configurable OTP Configurable No NA N/A 0 SWORST SD No NA 0 OTP Configurable OTP Configurable POWERHOLD (pin) No Low GPADC_SHUTDOWN Yes NA N/A 0 SWORST SD SWOFF_DLY OTP Configurable OTP Configurable Notes: • SWOFF_DLY is the same for all requests. When configured to a specific value (0, 1, 2, or 4 s) it is applied to all OFF requests. • RESET_LEVEL is selectable as HWRST (wide set of registers is reset to default values) or SWORTS (more limited set of registers is reset). • OFF requests are configured to force the EPC to either execute a shutdown (SD) or a cold restart (CR). – When configured to generate an SD, the EPC executes a transition to the OFF state (SLP2OFF or ACT2OFF power sequence) and remains in the OFF state. – When configured to generate a CR, the EPC executes a transition to the OFF state (SLP2OFF or ACT2OFF power sequence) and restarts, transitioning to the ACTIVE state (OFF2ACT power sequence) if none of the ON request gating conditions are present. • Watchdog is disabled by default. SW can enable watchdog and lock (write protect) watchdog register (WATCHDOG). • The DEV_ON event has a lower priority over other ON events; it forces the TPS659037 device to go to the OFF state only if no other ON conditions are keeping the device active (POWERHOLD). • The POWERHOLD event has a lower priority over other ON events; it forces the TPS659037 device to go to the OFF state only if no other ON conditions are keeping the device active (DEV_ON). 5.4.2.3 SLEEP and WAKE Requests SLEEP requests are used to put the TPS659037 device in the SLEEP state, meaning a transition from the ACTIVE to SLEEP state. This sets internal resources into low-power mode, as well as user-defined resources into their user predefined low-power mode. The states of the resources during active and sleep modes are defined in the LDO*_CTRL registers and SMPSx_CTRL registers. Table 5-12 lists the SLEEP requests. Any of these events trigger the ACT2SLP sequence unless pending interrupts (unmasked) occur. Only an interrupt or NSLEEP inactive (high) generates a WAKE request to wake up the TPS659037 device (exit from the SLEEP state). A WAKE request (only during the SLEEP state) wakes up the device and triggers a SLEEP2ACT or a SLEEP2OFF power sequence. Table 5-12. SLEEP Requests 64 EVENT MASKABLE POLARITY COMMENT NSLEEP (pin) Yes (Default: Masked) Low Level sensitive Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 For each resource, a transition from the ACTIVE to SLEEP state or SLEEP to ACTIVE state can be controlled in two different ways: • Through EPC sequencing (ACT2SLP or SLP2ACT power sequence), when the resource is associated to the NSLEEP signal. • Through direct control of the resource power mode (active or sleep). – The user can bypass SLEEP and WAKE sequencing by having resources assigned to one external control signal (ENABLE1). This signal has direct control on the power modes (active or sleep) of any resources associated to it and it triggers an immediate switch from one mode to the other, regardless of the EPC sequencing. All resources can therefore be associated to two external pins (NSLEEP and ENABLE1) and they switch between the SLEEP and ACTIVE states based on Table 5-13. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 65 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com Table 5-13. Resources SLEEP and ACTIVE Assignments ENABLE1 ASSIGNMENT NSLEEP ASSIGNMENT ENABLE1 PIN STATE NSLEEP PIN STATE 0 0 Don't care Don't care ACTIVE None 0 1 Don't care 0↔1 SLEEP ↔ ACTIVE Sequenced 1 0 0↔1 Don't care SLEEP ↔ ACTIVE Immediate 0 0↔1 SLEEP ↔ ACTIVE Sequenced 1 0↔1 ACTIVE None 0↔1 0 SLEEP ↔ ACTIVE Immediate 0↔1 1 ACTIVE None 1 1 STATE TRANSITION NOTE • The polarity of the NSLEEP and ENABLE1 signals is configurable through the POLARITY_CTRL register. By default: – ENABLE1 is active high; a transition from 0 to 1 requests a transition from SLEEP to ACTIVE. – NSLEEP is active low; a transition from 1 to 0 requests a transition from ACTIVE to SLEEP. Resource assignments to the NSLEEP and ENABLE1 signals are configured in the ENABLEx_YYY_ASSIGN and NSLEEP_YYY_ASSIGN registers (where x = 1 or 2 and YYY = RES or SMPS or LDO) Several resources can be assigned to the same ENABLE1 signal and therefore, when triggered, they all switch their power mode at the same time. When resources are assigned only to the NSLEEP signal, their respective switching order is controlled and defined in the power sequence. When a resource is not assigned to any signal (NSLEEP and ENABLE1), it never switches from the ACTIVE to SLEEP state. The resource always remains in active mode. • • • • CAUTION A defect in the digital controller of the TPS659037 device was discovered, which may cause the PLL to shut down unexpectedly under the following sequence of events: • • • • PLL is programmed to be OFF under SLEEP mode through the PLLEN_CTRL register NSLEEP is assigned to control the entering of SLEEP mode for the PLL through the NSLEEP_RES_ASSIGN register The TPS659037 device goes through a SLP2OFF state transition followed by an OFF2ACT state transition PLL is again assigned to be OFF in SLEEP mode through the programming of the PLLEN_CTRL and the NSLEEP_RES_ASSIGN registers while the TPS659037 device remains in ACTIVE mode Two possible actions are recommended to help prevent the PLL from shutting down unexpectedly: • • 66 [Hardware Implementation] Toggle the NSLEEP pin twice to force the ACT2SLP and SLP2ACT state transitions as soon as the TPS659037 device wakes up from back to back SLP2OFF and OFF2ACT state transitions [Software Implementation] Toggle the NSLEEP_POLARITY bit (0 → 1 → 0) of the POLARITY_CTRL register to force the ACT2SLP and SLP2ACT device state transitions as soon as the TPS659037 device wakes up from back to back SLP2OFF and OFF2ACT state transitions Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com 5.4.3 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Power Sequences A power sequence is an automatic pre-programmed sequence handled by the TPS659037 device to configure the device resources: SMPSs, LDOs, 32-kHz clock, part of GPIOs, , REGEN signals) into on, off, or sleep modes. See Section 5.3.6 for GPIO details. Figure 5-19 shows an example of an OFF2ACT transition followed by an ACT2OFF transition. The sequence is triggered through PWRON pin and the resources controlled (for this example) are: SMPS8, LDO1, SMPS12, SMPS45, REGEN1, LDOLN, LDOUSB, and LDO2. The time between each resource enable and disable (t(instX)) is also part of the preprogrammed sequence definition. When a resource is not assigned to any power sequence, it remains in off mode. The user (through software) can enable and configure this resource independently after the power sequence completes. OFF2ACT Power Sequence PWRON X ACT2OFF Power Sequence X X X SMPS8 t(inst16) t(inst1) LDO1 t(inst15) t(inst2) SMPS12 t(inst14) t(inst3) SMPS45 t(inst13) t(inst4) REGEN1 t(inst12) t(inst5) LDOLN t(inst11) t(inst6) LDOUSB t(inst10) t(inst7) LDO2 t(inst9) t(inst8) RESET_OUT INT PWRON_IT = 1 Interrupt Acknowledge PWRON_IT = 1 Interrupt Acknowledge Figure 5-19. Power Sequence Example The power sequence of the TPS659037 device is defined according to the processor requirements. For more information, refer to TPS659037 User's Guide to Power AM572x and AM571x. 5.4.4 Startup Timing and RESET_OUT Generation The total start-up time of the TPS659037 device from the first supply insertion until the release of reset to the processor is defined by the boot time of internal resources as well as the OTP defined boot sequence. Following figure shows the power up sequence timing and the generation of the RESET_OUT signal. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 67 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com VCC1 VRTC RC 32kHz td(1) VIO td(2) 16.384-MHz oscillator clock output 1st rail in power sequence td(3) RESET_OUT Figure 5-20. Startup Timing Diagram The td(1) time is the delay between VCC1 crossing the POR threshold and VIO (first rail in the power sequence) rising up. The td(1) time must be at least 6 ms. If the time from VCC to VIO is less than 6 ms, the VIO buffers are supplied while the OTP is still being initialized, which could cause glitches on any VIO output buffer. Supplying VIO at least 6 ms after supplying VCC makes sure that the OTP is initialized and the output buffers are held low when VIO is supplied. The VIO_IN pin may be supplied before or after the first rail in the power sequence is enabled, as long as it is at least 6 ms after VCC. The td(2) time is the internal 16.384-MHz crystal oscillator start-up time, or the external 32-kHz clock input availability delay time. The td(3) time is the delay between the power up sequence start and RESET_OUT release. RESET_OUT is released when the power up sequence is complete and one of the following: • The 16.384-MHz clock is stabilized if the 16.384-MHz crystal is present and the oscillator is enable. • The external 32-kHz clock is stabilized and the 16.384-MHz oscillator is bypassed. • The GATE_RESET_OUT_OTP bit is used to allow the TPS659037 device to power up without the presence of the 16.384-MHz crystal nor the external 32-kHz clock input. The duration of the power-up sequence depends on OTP programming; average value is about 10 ms. 5.4.5 Power On Acknowledge The TPS659037 device is designed to support the following power on acknowledge modes: POWERHOLD mode and AUTODEVON mode. 5.4.5.1 POWERHOLD Mode In POWERHOLD mode, the acknowledge of the power on is achieved through a dedicated pin, POWERHOLD. Upon receipt of an ON request, the TPS659037 device initiates the power-up sequence and asserts the RESET_OUT pin high when it is in the ACTIVE state (reset released). While in the ACTIVE state, the device remains active for 8 s and then automatically shuts down. During this timeframe, to keep the device active, the host processor must assert and keep the POWERHOLD pin high. If the POWERHOLD pin is then set back to low, it is interpreted as an OFF request by the TPS659037 device. Figure 5-21 shows the POWERHOLD mode timing diagrams. 68 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Switch-ON event Device maintained ACTIVE for 8 seconds Device switch off starts with no delay Power-up sequence RESET_OUT POWERHOLD Figure 5-21. POWERHOLD Mode Timing Diagrams 5.4.5.2 AUTODEVON Mode In this mode, at the end of the power-up sequence, the register bit DEV_CTRL.DEV_ON is automatically set to 1 and the TPS659037 device remains in its ACTIVE state until this bit is cleared by the host processor. Figure 5-22 and Figure 5-23 show the AUTODEVON mode timing diagrams. Switch-on event Device maintained ACTIVE for 8 seconds RESET_OUT Device switch off starts with no delay Power-up sequence DEV_ON I2C-SPI access Figure 5-22. AUTODEVON Mode Timing Diagrams The DEV_ON bit can also be configured so that it is not auto-updated (set to 1) at the end of the power-up sequence. In this case, the TPS659037 device behaves similarly to the POWERWHOLD mode, except the host has control over it using the DEV_CTRL.DEV_ON register bit instead of the POWERHOLD pin. Therefore, to keep the TPS659037 device active, the host must set and keep this bit at 1. Switch-on event Device maintained ACTIVE for 8 seconds RESET_OUT Device switch off starts with no delay Power-up sequence DEV_ON I2C-SPI access I2C-SPI access Figure 5-23. DEV_ON Mode Timing Diagrams Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 69 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 5.4.6 www.ti.com BOOT Configuration All of the device resource settings are stored under the form of registers. Therefore, any platform-related settings are linked to an action altering these registers. This action can be a static update (register initialization value) or a dynamic update of the register (either from the user or from a power sequence). Resources and platform settings are stored in nonvolatile memory (OTP): • Static platform settings: – These settings define, for example, SMPS or LDO default voltages, GPIO functionality, and the device switch-on events. Part of the static platform settings can have two different values, and these values are selected with the BOOT0 pin. Static platform settings can be overwritten by a power sequence or by the user. • Sequence platform settings: – These settings define the TPS659037 device power sequences between state transitions, for example, the OFF2ACT sequence when transitioning from OFF mode to ACTIVE mode. Each power sequence is composed of several register accesses that define which resources (and their corresponding registers) must be updated during the respective state transition. Three different sequences can be defined with the BOOT0 and BOOT1 pins. These settings can be overwritten by the user when the power sequence completes execution. Platform settings are modifiable by the MCU during an OFF, ACTIVE, or SLEEP transition Static Platform Settings (Default configuration for all boot, I/O mux, default, voltage, and others) Switch ON event Selectable Platform Settings Reload during the OFF state transition (According to the respective reset domain, SWORST and HWRST Power IC Resources configuration and control registers Initialization occurs at reset RD BOOT0 Sequence Platform Settings (State transition micro program) The register updates during OFF, ACTIVE, and SLEEP transitions RD Voltage modification, resource enable or disable MCU BOOT0 BOOT1 Figure 5-24. Boot Pin Control 70 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com 5.4.6.1 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Boot Pin Selection Table 5-14 lists the boot pins associated configurations. NOTE Generally two of the three power sequence definitions are small modifications from the main sequence to the respective OTP memory size. Table 5-14. Boot Pin Associated Configurations BOOT0 BOOT1 OTP CONFIGURATION POWER SEQUENCE SELECTOR 0 0 Set_0 Sel_0 0 1 Set_0 Sel_1 1 0 Set_1 Sel_2 1 1 Set_1 Sel_2 The BOOT0 and BOOT1 pins must be grounded or pulled up, but the pins must not be unconnected (high impedance). The BOOT0 pin is used to select between two different OTP sets (Set_0 and Set_1) of device configuration (referred to as selectable platform settings in Figure 5-24). For list of OTP programmable parameters with programmed values refer to the Application Note of the relevant part number. NOTE The respective VSEL[6:0] bit field in the SMPSn_VOLTAGE and SMPSn_FORCE registers is mapped on a same OTP memory location, meaning that they are loaded at reset with the same value and that the BOOT0 pin changes the setting for both of them. The BOOT0 pin can also be used with the BOOT1 pin as static selectors during execution of the power sequence. This is intended to provide a possibility from within a static power sequence, to branch to different instructions. This allows choosing power sequences (or subpart of power sequences) based on BOOT pins without altering power sequences themselves in OTP. 5.4.7 Reset Levels The TPS659037 device resource control registers are defined by three categories: • POR registers • HW (HARDWARE) registers • SWO (SWITCHOFF) registers These registers are associated to three levels of reset as described below: • Power-on reset (POR) – Power-on reset happens when the TPS659037 device gets its supplies and transition from the NOSUPPLY state to the BACKUP state. This is the global device reset. – Additionally, SMPS_THERMAL_STATUS, SMPS_SHORT_STATUS, SMPS_POWERGOOD_MASK, LDO_SHORT_STATUS and SWOFF_STATUS registers are in POR domain. This list is indicative only. • HWRST – Hardware reset – Hardware reset happens when any OFF request is configured to generate a hardware reset. This reset triggers a transition to the OFF state from either the ACTIVE or SLEEP state (execute either the ACT2OFF or SLP2OFF sequence). Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 71 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 • www.ti.com SWORST – Switch-off reset – Switch-off reset happens when any OFF request is configured to not generate a hardware reset. This reset acts as the HWRST, except only the SWO registers are reset. The device goes in the OFF state, from either ACTIVE or SLEEP, and therefore executes the ACT2OFF or SLP2OFF sequence. – Power resource control registers for SMPS and LDO voltage levels and operating mode control are in SWORST domain. Additionally some registers control the 32-kHz, REGENx and SYSENx, watchdog, external charger control, and VSYS_MON comparator. This list is indicative only. Table 5-15 lists the reset levels, and Figure 5-25 shows the reset levels versus registers. Table 5-15. Reset Levels LEVEL RESET TAG REGISTERS AFFECTED COMMENT 0 POR POR, HW, SWO This reset level is the lowest level, for which all registers are reset. 1 HWRST HW, SWO During hardware reset (HWRST), all registers are reset except the POR registers. 2 SWORST SWO Only the SWO registers are reset. POR reset HWRST reset SWORST reset POR registers HW registers v SWO registers Figure 5-25. Reset Levels versus Registers 5.4.8 Warm Reset The TPS659037 device can execute a warm reset. The main purpose of this reset is to recover the TPS659037 device from a locked or unknown state by reloading the default configuration. The warm reset is triggered by the NRESWARM pin. During a warm reset, the OFF2ACT sequence is executed regardless of the actual state (ACTIVE, SLEEP) and the TPS659037 device returns to or remains in the ACTIVE state. Resources that are not part of the OFF2ACT sequence are not impacted by warm reset and maintain the previous state. Resources that are part of power-up sequence go to ACTIVE mode and the output voltage level is reloaded from OTP or kept in the previous value depending on the WR_S bit in the SMPSx_CTRL register or the LDOx_STRL register. 5.4.9 RESET_IN RESET_IN is a gating signal for on request and causes a switch-off event (Cold Reset or Shutdown). Table 5-11 shows that the RESET_IN behavior is programmable. 5.4.10 Watchdog Timer (WDT) The watchdog timer has two modes of operation, periodic mode and interrupt mode. In periodic mode, an interrupt is generated with a regular period N that is defined by the WATCHDOG.TIMER setting. This interrupt is generated at the beginning of the period (when the watchdog internal counter equals 1). The IC initiates a shutdown at the end of the period (when the internal counter has reached N) only if the interrupt has not been cleared within the defined time frame (0 to N). In this mode, when the interrupt is cleared, the internal counter is not reset. The counter continues 72 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 to count until it reaches the maximum value (defined by the TIMER setting) and automatically rolls over to 0 in order to start a new counting period. Regardless of when the interrupt is cleared within a given period (N), the next interrupt is generated only when the ongoing period completes (reaches N). The internal watchdog counter is initialized and kept at 0 as long as the RESET_OUT pin is low. The counter begins counting as soon as the RESET_OUT pin is released. In interrupt mode, any interrupt source resets the watchdog counter and begins the counting. If the sources of the interrupts are not cleared (INT line released) before the end of the predefined period N (set by WATCHDOG.TIMER setting) then the device initiates a shutdown. If the sources of the interrupts are cleared within the predefined period, then the watchdog counter is discarded (DC) and no shutdown sequence is initiated. By default, the watchdog is disabled. Figure 5-27 and Figure 5-26 show the watchdog timings. Watchdog Internal Counter 1 0 ... i ... N 0 1 Watchdog IT cleared New Watchdog IT ... ... N 0 New IT (reset WDT counter) IT not cleared in allowed timeframe INT pin (active high) Device switch off RESET_OUT pin Figure 5-26. Watchdog Timing Diagrams—Periodic Mode Watchdog Internal Counter X 0 1 New IT (reset WDT counter) ... i dc dc 0 1 ... New IT (reset WDT counter) N 0 IT not cleared in allowed timeframe INT pin (active high) IT Cleared Device switch off RESET_OUT pin Figure 5-27. Watchdog Timing Diagrams—Interrupt Mode 5.4.11 System Voltage Monitoring The power state-machine of the TPS659037 device is controlled by comparators monitoring the voltage on the VCC_SENSE and VCC1 pins. For electrical parameters see Section 4.14. POR: When the supply at the VCC1 pin is below the POR threshold, the TPS659037 device is in the NO SUPPLY state. All functionality, including RTC, is off. When the voltage in VCC1 rises above the POR threshold, the device enters from the NO SUPPLY to the BACKUP state. VSYS_LO: When the voltage on VCC1 pin rises above VSYS_LO, the TPS659037 device enters from the BACKUP state to the OFF state. When the device is in the ACTIVE, SLEEP, or OFF state and the voltage on VCC1 decreases below VSYS_LO, the device enters BACKUP mode. When the device transitions from the ACTIVE state to the BACKUP state, all active SMPS and LDO regulators, except LDOVRTC, are disabled simultaneously. When operating with a 16.384-MHz crystal, the regulators are immediately disabled after VCC1 becomes less than VSYS_LO. When operating without a crystal, a 180-µs deglitch time occurs after VCC1 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 73 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com becomes less than VSYS_LO and before the regulators are disabled. The VSYS_LO level is OTP programmable. NOTE For silicon revision 1.3 or earlier, when operating without a crystal, transitioning from the ACTIVE state to the BACKUP state using VSYS_LO while the outputs are active must always be followed by a POR event to make sure the device is reset properly. See Section 5.3.10 to identify the silicon version in the device. VSYS_MON: During power up, the VSYS_HI OTP value is used as a threshold for the VSYS_MON comparator which is gating the PMIC start-up (as a threshold for transition from OFF to ACTIVE state). The VSYS_MON comparator monitors the VCC_SENSE pin. After power up, software can configure the comparator threshold in the VSYS_MON register. Figure 5-28 shows a block diagram of the system comparators. OTP bits Register bits VCC1 VSYS_LO VSYS_LO VCC_SENSE VSYS_MON VSYS_MON Default VSYS_HI VBUS_SENSE VBUS_DET VBUS_WKUP_UP VSYS_HI VSYS_MON VSYS_LO INT STATE OFF ACTIVE and SLEEP BACKUP Figure 5-28. System Comparators To use comparators in the system: • The VSYS_LO and VSYS_HI thresholds are defined in the OTP. Software cannot change these levels. 74 Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com • • SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 After start-up, the VSYS_MON comparator is automatically disabled. Software can select a new threshold level using the VSYS_MON register and enable the comparator. In order for the same coding on the rising and falling edge, the VSYS_MON comparator does not include hysteresis and therefore can generate multiple interrupts when the voltage level is at the threshold level. New interrupt generation has a 125-μs debounce time which allows the software to mask the interrupt and update the threshold level or disable the comparator before receiving a new interrupt. Figure 5-29 shows additional details on the VSYS_MON comparator. When the VSYS_MON comparator is enabled, and the internal buffer is bypassed, input impedance at the VCC_SENSE pin is 500 kΩ (typical). When the comparators are disabled, the VCC_SENSE pin is at high impedance mode. If GPADC is enabled to measure channel 6 or channel 7, 40 kΩ is added in parallel to the corresponding comparator. See Table 5-3 for the GPADC input range. To enable system voltage sensing above 5.25 V, an external resistive divider can be used. Internal buffers are enabled by setting OTP bit HIGH_VCC_SENSE = 1 to provide high impedance for the external resistive dividers. The maximum input level for the internal buffer is VCC1 – 1 V. HIGH_VCC_SENSE 0 : buffer bypassed (not enabled) 1 : buffer enabled, bypass disbaled (Hi-Z at SENSE input) VCC1 VCC_SENSE 1 0 VSYS_MON HIGH_VCC_SENSE VSYS_MON 500 kŸ Default VSYS_HI Scale down, divide by 4 30 kŸ GPADC 10 kŸ GPADC_IN7 Figure 5-29. VSYS_MON Comparator Details 5.4.11.1 Generating a POR NOTE This section applies to silicon revisions 1.3 or earlier. Newer silicon revisions do not have this requirement because the VCC is continuously sampled. See Section 5.3.10 to identify the silicon version in the device. Detailed Description Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 75 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com To generate a POR from a falling VCC, VCC is sampled every 1 ms and compared to the POR threshold.In case VCC is discharged and resupplied quickly, a POR may not be reliably generated if VCC crosses the POR threshold between samples. Another way to generate POR is to discharge the LDOVRTC regulator to 0 V after VCC is removed. With no external load, this could take 3 s for the LDOVRTC output to discharge to 0 V. The PMIC should not be restarted after VCC is removed but before LDOVRTC is discharged to 0 V. If necessary, TI recommends to add a pulldown resistor from the LDOVRTC output to GND with a minimum of 3.9 kΩ to speed up the LDOVRTC discharge time. For more details, refer to the POR Generation in TPS65903x and TPS6591x Devices application report. The value of the pulldown resistor should be chosen based on the desired discharge time and acceptable current draw in the OFF state, but no greater than 0.5 mA. Use Equation 8 to calculate the pulldown resistor based on the desired discharge time. RPD (kΩ) = tdischarge (ms) / [CO (µF) × 3] where • • • tdischarge = discharge time of the VRTC output RPD = pulldown resistance from the VRTC output to GND CO = output capacitance on the VRTC line (typically 2.2 µF) (8) Because LDOVRTC is always on when VCC is supplied, additional current is drawn through the pulldown resistor. The output current of LDOVRTC while the PMIC is in OFF state should not exceed 0.5 mA. Use Equation 9 to calculate the pulldown current. IPD = 1.8 V / RPD where • • 76 IPD = current through the pulldown resistor RPD = pulldown resistance from the VRTC regulator Detailed Description (9) Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 6 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 6.1 Application Information The TPS659037 device is integrated power management integrated circuits (PMIC), both available in a 169-pin, 0.8-mm pitch, 12-mm × 12-mm nFBGA package. It has seven configurable step-down converter rails, with the ability to combine power rails and supply up to 9 A of output current in multi-phase mode. The TPS659037 device also has seven LDOs. The device has a 12-bit GPADC with three external channels, eight configurable GPIOs, two I2C interface channels or one SPI channel, a real-time clock module with calendar function, a PLL for external clock sync and phase delay capability, and a programmable power sequencer and control for supporting different processors and applications. As the TPS659037 device is highly integrated PMIC device, users must take necessary actions to ensure the PMIC is operating under the recommended operating conditions to ensure desired performance from the device. Additional cooling strategies may be necessary to maintain the junction temperature below maximum limit allowed for the device. To minimize the interferences when turning on a power rail while the device is in operation, optimal PCB layout and grounding strategy are essential and are recommended in Section 8. In addition, users can take steps such as turning on additional rails only when the systems is operating in light load condition. The following sections provides the typical application use case with the recommended external components and layout guidelines. For application design guidance and cross checks, refer to the TPS659037 Design Guide and the TPS659037 Design Checklist. 6.2 Typical Application Following the typical application schematic and the list of recommended external components will allow the TPS659037 device to achieve accurate and stable regulation with its SMPS and LDO outputs. These power sources are internally compensated and have been designed to operate most effectively with the component values listed in Table 6-2. Deviating from these values is possible but is highly discouraged. Application and Implementation Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 77 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com VCC1 VSYS Processor TPS659037 VSYS VCC_SENSE VBAT_SENSE SMPS12 6A FDBK SMPS45 4A FDBK MPU FDBK_GND PWRON RPWRON(1) GPU and Video FDBK_GND RESET_IN(1) SMPS6 3A BOOT0 CORE FDBK BOOT1 3V3 GPIO_4 3.3-V buck GPIO_6 DDR supply SYSEN1 SMPS8 1A SYSEN2 SMPS7 1.8 V, 2 A DSPEVE VIO_IN 1.8-V IO 1.8-V IO REGEN1 SMPS9 3.3 V, 1 A GPIO_1 3.3-V Serial Interfaces GPIO_2 ENABLE1(1) LDO9_IN 3V3 VSYS VSYS VSYS LDOVRTC 1.8 V, 25 mA VDDA_RTC LDO9 1 V, 50 mA VDD_RTC LDOLN_IN LDOLN 1.8 V, 50 mA OSC, slicer, DPLL LDO12_IN LDO1 1.p V, 0.3 A Digital Core LDO2 3.3 V, 0.3 A RTC IO LDO3 1.8 V, 0.2 A 1.8-V PHY Supply LDO4 1.8 V, 0.2 A 1.8-V Interface LDO34_IN LDO7_LDOUSB_IN VSYS LDOUSB_IN2 VBUS LDOUSB 3.25 V, 0.1 A USB PHY GPADC_IN0(1) I2C1_SCL_SCK GPADC_IN1(1) I2C1_SDA_SDI GPADC_IN2(1) I2C2_SCL_SCE I2C2_SDA_SDO GPADC_VREF(1) INT VBUS GPIO_5 PREQ1 RESET_OUT PORZ NRESWARM POWERGOOD CLK32KGO1V8 POWERHOLD VBUSDET NRESWARM GPIO_7 GPIOx GPIO_1 USB PHY CLK32KGO SMPS3 1.8 V,3 A SR I2C INT NSLEEP POWERDOWN CNTL I2C 32-kHz IN DDR3 Copyright © 2017, Texas Instruments Incorporated (1) (2) Input can be left floating if not used. Processor connections are OTP dependent. For OTP-specific connections, refer to the TPS659037 User's Guide to Power AM572x and AM571x. Figure 6-1. Application Schematic 78 Application and Implementation Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 VSYS VIO Control inputs PWRDOWN External power on External power request PWRON LDOVANA ENABLE1 NSLEEP C6 VPROG VIO_GND VBUS TESTV RESET_IN VIO_IN PWRON LDOVRTC_OUT BOOT1 VCC1 VCC1 BOOT0 LDOVANA_OUT Boot mode selection VCC_SENSE C29 VSYS C17 C8 C37 SCC_SENSE2 C40 Power Management LDOVRTC EN VSEL RAMP I2C1_SCL_CLK I2C2_SCL_SCE Application Processor I2C2_SDA_SDO 2 I C CNTL, I2C DVS, or SPI GPIO GPIO_3 GPIO_4 SYSEN1 GPIO_6 SYSEN2 GPIO_7 Interrupt Handler (24 channels) VBUSDET GPIO signals and controls C11 C13 SMPS1_2_FDBK SMPS1_2_FDBK_GND C12 SMPS2_GND VSYS SMPS3_IN SMPS3 SMPS3_SW 3A SMPS3_FDBK [Multi Or Stand-alone] SMPS3_GND SMPS4 2A (DVS) [Slave] Programmable power sequencer controller VCC1 VSYS_LO GPIO_2 L3 L4 C14 C16 VSYS SMPS4_IN VCC1 POR GPIO_0 REGEN2 VSYS SMPS2_IN SMPS2_SW Registers Internal Interrupt events GPIO_1 EN VSEL OTP controller OTP memory Control outputs POWERGOOD C10 SMPS1_GND Triple-Phases JTAG RESET_OUT REGEN1 SMPS2 3A (DVS) [Master] VSYS L2 TPS659037 DFT INT SMPS1_SW Dual-Phases Test and program NRESWARM I2C1_SDA_SDI SMPS1_IN SMPS1 3A (DVS) [Slave] VPROG VSYS ECO PWM DVS Switch ON and OFF VCC_SENSE VSYS_MON VBUS_SENSE VBUS_WKUP_UP SMPS4_GND Dual-Phases EN VSEL RAMP WDT Thermal monitoring SMPS4_SW SMPS5 2A (DVS) [Master] EN VSEL POWERHOLD GPIO_5 VSYS L7 C20 C24 SMPS4_5_FDBK SMPS4_5_FDBK_GND C23 SMPS5_GND Triple-Phases Hot die detection C19 SMPS5_IN SMPS5_SW RTC Thermal shutdown L6 VSYS SMPS7_IN SMPS7 SMPS7_SW 2A SMPS7_FDBK [Multi Or Stand-alone] SMPS7_GND L9 C27 C28 CLK32KGO1V8 Output Buffers EN VSEL RAMP GPADC_IN0 MUX 12-bit SDADC GPADC_IN1 GPADC_IN2 GPADC_VREF EN VSEL C1 C2 C3 C4 C5 C31 C29 C30 C33 SMPS8_GND VSYS L10 C43 C42 SMPS8_IN SMPS8_GND VSEL EN SMPS9 1A SMPS8_SW SMPS8_FDBK SMPS8_SW VSYS L11 C45 C44 VBG Reference and bias C41 REFGND1 C9 Grounds GND_DIG LDO9_OUT LDOUSB_IN2 LDO9_OUT SMPS8_FDBK LDOUSB 100 mA LDOUSB_IN1 EN VSEL Bypass LDO9 50 mA LDO9_IN LDO4 200 mA LDO4_OUT (LDO34_IN) C32 VSEL EN EN LDO3 200 mA LDO3_OUT LDO2_OUT LDO2 300 mA VSEL VSEL EN EN VSEL LDO1 300 mA (LDO12_IN) LDOLN_OUT VSYS/ Preregulated (VPRE) LDOLN_IN LDO_SUPPLY LDOLN 50 mA LDO1_OUT EN VSEL (Optional) SMPS8_IN SMPS8 1A (DVS) C26 C25 PBKG C18 SMPS6_GND GND_ANA CLK32KGO SYNCDCDC VSYS L8 SMPS6_FDBK GND_ANA OSC16MCAP SMPS6_SW GND_ANA C22 GND_ANA C21 Internal RC Oscillator RC 32 kHz OSC16MOUT SMPS6_IN SMPS6 2A (DVS) GND_ANA Y1 EN VSEL RAMP 16-MHz Oscillator OSC16MIN C34 Copyright © 2017, Texas Instruments Incorporated Figure 6-2. Typical Application Schematic Application and Implementation Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 79 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 6.2.1 www.ti.com Design Requirements For this design example, use the parameters listed in Table 6-1. Table 6-1. Design Parameters DESIGN PARAMETER TPS6590378ZWSR TPS6590379ZWSR 3.3 V to 5 V 3.8 V to 5 V 2.2 MHz 2.2 MHz SMPS12 voltage 1.15 V 1.15 V SMPS12 current 6A 6A SMPS3 voltage 1.35 V or 1.5 V 1.35 V or 1.5 V Supply voltage Switching frequency SMPS3 current SMPS45 voltage 3A 3A 1.06 V 1.06 V SMPS45 current 4A 4A SMPS6 voltage 1.15 V 1.06 V SMPS6 current 3A 3A SMPS7 voltage 0.7 V to 3.3 V 1.15 V SMPS7 current 2A 2A SMPS8 voltage 1.06 V 1.06 V SMPS8 current 1A 1A SMPS9 voltage 0.7 V to 3.3 V 3.3 V SMPS9 current 1A 1A LDO1 voltage 3.3 V 3.3 V LDO1 current 300 mA 300 mA LDO2 voltage 3.3 V 1.8 V LDO2 current 300 mA 300 mA LDO3 voltage 1.8 V 1.8 V LDO3 current 200 mA 200 mA LDO4 voltage 1.8 V 1.8 V LDO4 current 200 mA 200 mA LDO9 voltage 1.05 V 1.05 V LDO9 current 50 mA 50 mA LDOLN voltage 1.8 V 1.8 V LDOLN current 50 mA 50 mA LDOUSB voltage 3.3 V 3.3 V LDOUSB current 100 mA 100 mA 80 Application and Implementation Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com 6.2.2 6.2.2.1 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Detailed Design Procedure Recommended External Components Table 6-2. Recommended External Components for Commercial Usage COMPONENT (1) REFERENCE COMPONENTS MANUFACTURER PART NUMBER VALUE EIA SIZE CODE SIZE (mm) INPUT POWER SUPPLIES EXTERNAL COMPONENTS C7, C8 VSYS (VCC1) tank capacitor (2) Murata GRM188R60J106ME84 10 µF, 6V3 0603 1.6 × 0.8 × 0.8 C6 Decoupling capacitor Murata GRM155R61C104KA88 100 nF, 6V3 0402 1 × 0.5 × 0.5 Crystal Epson FA-238 16.384 MHz - 3.2 × 2.5 × 0.6 TXC 7V-16.384MAAE-T 16.384 MHz - 3.2 × 2.5 × 0.8 CRYSTAL OSCILLATOR EXTERNAL COMPONENTS Y1 C21, C22 Crystal decoupling Murata GRM1555C1H100JA01 10 pF, 50V 0402 1 × 0.5 × 0.5 C18 Crystal supply decoupling Murata GRM155R60J225ME15 2.2 µF, 6V3 0402 1 × 0.5 × 0.5 TDK C1005X5R0J225M 2.2 µF, 6V3 0402 1 × 0.5 × 0.5 Capacitor Murata GRM155R61C104KA88 100 nF, 6V3 0402 1 × 0.5 × 0.5 C10, C12, C14, C19, C23, C26, C27, C43, C45 Input capacitor Murata GRM155R60J475ME47 4.7 µF, 6V3 0402 1 × 0.5 × 0.5 C11, C13, C16, C20, C24, C25, C28, C42, C44 Output Capacitance for all SMPS Murata GRM21BR60J476ME15 47 µF, 6V3 0805 2 × 1.25 × 1.25 2520 L2, L3, L4, L6, L7, L8, L9, L10, L11 Inductor (BUCK) BANDGAP EXTERNAL COMPONENTS C9 SMPS EXTERNAL COMPONENTS TOKO DFE252010C-1RON 1 µH Vishay IHLP1616ABER1R0M11 1 µH 2.5 × 2 × 1 Murata GRM155R60J225ME15 2.2 µF, 6V3 0402 1 × 0.5 × 0.5 TDK C1005X5R0J225M 2.2 µF, 6V3 0402 1 × 0.5 × 0.5 Murata GRM155R60J225ME15 2.2 µF, 6V3 0402 1 × 0.5 × 0.5 TDK C1005X5R0J225M 2.2 µF, 6V3 0402 1 × 0.5 × 0.5 Murata GRM188R71C104KA01 100 nF 16 V 0603 1.6 × 0.8 × 0.8 Murata GRM155R61C104KA88 100 nF 16 V 0402 1 × 0.5 × 0.5 4 × 4.4 × 1.2 LDO EXTERNAL COMPONENTS C1, C2, C3, C4, C5 C29, C30, C31, C32, C33, C34, C37, C40, C41 Input capacitor Output capacitor VBUS EXTERNAL COMPONENTS C17 (1) (2) VBUS decoupling capacitor Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP. The tank capacitors filter the VSYS/VCC1 input voltage of the LDO and SMPS core architectures. Application and Implementation Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 81 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 6.2.2.2 www.ti.com SMPS Input Capacitors All SMPS inputs require an input decoupling capacitor to minimize input ripple voltage. TI recommends using a 10-V, 4.7-µF capacitor for each SMPS. Depending on the input voltage of the SMPS, a 6.3-V or 10-V capacitor can be used. See Table 6-2 for the specific part number of the input capacitor that is recommended. For optimal performance, the input capacitors should be placed as close to the SMPS input pins as possible. See Section 8.1 for more information about component placement. 6.2.2.3 SMPS Output Capacitors All SMPS outputs require an output capacitor to hold up the output voltage during a load step or changes to the input voltage. To ensure stability across the entire switching frequency range, the TPS659037 device requires an output capacitance value between 33 µF and 57 µF. To meet this requirement across temperature and DC bias voltage, TI recommends using a 47-µF capacitor for each SMPS. It is important to remember that each SMPS requires an output capacitor, not just each output rail. For example, SMPS12 is a dual phase regulator and an output capacitor is required for the SMPS1 output and the SMPS2 output. Note, this requirement excludes any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional capacitance placed near the load can be supported, but the end application or system should be evaluated for stability. See Table 6-2 for the specific part number of the recommended output capacitor. 6.2.2.4 SMPS Inductors Again, to ensure stability across the entire switching frequency range, TI recommends using a 1-µH inductor on each SMPS. It is important to remember that each SMPS requires an inductor, not just each output rail. For example, SMPS12 is a dual phase regulator and an inductor is required for the SMPS1_SW pins and the SMPS2_SW pins. See Table 6-2 for the specific part number of the recommended inductor. 6.2.2.5 LDO Input Capacitors All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. TI recommends using a 2.2-µF capacitor for each LDO. Depending on the input voltage of the LDO, a 6.3-V or 10-V capacitor can be used. See Table 6-2 for the specific part number of the input capacitor that is recommended. For optimal performance, the input capacitors should be placed as close to the LDO input pins as possible. See Section 8.1 for more information about component placement. 6.2.2.6 LDO Output Capacitors All LDO outputs need an output capacitor to hold up the output voltage during a load step or changes to the input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note, this requirement excludes any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional capacitance placed near the load can be supported, but the end application or system should be evaluated for stability. See Table 6-2 for the specific part number of the recommended output capacitor. 6.2.2.7 VCC1 VCC1 is the supply for the analog input voltage of the device. This pin requires a 10-µF decoupling capacitor. Texas Instruments recommends to always power down the TPS659037 before removing power from VCC1. If the input voltage to the device is removed while the device is ACTIVE, the device will shut off when VCC1 reaches the VSYS_LO threshold. As mentioned in the Section 5.4.11 section, once VCC1 reaches VSYS_LO, there is about 180 us delay before all the output rails are disabled simultaneously. There are two scenarios to consider in the system-level design in the event of unexpected loss of power. 82 Application and Implementation Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 6.2.2.7.1 Meeting the Power Down Sequence To prevent a sequencing violation, it is important to block reverse current and implement a disable signal to the PMIC. A Schottky diode can block reverse current when the input is removed. Additionally, capacitors can help maintain the input voltage level while the power-down sequence occurs. Depending on the system design, there are a couple ways to implement a disable signal. For a system where the TPS659037 is powered by the system input voltage, a supervisor can be used to create a logic signal, indicating if the power is at a good level. An example of this solution is shown in Figure 6-3. VIN (5 V) VCC PMIC GND Supervisor ENABLE Figure 6-3. Supporting Uncontrolled Power Down When the PMIC is Supplied by the System Input Voltage An alternative solution is possible when a pre-regulator is present. In the case of the pre-regulator, the pre-regulator output capacitance can also act as the energy storage to maintain VCC1 for the necessary time. The total supply capacitance should be calculated to support the worst-case leakage current during power down so that the voltage is maintained until the power-down sequence completes. Figure 6-4 shows an example of this configuration. VIN (12 V) 5V Buck VCC PGOOD PMIC GND ENABLE Figure 6-4. Supporting Uncontrolled Power Down when the PMIC is Supplied by a Preregulator To determine the capacitance needed at the output of the pre-regulator, use Equation 10. This equation is used to ensure that the power down sequence is complete before the device is disabled. C = I × ΔT / (VCC1 – VSYS_LO) where • • • • • C is total capacitance on VCC1, including pre-regulator output capacitance and PMIC input capacitance I is the total current on the PMIC input supply ΔT is the time it takes the power-down sequence to complete VCC1 is the voltage at the VCC1 pin VSYS_LO is the threshold where the device is disabled (10) 6.2.2.7.2 Maintaining Sufficient Input Voltage In the event of high loading during loss of input voltage, there is a risk to go below the voltage level necessary for the internal logic of the device to work properly before the device is disabled. This means that when the VCC1 voltage supply level becomes lower than the VSYS_LO threshold, the input voltage may continue dropping to very low voltages during the 180 us ±10% delay before the device is disabled. Application and Implementation Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 83 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com If a large input voltage drop occurs before the device is disabled, the internal logic can no longer properly drive the FETs of the SMPS, and it is possible that the high-side FET and low-side FET of the SMPS are on at the same time. In the event that the high-side and low-side FETs for an SMPS are on at the same time, there is a direct path from SMPSx_IN to SMPSx_GND, allowing cross-conduction and possible damage of the device. In order to prevent damage or irregular switching behavior, it is important that the voltage at the SMPSx_IN pin stays above 1.8 V, including negative transients, before the device is disabled. The minimum voltage seen at the SMPSx_IN pin is dependent on VCC1 and the PCB inductance between the SMPSx_IN pin and the input capacitor. Use Equation 11 to determine the minimum capacitance needed on VCC1 to ensure that the device continues switching properly before it is disabled. C = I × ΔT / (VSYS_LO – VCC1MIN) where • • • • • C is total capacitance on VCC1, including pre-regulator output capacitance and PMIC input capacitance I is the total current on the PMIC input supply ΔT is the maximum debounce time after VCC1 = VSYS_LO before the device switches off (198us) VSYS_LO is the threshold where the device is disabled VCC1MIN is the minimum VCC1 voltage to keep the SMPSx_IN transients above 1.8 V (11) When measuring the SMPSx_IN and VCC1 during power down, use active differential probes and a high resolution oscilloscope (4GS/sec or more). VCC1 can be measured over the 10uF input capacitor. However, SMPSx_IN must be measured at the pin in order to measure the transients on this rail accurately. To measure SMPSx_IN, place the negative lead of the differential probe at a nearby GND, such as the GND of the SMPSx_IN input capacitor. Place the positive lead of the differential probe as close as possible to the SMPSx_IN pin. With this set up, verify that SMPSx_IN, including the ripple on this signal, does not drop below 1.8V before the SMPS stops switching. See Figure 6-5 for an example of how to take this measurement. For ways to decrease the amplitude of the transient spikes, see Table 8-1 for recommended parasitic inductance requirements. SMPSx_IN VCCA 1.8 V minimum SMPSx_SW Figure 6-5. Waveform of SMPSx_IN Transients 6.2.2.8 VIO_IN VIO_IN is the supply for the digital circuits inside the TPS659037 device. This pin requires a 0.1-µF decoupling capacitor. 84 Application and Implementation Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com 6.2.2.9 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 16-MHz Crystal The TPS659037 device has the ability to accept a 16-MHz crystal input. Providing the 16-MHz crystal input to the device allows the output of a stable and accurate 32-kHz clock to be used by the applications processor. The crystal input is divided down by 500 internally to produce the 32-kHz output clock. The crystal should be connected to the TPS659037 device as shown in Figure 6-6. 6.3 V C1 GND 2.2 µF A3 V1 16.384 MHz A2 OSC16MCAP OSC16MIN OSC16MOUT 10 pF 10 pF GND GND Figure 6-6. Crystal Input Configuration As shown in Figure 6-6, the OSC16MCAP pin requires a 2.2-µF 6.3-V filtering capacitor near the pin. Also, the crystal requires between 9 pF and 11 pF of load capacitance on both pins. To meet this requirement, using two 10-pF capacitors is recommended. See Table 6-2 for the specific load capacitors that are recommended. The 16-MHz crystal is not required for operation of the TPS659037 device. The OSC16M_CFG OTP bit can be set to disable the 16MHz crystal completely, and enable one of the following two alternative options for system clock generation: • A 32-kHz square wave can be supplied to the OSC16MIN pin. This option is typically used in applications where the processor requires an accurate system clock and there is one already available in the system. In that case, the available 32-kHz clock can be provided to the PMIC and added to the boot sequence as an output. In this configuration, the OSC16MOUT and OSC16MCAP pins can be left floating, and the internal 16-MHz oscillator is bypassed. Bypassing the 16-MHz oscillator results in a lower quiescent current. • If the application does not require an accurate system clock for the processor, then providing one to the PMIC is not required. This option produces a lower quiescent current as seen in Section 4. In this configuration, the OSC16MIN pin should be grounded, while the OSC16MOUT and OSCMCAP pins can be left floating. Lastly, the GATE_RESET_OUT OTP bit should be used to allow the TPS659037 device to power up without the presence of the 16.384-MHz crystal nor the 32-kHz clock input. Please note that if the OSC16M_CFG OTP bit is set to 0, a 16-MHz crystal must be present for the proper operation of the device. 6.2.2.10 GPADC Instructions on how to perform a software conversion with the GPADC: 1. Enable software conversion mode – GPADC_SW_SELECT.SW_CONV_EN 2. Select the channel to convert – GPADC_SW_SELECT.SW_CONV0_SEL – For channel 0, set up the current source in the GPADC_CTRL1 register if needed. 3. For minimum latency, the GPADC can be set to always on (instead of default enabled from conversion request) by GPADC_CTRL1.GPADC_FORCE. 4. Unmask software conversion interrupt – INT3_MASK.GPADC_EOC_SW 5. Start conversion – GPADC_SW_SELECT.SW_START_CONV0. 6. An interrupt is generated at the end of the conversion INT3_STATUS.GPADC_EOC_SW. 7. Read conversion result – GPADC_SW_CONV0_MSB and GPADC_SW_CONV0_LSB 8. Expected result = dec(GPADC_SW_CONV0_MSB[3:0].GPADC_SW_CONV0_LSB[7:0])/ 4096 × 1.25 Application and Implementation Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 85 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com × scalar Instructions on how to perform an auto conversion with the GPADC: 1. Select the channel to convert – GPADC_AUTO_SELECT.AUTO_CONV0_SEL 2. Configure auto conversion frequency – GPADC_AUTO_CTRL.COUNTER_CONV 3. Set the threshold level for comparison – GPADC_THRESH_CONV0_MSB.THRESH_CONV0_MSB, GPADC_THRESH_CONV0_LSB.THRESH_CONV0_LSB – Level = expected voltage threshold / (1.25 × scalar) × 4096 (in hexadecimal) 4. Set if the interrupt is triggered when conversion is above or below threshold – GPADC_THRESH_CONV0_MSB.THRESH_CONV0_POL 5. Triggering the threshold level can also be programmed to generate shutdown – GPADC_AUTO_CTRL.SHUTDOWN_CONV0 6. Unmask AUTO_CONV_0 interrupt – INT3_MASK.GPADC_AUTO_0 7. Enable AUTO CONV0 – GPADC_AUTO_CTRL.AUTO_CONV0_EN 8. When selected channel crosses programmed threshold, interrupt is generated – INT3_STATUS.GPADC_AUTO_0 9. Conversion results are available – GPADC_AUTO_CONV0_MSB, GPADC_AUTO_CONV0_LSB 10. If shutdown was enabled, chip switches off after SWOFF_DLY, unless interrupt is cleared The example above is for CONV0; a similar procedure applies to CONV1. Application Curves 0.2 0.2 0.16 0.16 0.12 0.12 Load Regulation (%) Load Regulation (%) 6.2.3 0.08 0.04 0 -0.04 -0.08 -0.12 0.04 0 -0.04 -0.08 -0.12 VO = 1.05 V VO = 1.2 V -0.16 VO = 1.05 V VO = 1.2 V -0.16 -0.2 -0.2 0 1.5 VI = 3.8 V 3 4.5 6 Output Current (A) 7.5 9 0 1 D011 ƒSW = 2.2 MHz VI = 3.8 V Figure 6-7. SMPS Load Regulation for 9-A Triple Phase 86 0.08 2 3 4 Output Current (A) 5 6 D012 D011 ƒSW = 2.2 MHz Figure 6-8. SMPS Load Regulation for 6-A Dual Phase Application and Implementation Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 0.2 0.2 0.16 0.16 0.12 0.12 Load Regulation (%) Load Regulation (%) www.ti.com 0.08 0.04 0 -0.04 -0.08 -0.12 0.04 0 -0.04 -0.08 VO = 1.05 V VO = 1.2 V VO = 1.8 V VO = 2.5 V -0.12 VO = 1.05 V VO = 1.2 V -0.16 -0.16 -0.2 -0.2 0 0.8 VI = 3.8 V 1.6 2.4 Output Current (A) 3.2 4 0 ƒSW = 2.2 MHz VI = 3.8 V 0.16 0.16 0.12 0.12 Load Regulation (%) 0.2 0.08 0.04 0 -0.04 -0.08 VO = 1.05 V VO = 1.2 V VO = 1.8 V VO = 2.5 V -0.16 1 1.5 2 Output Current (A) 2.5 3 D014 ƒSW = 2.2 MHz Figure 6-10. SMPS Load Regulation for 3-A Single Phase 0.2 -0.12 0.5 D013 Figure 6-9. SMPS Load Regulation for 4-A Dual Phase Load Regulation (%) 0.08 0.08 0.04 0 -0.04 -0.08 VO = 1.05 V VO = 1.2 V VO = 1.8 V VO = 2.5 V -0.12 -0.16 -0.2 -0.2 0 0.4 VI = 3.8 V 0.8 1.2 Output Current (A) 1.6 2 0 0.2 D015 ƒSW = 2.2 MHz VI = 3.8 V Figure 6-11. SMPS Regulation for 2-A Single Phase 0.4 0.6 Output Current (A) 0.8 1 D016 ƒSW = 2.2 MHz Figure 6-12. SMPS Load Regulation for 1-A Single Phase VO (10 mV/div, AC coupled) VO (20 mV/div, AC coupled) IO (500 mA/div) IO (500 mA/div) 0.5 mA to 500 mA load step, tr = tf = 1 µs Time = 2.5 ms/div VI = 3.5 V VO = 1.05 V 0.5 mA to 500 mA load step, tr = tf = 100 ns Time = 5 ms/div ƒSW = 2.2 Hz Figure 6-13. Typical SMPS Load Transient Response for SMPS8 and SMPS9 VI = 3.5 V VO = 1.05 V ƒSW = 2.2 Hz Figure 6-14. Typical SMPS Load Transient Response for SMPS12, SMPS3, SMPS45, SMPS6, and SMPS7 Application and Implementation Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 87 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com 7 Power Supply Recommendations The TPS659037 device is designed to work with an analog supply voltage range of 3.135 V to 5.25 V. The input supply should be well regulated and connected to the VCC1 pin, as well as SMPS and LDO input pins with appropriate bypass capacitors as recommended in Figure 6-1. If the input supply is located more than a few inches from the TPS659037 device, additional capacitance may be required in addition to the recommended input capacitors at the VCC1 pin and the SMPS and LDO input pins. 8 Layout 8.1 Layout Guidelines As • • • • • • • in every switch-mode-supply design, the following general layout rules apply: Use a solid ground-plane for power-ground (PGND) Use an independent ground for Logic, LDOs and Analog (AGND) Connect those Grounds at a star-point ideally underneath the device. Place input capacitors as close as possible to the input-pins of the device. This is paramount and more important than the output-loop! Place the inductor and output capacitor as close as possible to the phase node (or switch-node) of the device. Keep the loop-area formed by Phase-node, Inductor, output-capacitor and PGND as small as possible. For traces and vias on power-lines, keep inductance and resistance as small as possible by using wide traces, avoid switching layers but if needed, use plenty of vias. The goal of the previously listed guidelines is a layout that minimizes emissions, maximizes EMI-immunity, and maintains a safe operating area for the device. To minimize the spiking at the phase-node for both, high-side (VIN – SWx) as well as low-side (SWx – PGND), the decoupling of VIN is paramount. Appropriate decoupling and thorough layout should ensure that the spikes never exceed 7V across the high-side and low-side FETs. TI recommends the guidelines shown in Figure 8-1 regarding parasitic inductance and resistance. Parasitic Inductance: < 1 nH Parasitic resistance: < 3 PŸ Parasitic resistance: As small as possible to get best efficiency Parasitic inductance: < 1 nH Parasitic resistance: < 2 PŸ SMPSx_SW SMPSx_IN SMPSx_SW SMPSx_GND Connection to power plane Parasitic resistance: As small as possible to get best efficiency For multiple capacitors, keep the parasitic resistance as small as possible among capacitors Parasitic inductance: < 1 nH Parasitic resistance: < 2 PŸ Figure 8-1. Parasitic Inductance and Resistance 88 Layout Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Table 8-1 lists the maximum allowable parasitic (inductance measured at 100 MHz) and the achievable values in an optimized layout. Table 8-1. Maximum Allowable Parasitic CONNECTION MAXIMUM ALLOWABLE INDUCTANCE MAXIMUM ALLOWABLE RESISTANCE PowerPlane – CIN N/A N/A for SOA, keep small for efficiency N/A CIN – SMPSx_IN 1 nH 3 mΩ SMPS1 0.533 nH SMPS1 1.77 mΩ SMPS2 0.465 nH SMPS2 1.22 mΩ SMPS3 0.494 nH SMPS3 1.37 mΩ SMPS4 0.472 nH SMPS4 1.23 mΩ SMPS5 0.517 nH SMPS5 1.27 mΩ SMPS6 0.518 nH SMPS6 1.69 mΩ SMPS7 0.501 nH SMPS7 1.27 mΩ SMPS8 0.509 nH SMPS8 1.42 mΩ SMPS9 0.491 nH SMPS9 1.4 mΩ SMPS1 0.552 nH SMPS1 1.21 mΩ SMPS2 0.583 nH SMPS2 0.8 mΩ SMPS3 0.668 nH SMPS3 0.93 mΩ SMPS4 0.57 nH SMPS4 0.81 mΩ SMPS5 0.577 nH SMPS5 0.76 mΩ SMPS6 0.608 nH SMPS6 1.13 mΩ SMPS7 0.646 nH SMPS7 0.83 mΩ SMPS8 0.67 nH SMPS8 0.73 mΩ SMPS9 0.622 nH SMPS9 0.82 mΩ SMPS1 1.9 mΩ SMPS2 0.89 mΩ SMPS3 1.99 mΩ SMPS4 0.93 mΩ SMPS5 1.37 mΩ SMPS6 1.11 mΩ SMPS7 1.17 mΩ SMPS8 1.35 mΩ SMPS9 0.88 mΩ CIN – SMPSx_GND SMPSx_SW – Inductor 1 nH N/A 2 mΩ N/A for SOA, keep small for efficiency OPTIMIZED LAYOUT (EVM) INDUCTANCE OPTIMIZED LAYOUT (EVM) RESISTANCE N/A for SOA, keep small for efficiency N/A Inductor – COUT N/A N/A for SOA, keep small for efficiency N/A COUT – GND Use dedicated GND plane to keep inductance low mΩ SMPS1 0.552 nH SMPS1 1.21 mΩ SMPS2 0.583 nH SMPS2 0.8 mΩ SMPS3 0.668 nH SMPS3 0.93 mΩ SMPS4 0.57 nH SMPS4 0.81 mΩ SMPS5 0.577 nH SMPS5 0.76 mΩ SMPS6 0.608 nH SMPS6 1.13 mΩ SMPS7 0.646 nH SMPS7 0.83 mΩ SMPS8 0.67 nH SMPS8 0.73 mΩ SMPS9 0.622 nH SMPS9 0.82 mΩ GND(CIN) – GND(COUT) Use dedicated GND plane to keep inductance low mΩ N/A for SOA, keep small for efficiency Use dedicated GND plane to mΩ keep inductance low Layout Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 89 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com TI recommends to measure the voltages across the high-side FET (voltage at SMPSx_IN vs. SMPSx_SW) and the low-side FET (SMPSx_SW vs. SMPSx_GND) with a high-bandwidth high-sampling rate scope with a low-capacitance probe (ideally a differential probe). Measure the voltages as close as possible to the device-pins and verify the amplitude of the spikes. A small-loop-GND-connection to the closest accessible SMPSx_GND (of the particular rail) is essential. Ideally, this measurement should be performed during start-up of the respective SMPS-rail (to take in account the inrush-current) and at high temperature. When measuring the voltage difference between the SMPSx_IN and SMPSx_SW pins, there should be a maximum of 7V when measuring at the pins. Similarly, when measuring the voltage difference between the SMPSx_SW and SMPSx_GND pins, there should be a maximum of 7V when measuring at the pins. For more information on cursor-positioning, see Figure 8-2 and Figure 8-3. 7 V maximum SMPSx_IN - SMPSx_SW Measure across the high-side FET (SMPSx_IN – SMPSx_SW) as close to the IC as possible. The preferred measurement is with a differential probe. The negative side of the probe should be at SMPSx_SW and the positive side of the probe should measure SMPSx_IN. As shown in this image, the voltage across the high-side FET should not exceed 7V. Repeat the measurement for all SMPSs in use. Figure 8-2. Measuring the High-side FET (Differentially) 90 Layout Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 7 V maximum SMPSx_SW - SMPSx_GND Measure across the low-side FET (SMPSx_SW – SMPSx_GND) as close to the IC as possible. The preferred measurement is with a differential probe. The negative side of the probe should be at SMPSx_GND and the positive side of the probe should measure SMPSx_SW. As shown in this image, the voltage across the low-side FET should not exceed 7V.Repeat the measurement for all SMPSs in use. Figure 8-3. Measuring the Low-side FET (Differentially) 8.2 Layout Example Figure 8-4, Figure 8-5, Figure 8-6, and Figure 8-7 show the actual placement and routing on the EVM. Figure 8-4. Top-Layer Overview of Inductor Placement Layout Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 91 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com COUT COUT CIN CIN COUT Figure 8-5. Bottom-Layer Overview of Input and Output Capacitor Placement Figure 8-6. Top-Layer Zoomed-In View of SMPS123 SW Connections to Inductors 92 Layout Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 Figure 8-7. Bottom-Layer Zoomed-In View of SMPS123 Input and Output Capacitor Layout Layout Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 93 TPS659037 SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 www.ti.com 9 Device and Documentation Support 9.1 9.1.1 Device Support Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 9.2 9.2.1 Documentation Support Related Documentation For related documentation, see the following: • Texas Instruments, Guide to Using the GPADC in TPS65903x and TPS6591x Devices • Texas Instruments, Power and Thermal Design Considerations Using TI's AM57x Processor design guide • Texas Instruments, POR Generation in TPS65903x and TPS6591x Devices • Texas Instruments, TPS659037 Design Checklist • Texas Instruments, TPS659037 Design Guide • Texas Instruments, TPS659037 Register Map • Texas Instruments, TPS659037 User's Guide to Power AM572x and AM571x • Texas Instruments, TPS659037EVM User's Guide 9.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 9.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 9.5 Trademarks Eco-mode, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 9.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 9.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 94 Device and Documentation Support Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS659037 TPS659037 www.ti.com SLIS165G – DECEMBER 2014 – REVISED FEBRUARY 2019 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2014–2019, Texas Instruments Incorporated Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: TPS659037 95 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS6590376ZWSR NRND NFBGA ZWS 169 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659037 OTP 8A 1.3 TPS6590376ZWST NRND NFBGA ZWS 169 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659037 OTP 8A 1.3 TPS6590377ZWSR NRND NFBGA ZWS 169 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659037 OTP 8B 1.3 TPS6590377ZWST NRND NFBGA ZWS 169 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659037 OTP 8B 1.3 TPS6590378ZWSR ACTIVE NFBGA ZWS 169 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659037 OTP 96 1.3 TPS6590378ZWST ACTIVE NFBGA ZWS 169 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659037 OTP 96 1.3 TPS6590379ZWSR ACTIVE NFBGA ZWS 169 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659037 OTP 97 1.3 TPS6590379ZWST ACTIVE NFBGA ZWS 169 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TPS659037 OTP 97 1.3 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of