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TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
TPS65910x Integrated Power-Management Unit Top Specification
1 Device Overview
1.1
Features
1
• Embedded Power Controller
• Two Efficient Step-Down DC-DC Converters for
Processor Cores
• One Efficient Step-Down DC-DC Converter for I/O
Power
• One Efficient Step-Up 5-V DC-DC Converter
• SmartReflex™ Compliant Dynamic Voltage
Management for Processor Cores
• 8 LDO Voltage Regulators and One Real-Time
Clock (RTC) LDO (Internal Purpose)
• One High-Speed I2C Interface for General-Purpose
Control Commands (CTL-I2C)
• One High-Speed I2C Interface for SmartReflex
Class 3 Control and Command (SR-I2C)
1.2
•
Applications
Portable and Handheld Systems
1.3
• Two Enable Signals Multiplexed with SR-I2C,
Configurable to Control any Supply State and
Processor Cores Supply Voltage
• Thermal Shutdown Protection and Hot-Die
Detection
• An RTC Resource With:
– Oscillator for 32.768-kHz Crystal or 32-kHz
Built-in RC Oscillator
– Date, Time, and Calendar
– Alarm Capability
• One Configurable GPIO
• DC-DC Switching Synchronization Through
Internal or External 3-MHz Clock
•
Industrial Systems
Description
The TPS65910 device is an integrated power-management IC available in 48-QFN package and
dedicated to applications powered by one Li-Ion or Li-Ion polymer battery cell or 3-series Ni-MH cells, or
by a 5-V input; it requires multiple power rails. The device provides three step-down converters, one stepup converter, and eight LDOs and is designed to support the specific power requirements of OMAP-based
applications.
Two of the step-down converters provide power for dual processor cores and are controllable by a
dedicated class-3 SmartReflex interface for optimum power savings. The third converter provides power
for the I/Os and memory in the system.
The device includes eight general-purpose LDOs providing a wide range of voltage and current
capabilities. The LDOs are fully controllable by the I2C interface. The use of the LDOs is flexible; they are
intended to be used as follows: Two LDOs are designated to power the PLL and video DAC supply rails
on the OMAP-based processors, four general-purpose auxiliary LDOs are available to provide power to
other devices in the system, and two LDOs are provided to power DDR memory supplies in applications
requiring these memories.
In addition to the power resources, the device contains an embedded power controller (EPC) to manage
the power sequencing requirements of the OMAP systems and an RTC.
Table 1-1. Device Information (1)
PART NUMBER
TPS65910
(1)
PACKAGE (PIN)
BODY SIZE
PVQFN (48)
6.00 mm × 6.00 mm
For more information, see Section 8, Mechanical Packaging and Orderable Information.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
1.4
www.ti.com
Functional Block Diagram
VBACKUP
Figure 1-1 shows the top-level diagram of the device.
CBB
VBAT
VCC7
VBAT
Ci(VCC7)
VRTC
VRTC (LDO)
and POR
Co(VRTC)
VAUX33 VCC7
Backup
management
Ci(VDD3)
SW3
GNDA
GNDA
GND3
VDD3
(SMPS)
OSC32KIN
OSC
32-kHz
OSC32KOUT
VFB3
Real-time
clock
Co(VDD3)
AGND
VCC7
REFGND
VDDIO
SDA_SDI
SCL_SCK
VBAT
VCC1
CLK32KOUT
Ci(VCC1)
SW1
GND1
2
I C
VDD1
(SMPS)
Bus
control
GPIO_CKSYNC
Co(VDD1)
VFB1
AGND
VCC4
VBAT
VCC2
Ci(VCC2)
SW2
SDASR_EN2
SCLSR_EN1
GND2
2
I C
VDD2
(SMPS)
Co(VDD2)
VFB2
AGND
VCC7
INT1
SLEEP
PWRON
BOOT1
BOOT0
PWRHOLD
NRESPWRON
Power
control
statemachine
Co(VREF)
TESTV
REFGND
VIO
(SMPS)
VCC 7
Analog
references
and comparators
VDAC
Co(VDAC)
VBAT
VDIG1
(LDO)
Ci(VCC5)
VDDIO
VDIG1
Co(VDIG1)
DGND
AGND2
VCC7
VCC5
Co(VIO)
VFBIO
VCC7
Test interface
VDAC
(LDO)
Ci(VCCIO)
GNDIO
AGND2
VREF
VBAT
VCCIO
SWIO
VCC6
AGND
VDIG2
VPLL
VDIG2
(LDO)
VPLL
(LDO)
Co(VPLL)
Co(VDIG2)
AGND2
AGND
VAUX1
VAUX33
(LDO)
VAUX1
(LDO)
VAUX33
Co(VAUX33)
Co(VAUX1)
VBAT
VBAT
VCC4
AGND2
AGND2
VCC3
Ci(VCC4)
VAUX2
Co(VAUX2)
DGND AGND AGND2 GND3
VAUX2
(LDO)
Ci(VCC4)
VMMC
VMMC
(LDO)
Co(VMMC)
AGND2
GNDP
AGND2
GNDP: Power pad ground
SWCS046-001
Figure 1-1. 48-QFN Top-Level Diagram
2
Device Overview
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
Table of Contents
1
2
3
4
Device Overview ......................................... 1
5.20
VAUX1 and VAUX2 LDO
1.1
Features .............................................. 1
5.21
VDAC and VPLL LDO............................... 33
1.2
Applications ........................................... 1
5.22
Timing and Switching Characteristics ............... 35
1.3
Description ............................................ 1
1.4
Functional Block Diagram ............................ 2
6.1
Power Reference .................................... 45
Revision History ......................................... 4
Device Comparison ..................................... 6
Terminal Configuration and Functions .............. 7
6.2
Power Sources ...................................... 45
6.3
Embedded Power Controller ........................ 45
4.1
5
6
Signal Descriptions ................................... 8
Specifications ........................................... 10
5.1
Absolute Maximum Ratings ......................... 10
5.2
Handling Ratings .................................... 10
5.3
5.4
Recommended Operating Conditions ............... 11
Thermal Resistance Characteristics for RSL
Package ............................................. 13
5.5
I/O Pullup and Pulldown Characteristics ............ 14
5.6
Digital I/O Voltage Electrical Characteristics ........ 15
5.7
I2C Interface and Control Signals ................... 16
5.8
Power Consumption................................. 17
5.9
Power References and Thresholds ................. 17
5.10
Thermal Monitoring and Shutdown
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
.................
32-kHz RTC Clock ..................................
Backup Battery Charger ............................
VRTC LDO ..........................................
VIO SMPS...........................................
VDD1 SMPS ........................................
VDD2 SMPS ........................................
VDD3 SMPS ........................................
VDIG1 and VDIG2 LDO .............................
VAUX33 and VMMC LDO...........................
7
18
18
19
19
20
22
24
8
...........................
Detailed Description ................................... 45
..................................
.................................................
6.6
Backup Battery Management .......................
6.7
Backup Registers ...................................
6.8
I2C Interface .........................................
6.9
Thermal Monitoring and Shutdown .................
6.10 Interrupts ............................................
6.11 Package Description ................................
6.12 Functional Registers ................................
Device and Documentation Support ...............
7.1
Device Support ......................................
7.2
Documentation Support .............................
7.3
Related Links ........................................
7.4
Community Resources ..............................
7.5
Trademarks..........................................
7.6
Electrostatic Discharge Caution .....................
7.7
Export Control Notice ...............................
7.8
Glossary .............................................
7.9
Additional Acronyms ................................
6.4
32-kHz RTC Clock
52
6.5
RTC
53
55
56
56
56
57
57
58
95
95
96
96
97
97
97
97
97
98
26
Mechanical Packaging and Orderable
Information .............................................. 99
27
8.1
Packaging Information
..............................
99
29
Table of Contents
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
31
3
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
4
VERSION
DATE
*
03/2010
NOTES
See
(1)
A
05/2010
See
(2)
B
06/2010
See
(3)
C
06/2010
See
(4)
D
11/2010
See
(5)
E
01/2011
See
(6)
F
01/2011
See
(7)
G
05/2011
See
(8)
H
06/2011
See
(9)
I
07/2011
See
(10)
J
10/2011
See
(11)
K
10/2011
See
(12)
L
01/2012
See
(13)
M
03/2012
See
(14)
N
04/2012
See
(15)
O
06/2012
See
(16)
P
09/2012
See
(17)
Q
09/2012
See
(18)
R
02/2013
See
(19)
S
08/2013
See
(20)
Initial release
SWCS046A: Updated register tables VMMC_REG and VDAC_REG. Added register table VPLL_REG
SWCS046B: Updated Absolute Maximum Ratings, Recommended Operating Conditions, I/O Pullup and Pulldown Characteristics,
Digital I/Os Voltage Electrical Characteristics, Power Consumption, Power References and Thresholds, Thermal Monitoring and
Shutdown, 32-kHz RTC Clock, VRTC LDO, VIO SMPS, VDD1 SMPS, VDD2 SMPS, VDD3 SMPS, Switch-On/-Off Sequences and
Timing
SWCS046C: Associate parts; no change.
SWCS046D: Updated Recommended Operating Conditions - Backup Battery, I/O Pullup and Pulldown Characteristics, Backup Battery
Charger. Update Rated output current, PMOS current limit (High-Side), NMOS current limit (Low-Side), and Conversion Efficiency for
VIO SMPS, VDD1/VDD2/VDD3 SMPS and VDIG1/VDIG2 LDO. Update Input Voltage for VIO/VDD1/VDD2 SMPS. Update DC and
Transient Load and Line Regulation and Internal Resistance for VDIG1/VDIG2 LDO, VAUX33/VMMC LDO, VAUX1,VAUX2, LDO, and
VDAC/VPLL LDO. Update DC Load Regulation for VAUX3/VMMC/VDAC. Update Power Control Timing. Add Device SLEEP State
Control. Add SMPS Switching Synchronization. Update VIO_REG, VDD1_REG, and VDD2_REG.
SWCS046E: Manually added Thermal Pad Mechanical Data.
SWCS046F: UpdatedTable 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS.
SWCS046G: Updated Section 6.11, Section 5.3, Section 5.6, and Section 6.3.3.6.
SWCS046H: Updated Table 6-29, PUADEN_REG, Table 6-61, RESERVED, and Table 6-62, RESERVED.
SWCS046I: Updated DC Output voltage VOUT in Section 5.20.
SWCS046J: UpdatedTable 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS.
SWCS046K: UpdateTable 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS - Add AM335x.
SWCS046L: Updated Table 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS - Add AM335x with DDR2
and AM335x with DDR3.
SWCS046M: Updated Section 6.3.1, - Update Device Sleep enable conditions control information.
SWCS046N:
• Section 5.14 - Updated PMOS current limit (high side) conditions
• Table 6-63 - Updated INT_STS_REG register - VMBHI_IT description
• Updated Input voltage: Section 5.18
SWCS046O: Updated Table 5-5, Power Control Timing Characteristics
• Replace unit of µs for tdbPWRONF by ms
SWCS046P: Updated Table 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS • Add AM335x with DDR3 - TPS65910A31A1RSL
• Add Rockchip - RK30xx
SWCS046Q: Updated Table 3-1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS • Refer to SWCU093 document: Updated document reference from TBD to SWCU093
SWCS046R: Updated Section 5.13, VRTC LDO - Changed Input Voltage - Back-up mode - Max from 3V to 5.5V.
SWCS046S: Updated Section 5.20, VAUX1 AND VAUX2 LDO - Changed VAUX2 - Rated Output Current IOUTmax - On mode from 150
mA to 300 mA
Revision History
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
VERSION
DATE
T
09/2013
See
NOTES
(21)
U
10/2014
See
(22)
(21) SWCS046T: Updated
• Table 6-23, RTC_Reset_Status_Reg, Changed Reserved bits to 7:1 and changed RESET_STATUS's reset value to 0x0.
• Table 6-34, VDD1_OP_REG, Changed SEL Vout to Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G.
• Table 6-35, VDD1_SR_REG, Changed SEL Vout to Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G.
• Table 6-37, VDD2_OP_REG, Changed SEL Vout to Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G.
• Table 6-38, VDD2_SR_REG, Changed SEL Vout to Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G.
(22) SWCS046U: Updated data sheet to latest TI standards
• Updated Section 1.2, Applications
• Added Table 1-1, Device Information
• Moved Section 4, Terminal Configuration and Functions
• Moved appropriate data to Section 5.2
• Added Section 5.4, Thermal Resistance Characteristics for RSL Package
Revision History
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
5
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
3 Device Comparison
Table 3-1. Supported Processors and Corresponding Part Numbers
Compatible Processor (1)
(1)
(2)
6
Part Number (1)
TI processor - AM335x with DDR2
TPS65910AA1RSL
TI processor - AM335x with DDR3
TPS65910A3A1RSL
TI processor - AM335x with DDR3 (2)
TPS65910A31A1RSL
TI processors - AM1705/07, AM1806/08, AM3505/17, AM3703/15, DM3730/25,
OMAP-L137/38, OMAP3503/15/25/30, TMS320C6742/6/8
TPS65910A1RSL
Samsung - S5PV210, S5PC110
TPS659101A1RSL
Rockchip - RK29xx, RK30xx
TPS659102A1RSL
Samsung - S5PC100
TPS659103A1RSL
Samsung - S5P6440
TPS659104A1RSL
TI processors - DM643x, DM644x
TPS659105A1RSL
Reserved
TPS659106A1RSL
Freescale - i.MX27, Freescale - i.MX35
TPS659107A1RSL
Freescale - i.MX508
TPS659108A1RSL
Freescale - i.MX51
TPS659109A1RSL
The RSL package is available in tape and reel. See for details for corresponding part numbers, quantities and ordering information.
Refer to SWCU093, TPS65910Ax User's Guide For AM335x Processors
Device Comparison
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
4 Terminal Configuration and Functions
25 TESTV
26 BOOT0
27 VBACKUP
28 VCC7
29 VRRTC
30 VFB3
31 SW3
32 VFB1
33 PWRON
34 GND1
35 SW1
36 VCC1
Figure 4-1 shows the pin assignments.
SLEEP 37
24 VPLL
CLK32KOUT 38
23 VCC5
GPIO/CKSYN 39
22 VDAC
21 OSC32KOUT
NRESPWRON 40
20 OSC32KIN
VCC2 41
19 BOOT1
SW2 42
PowerPad
GND2 43
18 VREF
VFB2 44
17 REFGND
INT1 45
16 VFBIO
VAUX1 46
15 GNDIO
VDDIO 12
SCLSR/EN1 11
SDASR/EN2 10
SCL 9
SDA 8
VDIG1 7
VCC6 6
VDIG2 5
VAUX33 4
13 VCCIO
VCC3 3
VAUX2 48
VMMC 2
14 SWIO
PWRHOLD 1
VCC4 47
SWCS046-004
Figure 4-1. 48-QFN Top-View Pin Assignment
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
7
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
4.1
www.ti.com
Signal Descriptions
Table 4-1. Signal Descriptions
NAME
QFN PIN
VDDIO
SUPPLIES
TYPE
I/O
VDDIO/DGND
Power
I
DESCRIPTION
PU/PD
Digital I/Os supply
No
SDA_SDI
VDDIO/DGND
Digital
I/O
I2C bidirectional data signal/serial
peripheral interface data input
(multiplexed)
SCL_SCK
VDDIO/DGND
Digital
I/O
I2C bidirectional clock signal/serial
peripheral interface Clock Input
(multiplexed)
External PU
SDASR_EN2
VDDIO/DGND
Digital
I/O
I2C SmartReflex bidirectional data
signal/enable of supplies (multiplexed)
External PU
SCLSR_EN1
VDDIO/DGND
Digital
I/O
I2C SmartReflex bidirectional clock
signal/enable of supplies (multiplexed)
External PU
SLEEP
VDDIO/DGND
Digital
I
Active-sleep state transition control
signal
Programmable PD
(default active)
GPIO_CKSYNC
VDDIO/DGND
Digital
I/O
Configurable general-purpose I/O or
DC-DCs synchronization clock input
signal
Programmable PD
(default active)
PWRHOLD
VRTC/DGND
Digital
I
Switch-on/-off control signal
Programmable PD
(default active)
PWRON
VBAT/DGND
Digital
I
External switch-on control (ON button)
Programmable PU
(default active)
NRESPWRON
VDDIO/DGND
Digital
O
Power off reset
PD active during
device OFF state
INT1
VDDIO/DGND
Digital
O
Interrupt flag
External PU
No
BOOT0
VRTC/DGND
Digital
I
Power-up sequence selection
Programmable PD
(default active)
BOOT1
VRTC/DGND
Digital
I
Power-up sequence selection
Programmable PD
(default active)
CLK32KOUT
VDDIO/DGND
Digital
O
32-kHz clock output
PD disable in
ACTIVE or SLEEP
state
OSC32KIN
VRTC/REFGND
Analog
I
32-kHz crystal oscillator
No
OSC32KOUT
VRTC/REFGND
Analog
I
32-kHz crystal oscillator
No
VREF
VCC7/REFGND
Analog
O
Bandgap voltage
No
REFGND
Analog
I/O
Reference ground
No
VCC7/AGND
Analog
O
Analog test output (DFT)
No
VBACKUP/AGND
Power
I
Backup battery input (short to VCC5 if
not used)
No
VCC1
VCC1/GND1
Power
I
VDD1 DC-DC power input
No
GND1
VCC1/GND1
Power
I/O
VDD1 DC-DC power ground
No
REFGND
TESTV
VBACKUP
SW1
VCC1/GND1
Power
O
VDD1 DC-DC switched output
No
VFB1
VCC7/AGND
Analog
I
VDD1 feedback voltage
PD
VCC2
VCC2/GND2
Power
I
VDD2 DC-DC power input
No
GND2
VCC2/GND2
Power
I/O
VDD2 DC-DC power ground
No
SW2
VCC2/GND2
Power
O
VDD2 DC-DC switched output
No
VFB2
VCC4/AGND2
Analog
I
VDD2 DC-DC feedback voltage
PD
VCCIO
VCCIO/GNDIO
Power
I
VIO DC-DC power input
No
GNDIO
VCCIO/GNDIO
Power
I/O
VIO DC-DC power ground
No
SWIO
VCCIO/GNDIO
Power
O
VIO DC-DC switched output
No
VFBIO
VCC7/AGND
Analog
I
VIO feedback voltage
PD
VCC3
VCC3/AGND2
Power
I
VMMC VAUX33 power input
No
VMMC
VCC3/REFGND
Power
O
LDO regulator output
PD
8
Terminal Configuration and Functions
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
Table 4-1. Signal Descriptions (continued)
NAME
QFN PIN
VAUX33
VCC4
SUPPLIES
TYPE
VCC3/REFGND
Power
I/O
DESCRIPTION
O
LDO regulator output, VDD3 internal
regulated supply
PU/PD
PD
VCC4/AGND2
Power
I
VAUX1, VAUX2 power input
No
VAUX1
VCC4/REFGND
Power
O
LDO regulator output
PD
VAUX2
PD
VCC4/REFGND
Power
O
LDO regulator output
VCC5
VCC5/AGND
Power
I
VDAC, VPLL power input
No
VDAC
VCC5/REFGND
Power
O
LDO regulator output
PD
VPLL
VCC5/REFGND
Power
O
LDO regulator output
PD
VRTC
VCC7/REFGND
Power
O
LDO regulator output
PD
VCC6
VCC6/AGND2
Power
I
VDIG1, VDIG2 power input
No
VDIG1
VCC6/REFGND
Power
O
LDO regulator output
No
VDIG2
VCC6/REFGND
Power
O
LDO regulator output
No
I
VRTC power input, VDD3 internal and
analog references supply
No
VCC7
VCC7/REFGND
Power
VFB3
VCC7/AGND
Analog
I
VDD3 feedback voltage
No
SW3
VCC7/GND3
Power
O
VDD3 DC-DC switched output
No
GND3
Power
PAD
AGND
Power
I/O
VDD3 DC-DC power ground
No
AGND
Power
PAD
AGND
Power
I/O
Analog ground
No
AGND2
Power
PAD
AGND
Power
I/O
Analog ground
No
DGND
Power
PAD
DGND
Power
I/O
Digital ground
No
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1) (2)
5.1
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4, VCC5, VCC6, VCC7
–0.3
7
V
Voltage range on pins/balls VDDIO
–0.3
3.6
V
Voltage range on pins/balls OSC32KIN, OSC32KOUT, BOOT1, BOOT0
–0.3
VRTCMAX + 0.3
V
Voltage range on pins/balls SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1, SLEEP,
INT1, CLK32KOUT, NRESPWRON
–0.3
VDDIOMAX + 0.3
V
Voltage range on pins/balls PWRON
–0.3
7
V
Voltage range on pins/balls PWRHOLD (3) GPIO_CKSYNC (4)
–0.3
7
V
–5
5
mA
Peak output current on all other terminals than power resources
(1)
(2)
(3)
(4)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
I/O supplied from VDDIO but which can be driven from to a VBAT voltage level
I/O supplied from VRTC but can be driven to a VBAT voltage level
5.2
Handling Ratings
Tstg
Storage temperature range
VESD
(1)
(2)
10
Electrostatic discharge (ESD)
performance:
Human Body Model (HBM), per ANSI/ESDA/JEDEC
JS001 (1)
Charged Device Model (CDM),
per JESD22-C101 (2)
All pins
MIN
MAX
UNIT
–45
150
°C
–2
2
kV
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
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5.3
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Note 1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that
VCC2 and VCC4 can be higher than VCC7.
Note 2: VCC2 and VCC4 must be connected together (to the same voltage).
Note 3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.
PARAMETER
TEST CONDITIONS
VCC: Input voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4, VCC5,
VCC7
MIN
NOM
MAX
UNIT
2.7
3.6
5.5
V
VCCP: Input voltage range on pins/balls VCC6
1.7
3.6
5.5
V
Input voltage range on pins/balls VDDIO
1.65
1.8/3.3
3.45
V
Input voltage range on pins/balls PWRON
0
3.6
5.5
V
Input voltage range on pins/balls SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1,
SLEEP
1.65
VDDIO
3.45
V
Input voltage range on pins/balls PWRHOLD, GPIO_CKSYNC
1.65
VDDIO
5.5
V
Input voltage range on balls BOOT1, BOOT0, OSC32KIN
1.65
VRTC
1.95
V
Operating free-air temperature, TA
–40
27
85
°C
Junction temperature, TJ
–40
27
125
°C
Storage temperature range
–65
27
150
°C
Lead temperature (soldering, 10 s)
260
°C
100
nF
10
µF
Power References
VREF filtering capacitor CO(VREF)
Connected from VREF to REFGND
VDD1 SMPS
Input capacitor CI(VCC1)
X5R or X7R dielectric
Filter capacitor CO(VDD1)
X5R or X7R dielectric
CO filter capacitor ESR
f = 3 MHz
4
Inductor LO(VDD1)
10
12
µF
10
300
mΩ
125
mΩ
2.2
LO inductor dc resistor DCRL
µH
VDD2 SMPS
Input capacitor CI(VCC2)
X5R or X7R dielectric
Filter capacitor CO(VDD2)
X5R or X7R dielectric
CO filter capacitor ESR
f = 3 MHz
10
4
Inductor LO(VDD2)
µF
10
12
µF
10
300
mΩ
125
mΩ
2.2
LO inductor dc resistor DCRL
µH
VIO SMPS
Input capacitor CI(VIO)
X5R or X7R dielectric
Filter capacitor CO(VIO)
X5R or X7R dielectric
CO filter capacitor ESR
f = 3 MHz
10
4
Inductor LO(VIO)
µF
10
12
µF
10
300
mΩ
125
mΩ
2.2
LO inductor dc resistor DCRL
µH
VDIG1 LDO
Input capacitor CI(VCC6)
X5R or X7R dielectric
4.7
Filtering capacitor CO(VDIG1)
0.8
CO filtering capacitor ESR
2.2
0
µF
2.64
µF
500
mΩ
VDIG2 LDO
Filtering capacitor CO(VDIG2)
0.8
CO filtering capacitor ESR
2.2
0
2.64
µF
500
mΩ
VPLL LDO
Input capacitor CI(VCC5)
X5R or X7R dielectric
4.7
Filtering capacitor CO(VPLL)
0.8
CO filtering capacitor ESR
0
2.2
µF
2.64
µF
500
mΩ
Specifications
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SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
Note 1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that
VCC2 and VCC4 can be higher than VCC7.
Note 2: VCC2 and VCC4 must be connected together (to the same voltage).
Note 3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
0.8
2.2
2.64
µF
500
mΩ
VDAC LDO
Filtering capacitor CO(VDAC)
CO filtering capacitor ESR
0
VMMC LDO
Input capacitor CI(VCC4)
X5R or X7R dielectric
4.7
Filtering capacitor CO(VMMC)
0.8
CO filtering capacitor ESR
2.2
0
µF
2.64
µF
500
mΩ
2.64
µF
500
mΩ
VAUX33 LDO
Filtering capacitor CO(VAUX33)
0.8
CO filtering capacitor ESR
2.2
0
VAUX1 LDO
Input capacitor CI(VCC3)
X5R or X7R dielectric
4.7
Filtering capacitor CO(VAUX1)
0.8
CO filtering capacitor ESR
2.2
0
µF
2.64
µF
500
mΩ
VAUX2 LDO
Filtering capacitor CO(VAUX2)
0.8
CO filtering capacitor ESR
2.2
0
2.64
µF
500
mΩ
VRTC LDO
Input capacitor CI(VCC7)
X5R or X7R dielectric
4.7
Filtering capacitor CO(VRTC)
0.8
CO filtering capacitor ESR
0
2.2
µF
2.64
µF
500
mΩ
VDD3 SMPS
Input capacitor CI(VDD3)
X5R or X7R dielectric
Filter capacitor CO(VDD3)
X5R or X7R dielectric
CO filter capacitor ESR
f = 1 MHz
4.7
4
Inductor LO(VDD3)
2.8
LO inductor DC resistor DCRL
µF
10
12
µF
10
300
mΩ
4.7
6.6
µH
50
500
mΩ
10
2000
mF
µF
Backup Battery
Battery or superCap supplying VBACKUP
Backup battery capacitor CBB
Series resistors
5
Capacitor supplying VBACKUP
1
40
5 to 15 mF
10
1500
100 to 2000 mF
5
15
Ω
I2C Interfaces
SDA_SDI, SCL_SCK, SDASR_EN2,
SCLSR_EN1 external pull-up resistor
Connected to VDDIO
1.2
kΩ
Crystal Oscillator (connected from OSC32KIN to OSC32KOUT)
Crystal frequency
at specified load cap value
Crystal tolerance
at 27°C
–20
Frequency Temperature coefficient.
Oscillator contribution (not including crystal
variation)
–0.5
Secondary temperature coefficient
–0.04
Voltage coefficient
Max crystal series resistor
12
Specifications
32.768
–2
at fundamental frequency
0
–0.035
kHz
20
ppm
0.5
ppm/°C
–0.03
ppm/°C2
2
ppm/V
90
kΩ
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
Note 1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that
VCC2 and VCC4 can be higher than VCC7.
Note 2: VCC2 and VCC4 must be connected together (to the same voltage).
Note 3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.
MAX
UNIT
Crystal load capacitor
PARAMETER
According to crystal data sheet
TEST CONDITIONS
6
12.5
pF
Load crystal oscillator Coscin,
Coscout
parallel mode including parasitic PCB capacitor
12
25
pF
8000
80000
Quality factor
5.4
MIN
NOM
Thermal Resistance Characteristics for RSL Package
°C/W (1)
(2)
AIR FLOW (m/s) (3)
NAME
DESCRIPTION
RΘJC
Junction-to-case (top)
16.4
0.00
RΘJB
Junction-to-board
5.6
0.00
RΘJA
(High k PCB)
Junction-to-free air
37
0.00
PsiJT
Junction-to-package top
0.2
0.00
PsiJB
Junction-to-board
5.6
0.00
RΘJC
Junction-to-case (bottom)
1.3
0.00
(1)
(2)
(3)
°C/W = degrees Celsius per watt.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
m/s = meters per second.
Specifications
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SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
5.5
www.ti.com
I/O Pullup and Pulldown Characteristics (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–45%
8
+45%
kΩ
µA
SDA_SDI, SCL_SCK, SDASR_EN2,
SCLSR_EN1 Programmable pullup (DFT, default
inactive)
Grounded, VDDIO = 1.8 V
SLEEP programmable pulldown (default active)
at 1.8 V, VRTC = 1.8 V
2
4.5
10
PWRHOLD programmable pulldown (default
active)
at 1.8 V, VRTC = 1.8 V, VCC7 = 2.7 V
2
4.5
10
at 5.5 V, VRTC = 1.8 V, VCC7 = 5.5 V
7
14
30
BOOT0, BOOT1 programmable pulldown (default
at 1.8 V, VRTC = 1.8 V
active)
2
4.5
10
µA
NRESPWRON pulldown
at 1.8 V, VCC7 = 5.5 V, OFF state
2
4.5
10
µA
32KCLKOUT pulldown (disabled in active-sleep
state)
at 1.8 V, VRTC = 1.8 V, OFF state
2
4.5
10
µA
PWRON programmable pullup (default active)
Grounded, VCC7 = 5.5 V
–40
–31
–15
µA
GPIO_CKSYNC programmable pullup (default
active)
Grounded, VRTC = 1.8 V
–27
–18
–9
µA
(1)
14
µA
The internal pullups on the CTL-I2C and SR-I2C balls are used for test purposes or when the SR-I2C interface is not used. Discrete
pullups to the VIO supply must be mounted on the board in order to use the I2C interfaces. The internal I2C pullups must not be used for
functional applications
Specifications
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5.6
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
Digital I/O Voltage Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
0.3 x VCC7
V
Related I/O: PWRON
Low-level input voltage, VIL
High-level input voltage, VIH
0.7 x VCC7
V
Related I/Os: PWRHOLD, GPIO_CKSYNC
Low-level input voltage, VIL
High-level input voltage, VIH
1.3
VDDIO/V
CC7
0.45
V
VCC7
V
0.35 x VRTC
V
Related I/Os: BOOT0, BOOT1, OSC32KIN
Low-level input voltage, VIL
High-level input voltage, VIH
0.65 x VRTC
V
Related I/Os: SLEEP
Low-level input voltage, VIL
0.35 x VDDIO
High-level input voltage, VIH
0.65 x VDDIO
V
V
Related I/Os: NRESPWRON, INT1, 32KCLKOUT
Low-level output voltage, VOL
High-level output voltage, VOH
IOL = 100 µA
0.2
V
IOL = 2 mA
0.45
V
IOH = 100 µA
VDDIO – 0.2
V
IOH = 2 mA
VDDIO – 0.45
V
Related Open-Drain I/Os: GPIO0
Low-level output voltage, VOL
IOL = 100 µA
0.2
V
IOL = 2 mA
0.45
V
0.3 x VDDIO
V
2
I C-Specific Related I/Os: SCL, SDA, SCLSR_EN1, SDASR_EN2
Low-level input voltage, VIL
–0.5
High-level input voltage, VIH
0.7 x VDDIO
Hysteresis
0.1 x VDDIO
V
V
Low-level output voltage, VOL at 3 mA (sink current), VDDIO = 1.8 V
0.2 × VDDIO
V
Low-level output voltage, VOL at 3 mA (sink current), VDDIO = 3.3 V
0.4 x VDDIO
V
Specifications
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SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
5.7
www.ti.com
I2C Interface and Control Signals
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
INT1 rise and fall times, CL = 5 to 35 pF
5
10
ns
NRESPWRON rise and fall times, CL = 5 to 35 pF
5
10
ns
10
80
ns
3.4
Mbps
SLAVE HIGH–SPEED MODE
SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall
time, CL = 10 to 100 pF
Data rate
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
10
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
160
ns
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
160
ns
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
160
ns
0
ns
70
ns
SLAVE FAST MODE
SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall
time, CL = 10 to 400 pF
20 +
0.1 × CL
Data rate
250
ns
400
Kbps
0.9
µs
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
100
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
ns
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
0.6
µs
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
0.6
µs
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
0.6
µs
SLAVE STANDARD MODE
SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall
time, CL = 10 to 400 pF
250
ns
Data rate
100
Kbps
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
I7
tsu(SCLH-SDAL)
I8
th(SDAL-SCLL)
I9
tsu(SDAH-SCLH)
ns
0
µs
Setup time, SCL high to SDA low
4.7
µs
Hold time, SCL low from SDA low
4
µs
Setup time, SDA high to SCL high
4
µs
SWITCHING CHARACTERISTICS
SLAVE HIGH–SPEED MODE
I1
tw(SCLL)
Pulse duration, SCL low
160
ns
I2
tw(SCLH)
Pulse duration, SCL high
60
ns
SLAVE FAST MODE
I1
tw(SCLL)
Pulse duration, SCL low
1.3
µs
I2
tw(SCLH)
Pulse duration, SCL high
0.6
µs
SLAVE STANDARD MODE
I1
tw(SCLL)
Pulse duration, SCL low
4.7
µs
I2
tw(SCLH)
Pulse duration, SCL high
4
µs
16
Specifications
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TPS659106, TPS659107, TPS659108, TPS659109
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5.8
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
Power Consumption
over operating free-air temperature range (unless otherwise noted)
All current consumption measurements are relative to the FULL chip, all VCC inputs set to VBAT voltage.
PARAMETER
Device BACKUP state
Device OFF state
TYP
MAX
VBAT = 2.4 V, VBACKUP = 0 V,
TEST CONDITIONS
MIN
11
16
VBAT = 0 V, VBACKUP = 3.2 V
6
9
UNIT
µA
VBAT = 3.6 V, CK32K clock running
BOOT[1:0] = 00: 32-kHz RC oscillator
16.5
23
BOOT[1:0] = 01: 32-kHz quartz or bypass oscillator, BOOT0P = 0
15
20
BOOT[1:0] = 01, Backup Battery Charger on, VBACKUP = 3.2 V
32
42
VBAT = 5 V, CK32K clock running:
20
28
µA
BOOT[1:0] = 00: RC oscillator
Device SLEEP state
Device ACTIVE state
5.9
VBAT = 3.6 V, CK32K clock running, PWRHOLDP = 0
BOOT[1:0] = 00, 3 DC-DCs on, 5 LDOs and VRTC on, no load
295
BOOT[1:0] = 01, 3 DC-DCs on, 3 LDOs and VRTC on, no load,
BOOT0P = 0
279
µA
VBAT = 3.6 V, CK32K clock running, PWRHOLDP = 0
BOOT[1:0] = 00, 3 DC-DCs on, 5 LDOs and VRTC on, no load
1
BOOT[1:0] = 01, 3 DC-DCs on, 3 LDOs and VRTC on, no load,
BOOT0P = 0
0.9
BOOT[1:0] = 00, 3 DC-DCs on PWM mode (VDD1_PSKIP =
VDD2_PSKIP = VIO_PSKIP = 0), 5 LDOs and VRTC on, no load
21
mA
Power References and Thresholds
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output reference voltage (VREF
terminal)
PARAMETER
Device in active or low-power mode
–1%
0.85
+1%
V
Main battery charged
threshold VMBCH (programmable)
Measured on VCC7 terminal
Triggering monitored through NRESPRWON
VMBCH_VSEL = 11, BOOT[1:0] = 11 or 00
3
VMBCH_VSEL = 10
2.9
VMBCH_VSEL = 01
2.8
VMBCH_VSEL = 00
V
bypassed
Main battery discharged
Measured on VCC7 terminal (MTL prg)
threshold VMBDCH (programmable) Triggering monitored through INT1
VMBCH –
100 mV
V
Main battery low threshold VMBLO
(MB comparator)
Measured on VCC7 terminal (Triggering
monitored on terminal NRESPWRON)
2.5
2.6
2.7
Main battery high threshold VMBHI
VBACKUP = 0 V, measured on terminal VCC7
(MB comparator)
2.6
2.75
3
VBACKUP = 3.2 V, measured on terminal VCC7
2.5
2.55
3
Measured on terminal VCC7
(Triggering monitored on terminal VRTC)
1.9
2.1
2.2
Main battery not present threshold
VBNPR
Ground current (analog references
+ comparators + backup battery
switch)
V
V
V
VCC = 3.6 V
Device in OFF state
8
Device in ACTIVE or SLEEP state
20
Specifications
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Copyright © 2010–2014, Texas Instruments Incorporated
µA
17
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
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SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
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5.10 Thermal Monitoring and Shutdown
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Hot-die temperature rising threshold
MIN
THERM_HDSEL[1:0] = 00
121
113
THERM_HDSEL[1:0] = 11
125
136
10
Thermal shutdown temperature rising
threshold
UNIT
°C
130
Hot-die temperature hysteresis
136
Thermal shutdown temperature hysteresis
Device in ACTIVE state, Temp = 27°C,
VCC7 = 3.6 V
Ground current
MAX
117
THERM_HDSEL[1:0] = 01
THERM_HDSEL[1:0] = 10
TYP
148
°C
160
°C
10
°C
6
µA
5.11 32-kHz RTC Clock
over operating free-air temperature range (unless otherwise noted)
PARAMETER
CLK32KOUT rise and fall time
TEST CONDITIONS
MIN
TYP
CL = 35 pF
MAX
UNIT
10
ns
Bypass Clock (OSC32KIN: input, OSC32KOUT floating)
Input bypass clock frequency
OSCKIN input
Input bypass clock duty cycle
OSCKIN input
Input bypass clock rise and fall time
10% – 90%, OSC32KIN input
CLK32KOUT duty cycle
Logic output signal
Bypass clock setup time
32KCLKOUT output
Ground current
Bypass mode
32
40%
kHz
60%
10
40%
20
ns
60%
1
ms
1.5
µA
Crystal oscillator (connected from OSC32KIN to OSC32KOUT)
Output frequency
CK32KOUT output
Oscillator startup time
On power on
32.768
kHz
2
Ground current
1.5
s
µA
RC oscillator (OSC32KIN: grounded, OSC32KOUT floating)
Output frequency
CK32KOUT output
Output frequency accuracy
at 25°C
Cycle jitter (RMS)
Oscillator contribution
Output duty cycle
32
–15%
0%
+40%
+50%
+10%
Settling time
+60%
150
Ground current
18
kHz
+15%
Specifications
Active at fundamental frequency
4
µs
µA
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
5.12 Backup Battery Charger
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Backup battery charging current VBACKUP = 0 to 2.4 V, BBCHEN = 1
350
500
700
µA
End-of-charge backup battery
voltage (1)
VCC7 = 3.6 V, BBSEL = 10
–3%
3.15
+3%
VCC7 = 3.6 V, BBSEL = 00
–3%
3
+3%
VCC7 = 3.6 V, BBSEL = 01
–3%
2.52
+3%
VCC7 = 3.6 V, BBSEL = 11
VBAT –
0.3 V
Ground current
(1)
On mode
V
VBAT
10
µA
Note:
• BBSEL = 10, 00, or 01 intended to charge battery or superCap
• BBSEL = 11 intended to charge capacitor
5.13 VRTC LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage VIN
DC output voltage VOUT
Rated output current IOUTmax
DC load regulation
DC line regulation
Transient load regulation
TEST CONDITIONS
MIN
TYP
MAX
On mode
2.5
5.5
Back-up mode
1.9
5.5
On mode, 3.0 V < VIN < 5.5 V
1.78
1.83
1.88
Back-up mode, 2.3 V ≤ VIN ≤ 2.6 V
1.72
1.78
1.84
On mode
20
Back-up mode
0.1
UNIT
V
V
mA
On mode, IOUT = IOUTmax to 0
50
Back-up mode, IOUT = IOUTmax to 0
50
On mode, VIN = 3.0 V to VINmax at IOUT = IOUTmax
2.5
Back-up mode, VIN = 2.3 V to 5.5 V at IOUT =
IOUTmax
25
On mode, VIN = VINmin + 0.2 V to VINmax
mV
mV
50 (1)
mV
25 (1)
mV
IOUT = IOUTmax/2 to IOUTmax in 5 µs
and IOUT = IOUTmax to IOUTmax/2 in 5 µs
Transient line regulation
On mode, VIN = VINmin + 0.5 V to VINmin in 30 µs
And VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, VIN rising from 0 up to 3.6 V, at VOUT =
0.1 V up to VOUTmin
Ripple rejection
VIN = VINDC + 100 mVpp tone, VINDC+ = VINmin +
0.1 V to VINmax at IOUT = IOUTmax/2
Ground current
(1)
2.2
f = 217 Hz
55
f = 50 kHz
35
Device in ACTIVE state
23
Device in BACKUP or OFF state
3
ms
dB
µA
These parameters are not tested. They are used for design specification only.
Specifications
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Copyright © 2010–2014, Texas Instruments Incorporated
19
TPS65910, TPS65910A, TPS65910A3, TPS659101
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SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
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5.14 VIO SMPS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCCIO and VCC7) VIN
DC output voltage (VOUT)
TEST CONDITIONS
MIN
2.7
5.5
VOUT = 1.5 V or 1.8 V, IOUT > 800 mA
3.2
5.5
VOUT = 2.5 V, IOUT > 800 mA
4.0
5.5
VOUT = 3.3 V, IOUT > 800 mA
4.4
5.5
UNIT
V
PWM mode (VIO_PSKIP = 0) or pulse skip
mode IOUT to IMAX
VSEL=00
–3%
1.5
+3%
VSEL = 01, default BOOT[1:0] = 00 and 01
–3%
1.8
+3%
VSEL = 10
–3%
2.5
+3%
VSEL = 11
–3%
3.3
+3%
V
0
ILMAX[1:0] = 00, default
500
ILMAX[1:0] = 01
1000
mA
P-channel MOSFET
VIN = VINmin
300
On-resistance RDS(ON)_PMOS
VIN = 3.8 V
250
P-channel leakage current ILK_PMOS
VIN = VINMAX, SWIO = 0 V
N-channel MOSFET
VIN = VMIN
300
On-resistance RDS(ON)_NMOS
VIN = 3.8 V
250
N-channel leakage current ILK_NMOS
VIN = VINmax, SWIO = VINmax
PMOS current limit (high-side)
VIN = VINmin to VINmax, ILMAX[1:0] = 00
650
VIN = VINmin to VINmax, ILMAX[1:0] = 01
1200
VIN = VINmin to VINmax, ILMAX[1:0] = 10
1700
NMOS current limit (low-side)
MAX
IOUT ≤ 800 mA
Power down
Rated output current IOUTmax
TYP
400
2
400
2
mΩ
µA
mΩ
µA
mA
Source current load:
VIN = VINmin to VINmax, ILMAX[1:0] = 00
650
VIN = VINmin to VINmax, ILMAX[1:0] = 01
1200
VIN = VINmin to VINmax, ILMAX[1:0] = 10
1700
mA
Sink current load:
VIN = VINmin to VINmax, ILMAX[1:0] = 00
800
VIN = VINmin to VINmax, ILMAX[1:0] = 01
1200
VIN = VINmin to VINmax, ILMAX[1:0] = 10
1700
DC load regulation
On mode, IOUT = 0 to IOUTmax
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
20
mV
50
mV
VIN = 3.8 V, VOUT = 1.8 V
Transient load regulation
IOUT = 0 to 500 mA , Max slew = 100 mA/µs
IOUT = 700 to 1200 mA , Max slew = 100 mA/µs
t on, off to on
IOUT = 200 mA
350
Overshoot
SMPS turned on
3%
Power-save mode Ripple voltage
Pulse skipping mode, IOUT = 1 mA
µs
0.025 ×
VOUT
Switching frequency
VPP
3
Duty cycle
MHz
100
Minimum On Time TON(MIN)
%
35
ns
1
MΩ
P-channel MOSFET
VFBIO internal resistance
Discharge resistor for power-down
sequence RDIS
0.5
During device switch-off sequence
30
50
Ω
Note: No discharge resistor is applied if VIO is
turned off while the device is on.
20
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
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SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
VIO SMPS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Ground current (IQ)
TEST CONDITIONS
MIN
TYP
Off
MAX
UNIT
1
PWM mode, IOUT = 0 mA, VIN = 3.8 V,
VIO_PSKIP = 0
7500
Pulse skipping mode, no switching, 3-MHz clock
on
250
µA
Low-power (pulse skipping) mode, no switching
ST[1:0]=11
Conversion efficiency
63
PWM mode, DCRL < 50 mΩ, VOUT = 1.8 V, VIN
= 3.6 V:
IOUT = 10 mA
44%
IOUT = 100 mA
87%
IOUT = 400 mA
86%
IOUT = 800 mA
76%
IOUT = 1000 mA
72%
Pulse Skipping mode, DCRL < 50 mΩ, VOUT =
1.8 V, VIN = 3.6 V:
IOUT = 1 mA
71%
IOUT = 10 mA
80%
IOUT = 200 mA
87%
Specifications
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Copyright © 2010–2014, Texas Instruments Incorporated
21
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SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
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5.15 VDD1 SMPS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCC1 and VCC7) VIN
TEST CONDITIONS
IOUT ≤ 1200 mA
VOUT = 0.6 V to 1.5 V, VGAIN_SEL = 00,
IOUT > 1200 mA
2.5 V ≤ VOUT ≤ 3.3 V, VGAIN_SEL = 10 or 11,
IOUT > 1200 mA
DC output voltage (VOUT)
MIN
TYP
MAX
2.7
5.5
VOUT + 2 V
5.5
4.5
5.5
UNIT
V
VGAIN_SEL = 00, IOUT = 0 to IOUTmax:
max programmable voltage, SEL[6:0] = 1001011
1.5
default voltage, BOOT[1:0] = 00
–3%
1.2
+3%
default voltage, BOOT[1:0] = 01
–3%
1.2
+3%
V
min programmable voltage, SEL[6:0] = 0000011
0.6
SEL[6:0] = 000000: power down
0
VGAIN_SEL = 10, SEL = 0101011 = 43, IOUT = 0
to IOUTmax
–3%
2.2
+3%
V
VGAIN_SEL = 11, SEL = 0101000 = 40, IOUT = 0
to IOUTmax
–3%
3.2
+3%
V
DC output voltage programmable
step (VOUTSTEP)
VGAIN_SEL = 00, 72 steps
Rated output current IOUTmax
ILMAX = 0, default
1000
ILMAX = 1
1500
12.5
mV
mA
P-channel MOSFET
VIN = VINmin
300
On-resistance RDS(ON)_PMOS
VIN = 3.8 V
250
P-channel leakage current
VIN = VINmax, SW1 = 0 V
400
2
mΩ
µA
ILK_PMOS
N-channel MOSFET
VIN = VMIN
300
On-resistance RDS(ON)_NMOS
VIN = 3.8 V
250
N-channel leakage current ILK_NMOS
VIN = VINmax, SW1 = VINmax
PMOS current limit (high-side)
VIN = VINmin to VINmax, ILMAX = 0
1150
VIN = VINmin to VINmax, ILMAX = 1
2000
NMOS current limit (low-side)
400
2
mΩ
µA
mA
Source current load:
VIN = VINmin to VINmax, ILMAX = 0
1150
VIN = VINmin to VINmax, ILMAX = 1
2000
mA
Sink current load:
VIN = VINmin to VINmax, ILMAX = 0
1200
VIN = VINmin to VINmax, ILMAX = 1
2000
DC load regulation
On mode, IOUT = 0 to IOUTmax
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
20
mV
Transient load regulation
VIN = 3.8 V, VOUT = 1.2 V
50
mV
IOUT = 0 to 500 mA , Max slew = 100 mA/µs
IOUT = 700 mA to 1.2A , Max slew = 100 mA/µs
t on, off to on
IOUT = 200 mA
Output voltage transition rate
From VOUT = 0.6 V to 1.5 V and VOUT = 1.5 V to
0.6 V IOUT = 500 mA
Overshoot
Switching frequency
22
TSTEP[2:0] = 001
12.5
TSTEP[2:0] = 011 (default)
7.5
TSTEP[2:0] = 111
2.5
SMPS turned on
Power-save mode ripple voltage
Specifications
350
Pulse skipping mode, IOUT = 1 mA
µs
mV/µs
3%
0.025 ×
VOUT
VPP
3
MHz
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
VDD1 SMPS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Duty cycle
MAX
UNIT
100
Minimum on time tON(MIN)
%
35
ns
1
MΩ
P-channel MOSFET
VFB1 internal resistance
0.5
Discharge resistor for power-down
sequence RDIS
Ground current (IQ)
30
Off
PWM mode, IOUT = 0 mA, VIN = 3.8 V,
VDD1_PSKIP = 0
Pulse skipping mode, no switching
50
Ω
1
7500
78
µA
Low-power (pulse skipping) mode, no switching
ST[1:0] = 11
Conversion efficiency
63
PWM mode, DCRL < 0.1 Ω, VOUT = 1.2 V,
VIN = 3.6 V:
IOUT = 10 mA
35%
IOUT = 200 mA
82%
IOUT = 400 mA
81%
IOUT = 800 mA
74%
IOUT = 1500 mA
62%
Pulse skipping mode, DCRL < 0.1Ω, VOUT = 1.2
V, VIN = 3.6 V:
IOUT = 1 mA
59%
IOUT = 10 mA
70%
IOUT = 200 mA
82%
Specifications
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
23
TPS65910, TPS65910A, TPS65910A3, TPS659101
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SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
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5.16 VDD2 SMPS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input voltage (VCC2 and VCC4) VIN IOUT ≤ 1200 mA
VOUT = 0.6 V to 1.5 V, VGAIN_SEL = 00,
IOUT > 1200 mA
2.5 V ≤ VOUT ≤ 3.3 V, VGAIN_SEL = 10 or 11,
IOUT > 1200 mA
DC output voltage (VOUT)
MIN
TYP
2.7
5.5
VOUT + 2
V
5.5
4.5
5.5
UNIT
V
VGAIN_SEL = 00, IOUT = 0 to IOUTmax:
max programmable voltage, SEL[6:0] = 1001011
default, BOOT[1:0] = 01
1.5
–3%
min programmable voltage, SEL[6:0] = 0000011
1.2
+3%
0.6
SEL[6:0] = 000000: power down
V
0
VGAIN_SEL = 10, SEL = 0101011 = 43
–3%
2.2
+3%
VGAIN_SEL = 11, default, BOOT[1:0] = 00
–3%
3.3
+3%
DC output voltage programmable
step (VOUTSTEP)
VGAIN_SEL = 00, 72 steps
Rated output current IOUTmax
ILMAX = 0, default
1000
ILMAX = 1
1500
12.5
mV
mA
P-channel MOSFET
VIN = VINmin
300
On-resistance RDS(ON)_PMOS
VIN = 3.8 V
250
P-channel leakage current ILK_PMOS
VIN = VINmax, SW2 = 0 V
N-channel MOSFET
VIN = VMIN
300
On-resistance RDS(ON)_NMOS
VIN = 3.8 V
250
N-channel leakage current ILK_NMOS
VIN = VINmax, SW2 = VINmax
PMOS current limit (high-side)
VIN = VINmin to VINmax, ILMAX = 0
1150
VIN = VINmin to VINmax, ILMAX = 1
2200
Source current load:
1150
VIN = VINmin to VINmax, ILMAX = 0
2000
NMOS current limit (low-side)
MAX
400
2
400
2
mΩ
µA
mΩ
µA
mA
VIN = VINmin to VINmax, ILMAX = 1
mA
Sink current load:
VIN = VINmin to VINmax, ILMAX = 0
1200
VIN = VINmin to VINmax, ILMAX = 1
2000
DC load regulation
On mode, IOUT = 0 to IOUTmax
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
20
mV
Transient load regulation
VIN = 3.8 V, VOUT = 1.2 V
50
mV
IOUT = 0 to 500 mA , Max slew = 100 mA/µs
IOUT = 700 mA to 1.2 A , Max slew = 100 mA/µs
t on, off to on
IOUT = 200 mA
Output voltage transition rate
From VOUT = 0.6 V to 1.5 V and VOUT = 1.5 V to
0.6 V IOUT = 500 mA
Power-save mode ripple voltage
Overshoot
350
TSTEP[2:0] = 001
12.5
TSTEP[2:0] = 011 (default)
7.5
TSTEP[2:0] = 111
2.5
Pulse skipping mode, IOUT = 1 mA
µs
0.025
VOUT
VPP
3%
Switching frequency
3
Duty cycle
MHz
100
Minimum On time
P-Channel MOSFET
24
µs
Specifications
35
%
ns
Copyright © 2010–2014, Texas Instruments Incorporated
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Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
VDD2 SMPS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VFB2 internal resistance
Discharge resistor for power-down
sequence RDIS
Ground current (IQ)
MIN
TYP
0.5
1
30
Off
PWM mode, IOUT = 0 mA, VIN = 3.8 V,
VDD2_PSKIP = 0
Pulse skipping mode, no switching
MAX
UNIT
MΩ
50
Ω
1
7500
78
µA
Low-power (pulse skipping) mode, no switching
ST[1:0] = 11
Conversion efficiency
63
PWM mode, DCRL < 50 mΩ, VOUT = 1.2 V,
VIN = 3.6 V:
IOUT = 10 mA
35%
IOUT = 200 mA
82%
IOUT = 400 mA
81%
IOUT = 800 mA
74%
IOUT = 1200 mA
66%
IOUT = 1500 mA
62%
Pulse skipping mode mode, DCRL < 50 mΩ, VOUT
= 1.2 V, VIN = 3.6 V:
IOUT = 1 mA
59%
IOUT = 10 mA
70%
IOUT = 200 mA
82%
PWM mode, DCRL < 50 mΩ, VOUT = 3.3 V,
VIN = 5 V:
IOUT = 10 mA
44%
IOUT = 200 mA
90%
IOUT = 400 mA
91%
IOUT = 800 mA
88%
IOUT = 1200 mA
84%
IOUT = 1500 mA
81%
Pulse skipping mode mode, DCRL < 50 mΩ,
VOUT = 3.3 V, VIN = 5 V:
IOUT = 1 mA
75%
IOUT = 10 mA
83%
IOUT = 200 mA
90%
Specifications
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Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
25
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
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5.17 VDD3 SMPS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input voltage VIN
MIN
MAX
UNIT
5.5
V
5
5.25
3
DC output voltage (VOUT)
4.65
Rated output current IOUTmax
100
N-channel MOSFET
TYP
VIN = 3.6 V
V
mA
500
mΩ
On-resistance RDS(ON)_NMOS
N-channel MOSFET leakage
current ILK_NMOS
VIN = VINmax, SW3 = VINmax
N-channel MOSFET DC current
limit
VIN = VINmin to VINmax, sink current load
Turn-on inrush current
VIN = VINmin to VINmax
Ripple voltage
2
430
550
µA
mA
850
20
mA
mV
DC load regulation
On mode, IOUT = 0 to IOUTmax
100
mV
DC line regulation
On mode, VIN = VINmin to 5 V at IOUT = IOUTmax
100
mV
Turn-on time
IOUT = 8 mA, VOUT = 0 to 4.4 V
Overshoot
µs
3%
Switching frequency
VFB3 internal resistance
Ground current (IQ)
Conversion efficiency
Specifications
1
MHz
088
MΩ
Off
IOUT = 0 mA to IOUTmax, VIN = 3.6 V
26
200
1
360
µA
VIN = 3.6 V:
IOUT = 10 mA
81%
IOUT = 50 mA
85%
IOUT = 100 mA
85%
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
5.18 VDIG1 and VDIG2 LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCC6) VIN
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT (VDIG1) = 1.2 V at 300 mA / 1.5 V at 100
mA and
VOUT (VDIG2) = 1.2 V / 1.1 V / 1.0 V at 300 mA
1.7
5.5
VOUT (VDIG1) = 1.5 V and VOUT (VDIG2) = 1.8 V
at 200mA
2.1
5.5
VOUT (VDIG1) = 1.8 V and VOUT (VDIG2) = 1.8 V
2.7
5.5
VOUT (VDIG1) = 2.7 V
3.2
5
V
VDIG1
DC output voltage VOUT
Rated output current IOUTmax
On and Low-power mode, VIN = VINmin to VINmax
SEL = 11, IOUT = 0 to IOUTmax
–3%
2.7
+3%
SEL = 10 IOUT = 0 to IOUTmax
–3%
1.8
+3%
SEL = 01 IOUT = 0 to 100 mA/IOUTmax
–3%
1.5
+3%
SEL = 00, IOUT = 0 to IOUTmax, VIN = VINmin to 4 V,
default BOOT[1:0] = 00 or 01
–3%
1.2
+3%
On mode
300
Low-power mode
Load current limitation (short-circuit
On mode, VOUT = VOUTmin – 100 mV
protection)
Dropout voltage VDO
mA
1
350
V
600
mA
On mode, VDO = VIN – VOUT
VOUTtyp = 2.7 V, VIN = 2.8 V, IOUT = IOUTmax, T =
25°C
150
VOUTtyp = 1.5 V, VIN = 1.7 V, IOUT = IOUTmax, T =
25°C
300
mV
DC load regulation
On mode, IOUT = IOUTmax to 0
25
mV
DC line regulation
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
3
mV
Transient load regulation
On mode, VIN = 3.8 V
10
mV
2
mV
100
µs
300
mA
IOUT = 20 mA to 180 mA in 5µs and
IOUT = 180 mA to 20 mA in 5 µs
Transient line regulation
On mode, VIN = 2.7 + 0.5 V to 2.7 in 30 µs,
And VIN = 2.7 to 2.7 + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
Turn-on inrush current
Ripple rejection
VIN = VINDC + 100 mVpp tone, VINDC+= 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VDIG1 internal resistance
LDO off
400
Ground current
On mode, IOUT = 0, VCC6 = VBAT, VOUT = 2.7 V
54
On mode, IOUT = 0, VCC6 = 1.8 V, VOUT = 1.2 V
67
On mode, IOUT = IOUTmax, VCC6 = VBAT, VOUT =
2.7 V
1870
On mode, IOUT = IOUTmax, VCC6 = 1.8 V, VOUT =
1.2 V
1300
Low-power mode, VCC6 = VBAT, VOUT = 2.7 V
13
Low-power mode, VCC6 = 1.8 V, VOUT = 1.2 V
10
Off mode
dB
Ω
µA
1
Specifications
Submit Documentation Feedback
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
27
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
VDIG1 and VDIG2 LDO (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
SEL = 11, IOUT = 0 to IOUTmax
–3%
1.8
+3%
SEL = 10 IOUT = 0 to IOUTmax, VIN = VINmin to 4 V
–3%
1.2
+3%
SEL = 01 IOUT = 0 to 100 mA/IOUTmax, VIN= VINmin
to 4 V
–3%
1.1
+3%
SEL = 00, IOUT = 0 to IOUTmax, VIN = VINmin to 4 V,
default BOOT[1:0] = 00 or 01
–3%
1
+3%
On mode
300
UNIT
VDIG2
DC output voltage VOUT
Rated output current IOUTmax
On and low-power mode, VIN = VINmin to VINmax
Low-power mode
Load current limitation (short-circuit
On mode, VOUT = VOUTmin – 100 mV
protection)
Dropout voltage VDO
V
mA
1
350
600
mA
250
mV
On mode, VDO = VIN – VOUT,
VOUTtyp = 1.8 V, VIN = 2.1 V, IOUT=IOUTmax, T =
25°C
DC load regulation
On mode, IOUT = IOUTmax to 0
DC line regulation
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
Transient load regulation
On mode, VIN = 3.8 V
25
mV
3
mV
10
mV
2
mV
IOUT = 20 mA to 180 mA in 5 µs and
IOUT = 180 mA to 20 mA in 5 µs
Transient line regulation
On mode, VIN = 2.7 + 0.5 V to 2.7 in 30 µs,
And VIN = 2.7 to 2.7 + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
Turn-on inrush current
Ripple rejection
100
µs
300
mA
VIN = VINDC + 100 mVpp tone, VINDC+= 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VDIG2 internal resistance
LDO off
400
Ground current
On mode, IOUT = 0, VCC6 = VBAT, VOUT = 1.8 V
52
On mode, IOUT = 0, VCC6 = 1.8 V, VOUT = 1.0 V
67
On mode, IOUT = IOUTmax, VCC6 = VBAT, VOUT =
1.8 V
1750
On mode, IOUT = IOUTmax, VCC6 = 1.8 V, VOUT =
1.0 V
1300
Low-power mode, VCC6 = VBAT, VOUT = 1.8 V
11
Low-power mode, VCC6 = 1.8 V, VOUT = 1.0 V
10
Off mode
28
Specifications
dB
Ω
µA
1
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
5.19 VAUX33 and VMMC LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCC3) VIN
TEST CONDITIONS
MIN
TYP
MAX
VOUT (VAUX33) = 1.8 V / 2 V and VOUT (VMMC) =
1.8 V
2.7
5.5
VOUT (VAUX33) = 2.8 V
3.2
5.5
VOUT (VAUX33) = 3.3 V
3.6
5.5
VOUT (VMMC) = 2.8 V at 200 mA
3.2
5.5
VOUT (VMMC) = 3.0 V
3.6
5.5
VOUT (VMMC) = 3.3 V at 200 mA
3.6
5.5
UNIT
V
VAUX33
DC output voltage VOUT
Rated output current IOUTmax
On and low-power mode, VIN = VINmin to VINmax
SEL = 11, IOUT = 0 to IOUTmax, Default BOOT[1:0] =
01
–3%
3.3
+3%
SEL = 10, IOUT = 0 to IOUTmax
–3%
2.8
+3%
SEL = 01, IOUT = 0 to IOUTmax
–3%
2.0
+3%
SEL = 00, IOUT = 0 to IOUTmax, default BOOT[1:0] =
00
–3%
1.8
+3%
On mode
150
Low-power mode
mA
1
Load current limitation (shortcircuit protection)
On mode, VOUT = VOUTmin – 100 mV
Dropout Voltage VDO
On mode, VOUTtyp = 2.8 V, VDO = VIN – VOUT,
350
VIN = 2.9 V, IOUT = IOUTmax, T = 25°C
V
500
mA
150
mV
DC load regulation
On mode, IOUT = IOUTmax to 0
20
mV
DC line regulation
On mode, IOUT = IOUTmax
3
mV
Transient load regulation
On mode, VIN = 3.8 V
12
mV
2
mV
IOUT = 0.1 × IOUTmax to 0.9 × IOUTmax in 5 µs and
IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
Transient line regulation
On mode, IOUT = IOUTmax,VIN = VINmin + 0.5 V to
VINmin in 30 µs
and VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
Turn-on inrush current
Ripple Rejection
100
µs
600
mA
VIN = VINDC + 100 mVpp tone, VINDC+ = 3.8 V, IOUT
= IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VAUX33 internal resistance
LDO off
70
Ground current
On mode, IOUT = 0
55
On mode, IOUT = IOUTmax
dB
Ω
1600
Low-power mode
µA
15
Off mode
1
VMMC
DC output voltage VOUT
On and low-power mode, VIN = VINmin to VINmax
SEL = 11, IOUT = 0 to 200 mA, default BOOT[1:0] =
00
–3%
3.3
+3%
SEL = 10, IOUT = 0 to IOUTmax
–3%
3.0
+3%
SEL = 01, IOUT = 0 to 200 mA
–3%
2.8
+3%
SEL = 00, IOUT = 0 to IOUTmax, default BOOT[1:0] =
01
–3%
1.8
+3%
Specifications
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
V
29
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
VAUX33 and VMMC LDO (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Rated output current IOUTmax
TEST CONDITIONS
On mode
Low-power mode
Load current limitation (shortcircuit protection)
On mode, VOUT = VOUTmin – 100 mV
Dropout voltage VDO
Dropout voltage VDO
VIN = 3.0 V, IOUT = 200 mA, T = 25°C
MIN
TYP
MAX
300
mA
1
350
UNIT
500
mA
200
mV
DC load regulation
On mode, IOUT = IOUTmax to 0
25
mV
DC line regulation
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
3
mV
Transient load regulation
On mode, VIN = 3.8 V
12
mV
2
mV
100
µs
IOUT = 20 mA to 180 mA in 5 µs and IOUT = 180 mA
to 20 mA in 5 µs
Transient line regulation
On mode, IOUT = 200 mA, VIN = VINmin + 0.5 V to
VINmin in 30 µs
And VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
Ripple rejection
VIN = VINDC + 100 mVpp tone, VINDC+= 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VMMC internal resistance
LDO Off
70
Ground current
On mode, IOUT = 0
55
On mode, IOUT = IOUTmax
Low-power mode
Off mode
30
Specifications
dB
Ω
2700
µA
15
1
Copyright © 2010–2014, Texas Instruments Incorporated
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Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
5.20 VAUX1 and VAUX2 LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCC4) VIN
TEST CONDITIONS
MIN
TYP
MAX
VOUT (VAUX1) = 1.8 V and VOUT (AUX2) = 1.8 V
2.7
5.5
VOUT (VAUX1) = 2.5 V
3.2
5.5
VOUT (VAUX1) = 2.8 V at Iload = 200 mA and 2.85 V
at Iload = 200mA
3.2
5.5
VOUT (VAUX2) = 2.8 V
3.2
5.5
VOUT (VAUX2) = 2.9 V at Iload = 100mA
3.2
5.5
VOUT (VAUX2) = 3.3 V
3.6
5.5
UNIT
V
VAUX1
DC output voltage VOUT
Rated output current IOUTmax
On and low-power mode, VIN = VINmin to VINmax
SEL = 11, IOUT = 0 to 200 mA
–3%
2.85
+3%
SEL = 10, IOUT = 0 to 200 mA
–3%
2.8
+3%
SEL = 01, IOUT = 0 to IOUTmax
–3%
2.5
+3%
SEL = 00, IOUT = 0 to IOUTmax, default BOOT[1:0] =
00 or 01
–3%
1.8
+3%
On mode
300
Low-power mode
mA
1
Load current limitation (shortcircuit protection)
On mode, VOUT = VOUTmin – 100 mV
Dropout voltage VDO
On mode, VOUTtyp = 2.8 V, VDO = VIN – VOUT,
350
VIN = 3.0 V, IOUT = 200 mA, T = 25°C
V
500
mA
200
mV
DC load regulation
On mode, IOUT = 200 mA to 0
15
mA
DC line regulation
On mode, IOUT = 200 mA
5
V
Transient load regulation
On mode, VIN = 3.8 V, IOUT = 20 mA to 180 mA in 5
µs
15
mV
2
mV
and IOUT = 180 mA to 20 mA in 5µs
Transient line regulation
On mode, IOUT = 200 mA, VIN= VINmin + 0.5 V to
VINmin in 30 µs
and VIN = VINmin to VINmin + 0.5v in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, at VOUT = 0.1 V up to VOUTmin, no load
Turn-on inrush current
Ripple Rejection
100
µs
600
mA
VIN = VINDC + 100 mVpp tone, VINDC+ = 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VAUX1 internal resistance
LDO Off
80
Ground current
On mode, IOUT = 0
60
On mode, IOUT = IOUTmax
dB
Ω
2700
Low-power mode
µA
12
Off mode
1
VAUX2
On and low-power mode, VIN = VINmin to VINmax
Rated output current IOUTmax
SEL = 11, IOUT = 0 to IOUTmax
–3%
3.3
+3%
SEL = 10, IOUT = 0 to 100 mA
–3%
2.9
+3%
SEL = 01, IOUT = 0 to IOUTmax
–3%
2.8
+3%
SEL = 00, IOUT = 0 to IOUTmax, default BOOT[1:0] =
00 or 01
–3%
1.8
+3%
On mode
300
Low-power mode
1
Specifications
Submit Documentation Feedback
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
V
mA
31
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
VAUX1 and VAUX2 LDO (continued)
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
Load current limitation (shortcircuit protection)
PARAMETER
MAX
UNIT
On mode, VOUT = VOUTmin – 100 mV
350
500
mA
Dropout voltage VDO
On mode, VOUTtyp = 2.8 V, VDO = VIN – VOUT
150
mV
VIN = 2.9 V, IOUT = IOUTmax, T = 25°C
DC load regulation
On mode, IOUT = IOUTmax to 0
15
mV
DC line regulation
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
2
mV
Transient load regulation
On mode, VIN = 3.8 V, IOUT = 0.1 × IOUTmax to 0.9 ×
IOUTmax in 5µs
12
mV
2
mV
And IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5us
Transient line regulation
On mode, IOUT = IOUTmax, VIN = VINmin + 0.5 V to
VINmin in 30 µs
And VIN= VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
Turn-on Inrush current
Ripple rejection
100
µs
600
mA
VIN = VINDC + 100 mVpp tone, VINDC+ = 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VAUX2 internal resistance
LDO off
80
Ground current
On mode, IOUT = 0
60
On mode, IOUT = IOUTmax
Low-power mode
Off mode
32
Specifications
dB
Ω
1600
µA
12
1
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
5.21 VDAC and VPLL LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage (VCC5) VIN
TEST CONDITIONS
MIN
TYP
MAX
VOUT(VDAC) = 1.8 V and VOUT(VPLL) = 1.8 V / 1.1 V
/ 1.0 V
2.7
5.5
VOUT(VDAC) = 2.6 V and VOUT(VPLL) = 2.5 V
3.0
5.5
VOUT(VDAC) = 2.8 V / 2.85 V
3.2
5.5
UNIT
V
VDAC
DC Output voltage VOUT
Rated output current IOUTmax
On and low-power mode, VIN = VINmin to VINmax
SEL = 11, IOUT = 0 to IOUTmax
–3%
2.85
+3%
SEL = 10, IOUT = 0 to IOUTmax
–3%
2.8
+3%
SEL = 01, IOUT = 0 to IOUTmax
–3%
2.6
+3%
SEL = 00, IOUT = 0 to IOUTmax, default BOOT[1:0] =
00 or 01
–3%
1.8
+3%
On mode
150
Low-power mode
Load current limitation (shortcircuit protection)
On mode, VOUT = VOUTmin – 100 mV
Dropout Voltage VDO
On mode, VOUTtyp = 2.8 V, VDO = VIN – VOUT,
mA
1
350
V
500
mA
150
mV
VIN = 2.9 V, IOUT = IOUTmax, T = 25°C
DC load regulation
On mode, VOUT = VOUTmin – 100 mV
15
mV
DC line regulation
On mode, VOUT = 1.8 V, IOUT = IOUTmax
2
mV
Transient load regulation
On mode, VIN = 3.8 V, IOUT = 0.1 × IOUTmax to 0.9 ×
IOUTmax in 5 µs
15
mV
0.5
mV
And IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
Transient line regulation
On mode, IOUT = IOUTmax, VIN = VINmin + 0.5 V to
VINmin in 30 µs
And VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
Turn-on Inrush current
Ripple Rejection
100
µs
600
mA
VIN = VINDC + 100 mVpp tone, VINDC+ = 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VDAC internal resistance
LDO off
360
Ground current
On mode, IOUT = 0
60
On mode, IOUT = IOUTmax
Low-power mode
Off mode
dB
kΩ
1600
µA
12
1
Specifications
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
33
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
VDAC and VPLL LDO (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
SEL = 11, IOUT = 0 to IOUTmax
–3%
2.5
+3%
SEL = 10, IOUT = 0 to IOUTmax, default BOOT[1:0 = 00
or 01
–3%
1.8
+3%
SEL = 01, IOUT = 0 to IOUTmax
–3%
1.1
+3%
SEL = 00, IOUT = 0 to IOUTmax
–3%
1.0
+3%
UNIT
VPLL
DC output voltage VOUT
Rated output current IOUTmax
On and low-power mode, VIN = VINmin to VINmax
On mode
50
Low-power mode
1
Load current limitation (shortcircuit protection)
On mode, VOUT = VOUTmin – 100 mV
Dropout voltage VDO
On mode, VOUTtyp = 2.5 V, VDO = VIN – VOUT,
200
V
mA
400
mA
100
mV
VIN = 2.5 V, IOUT = IOUTmax, T = 25°C
DC load regulation
On mode, IOUT = IOUTmax to 0
10
mV
DC line regulation
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
1
mV
Transient load regulation
On mode, VIN = 3.8 V, IOUT = 0.1 × IOUTmax to 0.9 ×
IOUTmax in 5 µs
9
mV
0.5
mV
And IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
Transient line regulation
On mode, VIN = VINmin + 0.5 V to VINmin in 30 µs
And VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
Turn-on in rush current
Ripple rejection
100
µs
300
mA
VIN = VINDC + 100 mVpp tone, VINDC+ = 3.8 V, IOUT =
IOUTmax/2
f = 217 Hz
70
f = 50 kHz
40
VPLL internal resistance
LDO off
535
Ground current
On mode, IOUT = 0
60
On mode, IOUT = IOUTmax
Low-power mode
Off mode
34
Specifications
dB
kΩ
1600
µA
12
1
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
5.22 Timing and Switching Characteristics
5.22.1 Switch-On/-Off Sequences and Timing
Time slot length can be selected to be 0.5 ms or 2 ms through the EEPROM for an OFF-to-ACTIVE transition or
through the value programmed in the register DEVCTRL2_REG for a SLEEP-to-ACTIVE transition.
5.22.1.1 BOOT1 = 0, BOOT0 = 0
Table 5-1 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this
boot mode is provided in Figure 5-1.
Table 5-1. Fixed Boot Mode: 00
Register
VDD1_OP_REG
VDD1_REG
Bit
SEL
VGAIN_SEL
EEPROM
Description
VDD1 voltage level selection for boot
VDD1 gain selection, x1 or x2
VDD1 time slot selection
DCDCCTRL_REG
VDD2_OP_REG/VDD2_SR_REG
VDD2_REG
VDD1_PSKIP
SEL
VGAIN_SEL
EEPROM
VDD1 pulse skip mode enable
VDD2 voltage level selection for boot
VDD2 Gain selection, x1 or x3
VDD2 time slot selection
DCDCCTRL_REG
VIO_REG
VDD2_PSKIP
SEL
EEPROM
VDD2 pulse skip mode enable
VIO voltage selection
VIO time slot selection
DCDCCTRL_REG
VIO_PSKIP
EEPROM
VDIG1_REG
SEL
EEPROM
VDIG2_REG
SEL
EEPROM
VDAC_REG
SEL
EEPROM
VIO pulse skip mode enable
SEL
EEPROM
SEL
EEPROM
SEL
EEPROM
SEL
EEPROM
VAUX2_REG
SEL
1.1 V
x3
2
skip enabled
1.8 V
1
skip enabled
1.2 V
LDO time slot
OFF
LDO voltage selection
1.0 V
LDO time slot
OFF
LDO voltage selection
1.8 V
LDO voltage selection
LDO voltage selection
LDO voltage selection
LDO time slot
VAUX33_REG
3
skip enabled
LDO voltage selection
LDO time slot
VMMC_REG
x1
OFF
LDO time slot
VAUX1_REG
1.2 V
VDD3 time slot
LDO time slot
VPLL_REG
TPS65910
Boot 00
LDO voltage selection
5
1.8 V
4
1.8 V
1
3.3 V
6
1.8 V
LDO time slot
OFF
LDO voltage selection
1.8 V
EEPROM
LDO time slot
5
CLK32KOUT pin
CLK32KOUT time slot
7
NRESPWRON pin
NRESPWRON time slot
VRTC_OFFMAS
K
VRTC_REG
DEVCTRL_REG
RTC_PWDN
DEVCTRL_REG
CK32K_CTRL
0: VRTC LDO will be in low-power mode during OFF state
1: VRC LDO will be in full-power mode during OFF state
0: RTC in normal power mode
1: Clock gating of RTC register and logic, low-power mode
0: Clock source is crystal/external clock
1: Clock source is internal RC oscillator
7+1
Low-power mode
1
RC
Specifications
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
35
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
Table 5-1. Fixed Boot Mode: 00 (continued)
Register
Bit
TPS65910
Boot 00
Description
Boot sequence time slot duration:
TSLOT_LENGTH
0: 0.5 ms
[0]
1: 2 ms
DEVCTRL2_REG
DEVCTRL2_REG
IT_POL
INT_MSK_REG
VMBHI_IT_MSK
2 ms
0: INT1 signal will be active-low
Active-low
1: INT1 signal will be active-high
0: Device will automatically switch-on at NOSUPPLY to
OFF or BACKUP to OFF transition
1: Startup reason required before switch-on
VMBCH_REG
VMBCH_SEL[1:0]
0: Automatic
switch-on from
supply insertion
Select threshold for main battery comparator threshold
VMBCH.
3V
Figure 5-1 shows the 00 Boot mode timing characteristics.
tdSOFF2
PWRHOLD
tdSON1
1.8 V
VIO/VFBIO
VAUX1
1.8 V
tdSON2
VDD2/VFB2
3.3 V
tdSON3
1.2 V
VDD1/VFB1
tdSON4
1.8 V
VPLL
tdSON5
VDAC
1.8 V
VAUX2
1.8 V
tdSON6
3.3 V
VMMC
tdSON7
tdSOFF1
CLK32KOUT
tdSON8
NRESPWRON
tdSONT: Switch-on sequence
Switch-off sequence
SWCS046-018
Figure 5-1. Boot Mode: BOOT1 = 0, BOOT0 = 0
36
Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
Table 5-2 lists the 00 Boot mode timing characteristics.
Table 5-2. Boot Mode: BOOT1 = 0, BOOT0 = 0 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdSON1
PWRHOLD rising edge to VIO, VAUX1 enable delay
66 × tCK32k = 2060
µs
tdSON2
VIO to VDD2 enable delay
64 × tCK32k = 2000
µs
tdSON3
VDD2 to VDD1 enable delay
64 × tCK32k = 2000
µs
tdSON4
VDD1 to VPLL enable delay
64 × tCK32k = 2000
µs
tdSON5
VPLL to VDAC,VAUX2 enable delay
64 × tCK32k = 2000
µs
tdSON6
VDAC to VMMC enable delay
64 × tCK32k = 2000
µs
µs
VMMC to CLK32KOUT rising edge delay
64 × tCK32k = 2000
tdSON8
CLK32KOUT to NRESPWRON rising edge delay
64 × tCK32k = 2000
µs
tdSONT
Total switch-on delay
16
ms
tdSOFF1
PWRHOLD falling edge to NRESPWRON falling edge
delay
2 × tCK32k = 62.5
µs
tdSOFF1B
NRESPWRON falling edge to CLK32KOUT low delay
3 × tCK32k = 92
µs
tdSOFF2
PWRHOLD falling edge to supplies and reference
disable delay
5 × tCK32k = 154
µs
Registers default setting: CK32K_CTRL = 1 (32-kHz RC oscillator is used), RTC_PWDN = 1 (RTC domain off),
IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on Battery plug),
VMBCH_SEL = 11.
Specifications
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37
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
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SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
5.22.1.2 BOOT1 = 0, BOOT0 = 1
Table 5-3 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this
boot mode is provided in Figure 5-2.
Table 5-3. Fixed Boot Mode: 01
Register
VDD1_OP_REG
VDD1_REG
Bit
SEL
VGAIN_SEL
EEPROM
Description
TPS65910
Boot 01
VDD1 voltage level selection for boot
1.2 V
VDD1 Gain selection, x1 or x2
x1
VDD1 time slot selection
DCDCCTRL_REG
VDD2_OP_REG/VDD2_SR_REG
VDD2_REG
VDD1_PSKIP
SEL
VGAIN_SEL
EEPROM
3
VDD1 pulse skip mode enable
Skip enabled
VDD2 voltage level selection for boot
1.2 V
VDD2 Gain selection, x1 or x3
x1
VDD2 time slot selection
DCDCCTRL_REG
VIO_REG
VDD2_PSKIP
SEL
EEPROM
4
VDD2 pulse skip mode enable
Skip enabled
VIO voltage selection
1.8 V
VIO time slot selection
DCDCCTRL_REG
VIO_PSKIP
EEPROM
VDIG1_REG
SEL
EEPROM
VDIG2_REG
SEL
EEPROM
VDAC_REG
SEL
EEPROM
VPLL_REG
SEL
EEPROM
1
VIO pulse skip mode enable
Skip enabled
VDD3 time slot
OFF
LDO voltage selection
1.2 V
LDO time slot
OFF
LDO voltage selection
1.0 V
LDO time slot
OFF
LDO voltage selection
1.8 V
LDO time slot
OFF
LDO voltage selection
1.8 V
LDO time slot
VAUX1_REG
SEL
EEPROM
VMMC_REG
SEL
EEPROM
VAUX33_REG
SEL
EEPROM
2
LDO voltage selection
1.8 V
LDO time slot
OFF
LDO voltage selection
1.8 V
LDO time slot
OFF
LDO voltage selection
3.3 V
LDO time slot
VAUX2_REG
SEL
6
LDO voltage selection
1.8 V
EEPROM
LDO time slot
5
CLK32KOUT pin
CLK32KOUT time slot
7
NRESPWRON pin
NRESPWRON time slot
VRTC_OFFMAS
K
VRTC_REG
DEVCTRL_REG
RTC_PWDN
DEVCTRL_REG
CK32K_CTRL
DEVCTRL2_REG
DEVCTRL2_REG
38
Specifications
7+1
0: VRTC LDO will be in low-power mode during OFF state
1: VRC LDO will be in full-power mode during OFF state
low-power mode
0: RTC in normal power mode
1
1: Clock gating of RTC register and logic, low-power mode
0: Clock source is crystal/external clock
Crystal
1: Clock source is internal RC oscillator
Boot sequence time slot duration:
TSLOT_LENGTH
0: 0.5 ms
[0]
1: 2 ms
IT_POL
0: INT1 signal will be active-low
1: INT1 signal will be active-high
2 ms
Active-low
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TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
Table 5-3. Fixed Boot Mode: 01 (continued)
Register
Bit
INT_MSK_REG
TPS65910
Boot 01
Description
VMBHI_IT_MSK
0: Device will automatically switch-on at NOSUPPLY to
OFF or BACKUP to OFF transition
0: Automatic
switch-on from
supply insertion
1: Startup reason required before switch-on
VMBCH_REG
VMBCH_SEL[1:0]
Select threshold for main battery comparator threshold
VMBCH.
3V
Figure 5-2 shows the 01 Boot mode timing characteristics.
tdSOFF2
PWRHOLD
tdSON1
VIO/VFBIO
1.8 V
tdSON2
VPLL
1.8 V
tdSON3
1.2 V
VDD1/VFB1
tdSON4
1.2 V
VDD2/VFB2
tdSON5
VAUX2
1.8 V
tdSON6
VAUX33
3.3 V
tdSON7
tdSOFF1
CLK32KOUT
tdSON8
NRESPWRON
tdSONT: Switch-on sequence
Switch-off sequence
SWCS046-019
Figure 5-2. Boot Mode: BOOT1 = 0, BOOT0 = 1
Table 5-4 lists the 01 Boot mode timing characteristics.
Table 5-4. Boot Mode: BOOT1 = 0, BOOT0 = 1 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdSON1
PWRHOLD rising edge to VIO enable delay
66 × tCK32k = 2060
µs
tdSON2
VIO to VPLL enable delay
64 × tCK32k = 2000
µs
tdSON3
VPLL to VDD1 enable delay
64 × tCK32k = 2000
µs
tdSON4
VDD1 to VDD2 enable delay
64 × tCK32k = 2000
µs
tdSON5
VDD2 to VAUX2 enable delay
64 × tCK32k = 2000
µs
tdSON6
VAUX2 to VAUX33 enable delay
64 × tCK32k = 2000
µs
tdSON7
VAUX33 to CLK32KOUT enable delay
64 × tCK32k = 2000
µs
tdSON8
CLK32KOUT to NRESPWRON enable delay
64 × tCK32k = 2000
µs
tdSONT
Total switch-on delay
16
ms
tdSOFF1
PWRHOLD falling edge to NRESPWRON falling edge
2 × tCK32k = 62.5
µs
tdSOFF1B
NRESPWRON falling edge to CLK32KOUT low delay
3 × tCK32k = 92
µs
tdSOFF2
PWRHOLD falling edge to supplies disable delay
5 × tCK32k = 154
µs
Registers default setting: CK32K_CTRL = 0 (32-kHz quartz or external bypass clock is used), RTC_PWDN = 1
(RTC domain off), IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on
battery plug), VMBCH_SEL = 11.
Specifications
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
39
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
5.22.2 Power Control Timing
5.22.2.1 Device Turn-On/Off With Rising/Falling Input Voltage
Figure 5-3 shows the device turn-on/-off with rising/falling input voltage.
VMBCH threshold
VMBDCH threshold
VMBLO threshold
VMBHI threshold
VBNPR threshold
VCC7
VRTC
1.8V
VBACKUP > VBNPR
VIO
1.8V
CLK33KOUT
t dOINT1
NRESPWRON
t dbVMBLO
(1)
Interrupt aknowledge
INT1
t dbVMBDCH
VMBHI_IT=1
PWRHOLD
t d32KON
t dbVMBHI
t dSONT
Switch-on sequence
Switch-off sequence
t dONVMBHI
SWCS046-022
NOTE: (1) The DEV_ON control bit (set to 1) or the PWRHOLD signal (set high) can be used to maintain supplies on after
the switch-on sequence. If none of these devices Power-on enable conditions are set, the supplies will be turned off
after tdOINT1 delay.
Figure 5-3. Device Turn-On/Off with Rising/Falling Input Voltage
5.22.2.2 Device State Control Through PWRON Signal
Figure 5-4 shows the device state control through PWRON signal.
PWRON
VIO
1.8 V
CLK33KOUT
t dOINT1
NRESPWRON
(1)
Interrupt acknowledge
INT1
PWRON_IT=1
Interrupt acknowledge
PWRON_IT=1
PWRHOLD
t dbPWRHOLDF
t dbPWRONF
t dSONT
Switch-on sequence
t dONPWHOLD
t dbPWRONF
Switch-off
sequence
SWCS046-009
NOTE: (1) The DEV_ON control bit (set to 1) or the PWRHOLD signal (set high) can be used to maintain supplies on after
switch-on sequence, If none of these devices POWER-ON enable condition are set the supplies will be turned off
after TdOINT1 delay.
Figure 5-4. PWRON Turn-On/Turn-Off
40
Specifications
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TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
Figure 5-5 shows the long-press turn-off timing characteristics.
PWRON
VIO
NRESPWRON
INT1
PWRON_IT=1
PWRON_LP_IT=1
PWRON_IT=1
PWRHOLD
t dPWRONLP
Switch-off
sequence
t dPWRONLPTO
t dbPWRONF
SWCS046-010
NOTE: If the DEV_ON control bit is set to 1 or PWRHOLD is kept high, the device will be turned on again after PWRON long
press turn-off and PWRON released.
Figure 5-5. PWRON Long-Press Turn-Off
Table 5-5 lists the power control timing characteristics.
Table 5-5. Power Control Timing Characteristics
PARAMETER
td32KON: 32-kHz Oscillator turn-on time
TEST CONDITIONS
MIN
TYP
BOOT[1:0] = 00, RC oscillator
0.1
BOOT[1:0] = 01, Quartz
oscillator
400
BOOT[1:0] = 01, Bypass clock
MAX
UNIT
2000
ms
4 × tCK32k
= 125
µs
0.1
3×
tdbVMBHI: VMBHI rising-edge debouncing delay
tCK32k =
94
tdbVMBDCH: Main Battery voltage = VMBDCH threshold to INT1
falling-edge delay
3×
tCK32k =
94
4 × tCK32k
= 125
s
tdbVMBLO: Main Battery voltage = VMBLO threshold to
NRESPWRON falling-edge delay
3×
tCK32k =
94
4 × tCK32k
= 125
s
tdbPWRONF: PWRON falling-edge debouncing delay
500
550
ms
tdbPWRONR: PWRON rising-edge debouncing delay
3×
tCK32k=
94
4 × tCK32k
= 125
µs
tdbPWRHOLD: PWRON rising-edge debouncing delay
2×
tCK32k =
63
3×
tCK32k=
94
µs
tdOINT: INT1 (internal) Power-on pulse duration after PWRON
low-level (debounced) event
tdONPWHOLD: delay to set high PWRHOLD signal or DEV_ON
control bit after NRESPWRON released to keep on the supplies
1
s
984
ms
tdPWRONLP: PWRON long-press delay to interrupt
PWRON falling edge to
PWON_LP_IT = 1
6
s
tdPWRONLPTO: PWRON long-press delay to turn-off
PWRON falling edge to
NRESPWRON falling edge
8
s
Specifications
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
41
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
5.22.2.3 Device SLEEP State Control
Figure 5-6 shows the device SLEEP state control timing characteristics.
tACT2SLP
tSLP2ACT
SLEEP
1.8 V
PWM mode
1.8 V
Low-power mode
1.8 V
PWM mode
1.8 V
Active mode
1.8 V
Low-power mode
1.8 V
Active mode
3.3 V
Pulse skip mode
3.3 V
Low-power mode
3.3 V
Pulse skip mode
VIO/VFBIO
SWIO
VAUX1
VDD2/VFB2
SW2
1.2 V
PWM mode
Off
VPLL
1.8 V
Active mode
Off
VDD1/VFB1
tdONDCDCSLP
1.2 V
PWM mode
SW1
1.8 V
Active mode
1.8 V
Active mode
Off
VDAC
1.8 V
Active mode
VAUX2
1.8 V
Active mode
1.8 V
Active mode
VMMC
3.3 V
Active mode
3.3 V
Low-power mode
1.8 V
Active mode
3.3 V
Active mode
tSLP2ACTCK32K
CLK32KOUT
tACT2SLPCK32K
tdSLPON1
tdSLPONST
tdSLPONST
SWCS046-024
NOTE: Registers programming: VIO_PSKIP = 0, VDD1_PSKIP = 0, VDD1_SETOFF = 1, VDAC_SETOFF = 1,
VPLL_SETOFF = 1, VAUX2_KEEPON = 1
Figure 5-6. Device SLEEP State Control
Table 5-6. Device SLEEP State Control Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3 × tCK32k =
94
µs
188
µs
9 × tCK32k =
281
µs
tACT2SLP
SLEEP falling edge to supply in low power
mode
(SLEEP resynchronization delay)
tACT2SLP
SLEEP falling edge to CLK32KOUT low
tSLP2ACT
SLEEP rising edge to supply in high power
mode
8 × tCK32k =
250
tSLP2ACTCK32K
SLEEP rising edge to CLK32KOUT running
344
tSLP2ACT + 3 ×
tCK32k
375
µs
tdSLPON1
SLEEP rising edge to time step 1 of the tun-on
sequence from SLEEP state
281
tSLP2ACT + 1 ×
tCK32k
312
µs
2 × tCK32k =
62
tACT2SLP + 3 ×
tCK32k
156
turn-on sequence step duration, from SLEEP
state
tdSLPONST
0
TSLOT_LENGTH[1:0] = 01
200
TSLOT_LENGTH[1:0] = 10
500
TSLOT_LENGTH[1:0] = 11
2000
VDD1, VDD2 or VIO tun-on delay from tun-on
sequence time step
tdSLPONDCDC
42
TSLOT_LENGTH[1:0] = 00
Specifications
2 × tCK32k =
62
µs
us
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
5.22.2.4 Power Supplies State Control Through the SCLSR_EN1 and SDASR_EN2 Signals
Figure 5-7 andFigure 5-8 show the power supplies state control through the SCLSR_EN1 and SDASR_EN2
signals timing characteristics.
Switch-on sequence
Switch-off sequence
Device on
NRESPWRON
tdEN
SCLSR_EN1
tdVEN
VDIG1
tdEN
1.2 V
tdSOFF2
tdEN
SCLSR_EN2
VPLL
tdEN
Low-power mode
1.8 V
SWCS046-016
NOTE: Register setting: VDIG1_EN1 = 1, VPLL_EN2 = 1, and VPLL_KEEPON = 1
Figure 5-7. LDO Type Supplies State Control Through SCLSR_EN1 and SCLSR_EN2
Switch-on sequence
Switch-off sequence
Device on
NRESPWRON
tdEN
SCLSR_EN2
VDD2/VFB2
tdOEN
tdVDDEN
tdVDDEN
0V
3.3 V
tdSOFF2
SCLSR_EN1
VDD1/VFB1
1.2 V
PWM mode
tdEN
tdEN
Low-power mode
PFM (pulse skipping) mode
SW1
SWCS046-017
NOTE: Register setting: VDD2_EN2 = 1, VDD1_EN1 = 1, VDD1_KEEPON = 1, VDD1_PSKIP = 0, and SEL[6:0] = hex00 in
VDD2_SR_REG
Figure 5-8. VDD1 and VDD2 Supplies State Control Through SCLSR_EN1 and SCLSR_EN2
Table 5-7. Supplies State Control Though SCLSR_EN1 and SCLSR_EN2 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdEN: NREPSWON to supply state
change delay, SCLSR_EN1 or
SCLSR_EN2 driven
0
ms
tdEN: SCLSR_EN1 or
SCLSR_EN2 edge to supply state
change delay
1 × tCK32k = 31
µs
tdVDDEN: SCLSR_EN1 or
SCLSR_EN2 edge to VDD1 or
VDD2 DC-DC turn on delay
3 × tCK32k = 63
µs
Specifications
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
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TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
5.22.2.5 VDD1 and VDD2 Voltage Control Through SCLSR_EN1 and SDASR_EN2 Signals
Figure 5-9 shows the VDD1 and VDD2 voltage control through the SCLSR_EN1 and SDASR_EN2 signals timing
characteristics.
SCLSR_EN2
tdDVSEN
tdDVSENL
1.2 V
VDD1/VFB1
tdDVSEN
tdDVSENL
0.8 V
TSTEP[2:0]=001
TSTEP[2:0]=011
SW1
PFM (pulse skipping) mode
PWM mode
PFM (pulse
skipping) mode
PWM mode
PFM (pulse
skipping) mode
SWCS046-021
NOTE: Register setting: VDD1_EN1 = 1, SEL[6:0] = hex13 in VDD1_SR_REG
Figure 5-9. VDD1 Supply Voltage Control Though SCLSR_EN1
Table 5-8. VDD1 Supply Voltage Control Through SCLSR_EN1 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
tdDVSEN: SCLSR_EN1 or SCLSR_EN2 edge to
VDD1 or VDD2 voltage change delay
tdDVSENL: VDD1 or VDD2 voltage settling delay
UNIT
2 × tCK32k = 62
µs
32
µs
TSTEP[2:0] = 001
TSTEP[2:0] = 011 (default)
MAX
0.4/7.5 = 53
TSTEP[2:0] = 111
160
5.22.2.6 SMPS Switching Synchronization
Figure 5-10 shows the SMPS switching synchronization timing characteristics.
SWIO
SW1
tdswio2sw1
tdviosync
tdswio2sw2
SW2
tdswio2sw3
SW3
SWCS046-025
NOTE: VDD1 or VDD2 switching synchronization is available in PWM mode (VDD1_PSKIP = 0 or VDD2_PSKIP = 0). SMPS
external clock (GPIO_CKSYNC) synchronization is available when VIO PWM mode is set (VIO_PSKIP = 0).
Figure 5-10. SMPS Switching Synchronization
Table 5-9. SMPS Switching Synchronization Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD1_PSKIP = 0,
tdSWIO2SW1: delay from SWIO rising edge to SW1
rising edge
DCDCCKSYNC[1:0] = 11
160
DCDCCKSYNC[1:0] = 01
220
ns
VDD2_PSKIP = 0,
tdSWIO2SW2: delay from SWIO rising edge to SW1
rising edge
tdSWIO2SW3: delay from SWIO rising edge to SW3
rising edge
44
Specifications
DCDCCKSYNC[1:0] = 11
160
DCDCCKSYNC[1:0] = 01
290
206
ns
ns
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
6 Detailed Description
6.1
Power Reference
The bandgap voltage reference is filtered by using an external capacitor connected across the VREF
output and the analog ground REFGND (see Section 5.3, Recommended Operating Conditions). The
VREF voltage is distributed and buffered inside the device.
6.2
Power Sources
The power resources provided by the TPS65910 device include inductor-based switched mode power
supplies (SMPS) and linear low drop-out voltage regulators (LDOs). These supply resources provide the
required power to the external processor cores and external components, and to modules embedded in
the TPS65910 device.
Two of these SMPS have DVS capability SmartReflex Class 3 compatible. These SMPS provide
independent core voltage domains to the host processor. The remaining SMPS provides supply voltage
for the host processor I/Os.
Table 6-1 lists the power sources provided by the TPS65910 device.
Table 6-1. Power Sources
RESOURCE
TYPE
VIO
SMPS
1.5 V / 1.8 V / 2.5 V / 3.3 V
VOLTAGES
1000 mA
POWER
VDD1
SMPS
0.6 ... 1.5 in 12.5-mV steps
1500 mA
Programmable multiplication factor: x2, x3
VDD2
SMPS
0.6 ... 1.5 in 12.5-mV steps
1500 mA
Programmable multiplication factor: x2, x3
6.3
VDD3
SMPS
5V
100 mA
VDIG1
LDO
1.2 V, 1.5 V, 1.8 V, 2.7 V
300 mA
VDIG2
LDO
1 V, 1.1 V, 1.2 V, 1.8 V
300 mA
VPLL
LDO
1.0 V, 1.1 V, 1.8 V, 2.5 V
50 mA
VDAC
LDO
1.8 V, 2.6 V, 2.8 V, 2.85 V
150 mA
VAUX1
LDO
1.8 V, 2.5 V, 2.8 V, 2.85 V
300 mA
VAUX2
LDO
1.8 V, 2.8 V, 2.9 V, 3.3 V
150 mA
VAUX33
LDO
1.8 V, 2.0 V, 2.8 V, 3.3 V
150 mA
VMMC
LDO
1.8 V, 2.8 V, 3.0 V, 3.3 V
300 mA
Embedded Power Controller
The embedded power controller manages the state of the device and controls the power-up sequence.
6.3.1
State-Machine
The EPC supports the following states:
No supply: The main battery supply voltage is not high enough to power the VRTC regulator. A global
reset is asserted in this case. Everything on the device is off.
Backup: The main battery supply voltage is high enough to enable the VRTC domain but not enough to
switch on all the resources. In this state, the VRTC regulator is in backup mode and only the 32-K
oscillator and RTC module are operating (if enabled). All other resources are off or under reset.
Off: The main battery supply voltage is high enough to start the power-up sequence but device power on
is not enabled. All power supplies are in OFF state except VRTC.
Active: Device power-on enable conditions are met and regulated power supplies are on or can be
enabled with full current capability.
Detailed Description
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
45
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
Sleep: Device SLEEP enable conditions are met and some selected regulated power supplies are in lowpower mode.
Figure 6-1 shows the transitions of the state-machine.
PWRHOLD
NRESPWRON
Pulse
generator
INT1
DEV_ON
POWER ON
enable
tDOINT
PWRON
PWRON_LP_IT
tD
THERM_TS
DEV_OFF
NO SUPPLY
DEV_OFF_RST
SLEEPSIG_POL
MB and BBVMBHI
MBVBNPR and
MB VMBHI event interrupt status
RW
W1 to Clr
0
0
VMBDCH_IT
VBAT > VMBDCH event interrupt status.
Active only if Main Battery comparator VMBCH programmable threshold
is not bypassed (VMBCH_SEL[1:0] ≠ 00)
RW
W1 to Clr
0
Detailed Description
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
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91
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
Table 6-64. INT_MSK_REG
Address Offset
0x51
Physical Address
Instance
Description
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type
RW
7
6
RTC_PERIOD_ RTC_ALARM_I
IT_MSK
T_MSK
Bits
Field Name
5
4
HOTDIE_IT_M
SK
3
PWRHOLD_IT_ PWRON_LP_IT
MSK
_MSK
2
1
0
PWRON_IT_M
SK
VMBHI_IT_MS
K
VMBDCH_IT_
MSK
Type
Reset
7
RTC_PERIOD_IT_MS RTC period event interrupt mask.
K
Description
RW
0
6
RTC_ALARM_IT_MS
K
RTC alarm event interrupt mask.
RW
0
5
HOTDIE_IT_MSK
Hot die event interrupt mask.
RW
0
4
PWRHOLD_IT_MSK
PWRHOLD rising edge event interrupt mask.
RW
0
3
PWRON_LP_IT_MSK PWRON Long Press event interrupt mask.
RW
0
2
PWRON_IT_MSK
PWRON event interrupt mask.
RW
0
1
VMBHI_IT_MSK
VBAT > VMBHI event interrupt mask.
When 0, enable the device automatic switch on at BACKUP to OFF or
NOSUPPLY to OFF device state transition (EEPROM bit)
RW
1
0
VMBDCH_IT_MSK
VBAT < VMBDCH event interrupt status.
Active only if the main battery comparator VMBCH programmable
threshold is not bypassed (VMBCH_SEL[1:0] ≠ 00).
RW
0
Table 6-65. INT_STS2_REG
Address Offset
0x52
Physical Address
Instance
Description
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type
RW
7
6
5
4
3
Reserved
92
2
1
0
GPIO0_F_IT
GPIO0_R_IT
Bits
Field Name
Description
Type
Reset
7:2
Reserved
Reserved bit
RW
W1 to Clr
0
1
GPIO0_F_IT
GPIO_CKSYNC falling edge detection interrupt status
RW
W1 to Clr
0
0
GPIO0_R_IT
GPIO_CKSYNC rising edge detection interrupt status
RW
W1 to Clr
0
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
Table 6-66. INT_MSK2_REG
Address Offset
0x53
Physical Address
Instance
Description
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type
RW
7
6
5
4
3
2
Reserved
1
0
GPIO0_F_IT_M
SK
GPIO0_R_IT_
MSK
Bits
Field Name
Description
Type
Reset
7:2
Reserved
Reserved bit
RW
0
1
GPIO0_F_IT_MSK
GPIO_CKSYNC falling edge detection interrupt mask.
RW
0
0
GPIO0_R_IT_MSK
GPIO_CKSYNC rising edge detection interrupt mask.
RW
0
Table 6-67. GPIO0_REG
Address Offset
0x60
Physical Address
Instance
Description
GPIO0 configuration register
Type
RW
7
6
5
Reserved
4
3
2
1
0
GPIO_DEB
GPIO_PUEN
GPIO_CFG
GPIO_STS
GPIO_SET
Bits
Field Name
Description
Type
Reset
7:5
Reserved
Reserved bit
RO
R returns
0s
0x0
4
GPIO_DEB
GPIO_CKSYNC input debouncing time configuration:
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate
RW
0
3
GPIO_PUEN
GPIO_CKSYNC pad pull-up control:
1: Pull-up is enabled
0: Pull-up is disabled
RW
1
2
GPIO_CFG
Configuration of the GPIO_CKSYNC pad direction:
When 0, the pad is configured as an input
When 1, the pad is configured as an output
RW
0
1
GPIO_STS
Status of the GPIO_CKSYNC pad
RO
1
0
GPIO_SET
Value set on the GPIO output when configured in output mode
RW
0
Detailed Description
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
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93
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
Table 6-68. JTAGVERNUM_REG
Address Offset
0x80
Physical Address
Instance
Description
Silicon version number
Type
RO
7
6
5
4
3
2
Reserved
94
1
0
VERNUM
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:0
VERNUM
Value depending on silicon version number 0000 - Revision 1.0
RO
0x0
Detailed Description
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
7 Device and Documentation Support
7.1
7.1.1
Device Support
Development Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of the TPS65910 device applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any TPS65910 device application.
Hardware Development Tools: Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the TPS65910 platform, visit the Texas
Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field
sales office or authorized distributor.
7.1.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, TPS65910). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, RSL) and the temperature range (for example, blank is the default commercial
temperature range).
Device and Documentation Support
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
95
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
www.ti.com
For orderable part numbers of TPS65910x devices in the RSL package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
7.2
Documentation Support
The following documents describe the TPS65910 device. Copies of these documents are available on the
Internet at www.ti.com.
7.3
SWCZ010
TPS65910 Silicon Errata
SWCA139
TPS65910x Schematic Checklist
SWCU078
TPS65910 User Guide for OMAP3 Family of Processors
SWCU093
TPS65910Ax User's Guide for AM335x Processors
SWCU065
TPS65910 EVM User's Guide
SWCU071
TPS65910 User Guide for OMAPL137, OMAPL138 and C674x
SWCA089
TPS65910 User Guide for AM3517/AM3505 Processor
SWCU073
TPS659107 User Guide for i.MX27 and i.MX35 Processors
SWCU074
TPS659105 User Guide for DaVinci Family Processors
Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7-1. Related Links
96
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS65910
Click here
Click here
Click here
Click here
Click here
TPS65910A
Click here
Click here
Click here
Click here
Click here
TPS65910A3
Click here
Click here
Click here
Click here
Click here
TPS659101
Click here
Click here
Click here
Click here
Click here
TPS659102
Click here
Click here
Click here
Click here
Click here
TPS659103
Click here
Click here
Click here
Click here
Click here
TPS659104
Click here
Click here
Click here
Click here
Click here
TPS659105
Click here
Click here
Click here
Click here
Click here
TPS659106
Click here
Click here
Click here
Click here
Click here
TPS659107
Click here
Click here
Click here
Click here
Click here
TPS659108
Click here
Click here
Click here
Click here
Click here
TPS659109
Click here
Click here
Click here
Click here
Click here
Device and Documentation Support
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
7.4
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
7.5
Trademarks
SmartReflex, E2E are trademarks of Texas Instruments.
7.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
7.8
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
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97
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
7.9
www.ti.com
Additional Acronyms
Additional acronyms used in this data sheet are described below.
ACRONYM
DEFINITION
DDR
Dual-Data Rate (memory)
ES
Engineering Sample
ESD
Electrostatic Discharge
FET
Field Effect Transistor
EPC
Embedded Power Controller
FSM
Finite State Machine
GND
Ground
GPIO
General-Purpose I/O
HBM
Human Body Model
HD
Hot-Die
HS-I2C
High-Speed I2C
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
ID
Identification
IDDQ
Quiescent supply current
IEEE
Institute of Electrical and Electronics Engineers
IR
Instruction Register
I/O
Input/Output
JEDEC
Joint Electron Device Engineering Council
JTAG
Joint Test Action Group
LBC7
Lin Bi-CMOS 7 (360 nm)
LDO
Low Drop Output voltage linear regulator
LP
Low-Power application mode
LSB
Least Significant Bit
MMC
Multimedia Card
MOSFET
Metal Oxide Semiconductor Field Effect Transistor
NVM
Nonvolatile Memory
OMAP™
Open Multimedia Application Platform™
RTC
Real-Time Clock
SMPS
Switched Mode Power Supply
SPI
Serial Peripheral Interface
POR
Power-On Reset
98
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Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
TPS65910, TPS65910A, TPS65910A3, TPS659101
TPS659102, TPS659103, TPS659104, TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046U – MARCH 2010 – REVISED OCTOBER 2014
8 Mechanical Packaging and Orderable Information
8.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Mechanical Packaging and Orderable Information
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Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
Copyright © 2010–2014, Texas Instruments Incorporated
99
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS659101A1RSL
ACTIVE
VQFN
RSL
48
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T659101
A1
TPS659101A1RSLR
ACTIVE
VQFN
RSL
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T659101
A1
TPS659102A1RSL
ACTIVE
VQFN
RSL
48
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T659102
A1
TPS659102A1RSLR
ACTIVE
VQFN
RSL
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T659102
A1
TPS659106A1RSL
ACTIVE
VQFN
RSL
48
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T659106
A1
TPS659106A1RSLR
ACTIVE
VQFN
RSL
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T659106
A1
TPS659108A1RSL
ACTIVE
VQFN
RSL
48
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T659108
A1
TPS659108A1RSLR
ACTIVE
VQFN
RSL
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T659108
A1
TPS659109A1RSL
ACTIVE
VQFN
RSL
48
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T659109
A1
TPS659109A1RSLR
ACTIVE
VQFN
RSL
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T659109
A1
TPS65910A1RSL
ACTIVE
VQFN
RSL
48
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS
65910A1
TPS65910A1RSLR
ACTIVE
VQFN
RSL
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS
65910A1
TPS65910A31A1RSLR
ACTIVE
VQFN
RSL
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
65910
A31A1
TPS65910A31A1RSLT
ACTIVE
VQFN
RSL
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
65910
A31A1
TPS65910A3A1RSL
ACTIVE
VQFN
RSL
48
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T65910
A3A1
TPS65910A3A1RSLR
ACTIVE
VQFN
RSL
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T65910
A3A1
TPS65910AA1RSL
ACTIVE
VQFN
RSL
48
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T65910A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
A1
TPS65910AA1RSLR
ACTIVE
VQFN
RSL
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
T65910A
A1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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