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TPS65921
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
TPS65921 Power Management and USB Single Chip
1 Device Overview
1.1
Features
1
• Three Step-Down Converters:
– Up to 1.2 A of Output Current for VDD1
• TPS65921B Supports VDD1 up to 1.2 A
• TPS65921B1 Supports VDD1 up to 1.4 A
(Necessary for 1-GHz Operation)
– SmartReflex™ Dynamic Voltage Management
– 3.2-MHz Fixed Frequency Operation
– VIN Range from 2.7 to 4.5 V
– Typical 30 µA Quiescent per Converter
• Four General-Purpose Configurable LDOs:
– Dynamic Voltage Scaling
– 220-mA Maximum Current for One LDO
– VIN Range from 2.7 to 4.5 V
– 2 LDOs With Low Noise and High PSRR
• RTC With Alarm Wake-Up Mechanism
• Clock Management
1.2
•
•
•
•
•
•
•
•
Applications
Mobile Phones and Smart Phones
MP3 Players
Handheld Devices
1.3
•
– 32-kHz Crystal Oscillator
– Clock Slicer for 26, 19.2, and 38.4 MHz
– HF Clock Output Buffer
USB:
– USB HS 2.0 Transceiver
– USB 1.3 OTG-Compliant
– 12-Bit ULPI 1.1 Interface
– USB Power Supply (5-V CP for VBUS)
Control
– High-Speed I2C Interface
– All Resource Configurable by I2C
Keypad Interface up to 8 × 8
10-Bit A/D Converter
Hot-Die, Thermal Shutdown Protection
µ*BGA 120 Balls ZQZ
•
•
E-Books
OMAP™ and Low-Power DSP Supply
Description
The TPS65921 device is a highly integrated power-management circuit (IC) that supports the power and
peripheral requirements of the OMAP application processors. The device contains power management, a
universal serial bus (USB) high-speed (HS) transceiver, an analog-to-digital converter (ADC), a real-time
clock (RTC), a keypad interface, and an embedded power control (EPC). The power portion of the device
contains three buck converters, two controllable by a dedicated SmartReflex class-3 interface, multiple
low-dropout (LDO) regulators, an EPC to manage the power-sequencing requirements of OMAP, and an
RTC module. The USB module provides an HS 2.0 transceiver suitable for direct connection to the OMAP
universal transceiver macrocell interface (UTMI) + low pin interface (ULPI) with an integrated charge pump
(CP).
The device also provides auxiliary modules: ADC, keypad interface, and general-purpose inputs/outputs
(GPIOs) muxed with the JTAG functions. The keypad interface implements a built-in scanning algorithm to
decode hardware-based key presses and to reduce software use, with multiple additional GPIOs that can
be used as interrupts when they are configured as inputs.
Device Information (1)
PART NUMBER
TPS65921ZQZ
(1)
PACKAGE
BODY SIZE
ZQZ (120)
6.00 mm × 6.00 mm
For more information, see Section 7, Mechanical Packaging and Orderable Information.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65921
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
1.4
www.ti.com
Functional Block Diagram
REFS
VRTC
TEST/GPIO
TESTV1
TESTV2
TEST
JTAG.TCK
JTAG.TDO
JTAG.TMS
JTAG.TDI
VPROG
VREF
REFGND
VINTANA2
VINTANA1
VINT.IN
VRTC_OUT
Figure 1-1 shows the functional block diagram of the device.
AGND
VBAT
VDD1_IN
TEST/MUXed I/O’s
VINTANA2
VINTANA1
VDD1_L
VDD1
IO.1P8
DGND
VDD1_FDBK
SRI2C_SCL
VDD1_GND
VDD2_IN
I2C Smart-Reflex
SRI2C_SDA
VDD2_L
32KXIN
32KXOUT
VDD2
Xtal
32K
HFCLKIN
HFCLKOUT
VDD2_FDBK
RTC
Clock sys
32KCLKOUT
VDD2_GND
VIO_IN
Clock
slicer
VIO_L
VIO
MSECURE
VIO_FDBK
BOOT0
BOOT1
VIO_GND
RESPWRON
NRESWARM
VPLLA3RIN
Power control
PWRON
NSLEEP
VPLL1OUT
Control I/Os
VPLL1
INT
SYSEN
REGEN
CLKEN
TESTRESET
CLKREQ
VDAC.IN
VDAC.OUT
VDAC
CTLI2C_SCL
I2C control
CTLI2C_SDA
Control, Data
and Test
logic
DP
DM
MUX
10- bit
ADC
VMMC1OUT
VMMC1
VAUX12SIN
VAUX2_OUT
ULPI
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
NXT
DIR
STP
UCLK
ID
VBUS
Scalars
VMMC1_IN
ADCIN0
VAUX2
USB 2.0
OTG
CP_IN
USB
CP
USB
PHY
CP_CAPP
CP_CAPM
CP_GND
AVSS1
VINT.IN
VINTDIG
VBAT_USB
KPD_R0
KPD_R1
KPD_R2
KPD_R3
KPD_R4
KPD_R5
KPD_R6
KPD_R7
KPD_C7
KPD_C6
KPD_C5
KPD_C4
KPD_C3
KPD_C2
KPD_C1
KPD_C0
KEY
PAD
VINTDIG
VINTUSB1P5
VINTUSB1P5_OUT
VINTUSB1P8
VINTUSB1P8_OUT
VUSB3P1
VUSB3P1
AVSS2
AVSS3
AVSS4
SWCS048-010
Figure 1-1. Functional Block Diagram
2
Device Overview
Copyright © 2010–2014, Texas Instruments Incorporated
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Product Folder Links: TPS65921
TPS65921
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SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
Table of Contents
1
2
3
Device Overview ......................................... 1
4.18
Battery Threshold Levels............................ 24
1.1
Features .............................................. 1
4.19
Power Consumption................................. 25
1.2
Applications ........................................... 1
4.20
USB Charge Pump
1.3
Description ............................................ 1
4.21
Hot-Die Detection and Thermal Shutdown.......... 26
1.4
Functional Block Diagram ............................ 2
.................................................
...............................................
4.24 TPS65921 Interface Target Frequencies ...........
4.25 JTAG Interfaces .....................................
Detailed Description ...................................
5.1
Functional Block Diagram ...........................
5.2
Clock System .......................................
5.3
32-kHz Oscillator ....................................
5.4
Clock Slicer .........................................
5.5
Power Path ..........................................
5.6
Charger Detection ...................................
5.7
MADC ...............................................
5.8
JTAG Interfaces .....................................
Device and Documentation Support ...............
6.1
Device Support ......................................
6.2
Documentation Support .............................
6.3
Trademarks..........................................
6.4
Electrostatic Discharge Caution .....................
6.5
Export Control Notice ...............................
6.6
Glossary .............................................
Revision History ......................................... 4
Terminal Configuration and Functions .............. 5
3.1
4
Signal Descriptions ................................... 6
Specifications ........................................... 10
4.1
Absolute Maximum Ratings ......................... 10
4.2
Handling Ratings .................................... 10
4.3
4.4
Recommended Operating Conditions ............... 10
Thermal Resistance Characteristics for ZQZ
Package ............................................. 13
4.5
Crystal Oscillator .................................... 13
4.6
.........................................
32KCLKOUT Output Clock..........................
HFCLKOUT Output Clock ...........................
VDD1 DC-DC Converter ............................
VDD2 DC-DC Converter ............................
VIO DC-DC Converter ..............................
VMMC1 Low Dropout Regulator ....................
VDAC Low Dropout Regulator ......................
VAUX2 Low Dropout Regulator .....................
VPLL1 Low Dropout Regulator .....................
Internal LDOs .......................................
Voltage References .................................
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
Clock Slicer
5
14
14
15
6
17
18
19
20
21
22
23
7
.................................
25
4.22
USB
26
4.23
MADC
31
33
36
38
38
39
39
40
43
54
57
58
60
60
61
61
61
61
61
24
Mechanical Packaging and Orderable
Information .............................................. 62
24
7.1
Packaging Information
..............................
Table of Contents
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62
3
TPS65921
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2012) to Revision G
•
4
Changed the format to the latest TI standards
Page
...................................................................................
Revision History
1
Copyright © 2010–2014, Texas Instruments Incorporated
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Product Folder Links: TPS65921
TPS65921
www.ti.com
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
3 Terminal Configuration and Functions
shows the ball locations for the 120-ball plastic ball grid array (PBGA) package and is used in conjunction
with ball description to locate signal names and ball grid numbers.
1
2
3
4
5
6
7
8
9
10
11
A
VMMC1.OUT
VINTANA2.
OUT
VMODE2/
I2C.SR.SCL
AVSS4
DIR/GPIO.10
VPLLA3R.IN
VINT.IN
VPLL1.OUT
INT1
IO.1P8
VDD1.GND
A
B
VMMC1.IN
KPD.C3
I2C.CNTL.
SCL
KPD.C0
VRTC.OUT
DATA0/
UART4.TXD
VINTDIG.
OUT
DGND
SYSEN
VDD1.GND
VDD1.GND
B
C
VDAC.IN
KPD.C4
#N/A
I2C.CNTL.
SDA
NXT/GPIO.11
DATA1/
UART4.RXD
DATA2/
UART4.RTSI
HFCLKIN
TESTV2
VDD1.L
VDD1.L
C
D
VINTANA1.
OUT
KPD.C1
TEST
PWROK2/
12C.SR.SDA
PWRON
UCLK
DATA3/
UART4.
CTSO/
GPIO.12
CLKREQ
DATA7/
GPIO.5
VDD1.L
VDD1.OUT
D
E
VDAC.OUT
KPD.C2
KPD.C6
KPD.C5
BOOT0
DATA6/
GPIO.4
VDD1.IN
VDD1.IN
VDD1.IN
E
F
VAUX12S.IN
ADCIN0
AVSS1
KPD.C7
KPD.R7
BOOT1
JTAG.TCK/
BERCLK
DATA4/
GPIO.14
AVSS3
CLKEN
DATA5/
GPIO.3
F
G
VAUX2.OUT
GPIO.2/
TEST1
REGEN
KPD.R1
KPD.R3
32KCLKOUT
KPD.R6
MSECURE
BKBAT
VREF
32KXOUT
G
H
VIO.OUT
TESTV1
VPROG
KPD.R2
KPD.R0
AVSS2
STARTADC
NRESWARM
VDD2.OUT
AGND
32KXIN
H
J
VIO.GND
VIO.GND
CP.GND
KPD.R4
ID
KPD.R5
TEST.RESET
VDD2.GND
VDD2.GND
J
K
VIO.L
VIO.IN
VBAT
NSLEEP1
VBUS
VBAT.USB
GND_AGND
HFCLKOUT
GPIO.1/CD2/
JTAG.TMS
VDD2.IN
VDD2.L
K
L
VIO.L
VIO.IN
CP.CAPM
CP.IN
CP.CAPP
VUSB.3P1
DP/UART3.
RXD
DN/UART3.
TXD
GPIO.0/CD1/
JTAG.TD0
VDD2.IN
VDD2.L
L
1
2
3
4
5
6
7
8
9
10
11
STP/GPIO.9 NRESPWRON
VINTUSB1P5. VINTUSB1P8.
OUT
OUT
SWCS048-009
Figure 3-1. Ball Placement (Top View)
Terminal Configuration and Functions
Copyright © 2010–2014, Texas Instruments Incorporated
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TPS65921
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
3.1
www.ti.com
Signal Descriptions
Table 3-1. Signal Descriptions
NAME
ADCIN0
BALL
SUPPLIES
F2
TYPE
I/O
DESCRIPTION
PU/PD
Analog
I/O
General-purpose ADC input
NO
ADC conversion
request/JTAG test data
input
NO
STARTADC
H7
VDDIO/DGND
Digital
I
I2C.CNTL.SDA
C4
VDDIO/DGND
Digital
I/O
I2C bidirectional data signal
External PU
External PU
I2C.CNTL.SCL
B3
VDDIO/DGND
Digital
I/O
I2C bidirectional clock
signal
I2C.SR.SDA
D4
VDDIO/DGND
Digital
I/O
HS I2C bidirectional data
signal
External PU
I2C.SR.SCL
A3
VDDIO/DGND
Digital
I/O
HS I2C bidirectional Clock
signal
External PU
PWRON
D5
VBAT/GND
Digital
I
Input detects a control
command to start or stop
the system.
External PU
REGEN
G3
Digital
O
Enable signal for external
LDO
PU
MSECURE
G8
VDDIO/DGND
Digital
I
Security and digital rights
management
NO
BOOT0
E5
VBAT/GND
Digital
I
Power-up sequence
selection
Programmable
PD (default
active)
BOOT1
F6
VBAT/GND
Digital
I
Power-up sequence
selection
Programmable
PD (default
active)
NRESPWRON
E7
VDDIO/DGND
Digital
O
Output control the
NRESPWRON of the
application processor
NO
NRESWARM
H8
VDDIO/DGND
Digital
I
Warm reset signal
PU
NSLEEP1
K4
VDDIO/DGND
Digital
I
ACTIVE-SLEEP state
transition control signal
NO
INT1
A9
VDDIO/DGND
Digital
O
Output line interrupt
NO
SYSEN
B9
VDDIO/DGND
Digital
O
System enable output
NO
CLKEN
F10
VDDIO/DGND
Digital
O
Clock Enable
NO
PD disabled in
ACTIVE state
32KCLKOUT
G6
VDDIO/DGND
Digital
O
32-kHz clock output
32KXOUT
G11
VRTC/REFGND
Analog
I
32-kHz crystal oscillator
NO
32KXIN
H11
VRTC/REFGND
Analog
I
32-kHz crystal oscillator
NO
NO
HFCLKIN
C8
VDDIO/DGND
Analog
I
Sine wave or square wave
input
HFCLKOUT
K8
VDDIO/DGND
Digital
O
50% duty cycle square
wave output
NO
G10
VREF/REFGND
Analog
O
Bandgap voltage
NO
VREF
GND_AGND
K7
AGND
Analog
I/O
Substrate ground
NO
AGND
H10
REFGND
Analog
I/O
Reference ground
NO
DGND
B8
DGND
Power
I/O
Digital ground
NO
NO
IO.1P8
A10
BKBAT
G9
VDD1.IN
VDD1.GND
6
VBACKUP/AGND
E9, E10, E11
A11, B10,
B11
Power
I
Supply for I/O buffers
(VDDIO)
Power
I
Not used. Must be
grounded
NO
Power
I
VDD1 DC-DC input
NO
I/O
VDD1 DC-DC power
ground
NO
Power
Terminal Configuration and Functions
Copyright © 2010–2014, Texas Instruments Incorporated
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SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
Table 3-1. Signal Descriptions (continued)
NAME
VDD1.L
VDD1.OUT
BALL
SUPPLIES
TYPE
I/O
DESCRIPTION
C10, C11,
D10
Power
O
VDD1 DC-DC switched
output
PU/PD
NO
D11
Analog
I
VDD1 feedback voltage
PD
VDD2.IN
K10, L10
Power
I
VDD2 DC-DC input
NO
VDD2.GND
J10, J11
Power
I/O
VDD2 DC-DC power
ground
NO
VDD2.L
K11, L11
Power
O
VDD2 DC-DC switched
output
NO
VDD2.OUT
H9
Analog
I
VDD2 feedback voltage
PD
VIO.IN
K2, L2
Power
I
VIO DC-DC input
NO
VIO.GND
J1, J2
Power
I/O
VIO DC-DC power ground
NO
VIO.L
K1, L1
Power
O
VIO DC-DC switched
output
NO
VIO.OUT
H1
Analog
I
VIO feedback voltage
PD
VAUX12S.IN
F1
Power
I
VAUX2 LDO input
NO
VAUX2.OUT
G1
Power
O
VAUX2 regulator output
PD
VPLLA3R.IN
A6
Power
I
VPLL1/VRTC LDO input
NO
VPLL1.OUT
A8
Power
O
VPLL1 LDO regulator
output
PD
VRTC.OUT
B5
Power
O
VRTC internal LDO
regulator output (internal
use only)
PD
VINT.IN
A7
Power
I
VINTDIG LDO input
NO
PD
VINTANA1.OUT
D1
Power
O
VINTANA1 internal LDO
regulator output (internal
use only)
VINTANA2.OUT
A2
Power
O
VINTANA2 internal LDO
regulator output (internal
use only)
PD
VDAC.IN
C1
Power
I
VDAC/VINTANA1/VINTAN2
LDO input
NO
VDAC.OUT
E1
Power
O
VDAC LDO regulator output
PD
PD
VINTDIG.OUT
B7
Power
O
VINTDIG internal LDO
regulator output (internal
use only)
VMMC1.OUT
A1
Power
O
VMMC1 LDO regulator
output
PD
VBAT.USB
K6
Power
I
VINTUSBiP5,VINTUSB1P8,
VUSB.3P1 input regulator
NO
VUSB.3P1
L6
Power
O
VUSB.3P1 LDO regulator
output
PD
VINTUSB1P8.OUT
J6
Power
O
VUSB1P8 LDO regulator
output (internal use only)
PD
VINTUSB1P5.OUT
J5
Power
O
VUSB1P5 LDO regulator
output (internal use only)
PD
TESTV1
H2
Analog
IO
Analog test pin 1
NO
TESTV2
C9
Analog
IO
Analog test pin 2
NO
TEST
D3
VDDIO/DGND
Digital
IO
Selection between JTAG
mode and application mode
PD
AVSS1
F3
AGND
Power
I/O
Analog ground
NO
AVSS2
H6
AGND
Power
I/O
Analog ground
NO
AVSS3
F9
AGND
Power
I/O
Analog ground
NO
AVSS4
A4
AGND
Power
I/O
Analog ground
NO
VBUS
K5
VBUS power rail
NO
Power
Terminal Configuration and Functions
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TPS65921
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
www.ti.com
Table 3-1. Signal Descriptions (continued)
NAME
BALL
SUPPLIES
TYPE
I/O
Analog
I/O
USB differential data line
NO
Analog
I/O
USB differential data line
NO
Digital
I/O
USB ID
NO
VDDIO/DGND
Digital
I/O
HS USB Clock
NO
E6
VDDIO/DGND
Digital
I/O
HS USB Stop
NO
A5
VDDIO/DGND
Digital
I/O
HS USB Direction
NO
C5
VDDIO/DGND
Digital
I/O
HS USB Next
NO
DATA0/UART4.TXD
B6
VDDIO/DGND
Digital
I/O
HS USB Data0
NO
DATA1/UART4.RXD
C6
VDDIO/DGND
Digital
I/O
HS USB Data1
NO
DATA2/UART4.RTSI
C7
VDDIO/DGND
Digital
I/O
HS USB Data2
NO
DATA3/UART4.CTSO/
GPIO.12
D7
VDDIO/DGND
Digital
I/O
HS USB Data3
NO
DATA4/GPIO.14
F8
VDDIO/DGND
Digital
I/O
HS USB Data4
NO
DATA5/GPIO.3
F11
VDDIO/DGND
Digital
I/O
HS USB Data5
NO
DATA6/GPIO.4
E8
VDDIO/DGND
Digital
I/O
HS USB Data6
NO
DATA7/GPIO.5
D9
VDDIO/DGND
Digital
I/O
HS USB Data7
NO
CP.IN
L4
Power
I/O
Charge pump input voltage
NO
CP.GND
J3
Power Gnd
I/O
Charge pump ground
NO
CP.CAPP
L5
Analog
I/O
Charge pump flying
capacitor P
NO
CP.CAPM
L3
Analog
I/O
Charge pump flying
capacitor M
NO
DP/UART3.RXD
L7
DN/UART3.TXD
L8
ID
J7
VDDIO/DGND
UCLK
D6
STP/GPIO.9
DIR/GPIO.10
NXT/GPIO.11
DESCRIPTION
PU/PD
KPD.C0
B4
VDDIO/DGND
Open Drain
O
Keypad column 0
PU
KPD.C1
D2
VDDIO/DGND
Open Drain
O
Keypad column 1
PU
KPD.C2
E2
VDDIO/DGND
Open Drain
O
Keypad column 2
PU
KPD.C3
B2
VDDIO/DGND
Open Drain
O
Keypad column 3
PU
KPD.C4
C2
VDDIO/DGND
Open Drain
O
Keypad column 4
PU
KPD.C5
E4
VDDIO/DGND
Open Drain
O
Keypad column 5
PU
KPD.C6
E3
VDDIO/DGND
Open Drain
O
Keypad column 6
PU
KPD.C7
F4
VDDIO/DGND
Open Drain
O
Keypad column 7
PU
KPD.R0
H5
VDDIO/DGND
Digital
I
Keypad row 0
PU
KPD.R1
G4
VDDIO/DGND
Digital
I
Keypad row 1
PU
KPD.R2
H4
VDDIO/DGND
Digital
I
Keypad row 2
PU
KPD.R3
G5
VDDIO/DGND
Digital
I
Keypad row 3
PU
KPD.R4
J4
VDDIO/DGND
Digital
I
Keypad row 4
PU
KPD.R5
J8
VDDIO/DGND
Digital
I
Keypad row 5
PU
KPD.R6
G7
VDDIO/DGND
Digital
I
Keypad row 6
PU
KPD.R7
F5
VDDIO/DGND
Digital
I
Keypad row 7
PU
VBAT
K3
Power
I/O
Battery input voltage
(Sense)
NO
CLKREQ
D8
VDDIO/DGND
Digital
I
Clock request line
PD
TEST.RESET
J9
VBAT/GND
Digital
I
Reset the device (except
the state-machine)
PD
VPROG
H3
Analog
I
Reserved. Must be
grounded.
NO
JTAG/TCK/BERCLK
F7
Digital
I
JTAG clock input
NO
PD
PD
VDDIO/DGND
GPIO.0/CD1/JTAG.TD
O
L9
VDDIO/DGND
Digital
I/O
JTAG test output or
GPIO0/card detection 1
GPIO.1/CD2/JTAG.TM
S
K9
VDDIO/DGND
Digital
I/O
JTAG test mode state or
GPIO1/card detection 2
8
Terminal Configuration and Functions
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Table 3-1. Signal Descriptions (continued)
NAME
GPIO.2/TEST1
BALL
G2
VMMC1.IN
B1
N/A
C3
SUPPLIES
VDDIO/DGND
N/A
TYPE
Digital
I/O
DESCRIPTION
PU/PD
Programmable
PD
I
GPIO/Digital test pin
Power
I
VMMC1 input LDO
NO
N/A
N/A
N/A
N/A
Terminal Configuration and Functions
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4 Specifications
Absolute Maximum Ratings (1)
4.1
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
0.0
5.0
V
–0.3
1.0 × Supply + 0.3
V
VBUS input
–0.3
7
V
Operating ambient
temperature (TA)
–40
85
°C
–40
125
°C
–40
150
°C
–40
85
°C
Main battery supply
voltage (2)
Where supply represents the voltage
applied to the power supply pin
associated with the input (4)
Voltage on any input (3)
Operating junction
temperature (TJ)
Absolute maximum rating
Operating junction
temperature (TJ)
For parametric compliance
Ambient temperature for
parametric compliance
With maximum 125°C as junction
temperature (TJ)
(1)
(2)
(3)
(4)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
The product will have negligible reliability impact if voltage spikes of 5.2 V occur for a total (cumulative over lifetime) duration of 10
milliseconds.
Excepts VBAT input pads and VBUS pad.
Supply equals the reference level of each pin.
4.2
Handling Ratings
Tstg
Storage temperature range
VESD
Electrostatic discharge (ESD)
performance:
(1)
(2)
NOM
MIN
MAX
UNIT
–55
125
°C
–1
1
kV
–250
250
V
Human Body Model (HBM), per ANSI/ESDA/JEDEC
JS001 (1)
Charged Device Model (CDM),
per JESD22-C101 (2)
All pins
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4.3
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
2.7
3.6
4.5
V
7
V
Power and USB Path
VBAT/VBAT.USB main battery supply voltage and
VBUS
0
HFCLKIN Input Clock
Frequency 1/tC(HFCLKIN)
19.2, 26 or 38.4
Pulse duration, HFCLKIN low or high (BP)
0.45 × tC(HFCLKIN)
HFCLKIN stability
MHz
0.55 ×
tC(HFCLKIN)
ns
–150
150
ppm
Rise time of HFCLKIN (BP)
0
5
ns
Fall time of HFCLKIN (BP)
0
5
ns
1.45
Vpp
1.85 (1)
Vpp
–25
dBc
Input dynamic range
LP/HP (sine wave)
0.3
BP/PD (square wave)
0.7
0
Harmonic content of input signal (with 0.7-VPP amplitude): Second
component - LP/HP (sine wave)
VIH voltage input
high (1)
(1)
10
BP (square mode)
0.65 × IO.1P8
V
Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface (IO.1P8V).
Specifications
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VIL voltage input low (1)
MIN
TYP
BP (square mode)
MAX
0.35 × IO.1P8
UNIT
V
Crystal Oscillator
Parallel resonance crystal frequency 1/tC(32KHZ)
32.768
Input voltage, Vin (normal mode)
1.0
Crystal tolerance at room temperature, 25°C
Crystal tolerance versus temperature range (–40°C to 85°C)
Crystal quality factor
1.3
kHz
1.55
V
–30
30
ppm
–200
200
ppm
13k
54k
Maximum drive power
Operating drive level
1
µW
0.5
µW
32KXIN 32KXOUT
duty cycle
Crystal
40%
60%
Square wave
45%
55%
32-kHz clock rise/fall
time
Square wave with capacitive load equivalent to
30 pF
(2)
VIH voltage input high
Square wave in bypass mode
VIL voltage input low
Square wave in bypass mode (2)
0.1 × tC(32KHZ)
0.65 × VBRTC
µs
V
0.35 × VBRTC
V
DC-DC Converters and LDOs
VDD1.IN, VDD2.IN, VDD3.IN input voltage range for step-down converter
VDD1, VDD2, VIO
VMMC1.IN input voltage range for LDO VMMC1
2.7
3.6
4.5
V
Maximum (2.7,
output voltage
selected + 250 mV)
3.6
4.5
V
VDAC.IN input voltage range for LDO VDAC
2.7
3.6
4.5
V
VAUX12S.IN input voltage range for LDO VAUX2
Maximum (2.7,
output voltage
selected + 250 mV)
3.6
4.5
V
VINT.IN input voltage range for LDO VINTANA1, VINTANA2, VINTDIG
and VRTC
Maximum (2.7,
output voltage
selected + 200 mV)
3.6
4.5
V
VPLLA3R.IN input voltage range for LDO VPLL1
2.7
3.6
VDD1.OUT ouput voltage range for VDD1 step-down converter
0.6
VDD2.OUT ouput voltage range for VDD2 step-down converter
0.6
VIO.OUT ouput voltage range for VIO step-down converter
4.5
V
1.45
V
1.5
V
1.8/1.85
V
VMMC1.OUT output voltage range for LDO VMMC1
1.85
3.15
V
VDAC.OUT output voltage range for LDO VDAC
1.2
1.8
V
VAUX2.OUT output voltage range for LDO VAUX2
1.3
2.8
V
VPLL1.OUT output voltage range for LDO VPLL1
1.0
1.8
V
VINTANA1.OUT output voltage for LDO VINTANA1
1.5
VINTANA2.OUT output voltage for LDO VINTANA2
V
2.5/2.75
V
VINTUSB1P5V.OUT output voltage for LDO VINTUSB1P5
1.35
1.5
1.65
V
VINTUSB1P8V.OUT output voltage for LDO VINTUSB1P8
1.62
1.8
1.98
V
VUSB3P1V.OUT output voltage for LDO VUSB3P1
3.1
VINTDIG.OUT output voltage range for LDO VINTDIG
VRTC.OUT output
voltage range
Normal mode
Backup mode
V
1.35
1.5
1.65
V
1.45
1.5
1.55
V
1.0
1.3
1.55
V
9
10
12.5
pF
External Components
Crystal: Nominal load cap on each oscillator input CXIN and CXOUT (3)
(2)
(3)
Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface (IO.1P8V).
Nominal load capacitor on each oscillator input defined as CXIN = CXOUT = Cosc × 2 – (Cint + Cpin). Cosc is the load capacitor
defined in the crystal oscillator specification, Cint is the internal capacitor, and Cpin is the parallel input capacitor.
Specifications
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MAX
UNIT
Crystal ESR (4)
PARAMETER
MIN
90
kΩ
Crystal shunt capacitance, CO
1
pF
1.3
µH
0.1
Ω
Value
External coil for VDD1
External coil for VDD2
and VIO
TYP
0.7
1
DCR
Saturation current for TPS65921B
1.8
Saturation current for TPS65921B1
2.1
Value
0.7
A
A
1
DCR
1.3
0.1
Saturation current
900
External capacitor for
Value (5)
VDD1, VDD2, VIO
connected to VDD1.IN,
VDD2.IN, VDD3.IN,
ESR at switching frequency
and VDD1.OUT,
VDD2.OUT, VIO.OUT
µH
Ω
mA
5
10
1
μF
20
mΩ
2.7
µF
600
mΩ
6.5
µF
600
mΩ
Filtering capacitor for
VMCC1.IN, VDAC.IN,
VAUX12S.IN,
VPPLA3R.IN, VINT.IN,
VBAT.USB,
VMMC1.OUT,
VDAC.OUT,
VAUX2.OUT, VPPL1,
VINTDIG, VINTANA1,
VINTANA2, VRRTC
Value
0.3
ESR
20
Filtering capacitor for
VUSB3V1, VUSB1V8,
VUSB1V5
Value
0.5
ESR
20
Connected from VREF to REFGND
0.3
1
2.7
µF
Filtering capacitor (Connected between
VBUS.CPOUT and GND) and called CVBUS
1.41 (The minimum
can be reduced to
1.2 µF, provided the
charge-pump is only
used to supply
VUSB3V1 LDO)
4.7
6.5
µF
Flying capacitor (Connected between CP.CAPP
and CP.CAPM) called CVBUS.FC
1.32 (The minimum
can be reduced to
1.2 µF, provided the
charge-pump is only
used to supply
VUSB3V1 LDO)
2.2
3.08
µF
20
mΩ
Filtering capacitor for
voltage reference
External capacitor for
charge pump and
VBUS
1
15
2.2
Filtering capacitor ESR for CVUSB.IN and
CVBUS.FC
Filtering capacitor CVBUS.IN
External capacitor for
power reference filter
(4)
Filtering capacitor
12
10
15
µF
0.3
1
2.7
µF
The crystal motional resistance Rm relates to the equivalent series resistance (ESR) by the following formula:
æ
C ö
ESR = Rm ç 1 + 0 ÷
è CL ø
(5)
5
2
Measured with the load capacitance specified by the crystal manufacturer. In fact, if CXIN = CXOUT = 10 pF, then CL = 5 pF. Parasitic
capacitance from the package and board must also be considered.
For TPS65921B1, in case of OMAP frequency ≥ 1 GHz, replace 10-µF capacitor on VDD1.OUT by two 22-µF capacitors. One capacitor
must be placed near the PMIC and one near the OMAP device.
Specifications
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4.4
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
Thermal Resistance Characteristics for ZQZ Package
°C/W (1)
(2)
AIR FLOW (m/s) (3)
NAME
DESCRIPTION
RΘJC
Junction-to-case
20
0.00
RΘJB
Junction-to-board
17
0.00
RΘJA
Junction-to-free air
46
0.00
PsiJT
Junction-to-package top
0.3
0.00
PsiJB
Junction-to-board
16
0.00
(1)
(2)
(3)
°C/W = degrees Celsius per watt.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
m/s = meters per second.
4.5
Crystal Oscillator
When selecting a crystal, the system designer must consider the temperature and aging characteristics of a
crystal versus the user environment and expected lifetime of the system. The following table lists the switching
characteristics of the oscillator.
Table 4-1. Base Oscillator Switching Characteristics
PARAMETER
Crystal: Internal capacitor on each input (Cint)
MIN
TYP
MAX
UNIT
8
10
12
pF
1.0
pF
Crystal: Parallel input capacitance (Cpin)
Parallel resonance crystal frequency
32.768
Pin-to-pin capacitance
1.6
Maximum drive power
Operating drive level
Crystal quality factor
tSX
13k
kHz
1.8
pF
1.0
µW
0.5
µW
54k
Start-up time, all conditions
500
Start-up time, 25°C
360
IDDA
Active current
consumption (configured
through the LOJIT bit)
IDDQ
Current consumption
High jitter mode
1.8
Low jitter mode
0.8
Low battery mode (1.2 V)
1
Startup
8
ms
µA
µA
Specifications
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4.6
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Clock Slicer
MODE (1)
PARAMETER
MIN
TYP
MAX
4.2
5
5.7
pF
Internal coupling capacitor
Parallel input resistance over 10 to 40 MHz range
Parallel input capacitance over 10 to 40 MHz range
Output duty cycle with VIN = 0.2 VPP
Propagation delay
Power supply rejection ratio sideband (1% RMS of supply voltage added
sine 5 MHz)
Current consumption at maximum input of 40 MHz
UNIT
LP
15
60
kΩ
HP
30
75
kΩ
BP/PD
1
100
MΩ
LP
0.3
0.8
HP
0.3
0.7
BP/PD
0.08
1
BP/PD
40
LP/HP
40%
pF
230
50%
60%
LP
4
18
HP
3
15
BP/PD
0.2
3
LP/HP
26
ns
dBc
LP
175
µA
HP
235
µA
BP/PD
39
nA
Power-up time
LP/HP
1
ms
Output peak-to-peak jitter with an input peak-to-peak jitter < 0.1% and for
jitter frequency below 300 kHz
LP/HP
0.2%
Output peak-to-peak jitter with an input peak-to-peak jitter < 0.1% and for
jitter frequency above 300 kHz
LP/HP
1.0%
(1)
Bypass input maximum voltage is the same as the maximum voltage provided for the I/O interface.
4.7
32KCLKOUT Output Clock
NAME
PARAMETER DESCRIPTION
f
Frequency
CL
Load capacitance
MIN
TYP
MAX
UNIT
32.768
kHz
40
VOUT
Output clock voltage, depending on output
reference level IO.1P8
VOH
Voltage output high
VOUT – 0.45
VOUT
V
VOL
Voltage output low
0
0.45
V
(1)
1.8
pF
(1)
V
The output voltage depends on output reference level which is IO.1P8.
The following table details the output clock timing characteristics. The following figure shows the 32KCLKOUT
output clock waveform.
NAME
CK0
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
1/tC(32KCLKOUT)
Frequency
tW(32KCLKOUT)
Pulse duration,
32KCLKOUT low or high
CK2
tR(32KCLKOUT)
Rise time, 32KCLKOUT (1)
16
ns
CK3
tF(32KCLKOUT)
Fall time, 32KCLKOUT (1)
16
ns
SSB Phase Noise
At 1-kHz offset from the
carrier
–110
dBc/Hz
CK1
(1)
32.768
kHz
0.40 ×
0.60 ×
tC(32KCLKOUT)
tC(32KCLKOUT)
ns
The output capacitive load is equivalent to 30 pF.
CK0
CK1
CK1
32KCLKOUT
SWCS048-001
Figure 4-1. 32KCLKOUT Output Clock
14
Specifications
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4.8
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
HFCLKOUT Output Clock
The following table summarizes the HFCLKOUT output clock electrical characteristics.
Table 4-2. HFCLKOUT Output Clock Electrical Characteristics
NAME
PARAMETER DESCRIPTION
MIN
TYP
MAX
UNIT
f
Frequency
CL
Load capacitance
VOUT
Output clock voltage, depending on
output reference level IO.1P8
VOH
Voltage output high
VOUT – 0.45
VOUT
V
Voltage output low
0
0.45
V
VOL
(1)
19.2, 26, or 38.4
MHz
30
pF
1.8 (1)
V
The output voltage depends on output reference level which is IO.1P8.
The following table details the HFCLKOUT output clock timing characteristics.
Table 4-3. HFCLKOUT Output Clock Switching Characteristics
NAME
CHO1
CHO2
PARAMETER
DESCRIPTION
1/tC(HFCLKOUT)
Frequency
tW(HFCLKOUT)
Pulse duration, HFCLKOUT low
or high
MIN
TYP
MAX
UNIT
19.2, 26, or 38.4
MHz
0.4 ×
0.6 ×
tC(HFCLKOUT)
tC(HFCLKOUT)
ns
Rise time, HFCLKOUT, low
drive (1)
CHO3
tR(HFCLKOUT)
- Load: 5 pF
3.8
- Load: 10 pF
5.5
ns
Rise time, HFCLKOUT, high
drive (1)
- Load: 10 pF
2.9
- Load: 20 pF
5.0
Fall time, HFCLKOUT, low
drive (1)
CHO4
(1)
tF(HFCLKOUT)
- Load: 5 pF
3.5
- Load: 10 pF
5.1
ns
Fall time, HFCLKOUT, high
drive (1)
- Load: 10 pF
2.7
- Load: 20 pF
4.7
Low drive: MISC_CFG[CLK_HF_DRV] = 0 (default)
High drive: MISC_CFG[CLK_HF_DRV] = 1
Figure 4-2 shows the HFCLKOUT output clock waveform.
CHO1
CHO1
CHO2
HFCLKOUT
SWCS048-002
Figure 4-2. HFCLKOUT Output Clock
Specifications
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Figure 4-3 shows the 32KCLKOUT and HFCLKOUT clock stabilization time.
XIN
Starting_Event
Tstartup
CLK32KOUTEN
CLK32KOUT
CLKEN
Delay1
HFCLKOUTEN
HFCLKOUT
Delay2
NRESPWRON
SWCS048-003
A.
Tstartup, Delay1, Delay2, and Delay3 depend on the boot mode (See Power timing chapter).
Figure 4-3. 32KCLKOUT and HFCLKOUT Clock Stabilization Time
HFCLKIN
HFCLKOUT
SWCS048-004
Figure 4-4. HFCLKOUT Behavior
16
Specifications
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4.9
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
VDD1 DC-DC Converter
MIN
TYP
MAX
UNIT
Input voltage range
PARAMETER
COMMENTS
2.7
3.6
4.5
V
Output voltage
0.6
Output voltage step
0.6 to 1.45 V
Output accuracy (1)
0.6 to < 0.8 V
–6%
0.8 to 1.45 V
–5%
12.5
Switching frequency
Conversion efficiency (2)
Output current
1.45
6%
5%
3.2
IO = 10 mA, sleep
82%
100 mA < IO < 400 mA
85%
400 mA < IO < 600 mA
80%
600 mA < IO < 800 mA
75%
1.2
A
Active mode
Output Voltage 1.2 V to 1.45 V
for TPS65921B1
1.4
A
Sleep mode
10
mA
3
Sleep, unloaded
30
Active, unloaded, not switching
Short-circuit current
VIN = VMAX
Load regulation
0 < IO < IMAX
Transient load regulation at 1.2 A (3)
IO = 10 mA to (IMAX/3) + 10 mA,
maximum slew rate is IMAX/3/100 ns
2.2
–65
300 mVPP ac input, 10-μs rise and fall
time
Start-up time
Recovery time
50
From sleep to on with constant load
Slew rate (rising or falling) (4)
4
A
20
mV
50
mV
10
mV
10
mV
ms
0.25
1
< 10
100
µs
8
16
mV/µs
mV
Active (PWM and PSM)
–10
10
Sleep (PFM)
–2%
2%
Current limit for PWM/PSM mode
switch. PSM is below this limit, and
PWM is above this limit.
Active mode
150
200
Overshoot
Softstart
Output pulldown resistance
In Off mode
Output ripple
(1)
(2)
(3)
(4)
µA
300
Line regulation
Transient line regulation
MHz
Active mode
Output voltage 0.6 V to 1.45 V
for TPS65921B/TPS65921B1
Off at 30°C
Ground current (IQ)
V
mV
mA
5%
500
700
Ω
Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process).
VBAT = 3.6 V, VDD1 = 1.2 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
For negative transient load, the output voltage must discharge completely and settle to its final value within 100 ms. Transient load is
specified at Vout max with a ±50% external capacitor accuracy and includes temperature and process variation.
Load current varies proportional to the output voltage. The slew rate is for increasing and decreasing voltages and the load current is 1.1
A.
Specifications
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4.10 VDD2 DC-DC Converter
MIN
TYP
MAX
UNIT
Input voltage range
PARAMETER
COMMENTS
2.7
3.6
4.5
V
Output voltage
0.6
1.0
1.5
Output voltage step
0.6 to 1.45 V
12.5
Output accuracy (1)
0.6 to < 0.8 V
–6%
0.8 to 1.45 V
–5%
Switching frequency
Conversion efficiency (2)
Output current
Ground current (IQ)
6%
5%
3.2
IO = 10 mA, sleep
82%
100 mA < IO < 300 mA
85%
300 mA < IO < 500 mA
80%
600
mA
Sleep mode
10
mA
Off at 30°C
1
Sleep, unloaded
30
Active, unloaded, not switching
VIN = VMAX
Load regulation
0 < IO < IMAX
Transient load regulation (3)
IO = 10 mA to (IMAX/3) + 10 mA,
maximum slew rate is IMAX/3/100 ns
50
Transient line regulation
300 mVPP ac input, 10-μs rise and fall
time
Output pulldown resistance
In OFF mode
–65
Start-up time
From sleep to on with constant load
Slew rate (rising or falling) (4)
4
A
20
mV
50
mV
10
mV
10
mV
500
700
Ω
0.25
1
ms
25
100
µs
8
16
mV/µs
mV
Active (PWM and PSM)
–10
10
Sleep (PFM)
–2%
2%
Current limit for PWM/PSM mode
switch. PSM is below this limit, and
PWM is above this limit.
Active mode
150
200
Overshoot
Softstart
(1)
(2)
(3)
(4)
18
µA
300
1.2
Line regulation
Output ripple
MHz
Active mode
Short-circuit current
Recovery time
V
mV
mA
5%
Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process).
VBAT = 3.8 V, VDD1 = 1.3 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
Output voltage must be able to discharge the load current completely and settle to its final value within 100 μs.
Load current varies proportional to the output voltage. The slew rate is for increasing and decreasing voltages and the load current is 1.1
A.
Specifications
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4.11 VIO DC-DC Converter
PARAMETER
COMMENTS
Input voltage range
Output voltage
MIN
TYP
MAX
UNIT
2.7
3.6
4.5
V
1.8
1.85
(1)
Output accuracy
DC accuracy only
–3%
3%
Including all variations (line and load
regulations, line and load transients,
temperature, and process)
–4%
4%
Switching frequency
Conversion efficiency (2)
Output current
3.2
IO = 10 mA, sleep
85%
100 mA < IO < 400 mA
85%
400 mA < IO < 600 mA
80%
Load regulation
700
mA
Sleep mode
10
mA
1
Sleep, unloaded
30
50
300
0 < IO < IMAX
20
mV
10
mV
50
mV
10
mV
0.25
1
ms
< 10
100
µs
8
16
mV/µs
mV
Transient load regulation
IO = 10 mA to (IMAX/3) + 10 mA,
maximum slew rate is IMAX/3/100 ns
Transient line regulation
300 mVPP ac input, 10-μs rise and fall
time
–65
Start-up time
From sleep to on with constant load
Slew rate (rising or falling)
4
Active (PWM and PSM)
–10
10
Sleep (PFM)
–2%
2%
Current limit for PWM/PSM mode
switch. PSM is below this limit, and
PWM is above this limit.
Active mode
150
200
Overshoot
Softstart
Output pulldown resistance
In Off mode
Output ripple
(1)
(2)
µA
Active, unloaded, not switching
Line regulation
Recovery time
MHz
On mode
Off at 30°C
Ground current (IQ)
V
mA
5%
500
700
Ω
This voltage is tuned according to the platform and transient requirements.
VBAT = 3.8 V, VIO = 1.8 V, Fs = 3.2 MHz, L = 1 μH, LDCR = 100 mΩ, C = 10 μF, ESR = 10 mΩ
Specifications
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4.12 VMMC1 Low Dropout Regulator
PARAMETER
VIN
Input voltage
VOUT
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
IOUT
Rated output current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.7
3.6
5.5
V
1.7945
2.7645
2.91
3.0555
1.85
2.85
3.0
3.15
1.9055
2.9355
3.09
3.2445
V
On mode
220
mA
Low-power mode
5
DC load regulation
On mode: 0 < IO < IMAX
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
mV
Turn-on time
IOUT = 0, CL = 1 μF (within 10%
of VOUT)
100
µs
Wake-up time
Full load capability
10
µs
Ripple rejection
f < 10 kHz
50
10 kHz < f < 100 kHz
40
f = 1 MHz
25
dB
VIN = VOUT + 1 V, IO = IMAX
Ground current
On mode, IOUT = 0
70
On mode, IOUT = IOUTmax
290
Low-power mode, IOUT = 0
17
Low-power mode, IOUT = 5 mA
20
Off mode at 55°C
VDO
Dropout voltage (1)
Transient load regulation (2)
Transient line regulation
(1)
(2)
20
1
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
Slew: 40 mA/μs
–40
VIN drops 500 mV
Slew: 40 mV/μs
Overshoot
Softstart
Pulldown resistance
Default in off mode
µA
250
mV
40
mV
10
mV
3%
250
320
450
Ω
For nominal output voltage
Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
Specifications
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4.13 VDAC Low Dropout Regulator
PARAMETER
VIN
Input voltage
VOUT
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
IOUT
Rated output current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.7
3.6
4.5
V
1.164
1.261
1.746
12
1.3
1.8
1.236
1.339
1.854
V
On mode
70
Low-power mode
5
DC load regulation
On mode: 0 < IO < IMAX
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
mV
Turn-on time
IOUT = 0, CL = 1 μF (within 10% of
VOUT)
100
µs
Wake-up time
Full load capability
10
µs
Ripple rejection
f < 20 kHz
65
20 kHz < f < 100 kHz
45
f = 1 MHz
40
mA
dB
VIN = VOUT + 1 V, IO = IMAX
Output noise
Ground current
200 Hz < f < 5 kHz
400
5 kHz < f < 400 kHz
125
400 kHz < f < 10 MHz
50
On mode, IOUT = 0
150
On mode, IOUT = IOUTmax
350
Low-power mode, IOUT = 0
15
Low-power mode, IOUT = 1 mA
25
Off mode at 55°C
VDO
Dropout voltage (1)
Transient load regulation (2)
Transient line regulation
(1)
(2)
Slew: 60 mA/μs
–40
VIN drops 500 mV
Slew: 40 mV/μs
Overshoot
Softstart
Pull down resistance
Default in off mode
µA
1
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
nV/√Hz
250
mV
40
mV
10
mV
3%
250
320
450
Ω
For nominal output voltage
Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
Specifications
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4.14 VAUX2 Low Dropout Regulator
PARAMETER
VIN
TEST CONDITIONS
Input voltage
VOUT
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
IOUT
Rated output current
MIN
TYP
MAX
UNIT
2.7
3.6
4.5
V
–3%
1.3
1.5
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.8
+3%
V
On mode
100
mA
Low-power mode
5
DC load regulation
On mode: 0 < IO < IMAX
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
mV
Turn-on time
IOUT = 0, CL = 1 μF (within 10% of
VOUT)
100
µs
Wake-up time
Full load capability
10
µs
Ripple rejection
f < 10 kHz
50
10 kHz < f < 100 kHz
40
f = 1 MHz
30
dB
VIN = VOUT + 1 V, IO = IMAX
Ground current
On mode, IOUT = 0
70
On mode, IOUT = IOUTmax
170
Low-power mode, IOUT = 0
17
Low-power mode, IOUT = 5 mA
20
Off mode at 55°C
VDO
Dropout voltage (1)
Transient load regulation (2)
Transient line regulation
Overshoot
Pulldown resistance
(1)
(2)
22
1
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
Slew: 40 mA/μs
µA
–40
VIN drops 500 mV
Slew: 40 mV/μs
Softstart
250
mV
40
mV
10
mV
3%
Default in off mode
250
Configurable as HighZ in off mode
100
320
450
Ω
MΩ
For nominal output voltage
Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
Specifications
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4.15 VPLL1 Low Dropout Regulator
PARAMETER
VIN
VOUT
IOUT
MIN
TYP
MAX
UNIT
Input voltage
TEST CONDITIONS
2.7
3.6
4.5
V
Output voltage including all
variations (line and load
regulations, line and load
transients, temperature, and
process)
0.97
1.0
1.03
1.164
1.2
1.236
1.261
1.3
1.339
1.746
1.8
1.854
V
On mode
40
Low-power mode
5
DC load regulation
On mode: 0 < IO < IMAX
20
mV
DC line regulation
On mode, VIN = VINmin to VINmax
at IOUT = IOUTmax
3
mV
Turn-on time
IOUT = 0, CL = 1 μF (within 10% of
VOUT)
100
µs
Wake-up time
Full load capability
10
µs
Rated output current
Ripple rejection
f < 10 kHz
50
10 kHz < f < 100 kHz
40
f = 1 MHz
30
mA
dB
VIN = VOUT + 1 V, IO = IMAX
Ground current
On mode, IOUT = 0
70
On mode, IOUT = IOUTmax
110
Low-power mode, IOUT = 0
15
Low-power mode, IOUT = 1 mA
16
Off mode at 55°C
VDO
Dropout voltage (1)
Transient load regulation (2)
Transient line regulation
(1)
(2)
1
On mode, IOUT = IOUTmax
ILOAD: IMIN – IMAX
Slew: 60 mA/μs
–40
VIN drops 500 mV
Slew: 40 mV/μs
Overshoot
Softstart
Pulldown resistance
Default in off mode
µA
250
mV
40
mV
10
mV
3%
250
320
450
Ω
For nominal output voltage
Transient load regulation is always included in the overall accuracy of the selected output voltage option. For voltage levels that have a
tighter output voltage specification than the transient load regulation, follow the output voltage specification.
Specifications
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4.16 Internal LDOs
Internal LDOs (except USBCP, which is a boost) are described in following table.
NAME
USAGE
TYPE
VOLTAGE RANGE
(V)
DEFAULT
VOLTAGE (V)
MAXIMUM
CURRENT
VINTANA1
Internal
LDO
1.5
1.5
50 mA
VINTANA2
Internal
LDO
2.5, 2.75
2.75
250 mA
VINTDIG
Internal
LDO
1.5
1.5
100 mA
USBCP
Internal
Charge pump
5
5
100 mA
VUSB1V5
Internal
LDO
1.5
1.5
30 mA
VUSB1V8
Internal
LDO
1.8
1.8
30 mA
VUSB3V1
Internal
LDO
3.1
3.1
14 mA
VRRTC
Internal
LDO
1.5
1.5
30 mA
VBRTC
Internal
LDO
1.3
1.3
100 μA
4.17 Voltage References
TEST CONDITONS
MIN
TYP
MAX
UNIT
Internal bandgap reference
voltage
PARAMETER
On mode, measured through
TESTV terminal
1.272
1.285
1.298
V
Reference voltage (VREF
terminal)
On mode
0.7425
0.75
0.7575
V
Retention mode reference
On mode
0.492
0.5
0.508
V
0.9
1.0
1.1
µA
IREF NMOS sink
Ground current
Output spot noise
Bandgap
25
IREF block
20
Preregulator
15
VREF buffer
10
Retention reference buffer
10
100 Hz
P-weighted noise (rms)
20 Hz to 100 kHz
200
nV (rms)
150
nV (rms)
2.2
µV
IBIAS trim bit LSB
Ripple rejection
μV/√Hz
1
A-weighted noise (rms)
Integrated noise
µA
< 1 MHz from VBAT
0.1
µA
1
ms
60
dB
Start-up time
4.18 Battery Threshold Levels (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Main battery charged
threshold VMBCH
Measured on VBAT terminal
3.14
3.2
3.3
V
Main battery low threshold
VMBLO
Measured on VBAT terminal (monitored
on terminal ONNOFF)
2.55
2.7
2.8
V
Main battery high threshold
VMBHI
Measured on terminal VBAT
2.5
2.65
3.0
V
Measured on terminal VBAT
1.6
1.8
2.6
V
Measured on terminal VBAT in slave
mode
1.95
2.1
2.6
V
Batteries not present
threshold VBNPR
(1)
24
Backup ball must always be tied to ground.
Specifications
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4.19 Power Consumption
The typical power consumption is obtained in the nominal operating conditions and with the TPS65921
standalone.
MODE
TYPICAL
CONSUMPTION
DESCRIPTION
C021 boot mode
WAIT-ON
ACTIVE No Load
HFCLK = 26 MHz
ACTIVE No Load
HFCLK = 38.4 MHz
The phone is apparently off for the user, a
main battery is present and well-charged.
The RTC registers, registers in backup
domain are maintained. The wakeup
capabilities (like the PWRON button) are
available.
VBAT = 3.8 V and
Quartz present
Subsystem is powered by the main battery.
All supplies are enabled with no external
load, internal reset is released, and the
associated processor is running. USB
interrupt handler consumes 433 µA (typ).
VBAT = 3.8 V
The main battery powers subsystem.
Selected supplies are enabled but in lowconsumption mode and associated
processor is in low-power mode.
VBAT = 3.8 V
SLEEP No Load
64 µA × 3.8 V =
243.2 μW
(2995 + 433) µA ×
3.8 V = 13026 µW
(3879 + 433) µA ×
3.8 V = 16386 µW
492 µA × 3.8 V =
1870 µW
4.20 USB Charge Pump
PARAMETER
VIN
Input voltage
VO
Output voltage
Iload
Rated output current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
On mode: VIN = VBAT
2.7
3.6
4.5
V
4.625
5.0
5.25
V
VBAT > 3 V at VBUS
0
100
2.7 V < VBAT < 3 V, at VBUS
0
50
Efficiency
ILOAD = 100 mA, VBAT = 3.6 V
55%
Setting time
ILOADmax/2 to ILOADmax in 5 μs
100
400
µs
3
ms
350
450
mA
250
500
mV
250
350
mV
300
350
Start-up time
Short-circuit limitation current
250
DC load regulation
ILOADmin to ILOADmax
3.0 V to VBATmax
DC line regulation
ILOAD = 100 mA
IVBUS_5Vmax/2 – IVBUS_5Vmax
50 μs, C = 2 × 4.7 μF
Transient load regulation
mV
0 – IVBUS_5Vmax/2, 50 μs, C = 2
× 4.7 μF
Transient line regulation
VBATmin to VBATmax in 50 μs,
C = 2 × 4.7 μF
mA
350
300
350
mV
Specifications
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4.21 Hot-Die Detection and Thermal Shutdown
PARAMETER
THRESHOLD (NOMINAL) (1)
Thermal hot-die selection THERM_HDSEL[1:0]
Threshold (nominal) (1)
Rising temp: 120°C
00 (1st hot-die threshold)
Falling temp: 111°C
Rising temp: 130°C
01 (2nd hot-die threshold)
Falling temp: 121°C
Rising temp: 140°C
10 (3rd hot-die threshold)
Falling temp: 131°C
11 (4th hot-die threshold)
Not used
Threshold (nominal) (1) - Rising temp: 150°C
Thermal shutdown enable
(1)
Threshold (nominal) (1) - Falling temp: 140°C
The minimum/maximum range is ±5%
4.22 USB
4.22.1 LS/FS Single-Ended Receivers
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
0
2
ns
USB Single-Ended Receivers
Skew
between VP
and VM
SKWVP_VM
Driver outputs unloaded
Single-ended
hysteresis
VSE_HYS
50
High (driven)
VIH
2
Low
VIL
Switching
threshold
VTH
–2
mV
V
0.8
0.8
V
2
V
MAX
UNIT
4.22.2 LS/FS Differential Receiver
PARAMETER
COMMENTS
MIN
Differential input sensitivity
VDI
Ref. USB2.0
200
Differential common mode
range
VCM
Ref. USB2.0
0.8
TYP
mV
2.5
V
MAX
UNIT
4.22.3 LS/FS Transmitter
PARAMETER
COMMENTS
MIN
TYP
Low
VOL
Ref. USB2.0
0
300
mV
High (driven)
VOH
Ref. USB2.0
2.8
3.6
V
Output signal crossover
voltage
VCRS
Ref. USB2.0, covered by eye
diagram
1.3
2.0
V
Rise time
TFR
75
300
ns
Fall time
TFF
75
300
ns
Differential rise and fall time
matching
TFRFM
80%
125%
Low-speed data rate
TFDRATE
Ref. USB2.0, covered by eye
diagram
1.4775
1.5225
Mbps
- To next transition
TDJ1
Ref. USB2.0, covered by eye
diagram
–25
25
ns
- For paired transitions
TDJ2
–10
10
Ref. USB2.0, covered by eye
diagram
Source jitter total (including
frequency tolerance):
26
Specifications
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PARAMETER
Source SE0 interval of EOP
TFEOPT
Downstream eye diagram
Differential common mode
range
COMMENTS
MIN
Ref. USB2.0, covered by eye
diagram
TYP
MAX
UNIT
1.25
1.5
µs
0.8
2.5
V
MAX
UNIT
Ref. USB2.0, covered by eye
diagram
VCM
Ref. USB2.0
4.22.4 FS Transmitter
PARAMETER
COMMENTS
MIN
TYP
Low
VOL
Ref. USB2.0
0
300
mV
High (driven)
VOH
Ref. USB2.0
2.8
3.6
V
Output signal crossover
voltage
VCRS
Ref. USB2.0, covered by eye
diagram
1.3
2.0
V
Rise time
TFR
Ref. USB2.0
4
20
ns
Fall time
TFF
Ref. USB2.0
4
20
ns
Differential rise and fall time
matching
TFRFM
Ref. USB2.0, covered by eye
diagram
90%
111.11%
Driver output resistance
ZDRV
Ref. USB2.0
28
44
Ω
Full-speed data rate
TFDRATE
Ref. USB2.0, covered by eye
diagram
11.97
12.03
Mbps
- To next transition
TDJ1
Ref. USB2.0, covered by eye
diagram
–2
2
ns
- For paired transitions
TDJ2
–1
1
Source SE0 interval of EOP
TFEOPT
160
175
ns
MAX
UNIT
Source jitter total (including
frequency tolerance):
Downstream eye diagram
Ref. USB2.0, covered by eye
diagram
Ref. USB2.0, covered by eye
diagram
Upstream eye diagram
4.22.5 HS Differential Receiver
PARAMETER
COMMENTS
MIN
TYP
High-speed squelch detection VHSSQ
threshold (differential signal
amplitude)
Ref. USB2.0
100
150
mV
High-speed disconnect
detection threshold
(differential signal amplitude)
Ref. USB2.0
525
625
V
VHSDSC
High-speed differential input
signaling levels
Ref. USB2.0, specified by
eye pattern templates
High-speed data signaling
VHSCM
common mode voltage range
(guidelines for receiver)
Ref. USB2.0
Receiver jitter tolerance
mV
–50
Ref. USB2.0, specified by
eye pattern templates
600
mV
150
ps
Specifications
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4.22.6 HS Transmitter
PARAMETER
MAX
UNIT
Ref. USB2.0
COMMENTS
–10
10
mV
Ref. USB2.0
360
440
mV
Ref. USB2.0
–10
10
mV
Ref. USB2.0
700
1100
mV
Ref. USB2.0
–825
–500
mV
THSR
Ref. USB2.0, covered by eye
diagram
500
Fall time (10% – 90%)
THSR
Ref. USB2.0, covered by eye
diagram
500
Driver output resistance
(which also serves as highspeed termination)
ZHSDRV
Ref. USB2.0
40.5
49.5
Ω
High-speed data range
THSDRAT
479.76
480.24
Mbps
High-speed idle level
VHSOI
High-speed data signaling
high
VHSOH
High-speed data signaling
low
VHSOL
Chirp J level (differential
voltage)
VCHIRPJ
Chirp K level (differential
voltage)
VCHIRPK
Rise Time (10% – 90%)
Ref. USB2.0, covered by eye
diagram
Data source jitter
Ref. USB2.0, covered by eye
diagram
Downstream eye diagram
Ref. USB2.0, covered by eye
diagram
Upstream eye diagram
Ref. USB2.0, covered by eye
diagram
MIN
TYP
4.22.7 UART Transceiver
PARAMETER
MIN
tPH_DP_CON
Phone D+ connect time
100
tPH_DISC_DET
Phone D+ disconnect time
150
fUART_DFLT
Default UART signaling rate (typical rate)
PARAMETER
COMMENTS
MAX
UNIT
ms
ms
9600
MIN
bps
TYP
MAX
UNIT
1
ms
2.4
3.3
3.6
V
0
0.1
0.4
V
UART Transmitter CEA-2011
Phone UART edge rates
tPH_UART_EDGE
DP_PULLDOWN asserted
Serial interface output high
VOH_SER
ISOURCE = 4 mA
Serial interface output low
VOL_SER
ISINK = –4 mA
Serial interface input high
VIH_SER
DP_PULLDOWN asserted
Serial interface input low
VIL_SER
DP_PULLDOWN asserted
Switching threshold
VTH
UART Receiver CEA-2011
28
2.0
0.8
Specifications
V
0.8
V
2.0
V
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4.22.8 Pullup/Pulldown Resistors
PARAMETER
COMMENTS
MIN
TYP
MAX
0.9
1.1
1.575
2.2
3.09
UNIT
Pullup Resistors
Bus pullup resistor on
upstream port (idle bus)
RPUI
Bus idle
Bus pullup resistor on
upstream port (receiving)
RPUA
Bus driven/driver's outputs
unloaded
1.425
High (floating)
VIHZ
Pullups/pulldowns on both
DP and DM lines
2.7
Phone D+ pullup voltage
VPH_DP_UP
Driver's outputs unloaded
3.0
Driver's outputs unloaded
14.25
2.7
kΩ
3.6
V
3.3
3.6
V
18
24.8
kΩ
3.6
V
75
pF
0.342
V
Pulldown Resistors
Phone D+/– pulldown
RPH_DP_DWN
RPH_DM_DWN
High (floating)
VIHZ
Pullups/pulldowns on both
DP and DM lines
Upstream facing port
CINUB
[1.0]
On-the-go device leakage
VOTG_DATA_LKG
[2]
Input impedance exclusive
of pullup/pulldown
ZINP
Driver’s outputs unloaded
D+/– Data line
22
300
kΩ
4.22.9 OTG VBUS
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
15
µs
VBUS Wakeup Comparator
VBUS wake-up delay
DELVBUS_WK_
UP
VBUS Comparators
A-device session valid
VA_SESS_VLD
0.8
1.1
1.4
V
A-device VBUS valid
VA_VBUS_VLD
4.4
4.5
4.625
V
B-device session end
VB_SESS_END
0.2
0.5
0.8
V
B-device session valid
VB_SESS_VLD
2.1
2.4
2.7
V
100
kΩ
VBUS Line
A-device VBUS input
impedance to ground
RA_BUS_IN
SRP (VBUS pulsing) capable
A-device not driving VBUS
13.77
B-device VBUS SRP
pulldown
RB_SRP_DWN
5.25 V / 8 mA, pullup voltage
=3V
0.656
10
RB_SRP_UP
(5.25 V – 3 V) / 8 mA, pullup
voltage = 3 V
0.85
1.3
B-device VBUS SRP rise
time maximum for OTG-A
communication
tRISE_SRP_UP_
0 to 2.1 V with < 13 μF load
B-device VBUS SRP rise
time minimum for standard
host connection
tRISE_SRP_UP_
B-device VBUS SRP pullup
kΩ
1.75
kΩ
34
ms
MAX
0.8 to 2.0 V with > 97 μF load
46
COMMENTS
MIN
ms
MIN
4.22.10 OTG ID
PARAMETER
TYP
MAX
UNIT
100
kΩ
25
kΩ
500
kΩ
VBUS Wakeup Comparator
ID wake-up comparator
RID_WK_UP
Wakeup when ID shorted to
ground.
30
ID Comparators — ID External Resistors Specifications
ID ground comparator
RID_GND
ID_GND interrupt
ID Float comparator
RID_FLOAT
ID_FLOAT interrupt
4
200
20
ID Line
Specifications
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MIN
TYP
MAX
UNIT
Phone ID pullup to VPH_ID_UP
PARAMETER
RPH_ID_UP
ID unloaded (VRUSB)
COMMENTS
70
90
286
kΩ
Phone ID pullup voltage
VPH_ID_UP
Connected to VRUSB
2.5
3.2
V
5.25
V
ID line maximum voltage
4.22.11 USB Charger Detection
USB Charger Detection Debounce Time
REQUIREMENT
PARAMETER
MAX
UNIT
Minimum 10 ms
DEBVBUS_TIME
NB CLOCK
448
ACTIVE/SLEEP mode
TEST CONDITIONS
13.7
MIN
TYP
13.7
ms
Minimum 20 ms
DEBUSBCHG_TIM
E
896
ACTIVE/SLEEP mode
27.3
27.3
ms
Table 4-4. Voltages
PARAMETER
SYMBOL
MIN
MAX
UNIT
REF
0.8
2.0
V
1.4.4
0.5
0.675
V
VDAT_REF
0.25
0.4
V
VDAT_LKG
0
3.6
V
3.9
MAX
UNIT
REF
710
mA
3.6.2
Logic Threshold
VLGC
D+ Source Voltage
VDP_SRC
Data Detect Voltage
Data Line Leakage Voltage
CONDITIONS
Output current
> 250 µA
Table 4-5. Currents
PARAMETER
SYMBOL
Portable Device Current from
Charging Host Port during chirp
CONDITIONS
MIN
IDEV_HCHG_CHRP
Data Contact Detect Current
Source
IDP_SRC
7
13
µA
D- Sink Current
IDM_SINK
50
150
µA
Table 4-6. Resistances
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNIT
D+ pulldown resistance
RDP_DWN
14.25
24.8
kΩ
D- pulldown resistance
RDM_DWN
14.25
24.8
kΩ
Table 4-7. USB Charger Detection (Wait and Debounce Timing)
USB Charger Detection (Wait and Debounce Timing)
Requirement
PARAMETER
NB
CLOCK
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum 200 us
D+ Current source ontime
TIDP_SRC_ON
8
ACTIVE/SLEEP
mode (1)
244.1
244.1
µs
Minimum 40 ms
D+ Voltage source ontime
TVDP_SRC_ON
1792
ACTIVE/SLEEP
mode (1)
54.7
54.7
ms
Minimum 40 ms
D+ Voltage source off
to high current
TVDP_SRC_HICRNT
1792
ACTIVE/SLEEP
mode (1)
54.7
54.7
ms
Minimum 2 s
DATA_CONTACT_DET
ECT Timeout
TDCD_TIMEOUT
89600
ACTIVE/SLEEP
mode (1)
2.73
2.73
s
(1)
30
Note: LS Device mode not supported
Specifications
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4.23 MADC
PARAMETER
CONDITIONS
MIN
TYP
Resolution
MAX
UNIT
10
Input dynamic range for external
input ADCIN0
Bit
0
1.5
V
–1
1
LSB
2
LSB
28.5
mV
MADC voltage reference
1.5
Differential nonlinearity
Integral nonlinearity
Best fitting
–2
Offset
Best fitting
–28.5
Input bias
V
μA
1
Input capacitor CBANK
10
pF
Input current leakage
1
μA
4.23.1 MADC Analog Input Range and Prescaler Ratio
MADC CHANNEL
INT/EXT
ADCIN0: Generalpurpose input (1)
External
ADCIN1:7 Reserved
Internal
ADCIN8: VBUS Voltage
(VBUS)
Internal
ADCIN9: Reserved
Internal
ADCIN10:11 Reserved
Internal
ADCIN12: Main battery
voltage (VBAT)
Internal
ADCIN13:15 Reserved
Internal
(1)
(2)
(3)
ANALOG INPUT RANGE
(V)
PRESCALER
OUTPUT RANGE (V)
MIN
MAX
DIVIDER
RATIO
1.5
N/A
N/A
1
N/A
N/A
N/A
N/A
MIN
MAX
0.0
N/A
NOTE
No prescaler
Not used
Prescaler in USB
subchip.
0.0
6.5
0.0
1.5
3/14
N/A
N/A
N/A
N/A
N/A
2.7
4.7
0.675
1.175
0.25
N/A
N/A
N/A
N/A
N/A
Rdivider = (6 × 2.76
kΩ)/(28 × 2.76 kΩ)
(typ) (2)
Not used
Prescaler integrated
Rdivider = 9.85 kΩ/(4 ×
9.85 kΩ) (typ) (3)
General-purpose input has to be tied to ground when TPS65921 internal power supply (VINTANA1) is off.
Tolerance for resistors-type (PL_VHSR): ±19%
Tolerance for resistors-type (PL_HR): ±12%
The table below summarizes the sequence conversion timing characteristics. Figure 4-5 shows one conversion
sequence general timing diagram.
Specifications
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Table 4-8. Sequence Conversion Timing Characteristics
PARAMETER
COMMENTS
MIN
TYP
MAX
UNIT
F
Running frequency
1
MHz
T = 1/F
Clock period
1
μs
N
Number of analog inputs to convert in a
single sequence
0
16
Tstart
SW1, SW2, or USB asynchronous request
or real-time STARTADC request
3
4
μs
Tsettling time
Settling time to wait before sampling a
stable analog input (capacitor bank charge
time)
260
μs
Tsettling is calculated from the max((Rs +
Ron)*Cbank) of all possible input sources
(internal or external). Ron is the resistance
of the selection analog input switches (5
kΩ). This time is software programmable by
OCP register; default value is 12 µs.
5
12
Tstartsar
The successive approximation registers
ADC start time
1
μs
Tadc time
The successive approximation registers
ADC conversion time
10
μs
Tcapture time
Tcapture time is the conversion result
capture time.
2
μs
Tstop
1
2
Full Conversion
Sequence Time
Only one channel (N = 1) (1)
22
39
All channels (2)
352
624
Conversion
Sequence Time
Without Tstart and Tstop: Only one channel
(N = 1) (1)
18
33
288
528
Without Tstart and Tstop: All channels
STARTADC pulse
duration
(1)
(2)
32
STARTADC period is T
(1)
μs
μs
μs
μs
0.33
General-purpose input ADCIN0 must be tied to ground when TPS65921 internal power supplies (VINTANA1) is off.
Total Sequence Conversion Time General Formula: Tstart + N × (1 + Tsettling + Tadc + Tcapture) + Tstop.
Specifications
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This table is illustrated in Figure 4-5. The Busy parameter indicates that a conversion sequence is running, and
the channel N result register parameter corresponds to the result register of RT/GP selected channel.
T one conversion
Tstartsar
Tstart
Tcapture
Tsettling
Tadc
Tstop
madc_clk
Busy
mux_sel_lowv[3:0]
Channel N selected
Acquire_lowv
start_sar_lowv
out_lowv[9:0]
Channel N
result register
New channel N value
Channel X value
Old value
New value
SWCS048-005
Figure 4-5. One Conversion Sequence General Timing Diagram
4.23.2 MADC Power Consumption
PARAMETER
Power on consumption
TEST CONDITIONS
MIN
Running frequency f = 1 MHz
TYP
UNIT
mA
1
μA
Power down consumption
(1)
MAX
1 (1)
The consumption is given in stand-alone mode.
4.24 TPS65921 Interface Target Frequencies
Table below assumes testing over the recommended operating conditions.
I/O INTERFACE
INTERFACE DESIGNATION
TARGET FREQUENCY
1.5 V
SmartReflex I2C
General-purpose I2C
USB
JTAG
I2C Interface
USB
Slave high-speed mode
3.6 Mbps
Slave fast-speed mode
400 kbps
Slave standard mode
100 kbps
High speed
480 Mbps
Full speed
12 Mbps
Low speed
1.5 Mbps
Real/View® ICE tool
30 MHz
XDS560 and XDS510 tools
30 MHz
Lauterbach™ tool
30 MHz
Specifications
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4.24.1 I2C Timing
The TPS65921 provides two I2C HS slave interfaces (one for general-purpose and one for SmartReflex). These
interfaces support the standard mode (100 kbps), fast mode (400 kbps), and HS mode (3.5 Mbps). The generalpurpose I2C module embeds four different slave hard-coded addresses (ID1 = 48h, ID2 = 49h, ID3 = 4Ah, and
ID4 = 4Bh). The SmartReflex I2C module uses one slave hard-coded address (ID5). The master mode is not
supported.
Table 4-9 and Table 4-10 assume testing over the recommended operating conditions.
START
I1
I2C.SCL
RESTART
STOP
I2
1
8
9
1
I8
8
9
I8
I3
I2C.SDA
I4
I7
MSB
LSB
ACK
I9
MSB
LSB
ACK
SWCS048-006
2
Figure 4-6. I C Interface—Transmit and Receive in Slave Mode
34
Specifications
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Table 4-9. I2C Interface Timing Requirements (1) (2)
NO.
PARAMETER
MIN
MAX
UNIT
Slave High-Speed Mode
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
10
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
ns
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
160
ns
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
160
ns
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
160
ns
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
100
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
0.6
µs
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
0.6
µs
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
0.6
µs
ns
70
ns
Slave Fast-Speed Mode
ns
0.9
µs
Slave Standard Mode
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
250
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
ns
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
4.7
µs
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
4
µs
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
4
µs
(1)
(2)
The input timing requirements are given by considering a rising or falling time of:
80 ns in high-speed mode (3.4 Mbits/s)
300 ns in fast-speed mode (400 Kbits/s)
1000 ns in standard mode (100 Kbits/s)
SDA is equal to I2C.SR.SDA or I2C.CNTL.SDA
SCL is equal to I2C.SR.SCL or I2C.CNTL.SCL
Table 4-10. I2C Interface Switching Requirements (1) (2)
NO.
PARAMETER
MIN
MAX
UNIT
Slave High-speed Mode
I1
tw(SCLL)
Pulse duration, SCL low
160
ns
I2
tw(SCLH)
Pulse duration, SCL high
60
ns
Slave Fast-speed Mode
I1
tw(SCLL)
Pulse duration, SCL low
1.3
µs
I2
tw(SCLH)
Pulse duration, SCL high
0.6
µs
Slave Standard Mode
I1
I2
(1)
(2)
tw(SCLL)
Pulse duration, SCL low
4.7
µs
tw(SCLH)
Pulse duration, SCL high
4
µs
The capacitive load is equivalent to:
100 pF in high-speed mode (3.4 Mbits/s)
400 pF in fast-speed mode (400 Kbits/s)
400 pF in standard mode (100 Kbits/s)
SDA is equal to I2C.SR.SDA or I2C.CNTL.SDA
SCL is equal to I2C.SR.SCL or I2C.CNTL.SCL
Specifications
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4.25 JTAG Interfaces
Table 4-11 and Table 4-12 assume testing over the recommended operating conditions.
JL1
JL2
JL2
JTAG.TCK
JL3
JL4
JL5
JL6
JTAG.TDI
JTAG.TMS
JL7
JTAG.TDO
SWCS048-007
Figure 4-7. JTAG Interface Timing
The input timing requirements are given by considering a rising or falling edge of 7 ns.
4.25.1 JTAG Interface Timing Requirements
Table 4-11. JTAG Interface Timing Requirements
NO.
PARAMETER
MIN
MAX
UNIT
Clock
JL1
tc(TCK)
Cycle time, JTAG.TCK period
JL2
tw(TCK)
Pulse duration, JTAG.TCK high or
low (1)
30
0.48 × P
ns
0.52 × P
ns
Read Timing
JL3
tsu(TDIV-TCKH)
Setup time, JTAG.TDI valid before
JTAG.TCK high
8
ns
JL4
th(TDIV-TCKH)
Hold time, JTAG.TDI valid after
JTAG.TCK high
5
ns
JL5
tsu(TMSV-TCKH)
Setup time, JTAG.TMS valid before
JTAG.TCK high
8
ns
JL6
th(TMSV-TCKH)
Hold time, JTAG.TMS valid after
JTAG.TCK high
5
ns
(1)
P = JTAG.TCK clock period
The capacitive load is equivalent to 35 pF.
36
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4.25.2 JTAG Interface Switching Characteristics
Table 4-12. JTAG Interface Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
0
14
ns
MIN
MAX
UNIT
Write Timing
td(TCK-TDOV))
JL7
NO.
Delay time, JTAG, TCK active edge to
JTAG.TDO valid
PARAMETER
Clock
JL1
tc(TCK)
Cycle time, JTAG.TCK period
JL2
tw(TCK)
Pulse duration, JTAG.TCK high or
low (1)
30
JL3
tsu(TDIV-TCKH)
Setup time, JTAG.TDI valid before
JTAG.TCK high
8
ns
JL4
th(TDIV-TCKH)
Hold time, JTAG.TDI valid after
JTAG.TCK high
5
ns
JL5
tsu(TMSV-TCKH)
Setup time, JTAG.TMS valid before
JTAG.TCK high
8
ns
JL6
th(TMSV-TCKH)
Hold time, JTAG.TMS valid after
JTAG.TCK high
5
ns
0.48 × P
ns
0.52 × P
ns
Read Timing
(1)
P = JTAG.TCK clock period
4.25.3 Debouncing Time
Debounce times are listed in Table 4-13.
Table 4-13. Debouncing Time
DEBOUNCING FUNCTIONS
PROGRAMMABLE
DEBOUNCING
TIME
DEFAULT
No
580 μs
580 μs
Main battery low threshold detection ( 3.0 V supply, USB PHY
cannot directly operate from VBAT.USB for battery voltages lower than 3.3 V.
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In such case, VBUS should be supplied by a boosted voltage to ensure enough overhead for USB LDO
operation. An internal charge pump (whose output is connected to VBUS) can be used for this purpose.
To select between these two power sources, a power mux is connected to the VUSB3V1 LDO supply.
The VUSB1V8 and VUSB1V5 internal LDO regulators power the USB subchip inside the TPS65921
device.
The short-circuit current for the LDOs and DC-DCs in the TPS65921 device is approximately twice the
maximum load current. In certain cases when the output of the block is shorted to ground, the power
dissipation can exceed the 1.2 W requirement if no action is taken. A short-circuit protection scheme is
included in the TPS65921 device to ensure that if the output of an LDO or DC-DC converter is shortcircuited, then the power dissipation does not exceed the 1.2-W level.
The three USB LDOs VUSB3V1, VUSB1V8, and VUSB1V5 are included in this short circuit protection
scheme which monitors the LDO output voltage at a frequency of 1 Hz, and generates an interrupt when a
short circuit is detected.
The scheme compares the LDO output voltage to a reference voltage and detects a short circuit if the
LDO voltage drops below this reference value (0.5 V or 0.75 V programmable). In the case of the
VUSB3V1 and VUSB1V8 LDOs, the reference is compared with a divided down voltage (1.5 V typical).
If a short circuit is detected on VUSB3V1, then the power subchip FSM switches this LDO to sleep-mode.
If a short circuit is detected on VUSB1V8 or VUSB1V5, then the power subchip FSM switches the relevant
LDO off.
5.5.3
Power Reference
The bandgap voltage reference is filtered (RC filter), using an external capacitor connected across the
VREF output and an analog ground (REFGND). The VREF voltage is scaled, distributed, and buffered
inside the device. The bandgap is started in fast mode (not filtered) and is set automatically by the power
state-machine in slow mode (filtered, less noisy) after switch on.
5.5.4
Power Use Cases
The TPS65921 device has two modes:
• Master: The TPS65921 device decides to power up or down the system and control the other power
ICs in the system with the SYSEN output.
• Slave: The TPS65921 device is controlled by another power IC with a digital signal on the PWRON
input. There is no battery management in slave mode.
The modes corresponding to BOOT0–BOOT1 combination value are:
BOOT0
BOOT1
MC021 (1)
NAME
Master_C021_Generic 10
1
0
SC021
Slave_C021_Generic 11
1
1
(1)
DESCRIPTION
Boot mode for OMAP3430 is c021 Master boot mode.
Process modes define:
• The boot voltage for the host core
• The boot sequence associated with the process
• The DVFS protocol associated with the process
MODE
C021.M
Boot core voltage
1.2 V
Power sequence
VIO followed by VPLL1, VDD2, VDD1
DVFS protocol
SmartReflex interface (I2C high speed)
44
Detailed Description
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Regulator states depending on use cases:
REGULATOR
MODE: C021 (MASTER/SLAVE)
BACKUP
WAIT ON
SLEEP NO LOAD
ACTIVE NO LOAD
VAUX2
OFF
OFF
OFF
OFF
VMMC1
OFF
OFF
OFF
OFF
VPLL1
OFF
OFF
SLEEP
ON
VDAC
OFF
OFF
OFF
OFF
VINTANA1
OFF
OFF
SLEEP
ON
VINTANA2
OFF
OFF
SLEEP
ON
VINTDIG
OFF
OFF
SLEEP
ON
VIO
OFF
OFF
SLEEP
ON
VDD1
OFF
OFF
SLEEP
ON
VDD2
OFF
OFF
SLEEP
ON
VUSB1V5
OFF
OFF
OFF
OFF
VUSB1V8
OFF
OFF
OFF
OFF
VUSB3V1
OFF
OFF
SLEEP
ON
5.5.5
Power Timing
Sequence start is a symbolic internal signal to ease the description of the power sequences and occurs
according to the different events detailed in Figure 5-7.
Sequence start timing depends on the TPS65921 starting event. If the starting event is:
• Main battery insertion, event time is 1.126 ms (time to set up internal LDO and relax internal reset)
• VBUS insertion, event time is 25 cycles of 32k
Starting_Event is main battery insertion
Vbat
1.126 ms
Sequence_Start
Starting_Event is VBUS insertion
Vbus
782 ms = 25 cycle32k
Sequence_Start
Starting_Event is PWRON button
PWRON
Pushbutton debouncing - 30 ms
Sequence_Start
Starting_Event is PWRON rising when device is in slave mode
PWRON
0 ms
Sequence_Start
SWCS048-018
Figure 5-7. Timings Before Sequence Start
Detailed Description
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Switch On In MASTER_C021_GENERIC Mode
Figure 5-8 describes the timing and control that must occur in Master_C021_Generic mode.
Sequence_Start is a symbolic internal signal to ease the description of the power sequences and occurs
according to the different events detailed in Figure 5-7.
Sequence_Start
4608 ms battery detection
REGEN
1068 ms - 3 MHz oscillator setting + clock switch
VIO
1.8 V
1179 ms for VIO stabilization
VPLL1
1.8 V
1022 ms for LDO stabilization and start DC-DC ramping
VDD2
1.2 V
1099 ms for VDD2 stabilization and VDD1 start ramping
VDD1
1.2 V
1175 ms for VDD1 stabilization
32KCLKOUT
61 ms
SYSEN
1179 ms for VIO stabilization
CLKEN
29.053 ms
32.410 ms
HFCLKOUT
T1
NRESPWRON
SWCS048-019
Figure 5-8. Timings—Switch On in Master_C021_Generic Mode
PARAMETER
T1
46
MIN
MAX
UNIT
10
11
32k clock cycles
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5.5.5.2
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
Switch On In SLAVE_C021_GENERIC Mode
Figure 5-9 describes the timing and control that must occur in Slave_C021_Generic mode.
Sequence_Start is a symbolic internal signal to ease the description of the power sequences and occurs
according to the different events detailed in Figure 5-7.
PWRON
4791 ms – 3 MHz oscillator setting + internal reg
REGEN
1068 ms for external supply ramp
VIO
1.8 V
1179 ms for VIO DC-DC stablilization
VPLL1
1.8 V
1022 ms
VDD2
1.2 V
1099 ms for VDD2 stabilization
VDD1
1.2 V
1175 ms for VDD1 stabilization
32KCLKOUT
61 ms
SYSEN
CLKEN
1099 ms for VDD2 stabilization
29.053 ms
1953 ms for digital clock setting
HFCLKOUT
T1
NRESPWRON
SWCS048-020
Figure 5-9. Timings—Switch On in Slave_C021_Generic Model
PARAMETER
T1
MIN
MAX
UNIT
10
11
32k clock cycles
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5.5.5.3
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Switch-Off Sequence
This section describes the signal behavior required to switch off the system.
48
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5.5.5.3.1 Switch-Off Sequence In Master Modes
Figure 5-10 describes the timing and control that occur during the switch-off sequence in master modes.
VBAT
DEVOFF (register)
18 ms
NRESPWRON
1,2 ms
REGEN
18 ms
32KCLKOUT
1,2 ms
DCDCs
1,2 ms
LDOs
18 ms
SYSEN
18 ms
HFCLKOUT
126 ms
CLKEN
3.42 ms before detection of starting event
NEXT_Startup_event
SWCS048-021
NOTE: All of the above timings are the typical values with the default setup (depending on the resynchronization between
power domains, state machinery priority, and so forth).
Figure 5-10. Switch-Off Sequence in Master Modes
In case the value of the HF clock is different from 19.2 MHz (with HFCLK_FREQ bit field values set
accordingly inside the CFG_BOOT register), then the delay between DEVOFF and
NRESPWRON/CLK32KOUT/SYSEN/HFCLKOUT is divided by 2 (meaning around 9 μs). This is due to
the internal frequency used by POWER STM switching from 3 MHz to 1.5 MHz in case the value of the
HF clock is 19.2 MHz.
The DEVOFF event is the PWRON falling edge in slave mode and the DEVOFF internal register write in
master mode.
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5.5.5.3.2 Switch-Off Sequence in Slave Mode
Figure 5-11 describes the timing and control that occur during the switch off-sequence in slave mode.
VBAT
PWRON
18 ms
NRESPWRON
1,2 ms
REGEN
18 ms
32KCLKOUT
1,2 ms
DCDCs
1,2 ms
LDOs
18 ms
SYSEN
18 ms
HFCLKOUT
3.42 ms before detection of starting event
NEXT_Startup_event
6 ms (see comment in notes
about reducing this interval)
VIO
6 ms
32KXIN
SWCS048-022
NOTE: All of the above timings are the typical values with the default setup (depending on the resynchronization between
power
domains,
state
machinery
priority,
and
so
forth).
If necessary, the 6-ms period to maintain VIO and 32KXIN after PWRON goes low can be reduced to 150 μs.
Figure 5-11. Switch-Off Sequence in Slave Mode
In case the value of the HF clock is different from 19.2 MHz (with HFCLK_FREQ bit field values set
accordingly inside the CFG_BOOT register), then the delay between DEVOFF and
NRESPWRON/CLK32KOUT/ SYSEN/HFCLKOUT is divided by 2 (meaning around 9 μs). This is due to
the internal frequency used by POWER STM switching from 3 MHz into 1.5 MHz in case the value of the
HF clock is 19.2 MHz.
5.5.5.4
Charge Pump
The charge pump generates a 5.0-V (nominal) power supply voltage from battery to the VBUS
CP.OUT/VUSB.IN pin. The input voltage range is 2.7 to 4.5 V for the battery voltage. The charge pump
operating frequency is 1 MHz.
The charge pump tolerates 6 V on VBUS when it is in power down mode. The charge pump integrates a
short-circuit current limitation at 450 mA.
Figure 5-12 shows the charge pump.
50
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Switched 3.3 V
USB connector
VBAT.USB
CP.IN
CP.GND
VBUS
CPOUT
Normal operation
USB @ VBUS > 4.4 V
5.0-V CP
Power-up
USB @ VBAT > 3.20 V
USBIN
USB3P3
TPS65921
DP
DM
USB PHY
ID
SWCS048-023
Figure 5-12. General Overview of the Charge Pump and Its Interfaces
The charge pump can be used to supply USB 3.1 V LDO when battery voltage is lower than this LDO
VBATmin voltage (see Section 4).
5.5.6
USB Transceiver
The TPS65921 device includes a USB OTG transceiver that support USB 480 Mbps HS, 12 Mbps FS, and
USB 1.5 Mbps LS through a 4-pin UTMI+ ULPI.
It also includes a module covering Battery Charging Specification v1.0. Figure 5-13 shows the USB 2.0
PHY highlight block diagram.
USB OTG device
OMAP
(LINK)
Device
USB PHY
ULPI
Phone connector
(USB)
PC
ADC inputs
(optional)
Charger
SWCS048-024
Figure 5-13. USB 2.0 PHY Highlight
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Figure 5-14 shows the USB system application schematic.
VBAT
CVBUS.IN
CVBUS.PC
CUSB.1P3
VUSB.3P1
CUSB3P1
VUSB.1P5
VUSB.1P8
CP.CAPN
CP.CAPP
CP.IN
CP.GND
CUSB.1P5
VBAT
VBAT.USB
CVBAT.USB
CVBUS
VBUS
ULPI_CLK
TPS65921
D+ / RXD
ULPI_STP
USB
PLL
ULPI_DIR
USB
CP
USB
PWR
ULPI_NXT
D– / TXD
ID
USB OTG
connector
OMAP
host
processor
(LINK)
ULP interface
GND
ULPI_DATA0
ULPI_DATA1
ULPI_DATA2
ULPI
USB 2.0 HS-OTG
transceiver (PHY)
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
Registers
OTG
ULPI_DATA6
Serial interface
ULPI_DATA7
TXEN
DAT
SE0
SWCS048-025
Figure 5-14. USB System Application Schematic
5.5.7
PHY
The PHY is the physical signaling layer of the USB 2.0. It contains all the drivers and receivers required
for physical data and protocol signaling on the DP and DM lines.
The PHY interfaces to the USB controller through a standard digital interface called the universal
transceiver macro cell interface (UTMI).
The transmitters and receivers inside the PHY are classified into two main classes:
• The FS and LS transceivers. These are the legacy USB1.x transceivers.
• The HS transceivers
To bias the transistors and run the logic, the PHY also contains reference generation circuitry consisting
of:
• A DPLL, which does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for
USB, and also the clock required for the switched capacitor resistance block.
• A switched capacitor resistance block used to replicate an external resistor on chip.
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
Apart from this, the PHY also contains circuitry that protects it from an accidental 5 V short on the DP and
DM lines.
52
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5.5.7.1
SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014
LS/FS Single-Ended Receivers
In addition to the differential receiver, there is a single-ended receiver (SE–, SE+) for each of the two data
lines D+/–. The main purpose of the single-ended receivers is to qualify the D+ and D– signals in the
FS/LS modes of operation.
5.5.7.2
LS/FS Differential Receiver
A differential input receiver (RX) retrieves the LS/FS differential data signaling. The differential voltage on
the line is converted into digital data by a differential comparator on DP/DM. This data is then sent to a
clock and data recovery circuit, which recovers the clock from the data. In an additional serial mode, the
differential data is directly output on the RXRCV pin.
5.5.7.3
LS/FS Transmitter
The USB transceiver (TX) uses a differential output driver to drive the USB data signal D+/– onto the USB
cable. The outputs of the driver support 3-state operation to achieve bidirectional half-duplex transactions.
5.5.7.4
HS Differential Receiver
The HS receiver consists of the following blocks:
• A differential input comparator to receive the serial data
• A squelch detector to qualify the received data
• An oversampler-based clock data recovery scheme followed by a NRZI decoder, bit unstuffing, and
serial-to-parallel converter to generate the UTMI DATAOUT
5.5.7.5
HS Differential Transmitter
The HS transmitter is always operated on the UTMI parallel interface. The parallel data on the interface is
serialized, bit-stuffed, NRZI-encoded, and transmitted as a DC output current on DP or DM depending on
the data. Each line has an effective 22.5-Ω load to ground, which generates the voltage levels for
signaling.
A disconnect detector is also part of the HS transmitter. A disconnect on the far end of the cable causes
the impedance seen by the transmitter to double, thereby doubling the differential amplitude seen on the
DP and DM lines.
5.5.7.6
UART Transceiver
In this mode, the ULPI data bus is redefined as a 2-pin UART interface, which exchanges data through a
direct access to the FS/LS analog transmitter and receiver.
ULPI
Device
USB connector
DATA0: UART_TX
DP/RXD/MIC
DATA1: UART_RX
DM/TXD/SPKR
SWCS048-026
Figure 5-15. USB UART Data Flow
The OTG block integrates three main functions:
• The USB plug detection function on VBUS and ID
• The ID resistor detection
• The VBUS level detection
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5.6
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Charger Detection
To support Battery Charging Specification v1.1 [BCS v1.1], a charger detection module is included in the
TPS65921 USB module.
The detection mechanism aims distinguishing several types of power sources that can be connected on
VBUS line:
• Dedicated charger port
• Standard host port
• Charging host port
The hardware includes:
• A dedicated voltage referenced pullup on DP line
• A dedicated current controlled pulldown on DM line
• A detection comparator on DM line
• A control/detection state-machine including timers
Additional circuitry is added on DP/DM respectively for data line symmetry (required for HS operation) and
for possible future extension
ID pin status detection (as defined per OTG v1.3 standard) and DP/DM single-ended receivers (as defined
per USB v2.0 standard) are also used to determine the type of device plugged on the USB connector.
For details on the detection mechanism, refer to [BCS v1.1] (1).
The charging detection feature has two modes (description of each mode follows):
1. Software CTL mode: Software has direct control of current source and USB charger detection
comparator on DP/DM (enabled when USB_SW_CTRL_EN=1) using USB_CHRG_CTRL registers
bits.
2. Software FSM mode: Software can start and stop USB charger detection state-machine.
For both modes, DPPULLDOWN and DMPULLDOWN bits in OTG_CTRL register are 1 by default. This
can cause errors in charger detection. Therefore, both bits must be cleared to 0 before software begins
charger detection sequence.
1- Software CTL Mode (Manual detection):
When in this mode the charger detection circuitry is fully under control of software. Refer to
POWER_CONTROL
register
bits
as
to
how
to
control
the
detection
circuitry.
Conditions:
• The TPS65921 device is powered and is in active mode.
• USB_SW_CHRG_CTRL_EN = 1, register bit set by the software
• USB_CHG_DET_EN_SW = 1, register bit set by the software
Control the USB_SW_CHRF_CTRL register to achieve charger detection.
2- Software FSM Mode (Automatic detection):
The TPS65921 also supports automated battery charger detection through the USB battery charger
detection FSM in Figure 5-16 while the chip is in active mode. This mode is set by software using the
SW_USB_DET bit. When in this mode, the automated charger detection finite state-machine (FSM) is
enabled.
Refer
to
the
state-machine
diagram
for
details.
Conditions:
• The TPS65921 device is powered and is in active mode.
• USB_HW_CHRG_DET_EN = 1
See the Register Map for more details.
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The TPS65921 device also supports automated data contact detection in the FSM through the
DATA_CONTACT_DET_EN bit which should be set at the same time as SW_USB_DET above, before
setting SW_CONTROL bit. This enables a block of the FSM, which performs data contact detect for a
maximum of DCD_TIMEOUT before automatically skipping to charger detection.
See Figure 5-16,USB Battery Charger FSM, for details of how context is stored if SW_CONTROL bit is set
while in software FSM mode.
USB_DET_ON
INIT
CHGD_INIT
DATA_CONTACT_DET_EN=0
CHGDCTRL=”000_0000"
CHGDCTRL=”011_0110"
DATA_CONTACT_DET_EN=1
CHGD_SETUP
DCD_INIT
Wait TVDP_SCR_ON
CHGDCTRL=”011_1010"
Dcounter=DCD_TIMEOUT
Or
CHGD_SERX_DP_DEB=0
DCD_SETUP
End wait
CHGD CHECK
_
Dcounter=0
Wait TIDP_SRC_ON
Always ON
End wait
CHGD_SERX_DM_DEB=0
and
CHGD_VDM_DEB=1
DCD_CHECK
Dcounter=Dcounter+1
USB500_WAIT
CHGDCTRL=010_0000
Wait TVDP_SRC_HICRNT
End wait
Dcounter
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