TPS65930BZCHR

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software TPS65930, TPS65920 SWCS037I – MAY 2008 – REVISED JANUARY 2015 TPS65920 and TPS65930 Integrated Power Management/Audio Codec (TPS65930 Only) – Silicon Revision 1.2 1 Device Overview 1.1 Features 1 • Power: – Three Efficient Step-down Converters – Four External Linear LDOs for Clocks and Peripherals – SmartReflex™ Dynamic Voltage Management • Audio (TPS65930 Device Only): – Differential Input Main Microphones – Mono Auxiliary/FM Input – External Predrivers for Class D (Stereo) – TDM Interface – Automatic Level Control (ALC) – Digital and Analog Mixing – 16-Bit Linear Audio Stereo DAC (96, 48, 44.1, and 32 kHz and Derivatives) – 16-Bit Linear Audio Stereo ADC (48, 44.1, and 32 kHz and Derivatives) – Carkit • USB: – USB 2.0 On-the-Go (OTG)-Compliant HS Transceivers – 12-Bit Universal Transceiver Macro Interface ULPI 1.2 • • Applications Smart Phones Tablets 1.3 – USB Power Supply (5-V Charge Pump for VBUS) – Consumer Electronics Association (CEA)-2011: OTG Transceiver Interface Specification – CEA-936A: Mini-USB Analog Carkit Specification • Additional Features: – LED Driver Circuit for Two External LEDs – Two External 10-Bit MADC Inputs – Real-Time Clock (RTC) and Retention Modules – HS I2C Serial Control – Thermal Shutdown and Hot-Die Detection – Keypad Interface (up to 6 × 6) – External Vibrator Control – 15 GPIOs – 0.65-mm Pitch, 139-Pin, 10-mm × 10-mm Package • Charger: – Backup Battery Charger • • Industrial Handheld Systems Description The TPS65920 and TPS65930 devices are power-management ICs for OMAP™ and other mobile applications. The devices include power-management, a universal serial bus (USB) high-speed (HS) transceiver, light-emitting diode (LED) drivers, an analog-to-digital converter (ADC), a real-time clock (RTC), and an embedded power control (EPC). In addition, the TPS65930 includes a full audio codec with two digital-to-analog converters (DACs) and two ADCs to implement dual voice channels, and a stereo downlink channel that can play all standard audio sample rates through a multiple format inter-integrated sound (I2S)/time division multiplexing (TDM) interface. These optimized devices support the power and peripheral requirements of the OMAP application processors. The power portion of the devices contains three buck converters, two controllable by a dedicated SmartReflex class-3 interface, multiple low dropout (LDO) regulators, an EPC to manage the power sequencing requirements of OMAP, and an RTC and backup module. The RTC can be powered by a backup battery when the main supply is not present, and the devices include a coin-cell charger to recharge the backup battery as needed. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65930, TPS65920 SWCS037I – MAY 2008 – REVISED JANUARY 2015 www.ti.com The USB module provides a HS 2.0 OTG transceiver suitable for direct connection to the OMAP UTMI+ low pin interface (ULPI), with an integrated charge pump and full support for the carkit CEA-936A specification. An ADC is provided for monitoring signals, such as supply voltage, entering the device, and two additional external ADC inputs are provided for system use. The devices provide driver circuitry to power two LED circuits that can illuminate a panel or provide user indicators. The drivers also provide pulse width modulation (PWM) circuits to control the illumination levels of the LEDs. A keypad interface implements a built-in scanning algorithm to decode hardware-based key presses and reduce software use, with multiple additional general-purpose input/output devices (GPIOs) that can be used as interrupts when configured as inputs. Device Information (1) PACKAGE BODY SIZE TPS65920A2ZCHR PART NUMBER ZCH (139) 10.0 mm × 10.0 mm TPS65930A2ZCHR ZCH (139) 10.0 mm × 10.0 mm (1) 2 For more information, see Section 8, Mechanical, Packaging, and Orderable Information. Device Overview Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 TPS65930, TPS65920 www.ti.com 1.4 SWCS037I – MAY 2008 – REVISED JANUARY 2015 Functional Block Diagram Figure 1-1 shows the TPS65920 device block diagram. TPS65920 Interface subchip (D) Digital signal(s) Analog signal(s) PIH I2C A pad Clock generator I2C B pad TAP OCP Clk In/Out Card Det1 GPIO pad GPIO SIH Card Det2 TAP SIH_INT TAP Clocks OCP OCP SR TAP OCP Clocks Clocks SIH_INT OCP PMC slave Smart Reflex RFIDEN Vibrator control (D) Clock slicer Power control (BBS-backup VRRTC-UVLO) USB power supply USB subchip (A-D) ULPI(12) UART(2) BERCLK BERDATA Auxiliary subchip (A-D) Power digital Keypad (D) Power analog RTC 32 kHz TAP Shundan RTC Clocks SIH OCP PMC master SIH_INT SIH_INT OTG module USB 2.0 transceiver USB digital (ULPI regist ers, interr upts, Thermal monitor system MADC digital state-machine MADC analog (SAR-Vref) MADCTOP Rc oscillator LEDTOP Power provider (LDOs-DcDcs) Power references (Vref-Iref-bandgap) LED digital LED analog Power subchip (A-D) LedSync Figure 1-1. TPS65920 Block Diagram Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 Device Overview 3 TPS65930, TPS65920 SWCS037I – MAY 2008 – REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 Device Overview ......................................... 1 1.1 Features .............................................. 1 1.2 Applications ........................................... 1 1.3 Description ............................................ 1 1.4 Functional Block Diagram ............................ 3 Revision History ......................................... 5 Terminal Configuration and Functions .............. 6 Pin Diagram 3.2 Pin Attributes ......................................... 6 3.3 Signal Descriptions .................................. 10 6 Specifications ........................................... 15 4.1 Absolute Maximum Ratings ......................... 15 4.2 ESD Ratings 4.4 4.5 4.6 4.7 4 .......................................... 3.1 4.3 5 5.3 ........................................ Recommended Operating Conditions ............... Thermal Characteristics for ZCH Package .......... Minimum Voltages and Associated Currents ....... Digital I/O Electrical Characteristics................. 6 7 15 15 15 16 16 Timing Requirements and Switching Characteristics ...................................................... Detailed Description ................................... 5.1 Power Module ....................................... 5.2 Real-Time Clock and Embedded Power Controller . Table of Contents 19 27 8 USB Transceiver .................................... 53 ............................................... ......................................... 5.6 Keyboard ............................................ 5.7 Clock Specifications ................................. 5.8 Debouncing Time ................................... 5.9 External Components ............................... Audio/Voice Module (TPS65930 Device Only) .... 6.1 Audio/Voice Downlink (RX) Module ................. 6.2 Audio Uplink (TX) Module ........................... Device and Documentation Support ............... 7.1 Device Support ...................................... 7.2 Community Resources .............................. 7.3 Related Links ........................................ 7.4 Trademarks.......................................... 7.5 Electrostatic Discharge Caution ..................... 7.6 Export Control Notice ............................... 7.7 Glossary ............................................. 7.8 Additional Acronyms ................................ 5.4 MADC 62 5.5 LED Drivers 64 65 66 77 78 82 82 88 96 96 97 97 97 98 98 98 98 27 Mechanical, Packaging, and Orderable Information ............................................. 101 52 8.1 Packaging Information ............................. 101 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 TPS65930, TPS65920 www.ti.com SWCS037I – MAY 2008 – REVISED JANUARY 2015 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (October 2014) to Revision I • Changed document to standard TI format Page ........................................................................................ Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 Revision History 1 5 TPS65930, TPS65920 SWCS037I – MAY 2008 – REVISED JANUARY 2015 www.ti.com 3 Terminal Configuration and Functions Figure 3-1 shows the ball locations for the 139-ball plastic ball grid array (PBGA) package. Use this array with Table 3-1 to locate signal names and ball grid numbers. 3.1 Pin Diagram 037-003 Figure 3-1. PBGA Bottom View 3.2 Pin Attributes Table 3-1 describes the terminal characteristics and the signals multiplexed on each pin. The following list describes the table column headers: Table 3-1. Pin Attributes TPS65920 BALL (1) TPS65930 BALL (1) H2 H2 F2 F2 M5 ADCIN0 A I/O VINTANA1.OUT ADCIN2 A I VINTANA2.OUT M5 PCHGAC A I VACCHARGER N1 N1 VPRECH A O VPRECH N5 N5 VBAT A Power VBAT GPIO0/CD1 D I/O IO_1P8 JTAG.TDO D I/O IO_1P8 GPIO1 D I/O IO_1P8 JTAG.TMS D I IO_1P8 GPIO2 D I/O IO_1P8 TEST1 D I/O IO_1P8 P2 6 REFERENCE LEVEL RL (5) TYPE (4) E7 (5) (6) (7) A/D (3) F7 (1) (2) (3) (4) PIN NAME (2) F7 E7 P2 PU (6) (kΩ) PD (6) (kΩ) MIN TYP MAX MIN TYP MAX 75 100 202 59 100 144 BUFFER STRENGTH (mA) (7) 8 8 2 75 100 202 59 100 144 156 220 450 59 100 144 2 2 Ball: Ball number(s) associated with each signal(s) Pin Name: The names of all the signals that are multiplexed on each ball A/D: Analog or digital signal Type: The terminal type when a particular signal is multiplexed on the terminal: • I = Input • O = Output Reference Level: See the power module chapter for values. PU/PD: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can be enabled or disabled by software. Buffer Strength: Drive strength of the associated output buffer Terminal Configuration and Functions Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 TPS65930, TPS65920 www.ti.com SWCS037I – MAY 2008 – REVISED JANUARY 2015 Table 3-1. Pin Attributes (continued) TPS65920 BALL (1) TPS65930 BALL (1) P13 P13 L5 L5 J7 PIN NAME (2) A/D REFERENCE LEVEL RL (5) PU (6) (kΩ) PD (6) (kΩ) BUFFER STRENGTH (mA) (7) (3) TYPE (4) GPIO15 D I/O IO_1P8 TEST2 D I/O IO_1P8 GPIO6 D I/O IO_1P8 PWM0 D O IO_1P8 TEST3 D I/O IO_1P8 2 GPIO7 D I/O IO_1P8 2 VIBRA.SYNC D I IO_1P8 PWM1 D O IO_1P8 TEST4 D I/O IO_1P8 J7 MIN TYP MAX MIN TYP MAX 156 220 450 59 100 144 2 2 2 75 75 100 100 202 202 59 59 100 100 144 4 144 4 2 D8 D8 SYSEN D Open drain/I IO_1P8 A4 A4 CLKEN D O IO_1P8 B13 B13 CLKREQ D I IO_1P8 C10 C10 INT1 D O IO_1P8 2 C8 C8 NRESPWRON D O IO_1P8 2 B9 B9 NRESWARM D I IO_1P8 2 D10 D10 PWRON D I VBAT G5 G5 NSLEEP1 D I IO_1P8 E10 E10 CLK256FS (8) D O IO_1P8 E4 E4 VMODE1 D I IO_1P8 E8 E8 BOOT0 A/D I/O VBAT D7 D7 BOOT1 A/D I/O VBAT B8 B8 REGEN D Open drain VBAT H4 H4 MSECURE D I IO_1P8 L13 L13 VREF A Power VREF A Power ground (GND) GND I2C.SR.SDA D I/O IO_1P8 VMODE2 D I IO_1P8 I2C.SR.SCL D I/O K13 K13 B3 B3 AGND 4.7 7.35 10 2 2 60 100 146 2 5.5 8 12 2 2.5 3.4 12 IO_1P8 2.5 3.4 12 N.C. C5 C3 C3 I2C.CNTL.SDA D I/O IO_1P8 2.5 3.4 12 B4 B4 I2C.CNTL.SCL D I IO_1P8 2.5 3.4 12 See (9) H3 I2S.CLK D I/O IO_1P8 2 See (9) K2 I2S.SYNC D I/O IO_1P8 2 See (9) K4 I2S.DIN D I IO_1P8 2 See (9) K3 I2S.DOUT D O IO_1P8 2 See (9) D1 MIC.MAIN.P A I MICBIAS1.OUT See (9) E1 MIC.MAIN.M A I MICBIAS1.OUT A10 VBAT.RIGHT A Power VBAT PreDriv.LEFT A O VINTANA2.OUT VMID A Power VINTANA2.OUT PreDriv.RIGHT A O VINTANA2.OUT ADCIN7 A I VINTANA2.OUT AUXR A I VINTANA2.OUT MICBIAS1.OUT A Power VINTANA2.OUT VMIC1.OUT A Power VINTANA2.OUT Power GND GND A10 See (9) See (9) See See See (8) (9) 2 C5 (9) (9) (9) A7 A8 G1 E2 D2 MICBIAS.GND G2 G2 AVSS1 A Power GND GND L7 L7 AVSS2 A Power GND GND N14 N14 AVSS3 A Power GND GND C7 C7 AVSS4 A Power GND GND To avoid reflection on this pin as a result of impedance mismatch, a serial resistance of 33 Ω must be added. This clock output is available in TPS65920 also. Can be used as a clock source, if required. Balls A7, A8, D1, D2, E1, E2, G1, H3, K2, K3, and K4 are present on TPS65920 package. However, there is no function associated with these pins. These can be left floating. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 Terminal Configuration and Functions 7 TPS65930, TPS65920 SWCS037I – MAY 2008 – REVISED JANUARY 2015 www.ti.com Table 3-1. Pin Attributes (continued) TPS65920 BALL (1) TPS65930 BALL (1) M10 M10 L14 L14 K14 A/D REFERENCE LEVEL RL (5) PU (6) (kΩ) PD (6) (kΩ) BUFFER STRENGTH (mA) (7) (3) TYPE (4) 32KCLKOUT D O IO_1P8 32KXIN A I IO_1P8 K14 32KXOUT A O IO_1P8 A11 A11 HFCLKIN A I IO_1P8 M11 M11 HFCLKOUT D O IO_1P8 P8 P8 VBUS A Power VBUS N10 N10 DP/UART3.RXD A I/O VBUS 2 P10 P10 DN/UART3.TXD A I/O VBUS 2 G6 G6 ID A I/O VBUS 2 K11 K11 UCLK D I IO_1P8 16 STP D I IO_1P8 H12 H12 GPIO9 D I/O IO_1P8 2 DIR D O IO_1P8 16 GPIO10 D I/O IO_1P8 2 NXT D O IO_1P8 16 GPIO11 D I/O IO_1P8 2 DATA0 D I/O IO_1P8 16 UART4.TXD D I IO_1P8 DATA1 D I/O IO_1P8 UART4.RXD D O IO_1P8 2 DATA2 D I/O IO_1P8 16 UART4.RTSI D I IO_1P8 DATA3 D I/O IO_1P8 UART4.CTSO D O IO_1P8 GPIO12 D I/O IO_1P8 DATA4 D I/O IO_1P8 GPIO14 D I/O IO_1P8 2 DATA5 D I/O IO_1P8 16 GPIO3 D I/O IO_1P8 2 DATA6 D I/O IO_1P8 16 GPIO4 D I/O IO_1P8 2 DATA7 D I/O IO_1P8 16 GPIO5 D I/O IO_1P8 A/D I VBAT H11 J8 L10 K10 G11 G10 E12 G9 G12 E11 P14 8 PIN NAME (2) MIN 75 J8 MAX MIN TYP MAX 16 75 H11 TYP 75 100 202 100 202 100 202 59 59 59 100 100 100 144 144 144 L10 16 K10 G11 G10 E12 G9 16 60 100 140 60 100 140 75 100 202 59 100 144 75 100 202 59 100 144 16 16 75 G12 75 E11 75 P14 TEST.RESET P1 P1 TESTV1 A I/O VBAT A14 A14 TESTV2 A I/O VINTANA2.OUT A1 A1 TEST D I IO_1P8 A13 A13 JTAG.TDI/ BERDATA D I IO_1P8 B14 B14 JTAG.TCK/ BERCLK D I IO_1P8 VBAT/VBUS P7 P7 CP.IN A Power N7 N7 CP.CAPP A O CP.CAPP N6 N6 CP.CAPM A O CP.CAPM P5 P5 CP.GND A Power GND GND N9 N9 VBAT.USB A Power VBAT M8 M8 VUSB.3P1 A Power VUSB.3P1 L1 L1 VAUX12S.IN A Power VBAT N2 N2 VAUX2.OUT A Power VAUX2.OUT H14 H14 VPLLA3R.IN A Power VBAT K12 K12 VRTC.OUT A Power VRTC.OUT G14 G14 VPLL1.OUT A Power VPLL1.OUT A2 A2 VMMC1.IN A Power VBAT B1 B1 VMMC1.OUT A Power VMMC1.OUT M7 M7 VINTUSB1P5. OUT A Power VINTUSB1P5.OUT Terminal Configuration and Functions 16 100 202 100 202 100 202 59 59 100 100 144 144 59 100 144 30 50 70 60 100 146 2 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 TPS65930, TPS65920 www.ti.com SWCS037I – MAY 2008 – REVISED JANUARY 2015 Table 3-1. Pin Attributes (continued) TPS65920 BALL (1) TPS65930 BALL (1) N8 N8 K1 PIN NAME (2) A/D REFERENCE LEVEL RL (5) (3) TYPE (4) VINTUSB1P8. OUT A Power K1 VDAC.IN A Power VBAT L2 L2 VDAC.OUT A Power VDAC.OUT H13 H13 VINT.IN A Power VBAT H1 H1 VINTANA1.OUT A Power VINTANA1.OUT J2 J2 VINTANA2.OUT A Power VINTANA2.OUT A5 VINTANA2.OUT A Power VINTANA2.OUT J13 J13 VINTDIG.OUT A Power VINTDIG.OUT D13 D13 VDD1.IN A Power VBAT D12 D12 VDD1.IN A Power VBAT D14 D14 VDD1.IN A Power VBAT C11 C11 VDD1.SW A O VBAT C12 C12 VDD1.SW A O VBAT C13 C13 VDD1.SW A O VBAT E14 E14 VDD1.FB A I A12 A12 VDD1.GND A Power GND GND B11 B11 VDD1.GND A Power GND GND B12 B12 VDD1.GND A Power GND GND M13 M13 VDD2.IN A Power VBAT M12 M12 VDD2.IN A Power VBAT N13 N13 VDD2.FB A I N11 N11 VDD2.SW A O VBAT P11 P11 VDD2.SW A O VBAT N12 N12 VDD2.GND A Power GND GND P12 P12 VDD2.GND A Power GND GND M2 M2 VIO.IN A Power VBAT M3 M3 VIO.IN A Power VBAT M4 M4 VIO.FB A I N4 N4 VIO.SW A O VBAT P4 P4 VIO.SW A O VBAT N3 N3 VIO.GND A Power GND GND P3 P3 VIO.GND A Power GND GND H9 H9 BKBAT A Power VBACK B7 B7 IO.1P8 A Power IO_1P8 H10 H10 DGND A Power GND GND F13 F13 LEDGND A Power GND GND GPIO13 D I/O IO_1P8 LEDSYNC D I IO_1P8 LEDA A Open drain VBAT VIBRA.P A Open drain VBAT LEDB A Open drain VBAT VIBRA.M A Open drain VBAT E13 G13 PD (6) (kΩ) MIN TYP MAX MIN TYP MAX 75 100 202 59 100 144 BUFFER STRENGTH (mA) (7) VINTUSB1P8.OUT A5 B10 PU (6) (kΩ) B10 E13 G13 G4 G4 KPD.C0 D Open drain IO_1P8 G3 G3 KPD.C1 D Open drain IO_1P8 E5 E5 KPD.C2 D Open drain IO_1P8 B2 B2 KPD.C3 D Open drain IO_1P8 E3 E3 KPD.C4 D Open drain IO_1P8 D5 D5 KPD.C5 D Open drain IO_1P8 K7 K7 KPD.R0 D I IO_1P8 8 10 12 H5 H5 KPD.R1 D I IO_1P8 8 10 12 K5 K5 KPD.R2 D I IO_1P8 8 10 12 H6 H6 KPD.R3 D I IO_1P8 8 10 12 K8 K8 KPD.R4 D I IO_1P8 8 10 12 L8 L8 KPD.R5 D I IO_1P8 8 10 12 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 Terminal Configuration and Functions 9 TPS65930, TPS65920 SWCS037I – MAY 2008 – REVISED JANUARY 2015 3.3 www.ti.com Signal Descriptions Table 3-2 describes the signals on the TPS65920 and TPS65930 devices; some signals are available on multiple pins. Table 3-2. Signal Description MODULE ADC Charger GPIOs/ JTAG CONTROL SIGNAL NAME DESCRIPTION TPS65920 BALL TPS65930 BALL SIGNAL TYPE INTERNA L PULL OR NOT FEATURES NOT USED ADCIN0 Battery type I/O H2 H2 ADCIN0 ADCIN2 General-purpose ADC input I F2 F2 ADCIN2 I GND PCHGAC AC precharge sense signal. Also used for EEPROM. I M5 M5 PCHGAC I GND VPRECH Precharge regulator output O N1 N1 VPRECH O Cap to GND VBAT Battery voltage sensing Power N5 N5 VBAT Power VBAT GPIO0/CD1 GPIO0/card detection 1 I/O JTAG.TDO JTAG test data output I/O F7 F7 GPIO0 I PD Floating GPIO1 GPIO1 I/O JTAG.TMS JTAG test mode state E7 E7 GPIO1 I PD Floating GPIO2 GPIO2 I/O TEST1 TEST1 pin used in test mode only I/O P2 P2 GPIO2 I PD Floating GPIO15 GPIO15 I/O TEST2 TEST2 pin used in test mode only I/O P13 P13 GPIO15 I PD Floating GPIO6 GPIO6 I/O PWM0 Pulse width driver 0 O L5 L5 GPIO6 I PD Floating TEST3 TEST3 pin used in test mode only (controlled by JTAG) I/O GPIO7 GPIO7 I/O VIBRA.SYNC Vibrator on-off synchronization I PWM1 Pulse width driver O J7 J7 GPIO7 I PD Floating TEST4 TEST4 pin used in test mode only (controlled by JTAG) I/O SYSEN System enable output D8 D8 SYSEN OD PU Floating CLKEN Clock enable O A4 A4 CLKEN O CLKREQ Clock request I B13 B13 CLKREQ I INT1 Output interrupt line 1 O C10 C10 INT1 O Floating NRESPWRON Output control the NRESPWRON of the application processor O C8 C8 NRESPWRON O Floating NRESWARM Input; detect user action on the reset button I B9 B9 NRESWARM I GND PWRON Input; detect a control command to start or stop the system I D10 D10 PWRON I VBAT NSLEEP1 Sleep request from device 1 I Open drain/I CLK256FS 10 TYPE DEFAULT CONFIGURATION AFTER RESET RELEASED GND Floating PD GND I G5 G5 NSLEEP1 I GND O E10 E10 CLK256FS O Floating E4 E4 VMODE1 I GND VMODE1 Digital voltage scaling linked with VDD1 I BOOT0 Boot pin 0 I E8 E8 BOOT0 I PD N/A BOOT1 Boot pin 1 I D7 D7 BOOT1 I PD N/A Open drain B8 B8 REGEN OD PU Floating I H4 H4 MSECURE REGEN Enable signal for external LDO MSECURE Security and digital rights management Terminal Configuration and Functions I N/A Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 TPS65930, TPS65920 www.ti.com SWCS037I – MAY 2008 – REVISED JANUARY 2015 Table 3-2. Signal Description (continued) SIGNAL NAME MODULE VREF 2 IC Smart Reflex I2C TDM ANA.MIC HandsFree Headset AUX Input VMIC BIAS DESCRIPTION TYPE VREF Reference voltage Power AGND Analog ground for reference voltage Power GND N.C. Not connected I2C.SR.SDA SmartReflex I2C data VMODE2 Digital voltage scaling linked with VDD2 I2C.SR.SCL SmartReflex I2C data I/O I2C.CNTL.SDA General-purpose I2C data I2C.CNTL.SCL General-purpose I2C clock I2S.CLK Clock signal (audio port) I2S.SYNC Synchronization signal (audio port) I2S.DIN TPS65930 BALL L13 L13 DEFAULT CONFIGURATION AFTER RESET RELEASED SIGNAL TYPE INTERNA L PULL OR NOT FEATURES NOT USED VREF Power N/A Power GND GND K13 K13 AGND B3 B3 Signal not functional C5 C5 VMODE2 I/O C3 C3 I2C.CNTL.SDA I/O PU I/O B4 B4 I2C.CNTL.SCL I/O PU I/O H3 I2S.CLK I/O Floating I/O K2 I2S.SYNC I/O Floating Data receive (audio port) I K4 I2S.DIN I GND I2S.DOUT Data transmit (audio port) O K3 I2S.DOUT O Floating MIC.MAIN.P Main microphone left input (P) I D1 MIC.MAIN.P I Cap to GND MIC.MAIN.M Main microphone left input (M) I E1 MIC.MAIN.M I Cap to GND VBAT.RIGHT Battery voltage input A10 VBAT.RIGHT Power VBAT PreDriv.LEFT Predriver output left P for external class-D amplifier A7 VMID Power Floating A8 ADCIN7 I GND G1 AUXR I Cap to GND E2 MICBIAS1.OUT Power Floating D2 MICBIAS.GND Power GND GND Power GND GND O Floating I/O Floating I Power VMID A10 O I GND N/A N/A Power PreDriv.RIGHT Predriver output right P for external class-D amplifier O ADCIN7 General-purpose ADC input 7 I AUXR Auxiliary audio input right I MICBIAS1. OUT Analog microphone bias 1 Power VMIC1.OUT Digital microphone power supply 1 Power MICBIAS.GND Dedicated ground for microphones Power GND AVSS1 G2 G2 AVSS1 AVSS2 L7 L7 AVSS2 N14 N14 AVSS3 C7 C7 AVSS4 M10 M10 32KCLKOUT AVSS3 Power GND Analog ground AVSS4 CLOCK TPS65920 BALL 32KCLKOUT Buffered output of the 32-kHz digital clock 32KXIN Input of the 32-kHz oscillator I L14 L14 32KXIN I N/A 32KXOUT Output of the 32-kHz oscillator O K14 K14 32KXOUT O Floating HFCLKIN Input of the digital (or sine) HS clock I A11 A11 HFCLKIN I N/A HFCLKOUT HS clock output O M11 M11 HFCLKOUT VBUS VBUS power rail Power P8 P8 DP/ UART3.RXD USB data P/USB carkit receive data/universal asynchronous receiver/transmitter (UART)3 receive data I/O N10 N10 DN/ UART3.TXD USB data N/USB carkit transmit data/UART3 transmit data I/O P10 ID USB ID I/O G6 USB PHY O O Floating Power N/A DP/UART3.RX D I/O N/A P10 DN/UART3.TX D I/O N/A G6 ID I/O Connected to VRUSB3V1 VBUS Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 Terminal Configuration and Functions 11 TPS65930, TPS65920 SWCS037I – MAY 2008 – REVISED JANUARY 2015 www.ti.com Table 3-2. Signal Description (continued) MODULE ULPI TEST USB CP SIGNAL NAME DESCRIPTION TYPE DEFAULT CONFIGURATION AFTER RESET RELEASED TPS65920 BALL TPS65930 BALL K11 K11 UCLK O H12 H12 STP I H11 H11 DIR O Floating J8 J8 NXT O Floating L10 L10 DATA0 O Floating K10 K10 DATA1 O Floating G11 G11 DATA2 O Floating G10 G10 DATA3 O Floating E12 E12 DATA4 O Floating G9 G9 DATA5 O Floating G12 G12 DATA6 O Floating E11 E11 DATA7 O Floating P14 P14 TEST.RESET I SIGNAL TYPE INTERNA L PULL OR NOT FEATURES NOT USED UCLK HS USB clock I STP HS USB stop I GPIO9 GPIO9 DIR HS USB direction O GPIO10 GPIO10 I/O NXT HS USB next O GPIO11 GPIO11 I/O DATA0 HS USB Data0 I/O UART4.TXD UART4.TXD DATA1 HS USB Data1 I/O UART4.RXD UART4.RXD O DATA2 HS USB Data2 I/O UART4.RTSI UART4.RTSI DATA3 HS USB Data3 UART4.CTSO UART4.CTSO O GPIO12 GPIO12 I/O DATA4 HS USB Data4 I/O GPIO14 GPIO14 I/O DATA5 HS USB Data5 I/O GPIO3 GPIO3 I/O DATA6 HS USB Data6 I/O GPIO4 GPIO4 I/O DATA7 HS USB Data7 I/O GPIO5 GPIO5 I/O TEST.RESET Reset T2 device (except power state-machine) TESTV1 Analog test I/O P1 P1 TESTV1 I/O Floating TESTV2 Analog test I/O A14 A14 TESTV2 I/O Floating TEST Selection between JTAG mode and application mode for JTAG/GPIOs (with PU or PD) I A1 A1 TEST I JTAG.TDI/ BERDATA JTAG.TDI/BERDATA I A13 A13 JTAG.TDI/ BERDATA I GND JTAG.TCK/ BERCLK JTAG.TCK/BERCLK I B14 B14 JTAG.TCK/ BERCLK I GND CP.IN Charge pump input voltage Power P7 P7 CP.IN Power VBAT CP.CAPP Charge pump flying capacitor P O N7 N7 CP.CAPP O Floating CP.CAPM Charge pump flying capacitor M O N6 N6 CP.CAPM O Floating GND I/O I I Floating PU Floating I/O I CP.GND Floating CP.GND Charge pump ground VBAT.US B VBAT.USB USB LDOs (VINTUSB1P5, VINTUSB1P8, VUSB.3P1) VBAT Power N9 N9 VBAT.USB Power VBAT USB.LDO VUSB.3P1 USB LDO output Power M8 M8 VUSB.3P1 Power N/A VAUX1 VAUX12S.IN VAUX1/VAUX2/VSIM LDO input voltage Power L1 L1 VAUX12S.IN Power VBAT VAUX2 VAUX2.OUT VAUX2 LDO output voltage Power N2 N2 VAUX2.OUT Power Floating VPLLA3R VPLLA3R.IN Input for VPLL1, VPLL2, VAUX3, and VRTC LDOs Power H14 H14 VPLLA3R.IN Power VBAT VRTC VRTC.OUT VRTC internal LDO output (internal use only) Power K12 K12 VRTC.OUT Power N/A VPLL1 VPLL1.OUT LDO output voltage Power G14 G14 VPLL1.OUT Power Floating Terminal Configuration and Functions P5 PD GND Power GND 12 P5 Power GND PD Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 TPS65930, TPS65920 www.ti.com SWCS037I – MAY 2008 – REVISED JANUARY 2015 Table 3-2. Signal Description (continued) MODULE SIGNAL NAME DESCRIPTION TYPE TPS65920 BALL TPS65930 BALL DEFAULT CONFIGURATION AFTER RESET RELEASED SIGNAL TYPE INTERNA L PULL OR NOT FEATURES NOT USED VMMC1.IN VMMC1 LDO input voltage Power A2 A2 VMMC1.IN Power VBAT VMMC1.OUT VMMC1 LDO output voltage Power B1 B1 VMMC1.OUT Power Floating VINTUSB1 VINTUSB1P5. P5 OUT VINTUSB1P5 internal LDO output (internal use only) Power M7 M7 VINTUSB1P5. OUT Power Floating VINTUSB1 VINTUSB1P8. P8 OUT VINTUSB1P8 internal LDO output (internal use only) Power N8 N8 VINTUSB1P8. OUT Power Floating K1 K1 VDAC.IN Power VBAT VMMC1 Video DAC VDAC.IN Input for VDAC, VINTANA1, and VINTANA2 LDOs Power VDAC.OUT Output voltage of the regulator Power L2 L2 VDAC.OUT Power Floating VINT VINT.IN Input for VINTDIG LDO Power H13 H13 VINT.IN Power VBAT Power N/A VINTANA1. VINTANA1 OUT VINTANA1 internal LDO output (internal use only) Power H1 H1 VINTANA1.OU T VINTANA2. OUT VINTANA2 internal LDO output (internal use only) Power J2 J2 VINTANA2.OU T Power N/A VINTANA2. OUT VINTANA2 internal LDO output (internal use only) Power A5 A5 VINTANA2.OU T Power N/A VINTDIG.OUT VINTDIG internal LDO output (internal use only) Power J13 J13 VINTDIG.OUT Power N/A VDD1.IN VDD1 DC-DC input voltage Power D13 D13 VDD1.IN Power VBAT VDD1.IN VDD1 DC-DC input voltage Power D12 D12 VDD1.IN Power VBAT VDD1.IN VDD1 DC-DC input voltage Power D14 D14 VDD1.IN Power VBAT VDD1.SW VDD1 DC-DC switch O C11 C11 VDD1.SW O Floating VDD1.SW VDD1 DC-DC switch O C12 C12 VDD1.SW O Floating VDD1.SW VDD1 DC-DC switch O C13 C13 VDD1.SW O Floating VDD1.FB VDD1 DC-DC output voltage (feedback) I E14 E14 VDD1.FB I GND VDD1.GND VDD1 DC-DC ground Power GND A12 A12 VDD1.GND Power GND GND VDD1.GND VDD1 DC-DC ground Power GND B11 B11 VDD1.GND Power GND GND VDD1.GND VDD1 DC-DC ground Power GND B12 B12 VDD1.GND Power GND GND VDD2.IN VDD2 DC-DC input voltage Power M13 M13 VDD2.IN Power VBAT VDD2.IN VDD2 DC-DC input voltage Power M12 M12 VDD2.IN Power VBAT VDD2.FB VDD2 DC-DC output voltage (feedback) I N13 N13 VDD2.FB I GND VDD2.SW VDD2 DC-DC switch O N11 N11 VDD2.SW O Floating VDD2.SW VDD2 DC-DC switch O P11 P11 VDD2.SW O Floating VDD2.GND VDD2 DC-DC ground Power GND N12 N12 VDD2.GND Power GND GND VDD2.GND VDD2 DC-DC ground Power GND P12 P12 VDD2.GND Power GND GND VIO.IN VIO DC-DC input voltage Power M2 M2 VIO.IN Power VBAT VIO.IN VIO DC-DC input voltage Power M3 M3 VIO.IN Power VBAT VIO.FB VIO DC-DC output voltage (feedback) I M4 M4 VIO.FB I GND VIO.SW VIO DC-DC switch O N4 N4 VIO.SW O Floating VIO.SW VIO DC-DC switch O P4 P4 VIO.SW O Floating VIO.GND VIO DC-DC ground Power GND N3 N3 VIO.GND Power GND GND VIO.GND VIO DC-DC ground Power GND P3 P3 VIO.GND Power GND GND BKBAT Backup battery Power H9 H9 BKBAT Power GND VINTANA2 VINTDIG VDD1 VDD2 VIO Backup battery Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 Terminal Configuration and Functions 13 TPS65930, TPS65920 SWCS037I – MAY 2008 – REVISED JANUARY 2015 www.ti.com Table 3-2. Signal Description (continued) MODULE SIGNAL NAME DESCRIPTION TYPE TPS65920 BALL TPS65930 BALL DEFAULT CONFIGURATION AFTER RESET RELEASED SIGNAL TYPE INTERNA L PULL OR NOT FEATURES NOT USED Digital VDD IO.1P8 TPS65920/TPS65930 device I/O input Power B7 B7 IO.1P8 Power N/A Digital ground DGND Digital ground Power GND H10 H10 DGND Power GND GND LEDGND LED driver ground Power GND F13 F13 LEDGND Power GND GND GPIO13 GPIO13 LEDSYNC LED synchronization input B10 B10 GPIO13 I LEDA LED leg A VIBRA.P H-bridge vibrator P Open drain E13 E13 Signal not functional Floating LEDB LED leg B VIBRA.M H-bridge vibrator M Open drain G13 G13 Signal not functional Floating KPD.C0 Keypad column 0 Open drain G4 G4 KPD.C0 OD Floating KPD.C1 Keypad column 1 Open drain G3 G3 KPD.C1 OD Floating KPD.C2 Keypad column 2 Open drain E5 E5 KPD.C2 OD Floating KPD.C3 Keypad column 3 Open drain B2 B2 KPD.C3 OD Floating KPD.C4 Keypad column 4 Open drain E3 E3 KPD.C4 OD Floating KPD.C5 Keypad column 5 Open drain D5 D5 KPD.C5 OD Floating KPD.R0 Keypad row 0 I K7 K7 KPD.R0 I PU Floating KPD.R1 Keypad row 1 I H5 H5 KPD.R1 I PU Floating KPD.R2 Keypad row 2 I K5 K5 KPD.R2 I PU Floating KPD.R3 Keypad row 3 I H6 H6 KPD.R3 I PU Floating KPD.R4 Keypad row 4 I K8 K8 KPD.R4 I PU Floating KPD.R5 Keypad row 5 I L8 L8 KPD.R5 I PU Floating LED driver Keypad I/O I PD Floating 1. This column provides the connection when the associated feature is not used or not connected. When there is a pin muxing, not all functions on the muxed pin are used. But even if a function is not used, the Default Configuration After Reset Released column still applies. Connection criteria: – Analog pins: – For input: GND – For output: Floating (except VPRECH is connected to GND) – For I/O if input by default: GND (except for audio features input: capacitor to ground with a 100nF typical value capacitor) – Digital pins: – For input: GND (except keypad and STP are left floating) – For input and pullup: Floating – For output: Floating – For I/O and pullup: Floating N/A (not applicable): When the associated feature is mandatory for correct functioning of the TPS65920/TPS65930 device 2. The signal VPRECH must be connected to the CPRECH capacitor to GND. 3. Signal not functional indicates that no signal is presented on the pad after a release reset. 14 Terminal Configuration and Functions Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 TPS65930, TPS65920 www.ti.com SWCS037I – MAY 2008 – REVISED JANUARY 2015 4 Specifications 4.1 Absolute Maximum Ratings PARAMETER TEST CONDITIONS MIN Main battery supply voltage (1) Voltage on any input Supply represents the voltage applied to the power supply pin associated with the input Ambient temperature TYP MAX 4.5 V 0.0 1.0*Supply V –40 Junction temperature (TJ) UNIT 2.1 At 1.4 W (Theta JB 11°C/W 2S2P board) 85 °C 105 °C Junction temperature (TJ) for parametric compliance –40 105 °C Storage temperature (Tstg) –55 125 °C (1) The product has negligible reliability impact if voltage spikes of 5.2 V occur for a total duration of 10 ms. 4.2 ESD Ratings VALUE VESD (1) (2) Electrostatic discharge (ESD) performance: Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1) All other pins UNIT ±2 CLK32KOUT pin kV ±1.5 Charged device model (CDM), per JESD22-C101 (2) ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 4.3 Recommended Operating Conditions MIN TYP MAX 2.7 (1) 3.6 4.5 Backup battery supply voltage 1.8 3.2 3.3 V Ambient temperature range –40 85 °C Main battery supply voltage (1) UNIT V 2.7 V is the minimum threshold for the battery at which the device will turn OFF. However, the minimum voltage at which the device will power ON is 3.2 V ±100 mV (if PWRON does not have a switch and is connected to VBAT) considering battery plug as the device switch on event. If PWRON has a switch then 3.2 V is the minimum for the device to turn ON. 4.4 Thermal Characteristics for ZCH Package TPS65920–2S2P NAME DESCRIPTION (°C/W) (2) TPS65920–1S0P TPS65930–2S2P (°C/W) (°C/W) (2) TPS65930–1S0P (°C/W) AIR FLOW (m/s) (1) RΘJC Junction-to-case (top) 6.74 6.74 33.42 57.05 0.00 RΘJB Junction-to-board 13.80 14.50 13.81 14.51 0.00 RΘJA Junction-to-free air 33.40 57.04 6.74 6.74 0.00 (1) (2) m/s = meters per second These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65930 TPS65920 Specifications 15 TPS65930, TPS65920 SWCS037I – MAY 2008 – REVISED JANUARY 2015 4.5 www.ti.com Minimum Voltages and Associated Currents Table 4-1 lists the VBAT minimum and maximum currents per VBAT ball. Table 4-1. VBAT Minimum Required Per VBAT Ball and Associated Maximum Current CATEGORY PIN AND MODULE MAXIMUM CURRENT SPECIFIED (mA) VBAT pin name VDD_VPLLA3R_IN_6POV 340 VPLL1 (LDO) 40 VDD1 core (DCDC)