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TPS65980
SLVSCK1A – APRIL 2014 – REVISED APRIL 2014
TPS65980 Thunderbolt™ Bus Power Buck/Boost
1 Features
3 Description
•
•
•
•
•
The TPS65980 DC/DC switching regulator that
receives
power
from
a
Thunderbolt™
or
Thunderbolt™ 2 power bus ranging from 2.5-V to
15.75-V and generates three separate 3.3-V supply
outputs.
1
Powered From Thunderbolt™ Bus
2.5-V to 15.75-V Input
3.3-V Outputs
Cable Power Out Current Limit
Thermal Shutdown
The TBT_OUT supply provides power to the local
peripheral Thunderbolt™ controller and support
circuitry. The CBL_OUT supply provides power back
to the Thunderbolt™ cable and has adjustable current
limit. The DEV_OUT supply provides power to all
other circuitry in the device to perform its designed
function.
2 Applications
•
•
•
Thunderbolt™/Thunderbolt™ 2 Systems
Bus Powered Systems
Power Management Systems
The TPS65980 is available in
5mm x 4mm x 0.9mm VQFN package.
a
24-pin
Device Information(1)
DEVICE NAME
TPS65980
PACKAGE
VQFN (24)
BODY SIZE
5mm x 4mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
DEV_OUT
CDEV_OUT
L
DEV_OUT
DEV_OUT
CPP
CPN
PGND
PGND
SW
CP
TBT_OUT
SW
TBT_OUT
BOOT
TBT_OUT
CBOOT
CTBT_OUT
CTBT_IN
TBT
Connector
TBT_IN
GND
TBT_IN
DEV_EN
GND
GND
GND
SS
CC
CSS
RESET
CBL_ILIMIT
RC
HV_OK
COMP
Thunderbolt
Controller
CBL_OUT
TBT_IN
CCBL_OUT
CBL_OUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65980
SLVSCK1A – APRIL 2014 – REVISED APRIL 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
Handling Ratings....................................................... 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 7
Timing Diagrams ....................................................... 8
Typical Characteristics ............................................ 10
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
13
14
14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 22
12.1 Trademarks ........................................................... 22
12.2 Electrostatic Discharge Caution ............................ 22
12.3 Glossary ................................................................ 22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
5 Revision History
Changes from Original (April 2014) to Revision A
•
2
Page
Revised document to full version. ......................................................................................................................................... 1
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SLVSCK1A – APRIL 2014 – REVISED APRIL 2014
6 Pin Configuration and Functions
VQFN (RHF) 24-Pin
TOP VIEW
24
23
22
21
20
12
11
10
PGND
CPN
CPP
DEV_OUT
DEV_OUT
CBL_OUT
RESET
17
16
15
14
13
DEV_OUT
18
DEV_OUT
19
CPP
HV_OK
CBL_ILIMIT
DEV_EN
GND
TBT_OUT
TBT_OUT
7
CPN
GND
Exposed Pad
(Connect to GND)
PGND
GND
7
12
9
PGND
6
PGND
GND
5
11
8
SW
4
SW
SS
3
10
6
SW
2
9
5
BOOT
1
8
4
CBL_ILIMIT
TBT_IN
CBL_OUT
3
DEV_EN
TBT_IN
RESET
2
GND
COMP
HV_OK
1
TBT_OUT
GND
Exposed Pad
(Connect to GND)
TBT_OUT
GND
13
GND
14
SS
15
24
COMP
16
23
TBT_IN
17
22
TBT_IN
18
21
BOOT
19
20
SW
VQFN (RHF) 24-Pin
BOTTOM
Pin Functions
PIN
NO.
1
2, 3, 4
NAME
I/O
DESCRIPTION
SS
ANALOG
Soft Start Capacitance. This pin sets the soft start ramp rate when the TBT_IN voltage ramps from
0V to high voltage.
GND
GND
Device Ground
5
HV_OK
OUTPUT
High Voltage Present Indicator. This pin indicates that a high voltage is present on TBT_IN. The
output asserts high when the TBT_IN pin is above the VHVT voltage and the RESET output is
asserting high.
6
RESET
OUTPUT
Reset output indicator. This pin asserts low when TBT_OUT is in under-voltage.
7
CBL_OUT
PWROUT
Current Limited Power Output to Thunderbolt™ Cable. This pin supplies power to the Thunderbolt™
cable. The current limit of this pin is set by the CBL_ILIMIT pin.
8
CBL_ILIMIT
INPUT
Current Limit Set. Logic input that sets the current limit state on the CBL_OUT pin. Tie pin to
TBT_OUT for a logic high input.
9
DEV_EN
INPUT
Device Enable Input. When input pin is high, DEV_OUT is high impedance. When input pin low,
DEV_OUT is connected to TBT_OUT.
10
GND
ANALOG
Device Ground
11, 12
TBT_OUT
PWROUT
Power Output to Thunderbolt™ circuitry. This pin supplies power to the Thunderbolt™ controller.
13, 14
DEV_OUT
PWROUT
Power Output to peripheral device. This pin supplies power to circuitry not associated with the
Thunderbolt™ controller or the Thunderbolt™ cable. It is intended to supply power to the peripheral
device main function.
15
CPP
ANALOG
Charge Pump Capacitance Positive Output
16
CPN
ANALOG
Charge Pump Capacitance Negative Output
17, 18
PGND
GND
Buck Controller Power Ground
19, 20
SW
ANALOG
Buck Controller Switch Output
BOOT
ANALOG
Buck Controller Bootstrap
22, 23
TBT_IN
PWRIN
Power Input from Thunderbolt™ Cable. This pin is the power supply to the device.
24
COMP
ANALOG
Buck Converter Compensation. This pin provides compensation to the buck converter feedback loop.
21
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
MIN
MAX
TBT_IN
–0.3
18
DEV_EN
–0.3
3.6
BOOT
–0.3
25
BOOT (10 ns transient)
–0.3
27
BOOT (vs SW)
–0.3
7
SW
–0.6
18
–2
20
COMP
–0.3
3.6
SS
–0.3
3.6
CBL_ILIMIT
–0.3
3.6
CPP
–0.3
7.2
CPN
–0.3
3.6
TBT_OUT, CBL_OUT, DEV_OUT
–0.3
3.6
RESET, HV_OK
–0.3
3.6
Voltage from GND to Thermal Pad
–0.2
0.2
Voltage from PGND to GND
–0.2
0.2
V
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
Input voltage range (2)
SW (10 ns transient)
Output voltage range (2)
Vdiff
(1)
(2)
UNIT
V
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground pin.
7.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
(1)
(2)
4
Electrostatic discharge
MAX
UNIT
–55
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2
kV
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature (unless otherwise noted)
TBT_IN
MAX
Supply input voltage range
Input voltage
range
VI
MIN
2.5
15.75
DEV_EN
–0.1
3.6
BOOT
–0.1
25
SW
–0.6
16.5
COMP
–0.1
3.6
SS
–0.1
3.6
CBL_ILIMIT
–0.1
3.6
CPP
–0.1
7.2
CPN
–0.1
3.6
TBT_OUT, CBL_OUT, DEV_OUT
–0.1
3.6
RESET, HV_OK
–0.1
3.6
UNIT
V
VO
Output voltage
range
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
V
7.4 Thermal Information
TPS65980
THERMAL METRIC (1)
RHF
UNIT
24 PIN
RθJA
Junction-to-ambient thermal resistance
30.1
RθJC(top)
Junction-to-case (top) thermal resistance
26.9
RθJB
Junction-to-board thermal resistance
8.2
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
8.2
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.5
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
Unless otherwise noted all specifications applies over the VTBT_IN range and operating ambient temperature of
–40°C ≤ TA ≤ 85°C, CTBT_IN = 22 µF, CTBT_OUT = 10 µF, CCBL_OUT = 1 µF, CSS = 10 nF, and 33 V/µs logic input transitions.
Typical values are for VTBT_IN = 12 V and TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
POWER SUPPLIES AND CURRENTS
VTBT_IN
TBT_IN Input voltage range
2.5
12
15.75
TBT_OUT to RESET clear high
TBT_OUT rising
3
3.1
3.2
TBT_OUT to RESET assert low
TBT_OUT falling
2.5
2.6
2.7
VHVTR
TBT_IN to HV_OK assert
TBT_IN rising
4.5
4.64
VHVTHYST
TBT_IN to HV_OK clear
TBT_IN Falling hysteresis
SR02L
TBT_IN Input slew rate
TBT_IN transition from 0 V to 3.3 V
0.1
30
kV/s
SRL2H
TBT_IN Input slew rate
TBT_IN transition from 3.3 V to 15 V
0.1
30
kV/s
IRAMP
Combined output di/dt (1)
5
kA/s
VREF_RSTN
Efficiency
4.36
100
Buck converter efficiency
ILOADTOTAL = 3 A, VTBT_IN = 12 V
87%
Charge pump efficiency
VTBT_IN = 3.3 V, ILOADTOTAL = 25 mA
47%
V
V
mV
POWER OUTPUT PINS (LOW VOLTAGE INPUT) (2)
VTBT_IN
TBT_IN Input voltage range
VTBT_OUT
TBT_OUT Output voltage range (3)
RESET high
TBT_OUT Load current (4) (5)
ITBT_OUT
2.5
3.3
3.4
3.135
3.25
3.4
V
50
mA
100
µA
V
5
RESET low
V
POWER OUTPUT PINS (HIGH VOLTAGE INPUT) (6)
VTBT_IN
TBT_IN Input voltage range
VTBT_OUT
TBT_OUT Output voltage range (3)
ITBT_OUT
TBT_OUT Load current (4)
10
12
15.75
I_LOADTOTAL = 1 A to 3.5 A
3.221
3.27
3.319
I_LOADTOTAL = 0.235 A to 3.5 A
3.221
3.27
3.42
ILIMIT = 0, ICBL_OUT = 0 to 720 mA
3.171
3.27
3.319
ILIMIT = 1, ICBL_OUT = 0 to 1.44 A
3.12
3.27
3.319
3
3.27
3.319
V
V
235
(3)
VCBL_OUT
CBL_OUT Output voltage range
VDEV_OUT
DEV_OUT Output Voltage Range
IDEV_OUT = 0 to 2500 mA
1000
V
mA
V
POWER OUTPUT PINS (HIGH VOLTAGE INPUT DURING SYSTEM SLEEP)
VTBT_IN
TBT_IN Input voltage range
5.2
12
15.75
I_LOADTOTAL = 1 A to 3.5 A
3.221
3.27
3.319
I_LOADTOTAL = 0.235 A to 3.5 A
3.221
3.27
3.42
VTBT_OUT
TBT_OUT DC Output voltage range
ITBT_OUT
TBT_OUT Load current
VCBL_OUT
CBL_OUT Output voltage range (3)
ICBL_OUT = 0 to 235 mA
3.171
3.27
3.319
V
VDEV_OUT
DEV_OUT Output voltage range
IDEV_OUT = 0 to 700 mA
3
3.3
3.319
V
5
31
V
mA
CABLE OUTPUT (HIGH VOLTAGE INPUT & HIGH VOLTAGE INPUT DURING SLEEP)
VCBL_OUT_MON
VCBL_OUT_RIP
CBL_OUT Ramp-up monotonicity (7)
CBL_OUT ramp from off to on
0
mV
CBL_OUT Voltage ripple
After settling
All output combined Load > 1 mA
2
%P-P
All output combined Load < 1 mA
40
mVP=P
ILIM_CBLOUT
CBL_OUT Current limit
tLIM_CBLOUT
Short circuit response time
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
ILIMIT = 0
0.8
1.1
1.4
ILIMIT = 1
1.6
2.2
2.8
RCBL_OUT = 0.5 Ω to GND, ILIMIT = 0
RCBL_OUT = 0.01 Ω to GND, ILIMIT = 0
500
8
A
µs
The three voltage outputs (TBT_OUT, CBL_OUT, DEV_OUT) all pull current from a single node. Therefore, the total combined current
cannot exceed the maximum di/dt.
CBL_OUT and DEV_OUT are open (high impedance) for this input voltage range.
During light load conditions, the average output voltage may reach 3.5 V with peaks not exceeding 3.42 V.
TBT_OUT load current flows from the TBT_OUT pin when the device is in charge pump mode and pulls the buck converter inductor
when the device is in buck mode.
TBT_OUT load current will not go higher than 50mA until after the device asserts HV_OK.
The maximum current supplied by the TPS65980 to all outputs is limited to 3.5 A. Max power depends on the Thunderbolt™ system and
how much power is supplied to the input.
A monotonicity of 0 mV means that the output does not have a negative going ramp at anytime during its power up ramp. A ripple of up
to 62 mV from the DC/DC will occur.
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Electrical Characteristics (continued)
Unless otherwise noted all specifications applies over the VTBT_IN range and operating ambient temperature of
–40°C ≤ TA ≤ 85°C, CTBT_IN = 22 µF, CTBT_OUT = 10 µF, CCBL_OUT = 1 µF, CSS = 10 nF, and 33 V/µs logic input transitions.
Typical values are for VTBT_IN = 12 V and TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEV_EN AND ILIMIT INPUT LOGIC
VIH
High-level input voltage
VIL
Low-level input voltage
IIN
Input leakage to GND
2.6
V
0.6
VDEV_EN = 3.3V
V
1
mA
–250
0
mV
0
250
mV
250
kA/s
150
°C
RESET AND HV_OK OUTPUT LOGIC
VOH
High-level output voltage
IL = –1.5 mA, Referenced to VTBT_OUT
VOL
Low-level output voltage
IL = 1.5 mA
SOFT START (8)
IINRUSH
Inrush current di/dt
THERMAL SHUTDOWN
TSD
Shutdown temperature
TSDHYST
Shutdown hysteresis
(8)
120
135
10
°C
The charge pump will limit the normal ramp of current. Soft start will control the inrush current when the input ramps from 0 V to high
voltage (not a normal operating condition). See recommended components section for required soft-start cap.
7.6 Timing Requirements
MIN
tIN2OR
TBT_IN to TBT_OUT On Time
VTBT_IN ≥ 0.9 × VTBT_IN(min) to
VTBT_OUT ≥ 0.99 × VTBT_OUT(min)
RTBT_OUT = 100 Ω
tIN2OF
TBT_IN to TBT_OUT Off Time
VTBT_IN ≤ 0.9 × VTBT_IN(min) to
VTBT_OUT ≤ 0.1 × VTBT_OUT(min)
RTBT_OUT = 100 Ω
tOUT2RR
TBT_OUT to RESETZ High time
tIN2RF
TYP
MAX
UNIT
20
ms
4
ms
VTBT_OUT ≥ VREF_RSTN(max) rising to
VRESET = 0.9 × VOH, CRESETN = 100 pF
20
µs
TBT_IN to RESETZ Low time
VTBT_IN ≤ 0.9 × VTBT_IN(min) to
VRESET = 0.1 × VOH, CRESETN = 100 pF
20
ms
tHV2OKR
TBT_IN Rise to HV_OK
VTBT_IN ≥ VHVTR to VHV_OK = 0.9 × VOH
CHV_OK = 100 pF
10
µs
tHV2OKF
TBT_IN Fall to HV_OK
VTBT_IN ≤ VHVTR-VHVTHYST to
VHV_OK = 0.1 × VOH, CHV_OK = 100 pF
10
µs
tHV2CR (1) (2)
HV_OK to CBL_OUT On time
VHV_OK ≥ 1.65 V to VCBL_OUT = 2.95 V
RCB_OUT = 100 Ω, CHV_OK = 100 pF
10
ms
tHV2CF
HV_OK to CBL_OUT Off time
VHV_OK ≤ 1.65 V to VCBL_OUT = 2.95 V
RCB_OUT = 100 Ω, CHV_OK = 100 pF
40
µs
tRCBL
CABLE_OUT Ramp time
VCBL_OUT ramp 10% to 90%
CCBL_OUT = 0 to 52 µF
0.1
10
ms
tDEVEN
DEV_EN to DEV_OUT On time
VDEV_EN ≤ 1.65 V to VDEV_OUT = 2.7 V
RDEV_OUT = 100 Ω
0.1
10
ms
tDEVDIS
DEV_EN to DEV_OUT Off time
VDEV_EN ≥ 1.65V to VDEV_OUT = 2.7 V
RDEV_OUT = 100 Ω
50
ms
tHV2DEVEN
Wait time from HV_OK High before
DEV_EN can be asserted low (2)
VHV_OK ≥ 1.65 V to VDEV_EN ≤ 1.65 V
CHV_OK = 100 pF
(1)
(2)
2.4
0.1
2
ms
TBT_IN must transition from 3.3 V to high voltage, not from 0 V to high voltage
During the transition from low voltage input to high voltage input, the total load of all outputs combined can not exceed 85 mA until 2 ms
after HV_OK asserts high.
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7.7 Timing Diagrams
15.75V
10V
SRL2H
3.4V
2.5V
TBT_IN
SR02L
0V
Figure 1. TBT_IN Slew Rates
The TPS65980 has two normal operating regions. The first region is when 2.5 V ≤ VTBT_IN ≤ 3.4 V. This is the
normal power-up state and is termed the low-voltage state. When the input transitions to this range, the input
slew rate must meet the SR02L limits. In this voltage range, the TPS65980 operates with a charge pump to
generate the nominally 3.3 V output. When the input voltage moves to the higher end of this range, the buck
converter takes over to produce the 3.3 V. In normal operation, the TPS65980 input voltage will transition from
the low-voltage range to a high-voltage range where 10 V ≤ VTBT_IN ≤ 15.75 V. This is the high-voltage state and
is the state where the TPS65980 will operate most of the time. In this state, the device operates as a buck
converter providing a nominally 3.3 V output. Figure 1 shows the input voltage transitions and states.
VHVTR - VHVTHYST
VHVTR
0.9·VTBT_IN(min)
TBT_IN
0.9·VTBT_IN(min)
0V
tIN2OR
TBT_OUT
VREF_RSTN
0.99·VTBT_OUT(Min)
0.1·VTBT_OUT(Min)
0V
tIN2OF
tOUT2RR
0.9·VOH
RESET
0.1·VOH
0V
tHV2OKF
tHV2OKR
HV_OK
0.9·VOH
0V
tIN2RF
0.1·VOH
Figure 2. Timing Diagram
Figure 2 shows normal operating timing diagram for the TBT_OUT output voltage and the RESET and HV_OK
output indicator signals. When TBT_IN transitions to the low-voltage range, TBT_OUT will power up a short time
later. Once TBT_OUT reaches the normal output range, RESET will transition high. However, timing for RESET
is measured from the input TBT_IN transitioning high. When TBT_IN transitions from the low-voltage input range
to the high-voltage input range, HV_OK will transition high. RESET is an active-high output indicating that the
TBT_OUT voltage is valid and. HV_OK is an active-high output indicating that the TBT_IN voltage is in the highvoltage range. When in the high-voltage state, the TPS65980 can provide much higher output current than when
in the low-voltage state.
8
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Timing Diagrams (continued)
When the TBT_IN input transitions from high-voltage to low-voltage, HV_OK will de-assert to a logic low. When
the TBT_IN input voltage falls below the minimum operating voltage, the RESET output will de-assert low.
HV_OK
1.65V
1.65V
1.65V
0V
DEV_EN
0V
tHV2CR
tHV2CF
0.95·VCBL_OUT(Min)
CBL_OUT
tHV2CR
0.95·VCBL_OUT(Min)
0.95·VCBL_OUT(Min)
0V
tDEVEN
0.95·VDEV_OUT(Min)
DEV_OUT
tDEVDIS
0.95·VDEV_OUT(Min)
0.95·VDEV_OUT(Min)
0.95·VDEV_OUT(Min)
0V
Figure 3. Timing Diagram
Figure 3 shows the CBL_OUT and DEV_OUT outputs and timing based on the HV_OK signal and the DEV_ENZ
input. The CBL_OUT output will be connected to TBT_OUT and supplying 3.3V when HV_OK is asserting high.
The DEV_OUT output will be connected to TBT_OUT and supplying 3.3 V when HV_OK is asserting high and
the DEV_ENZ input is low.
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100
100
90
90
80
80
70
70
Efficiency - %
Efficiency - %
7.8 Typical Characteristics
60
50
40
60
50
40
30
30
Vin
Vin
Vin
Vin
20
10
=
=
=
=
2.5V
2.8V
3.1V
3.3V
Vin
Vin
Vin
Vin
Vin
20
10
5.2V
8.2V
11.2V
14.2V
15.75V
0
0
0
0.0075
0.015 0.0225
0.03
0.0375
IO - Output Current - A
0
0.045
0.2
0.4
0.6
D001
Figure 4. Low Voltage Efficiency
0.8
1
1.2
ITBT_OUT - A
1.4
1.6
1.8
D002
Figure 5. High Voltage Efficiency (System Sleep)
100
3.27
90
3.268
80
3.266
70
3.264
VTBT_OUT - V
Efficiency - %
=
=
=
=
=
60
50
40
30
3.262
3.26
3.258
3.256
Vin
Vin
Vin
Vin
20
10
=
=
=
=
10V
12V
14V
15.75V
3.254
3.252
0
3.25
0
0.4
0.8
1.2
1.6
2
2.4
ITBT_OUT - A
2.8
3.2
3.6
4
0
5
10
15
D003
20
25
30
ITBT_OUT - mA
35
40
45
50
D004
VIN = 3.3V
Figure 6. High Voltage Efficiency (Active)
Figure 7. TBT_OUT Load Regulation
3.4
3.36
3.34
3.35
VDEV_OUT - V
VTBT_OUT - V
3.32
3.3
3.28
3.26
3.3
3.25
3.2
3.24
3.15
3.22
3.2
3.1
0
0.4
0.8
1.2
1.6
2
2.4
ITBT_OUT - A
2.8
3.2
3.6
0
0.3
VIN = 12V
0.9
1.2
1.5
1.8
IDEV_OUT - A
2.1
2.4
2.7
D006
VIN = 12V
Figure 8. TBT_OUT Load Regulation
10
0.6
D005
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Typical Characteristics (continued)
4
4
3.5
3.5
3
2.5
VCBL_OUT - V
VCBL_OUT - V
3
2.5
2
1.5
1
0.5
0
-0.5
1
-1
0.5
0
-0.2
2
1.5
-1.5
-2
0.2
VIN = 12V
0.6
1
1.4
ICBL_OUT - A
1.8
2.2
0
2.6
0.2
0.4
D007
CBL_ILIMIT = 1
VIN = 12V
Figure 10. CBL_OUT Load Regulation
0.6
0.8
ICBL_OUT - A
1
1.2
1.4
D008
CBL_ILIMIT = 0
Figure 11. CBL_OUT Load Regulation
3.36
500mA
1A
2A
3A
3.5A
3.34
TBT_OUT - V
3.32
3.3
3.28
3.26
3.24
3.22
3.2
5
6
7
8
9
10 11 12
VTBT_IN - V
13
14
15
16
D009
Figure 12. TBT_OUT Line Regulation
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8 Detailed Description
8.1 Overview
The TPS65980 is a switching regulator designed for Thunderbolt™ and Thunderbolt™ 2 bus-powered systems.
The TPS65980 receives power from a Thunderbolt™ host in the range of 2.5 V to 15.75 V and produces three
separate 3.3 V outputs. TBT_OUT is the main output from the regulator. This output is generated from a
switched-cap charge pump when the input is in the low-voltage range. The output is generated from a switching
buck converter when the input voltage is in the high-voltage range. The TBT_OUT output powers the local
Thunderbolt™ controller and any additional Thunderbolt™ circuitry. Once in the input has settled in the highvoltage range, the other two outputs can be powered from the TBT_OUT output. When the TBT_OUT is
supplying 3.3 V, the RESET output asserts high. When the TBT_OUT voltage is below the valid output range,
RESET asserts low. When TBT_IN is in the high-voltage input range and RESET is asserting high (valid output),
HV_OK will assert high indicating that high-voltage has been received.
The CBL_OUT output supplies power back to the Thunderbolt™ cable for powering the active cable circuitry.
This output is connected to the TBT_OUT output with a FET switch and is current limited.
The CBL_ILIMIT logic input pin sets the current limit level. The DEV_OUT output provides power to all other
circuitry in the system. This output is not current limited and is enabled/disabled by the DEV_EN logic input.
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8.2 Functional Block Diagram
BOOT
SS
TBT_IN
MN1A
I-Sense
Switch-Mode
Control
AERROR
MN1B
SW
RFB1
COMP
VREF
RFB2
MN2
PGND
RESET
CPN
VREF
Charge
Pump
CPP
HV_OK
TBT_IN
4.5V
TBT_OUT
Gate
Driver
CBL_OUT
HV_OK
HV_OK
MN3
MN3
I-Limit
CBL_ILIMIT
DEV_EN
DEV_OUT
GND
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8.3 Feature Description
8.3.1 2.5-V to 15.75-V Input
The TPS65980 is powered from a Thunderbolt™ Bus. This is typically an input to a port from Thunderbolt™
cable. This input will start at 3.3 V (2.5 V ≤ VTBT_IN ≤ 3.4 V) until a link is established between a host and the
peripheral device containing the TPS65980. Once the link is established, the voltage at the input can transition to
a higher operating voltage (10 V ≤ VTBT_IN ≤ 15.75 V).
8.3.2 3.3-V Outputs
The TPS65980 has three separate 3.3 V outputs. One output, TBT_OUT, is the output from the buck/boost and
the other outputs, CBL_OUT and DEV_OUT, are outputs that through load switches from TBT_OUT.
The TBT_OUT supply provides power to the local peripheral Thunderbolt™ controller and support circuitry. The
CBL_OUT supply provides power back to the Thunderbolt™ cable and has adjustable current limit. The
DEV_OUT supply provides power to all other circuitry in the device to perform its designed function.
8.3.3 Thermal Shutdown
The TPS65980 as a thermal shutdown feature preventing the device from over heating during current limiting
situations. The thermal shutdown occurs at a 135°C junction temperature typically. A 10°C hysteresis occurs
before the thermal shutdown is cleared.
8.3.4 Cable Power Out Current Limit
The CBL_OUT output is current limited internally. The current limit has two values which are set by the
CBL_ILIMIT logic input. When CBL_ILIMIT = 0, the current limit will bet set to 1.1 A typically. When CBL_ILIMIT
= 1, the current limit will be set to 2.2 A typically.
8.4 Device Functional Modes
8.4.1 Operation with 2.5 V ≤ VTBT_IN ≤ 3.4 V
The TPS65980 has two normal operating regions. The first region is when 2.5 V ≤ VTBT_IN ≤ 3.4 V. This is the
normal power-up state and is termed the low-voltage state. When the input transitions to this range, the input
slew rate must meet the SR02L limits. In this voltage range, the TPS65980 operates with a charge pump to
generate the nominally 3.3 V output. When the input voltage moves to the higher end of this range, the buck
converter takes over to produce the 3.3 V.
8.4.2 Operation with 10 V ≤ VTBT_IN ≤ 15.75 V
In normal operation, the TPS65980 input voltage will transition from the low-voltage range to a high-voltage
range where 10 V ≤ VTBT_IN ≤ 15.75 V. This is the high-voltage state and is the state where the TPS65980 will
operate most of the time. In this state, the device operates as a buck converter providing a nominally 3.3 V
output.
14
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9 Application and Implementation
9.1 Application Information
The TPS65980 DC/DC switching regulator that receives power from a Thunderbolt™ or Thunderbolt™ 2 power
bus ranging from 2.5 V to 15.75 V and generates three separate 3.3-V supply outputs.
9.2 Typical Application
9.2.1 Single-Port Bus-Powered Thunderbolt™ Device
DEV_OUT
CDEV _OUT
L
DEV_OUT
DEV_OUT
CPP
CPN
PGND
PGND
SW
CP
TBT_OUT
SW
TBT_OUT
BOOT
TBT_OUT
CBOOT
CTBT _OUT
CTBT_IN
TBT
Connector
TBT_IN
GND
TBT_IN
DEV_EN
COMP
CBL_ILIMIT
RESET
HV_OK
GND
GND
SS
GND
RC
CC
Thunderbolt
Controller
CSS
CBL_OUT
TBT_IN
CCBL_OUT
CBL_OUT
Figure 13. Typical Application (Single-Port Bus-Powered Thunderbolt™ Device)
9.2.1.1 Design Requirements
Table 1. Recommended Component Values
COMPONENT
DESCRIPTION
MIN
TYP
MAX
UNIT
CIN
TBT_IN Input Capacitance
17.6
22
52
µF
CBOOT
Converter Bootstrap Capacitance
8
10
12
nF
CCP
Charge Pump Capacitance (ceramic with ESR ≤ 10 mΩ)
0.8
1
1.2
µF
CSS
Soft Start Capacitance
8
10
12
nF
CTBT
TBT_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
16
20
24
µF
CCBL
CBL_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
0.8
1
1.2
µF
CDEV
DEV_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
0.8
1
1.2
µF
CC
Compensation Capacitance
8
10
12
nF
RC
Compensation Resistance
8
10
12
kΩ
L
Inductor SRR1280 (ESR ≤ 20 mΩ)
8
10
12
µH
9.2.1.2 Detailed Design Procedure
The TPS65980 should use the recommended component values in Table 1. The device is designed to fit the
needs of a Thunderbolt™ bus powered peripheral and the recommended component values are chosen to
satisfy those conditions. The input capacitance CIN can be as high as 52 µF, but this maximum capacitance must
include all capacitances seen at the input to the Thunderbolt™ port.
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9.2.1.3 Application Performance Plots
CTBT_OUT = 10 µF
16
VTBT_IN = 12 V
CTBT_OUT = 10 µF
VTBT_IN = 12 V
Figure 14. TBT_OUT Load Transient Response
(0.5A to 3.5A Step)
Figure 15. TBT_OUT Load Transient Response
(3.5A to 0.5A Step)
Figure 16. 0V to 3.3V Power Up With 50mA Load
Figure 17. 3.3V to 0V Power Down With 50mA Load
Figure 18. 3.3V to 15.75V Vin Step With 50mA Load
Figure 19. 15.75 to 3.3V Vin Step With 50mA Load
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CBL_ILIMIT = 0
CBL_ILIMIT = 1
Figure 20. Short Circuit Current Limit Response
Figure 21. Short Circuit Current Limit Response
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9.2.2 Dual-Port Bus-Powered Thunderbolt™ Device
DEV_OUT
CDEV
L
CBOOT
I-Limit
DEV_OUT
DEV_OUT
CPP
CPN
PGND
PGND
SW
CP
TBT_OUT
SW
TBT_OUT
BOOT
TBT_OUT
CTBT
TBT_IN
I-Limit
TBT Port2
Connector
TBT_IN
GND
TBT_IN
DEV_EN
COMP
CBL_ILIMIT
RESET
HV_OK
GND
GND
SS
GND
RC
CC
Thunderbolt
Controller
CBL_OUT
TBT Port 1
Connector
CSS
CCBL
CBL_OUT
Figure 22. Typical Application (Dual-Port Bus-Powered Thunderbolt™ Device)
9.2.2.1 Design Requirements
In a dual-port application, the TBT_IN input voltage will be selected from either port. A simple diode-or function
will produce TBT_IN from the higher of the two inputs. The diode-or selection will allow the high-voltage supply to
be at TBT_IN.
In a dual port system, the TPS65980 must provide cable power to both ports. In this case, a second current
limiting device (TPS22920) connected between TBT_OUT and the port is recommended. The CBL_OUT pin can
also supply current to both ports. In this case, tying CBL_ILIMIT to TBT_OUT will double the amount of current
that can be supplied before current limiting. When using this method, the voltage drop to the CBL_OUT pin will
increase and care must be taken that other systems resistance do not cause the cable voltage to drop below the
allowed pin voltage specified in the Thunderbolt™ specification. To avoid issues with voltage drop in the system,
it is recommended that the second port be powered from TBT_OUT as shown in Figure 22. This relieves the
voltage drop due to extra current through the CBL_OUT load switch.
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Table 2. Recommended Component Values
COMPONENT
DESCRIPTION
MIN
TYP
MAX
UNIT
CIN
TBT_IN Input Capacitance
17.6
22
52
µF
CBOOT
Converter Bootstrap Capacitance
CCP
Charge Pump Capacitance (ceramic with ESR ≤ 10 mΩ)
CSS
8
10
12
nF
0.8
1
1.2
µF
Soft Start Capacitance
8
10
12
nF
CTBT
TBT_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
16
20
24
µF
CCBL
CBL_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
0.8
1
1.2
µF
CDEV
DEV_OUT Output Capacitance (ceramic with ESR ≤ 10 mΩ)
0.8
1
1.2
µF
CC
Compensation Capacitance
8
10
12
nF
RC
Compensation Resistance
8
10
12
kΩ
L
Inductor SRR1280 (ESR ≤ 20 mΩ)
8
10
12
µH
9.2.2.2 Detailed Design Procedure
Refer to Detailed Design Procedure in the Single-Port Bus-Powered Thunderbolt™ Device section.
9.2.2.3 Application Performance Plots
Refer to Application Performance Plots in the Single-Port Bus-Powered Thunderbolt™ Device section.
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10 Power Supply Recommendations
The TPS65980 is designed to operate from a Thunderbolt™ bus. The input will range from 2.5 V to 15.75 V. The
input should be placed as near to the port connector as possible.
11 Layout
11.1 Layout Guidelines
Proper placement and routing will maximize the performance of the TPS65980. Follow Figure 23 for optimized
layout and routing (hashed planes indicate bottom layer).
11.2 Layout Example
TBT_OUT Plan
DEV_OUT
Planes
SW
Plane
TBT_IN Plane
CBL_OUT Plane
GND Plane
Figure 23. Top View Board Layout
20
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Layout Example (continued)
For TBT_IN, the input capacitors must be placed close to the device with an inductance less than 1nH from input
capacitors to the TBT_IN pins. Layout tools and calculators are available to approximate the inductance. The
input capacitors must have their GND side area via stitched to the GND plane. The GND side of the input cap
should also share the same polygon as the PGND/PowerPad on the top layer. PowerPad should be connected to
the GND plane through multiple vias.
Inductor placement should be above the TPS65980, slightly to the left of the device. The SW pins to the inductor
must be connected though a plane as shown in Figure 23. The TBT_OUT pins also have to be connected to the
other side of the inductor with a plane. This plane should be wide to overlap the output capacitors. The GND side
of the output capacitors should be stitched to the GND plane.
The CBL_OUT output capacitor should be placed close to the device on the top layer with an inductance less
than 1 nH from the capacitor to the CBL_OUT pin. The DEV_OUT capacitor is best placed on the bottom side of
the board with two planes (top and bottom) connect through a set of vias. The number of vias placed should be
able to carry at least 3 A (DEV_OUT = 2.5 A max) for margin and inductance path less than 1nH from DEV_OUT
pins to capacitor. When routing DEV_OUT to an internal power plane, follow Figure 24 for via paths.
DEV_OUT Pins
TPS65980
Top
Power
Vias
GND
Bottom
(Indicates Current Flow)
DEV_OUT Cap
Figure 24. DEV_OUT Recommended Routing
The charge pump capacitor must be placed on the top layer close to the CPP and CPN pins. The inductance
paths from capacitor to the pins must be less than 1 nH. SS and Compensation components should be placed on
the top layer close to the device.
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12 Device and Documentation Support
12.1 Trademarks
Thunderbolt is a trademark of Intel Corporation.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65980RHFR
ACTIVE
VQFN
RHF
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65980
TPS65980RHFT
ACTIVE
VQFN
RHF
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65980
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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