TPS68401, TPS68402
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SLVSA68A – MARCH 2010 – REVISED JANUARY 2011
MULTIFUNCTION 3-CHANNEL LED DRIVERS
Check for Samples: TPS68401, TPS68402
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
Multifunction LED Driver With Three
Independent Channels
Integrated High Efficiency 1x / 1.5x Charge
Pump With Automatic or Manual Gain Change
3 x 25.5-mA Total Output Current
3 x 25.5-mA Total Output Current
Three Independent Program Execution
Engines (3 x 16 Instructions)
8-Bit PWM With Exponential Control Option
8-Bit Current DAC Control
200-nA Typical Shutdown Current
Automatic Power-Save Mode
Autonomous Operation Without External
Control
Trigger I/O for Synchronizing Multiple Devices
One or Two General Purpose Output
Controlled Via Serial Interface
•
•
I2C Interface
Operating Temperature Range: -30ºC to 85ºC
APPLICATIONS
•
•
•
•
•
LED Control for Portable Applications
Accent Lighting (Mood, Personalization, etc.)
Function Indication (Charge, Messages, etc.)
Keypad Illumination / Backlight (White or RGB)
Display Backlight
DESCRIPTION
The TPS68401/TPS68402 is an advanced lighting management unit for handheld devices. It has three
independent channels optimized for driving RGB LEDs. The built-in fractional charge pump boosts the input
voltage to power the LEDs at low input voltage. Channel one can optionally be supplied directly from the battery
voltage to reduce power consumption and improve efficiency.
At the heart of the device is a programmable state machine which executes a lighting program consisting of up to
16 instructions per channel. Once the program is loaded through the I2C interface the device is fully independent
from the main processor resulting in significant system-level power savings. The device can issue an interrupt to
the main processor via the INT pin.
The TRIG I/O allows synchronization between multiple devices. A general-purpose output pin is provided which
is addressable through the serial interface. In addition, the INT pin can also be configured as general-purpose
output.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
TPS68401, TPS68402
SLVSA68A – MARCH 2010 – REVISED JANUARY 2011
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
VOUT
VDD
R_TO_BATT
CPLY 1P
8bit DAC
CPLY1N
CPLY 2P
1x/1.5x
Charge Pump
8-bit PWM
Charge Pump
Control
8bit DAC
R
CPLY2N
EN
G
8-bit PWM
GND
Reference
TRIM
GND
1.25 MHz Qpump
Oscillator
8bit DAC
HF PWM
32768 Hz (PWM)
CLK32K
B
8-bit PWM
Ext. PWM clock
Control
Register
PUC
SCL
SDA
ADDR_SEL0
ADDR_SEL1
Controller / Sequencer
ENABLE
VDD
GPO
2
Program
Register
INT_AS_GPO
I2C
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VDD
INT
TRIG
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ORDERING INFORMATION
TA
PACKAGE
-30°C to 85°C
ORDERABLE PART NUMBER
TOP-SIDE MARKING
YFF
TPS68401C4YFFR
TPS68401C4YFF
RHF
TPS68402A0RHFR
24RHF
TERMINAL FUNCTIONS
NanoFree YFF PACKAGE
(BOTTOM VIEW )
PACKAGE MARKING
TRIG
GND
VDD
CFLY
1P
CFLY
2P
4
INT
CLK
32K
GND
CFLY
1N
CFLY
2N
3
EN
GPO
ADDR
SEL0
ADDR
SEL1
VOUT
2
SDA
SCL
R
G
B
1
E
D
C
B
A
TERMINAL
NAME
NO.
YMILLL
PA1S
I/O
YM = YEAR / MONTH DATE CODE
LLLL = LOT TRACE CODE
S
= ASSEMBLY SITE CODE
A
= MAJOR DIE REVISION
1
= MINOR DIE REVISION
P
= PREPRODUCTION INDICATOR
0
= Pin A1 (Filled Solid)
DESCRIPTION
CFLY1P
4B
Positive terminal of charge pump fly capacitor
CFLY1N
3B
Negative terminal of charge pump fly capacitor
CFLY2P
4A
Positive terminal of charge pump fly capacitor
CFLY2N
3A
Negative terminal of charge pump fly capacitor
VDD
4C
Power pin
GND
4D
Ground
VOUT
2A
R
1C
O
Charge pump output
Current source output, Channel 1 (Red)
G
1B
O
Current source output, Channel 2 (Green)
B
1A
O
Current source output, Channel 3 (Blue)
SCL
1D
I
I2C Serial interface clock input
SDA
1E
I/O
CLK32K
3D
I
32.768-kHz clock input – If no clock present on power-up or after RESET, uses internal
oscillator
I2C Serial interface data input/output (open drain)
EN
2E
I
Chip enable (active high)
ADDR_SEL0
2C
I
I2C address select input
ADDR_SEL1
2B
I
I2C address select input
INT
3E
O
Interrupt output (open drain, active low); Can be configured as push-pull GPO
TRIG
4E
I/O
Trigger input / output (open drain, active low)
GPO
2D
O
General purpose output
GND
3C
Ground
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RHF PACKAGE MARKING - TOP VIEW
RHF PACKAGE - BOTTOM VIEW
TERMINAL
4
I/O
DESCRIPTION
NAME
NO.
CFLY2P
1
Positive terminal of charge pump fly capacitor
CFLY1P
2
Positive terminal of charge pump fly capacitor
VDD
3
Power pin
GND
4
Ground
CLK32K
5
I
32.768-kHz clock input. If no clock present on power-up or after RESET, uses internal
oscillator.
INT
6
O
Interrupt output (open drain, active low); Can be configured as push-pull GPO.
TRIG
7
I/O
Trigger input/output (open drain, active low)
N/C
8
Not connected
N/C
9
Not connected
N/C
10
Not connected
N/C
11
Not connected
N/C
12
SDA
13
I/O
Not connected
I2C Serial interface data input/output (open drain)
EN
14
I
Chip enable (active high)
SCL
15
I
I2C Serial interface clock input
GPO
16
O
General purpose output.
R
17
O
Current source output, Channel 1 (Red)
G
18
O
Current source output, Channel 2 (Green)
B
19
O
Current source output, Channel 3 (Blue)
ADDR_SEL0
20
I
I2C address select input
ADDR_SEL1
21
I
I2C address select input
VOUT
22
Charge pump output
CFLY2N
23
Negative terminal of charge pump fly capacitor
CFLY1N
24
Negative terminal of charge pump fly capacitor
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VOUT VDD (unregulated input battery voltage)
INT, GPO, R, G, B, CFLY1N,
CFLY1P, CFLY2N, CFLY2P,
Input/Output voltage range (with respect to PGND) ADDR_SEL0, ADDR_SEL1
VALUE
UNIT
-0.3 to 6
V
-0.3 to VDD+0.3
(6.0 max)
V
100
°C/W
SDA, SCL, EN, TRIG, CLK32K
qJA
Junction-to-ambient thermal resistance
PD
Continuous power dissipation
TJ
Operating junction temperature
Tstg
Storage temperature
ESD rating
(1)
(2)
Internally limited
W
-30 to 125
°C
-65 to 150
°C
(HBM) Human body model
±2000
(CDM) Charged device model
±100
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VDD
Unregulated input battery voltage
MIN
NOM
MAX
UNIT
2.7
3.6
5.5
V
INT, GPO,
ADDR_SEL0,
ADDR_SEL1
0
5.5
V
SDA, SCL, EN,
TRIG
0
1.8
V
64
kHz
CLK_32K
External clock frequency
16
TA
Operating ambient temperature
Flying capacitor
Input capacitor (VDD)
Output capacitor (VOUT)
32
-30
85
°C
0.47
mF
1
mF
1
mF
SCA, SDA pull-up resistor value
10
kΩ
INT pull-up resistor value
10
kΩ
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ELECTRICAL CHARACTERISTICS
VBAT = 3.6 V ±5%, TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
SUPPLY CURRENT
Shutdown current
EN = 0
Standby current
IDD
Normal mode supply current
Power save current
0.2
2.0
EN = 1; CHIP_EN = 0
Ext. 32-kHz clock not running
1
2.0
EN = 1; CHIP_EN = 0
Ext. 32-kHz clock running
1
2.0
mA
EN = 1, CHIP_EN = 1
Ext. 32-kHz clock running
C/P, G & B channel disabled
R_TO_BATT = 1 (R channel enabled)
[CLK_DET_EN : INT_CLK_EN] = 00b
(clock detection disabled)
ILED = 5 mA, 50% duty cycle
180
EN = 1, CHIP_EN = 1
C/P and LED drivers disabled
[CLK_DET_EN : INT_CLK_EN] = 10b
(automatic clock source selection)
PWRSAVE_EN = 0
190
EN = 1, CHIP_EN = 1
C/P in 1x mode, no load (1),
LED drivers disabled
Ext. 32-kHz clock running
70
EN = 1, CHIP_EN = 1
C/P in 1.5x mode, no load (1),
LED drivers disabled
1700
EN = 1, CHIP_EN = 1
C/P in 1x mode, no load (1),
LED drivers enabled
Ext. 32-kHz clock running
650
EN = 1, CHIP_EN = 1
C/P in 1x mode, 5-mA load LED drivers
enabled
Ext. 32-kHz clock running
800
EN = 1, CHIP_EN = 1
CLK32K active
10
EN = 1, CHIP_EN = 1
Internal oscillator running
190
STANDBY to NORMAL mode
500
mA
mA
STARTUP
tSTARTUP
Startup time
1000
ms
BOOST VOLTAGE (VOUT)
1x mode, no load (1)
VOUT
Output voltage
VHYS
Automatic gain change hysteresis
VDD
1.5x mode, VDD = 3.6 V, no load (1)
4.55
C/P in automatic mode, no load (1)
200
Continuous output current
IOUT
fS
ZO
tON
(1)
(2)
6
V
mV
150
VOUT < 1V
Max output current
150
VOUT > 1V
150
Switching frequency
1.25
Open loop output impedance
mA
250
1x mode (VDD - VOUT) / IOUT
1.1
1.5x mode (2)
4.1
Turn on time from 1x to 1.5x mode.
VDD = 3.6 V
50
Turn on time from off to 1.5x mode.
VOUT = 0 V
100
MHz
Ω
ms
No-load measurement condition is as follows: DAC setting = default (17.5 mA); PWM = 0; Output connected to ground via 150-Ω
resistor.
Charge pump Impedance is measured at VDD = 3 V, IOUT = 50 mA follows: [VOUT (IOUT = 0) – VOUT (IOUT)] / IOUT
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ELECTRICAL CHARACTERISTICS (continued)
VBAT = 3.6 V ±5%, TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL OSCILLATOR
fOSC
Internal oscillator frequency
TA = 25 ºC
-4
4
-30 ºC ≤ TA ≤ 85 ºC
-7
7
%
OUTPUT CHANNELS (R,G,B)
VLED
VDRP
LED forward voltage
1.5
Driver saturation voltage
IR,G,B = 17.5 mA
LED current
IR,G,B
fPWM
(3)
Per channel
50
0
LED current resolution
IR,G,B = 17.5 mA
LED current matching
IR,G,B = 17.5 mA, Vf = 3.0 V
PWM frequency
Pin leakage current
PWMRES
PWM resolution
mV
mA
8
LED current accuracy
ILEAK
100
25.5
-4
1
PWM_HF = 1
Internal high frequency oscillator
558
PWM_HF = 0
Internal clock or CLK_32K
256
TA = 25 ºC
0.1
Bit
4
%
2
%
Hz
-30 ºC ≤ TA ≤ 85 ºC
1
8
mA
Bit
LOGIC INPUT LEVELS (EN)
VIL
Input low level
VIH
Input high level
IIH, IIL
Input bias current
tdelay
Input delay
0.5
V
1
mA
1.2
VEN = 0 V to 1.65 V
V
-1
EN pin low to high
2
ms
LOGIC INPUT LEVELS (SCL, SDA, TRIG, CLK_32K)
VIL
Input low level
VEN = 1.65 V to 3.6 V
VIH
Input high level
VEN = 1.65V to 3.6 V
IIH, IIL
Input bias current
fSCL
I2C clock frequency
0.2 x VEN
0.8 x VEN
V
V
-1.0
1.0
mA
400
kHz
LOGIC INPUT LEVELS (ADD_SEL0, ADD_SEL1)
VIL
Input low level
VIH
Input high level
IIH, IIL
Input bias current
0.2 x VDD
V
1.0
mA
0.5
V
1.0
mA
0.5
V
0.8 x VDD
VADD_SEL0, ADD_SEL1 = 3.6 V
V
-1.0
LOGIC OUTPUT LEVELS (SDA, TRIG, INT pin as INT)
VOL
IIL
Output low level
IOUT = 3 mA through pull-up
0.3
INT pin as INT (open drain), INT = high,
VINT = 0 V to 1.65 V
Output leakage current
LOGIC OUTPUT LEVELS (GPO, INT pin as GPO)
VOL
Output low level
IOUT = 3 mA
VOH
Output high level
IOUT = -2 mA
(3)
0.3
VDD - 0.5
VDD - 0.3
V
IOUT at VDRP = 0.9 x IOUT at (VDD - VLED) = 1 V
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DESCRIPTION OF CHARGE PUMP OPERATION
The TPS68401/TPS68402 includes a regulated fractional charge pump with bypass mode. It is used to boost the
supply voltage for the output drivers when the battery voltage is close to or below the forward bias voltage of the
LEDs. In 1.5x mode VOUT is boosted to 1.5x VDD or 4.55 V, whichever value is lower. In 1x (bypass) mode the
output is connected directly to the input supply.
The charge pump is controlled with two CP_MODE bits in the CONFIG register. When disabled, VOUT is
connected to ground through a 300-kΩ resistive path. The user can manually select 1x and 1.5x mode or select
automatic mode. When automatic mode is enabled, the charge pump will operate in bypass mode as long as the
input supply voltage is sufficient to drive the LEDs. Dropout voltage of all three channels is monitored and charge
pump gain is set to 1.5x if any one driver does not have enough headroom to drive the LED. When the part
enters Power Save mode the output capacitor is connected to the input supply through a resistive path. See
Power Save mode description for details.
The mode selection logic utilizes digital filtering to prevent glitches of the supply voltage from triggering gain
changes. If R-driver current source is connected to battery (CONFIG register, bit R_TO_BATT set to 1) voltage
monitoring is disabled in R output, but still functional in G and B output.
BYPASS
VDD
CIN
WEAK 1x
CP _MODE [ 1:0]
REG
1x/1.5x
C/P
VOUT
COUT
CP _MODE [ 1:0] = OFF
Figure 1. Functional Model of Charge Pump
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5.5
1 .5
xM
OD
E
1x
M
O
D
E
V OUT [V]
4.5
3.0
5.5
V DD [V]
Figure 2. Charge Pump Output Voltage
LED DRIVER OPERATIONAL DESCRIPTION
The TPS68401/TPS68402 has three independent constant current LED drivers with 8-bit PWM control. Output
current is programmed through the I2C register and ranges from 0 mA to 25.5 mA with 8-bit resolution. PWM
duty cycle is controlled either by program instructions or R/G/B PWM registers. Green and blue channels are
always connected to the charge pump output VOUT. The red channel is connected to either VOUT or VDD
depending on R_TO_BAT bit setting of the CONFIG register. If red channel is connected to VDD, automatic
charge pump gain control is not used for this output. Connecting the red channel to VDD provides better efficiency
when driving LEDs with low VF or the supply voltage is high enough to drive a LED with high VF.
PWM frequency is either 256 Hz or 558 Hz and is selected through PWM_HF bit in the CONFIG register. Linear
and logarithmic PWM duty-cycle-to-input response is selectable through the LOG_EN bit of the ENABLE register.
LOG_EN bit controls PWM response for all three channels. Logarithmic response is approximated by
piece-wise-linear function as shown below.
When the external clock source is selected for driving the PWM, PWM frequency scales with the external clock
frequency. Nominal 256-Hz PWM frequency requires external clock frequency of 32.768 kHz.
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PWM CONTROL
Table 1. PWM Value and Output in LIN and EXP Mode
PWM OUTPUT
PWM REGISTER VALUE
PWM REGISTER VALUE
PWM OUTPUT
LIN
EXP
LIN
EXP
0
0
0
128
128
64
1
1
0
129
129
65
2
2
1
130
130
66
3
3
1
131
131
67
4
4
2
132
132
68
69
5
5
2
133
133
...
...
...
...
...
...
61
61
30
189
189
125
62
62
31
190
190
126
63
63
31
191
191
127
64
64
32
192
192
129
65
65
32
193
193
131
66
66
33
194
194
133
...
...
...
...
...
...
125
125
62
253
253
251
126
126
63
254
254
253
127
127
63
255
255
255
256
224
EXP
LIN
PWM OUT PUT [T ICKS]
192
160
128
96
64
32
0
0
32
64
96
128
160
192
224
256
PWM LINEAR INPUT
Figure 3. Graph of PWM Output vs. PWM Input
10
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Table 2. LED Channel Output Current Control
REGISTER
R_CURRENT,
G_CURRENT,
B_CURRENT
BITS
7:0
VALUE
CHANNEL CURRENT
0x00
0.0 mA
0x01
0.1 mA
↕
↕
0xAE
17.4 mA
0xAF
17.5 mA
0xB0
17.6 mA
↕
↕
0xFE
25.4 mA
0xFF
25.5 mA
DATA TRANSMISSION
TPS68401/TPS68402 features an I2C slave interface for communication to a controlling microprocessor. SDA,
SCL, CLK_32K and TRIG pins input levels are defined by EN pin. EN pin is used as voltage reference for logic
inputs and therefore no dedicated VIO pin is required.
VDD
EN
Input
Buffer
SDA
Level
Shifter
SCL
Level
Shifter
CLK32K
Level
Shifter
TRIG
Level
Shifter
Figure 4. Internal Logic Level Shifters
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SUBADDRESS DEFINITION
Slave Address + R/nW
Start
G3
G2
G1
G0
A2
A1
A0
Sub Address
R/nW
ACK
S7
S6
S5
S4
S3
S2
Data
S1
S0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Stop
Figure 5. Subaddress in I2C Transmission
Start – Start Condition
ACK – Acknowledge
G(3:0) – Group ID: Address fixed at 0110b
S(7:0) – Subaddress: defined per register map
– Device address: Device address is selectable via
A(2:0)
ADDR_SEL input pin.
D(7:0) – Data; Data to be loaded into the device
R/nW – Read / not Write select bit
Stop – Stop condition
Table 3. Subaddress Bits
Defined by ADDR_SEL Inputs
ADDR_SEL
[1:0]
A [2:0]
00
010
01
011
10
100
11
101
The address bits used in the slave address portion of the I2C transaction are defined by the device pins
ADDR_SEL1 and ADDR_SEL0 (combined as ADDR_SEL [1:0] above). The table above gives the values of the
address bits for all combinations of ADDR_SEL1 and ADDR_SEL0.
I2C BUS OPERATION
The I2C bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 6. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate group and address bits are set for the device, then the device will issue an
acknowledge pulse and prepare the receive subaddress data. Subaddress data is decoded and responded to as
per the Register Map section of this document. Data transmission is completed by either the reception of a stop
condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high
transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must
occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address,
sub-address and data words. The I2C interface will auto-sequence through register addresses, so that multiple
data words can be sent for a given I2C transmission.
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...
SDA
SCL
1
2
3
4
5
6
7
START CONDITION
8
...
9
ACKNOWLEDGE
STOP CONDITION
2
Figure 6. I C Start / Stop / Acknowledge Protocol
tLOW
tr(
t H(STA )
tF
SCL
t H(STA )
t H(DAT)
tHIGH
t S(DAT)
tS(STO)
tS(STA )
SDA
t(BUF )
P
S
S
P
Figure 7. I2C Data Transmission Timing
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DATA TRANSMISSION TIMING
VBAT = 3.6 ±5%, TA = 25 ºC, CL = 100 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
100
f(SCL)
Serial clock frequency
t(BUF)
Bus free time between stop and start
condition
t(SP)
Tolerable spike width on bus
tLOW
SCL low time
tHIGH
SCL high time
tS(DAT)
SDA → SCL setup time
tS(STA)
Start condition setup time
tS(STO)
Stop condition setup time
tH(DAT)
SDA → SCL hold time
tH(STA)
Start condition hold time
tr(SCL)
Rise time of SCL Signal
tf(SCL)
Fall time of SCL Signal
tr(SDA)
Rise time of SDA Signal
tf(SDA)
Fall time of SDA Signal
400
SCL = 100 kHz
4.7
SCL = 400 kHz
1.3
SCL = 100 kHz
SCL = 400 kHz
4.7
SCL = 400 kHz
1.3
4
SCL = 400 kHz
0.6
SCL = 100 kHz
250
SCL = 400 kHz
100
SCL = 100 kHz
4.7
SCL = 400 kHz
0.6
SCL = 100 kHz
4
SCL = 400 kHz
0.6
SCL = 100 kHz
0
3.45
SCL = 400 kHz
0
0.9
4
SCL = 400 kHz
0.6
ns
µs
SCL = 100 kHz
SCL = 100 kHz
KHz
µs
50
SCL = 100 kHz
UNIT
µs
ns
µs
µs
µs
µs
SCL = 100 kHz
1000
SCL = 400 kHz
300
SCL = 100 kHz
300
SCL = 400 kHz
300
SCL = 100 kHz
1000
SCL = 400 kHz
300
SCL = 100 KHz
300
SCL = 400 kHz
300
ns
ns
ns
ns
FUNCTIONAL DESCRIPTION OF DEVICE PINS
ADDR_SEL0 AND ADDR_SEL1 PINS
ADDR_SEL0 and ADDR_SEL1 pins define the chip I2C address. Pins are referenced to VDD signal level. See
Data Transmission section for I2C address definitions.
GENERAL PURPOSE OUTPUT PIN
The TPS68401/TPS68402 has one dedicated general purpose output pin (GPO) with digital CMOS output.
High-level output voltage is defined by VDD and no pull-up resistor is needed. GPO output is controlled by GPO
bit of the GPO register.
INT PIN
The INT pin is used to issue an interrupt to a host processor when END instruction is executed and the INT bit is
set (see Instruction Description section for details). The INT pin can also be configured as a GPO pin by setting
the INT_AS_GPO bit of the GPO register. When configured as INT pin it has an open drain output and requires
an external pull-up resistor. As GPO pin it has a digital CMOS output, high-level output voltage is defined by VDD,
and no pull-up resistor is needed. In GPO mode the output is controlled by the INT bit of the GPO register.
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TRIG PIN
TRIG pin is used to send and receive trigger pulses between multiple TPS68401/TPS68402 devices for pattern
synchronization. TRIG is an open drain output and requires an external pull-up resistor. External trigger input
signal must be at least two 32-kHz clock cycles long to be recognized. Trigger output signal is three 32-kHz clock
cycles long. If TRIG pin is not used on application, it should be connected to GND.
CLK_32K PIN
CLK_32K pin is used for connecting external 32.768-kHz clock to TPS68401/TPS68402. Connecting several
devices to the same clock source ensures synchronous instruction execution. When external clock source is
used the internal oscillator is shut down during automatic power save mode to achieve lowest possible current
consumption. An external clock source is not required for device operation. If external clock is not used,
CLK_32K pin should be connected to GND.
CLK_32K EXTERNAL CLOCK DETECTION
The instruction execution engine and PWM are clocked either by an internal 32.768-kHz or an external clock.
The user can manually select internal or external clock or enable automatic clock source selection. In automatic
mode the TPS68401/TPS68402 monitors the CLK32K pin; If external clock frequency is < 15 kHz, stuck-at-zero,
or stuck-at-one, the clock detector indicates that no external clock is present and switches to internal clock
source. It switches back to external clock source once the external clock is detected again. In any mode (manual
or automatic selection) the clock source can be checked by reading the EXT_CLK_USED bit of the STATUS
register. Clock source selection is controlled by CONFIG register bits INT_CLK_EN and CLK_DET_EN. External
clock detection is disabled in POWER SAVE mode.
When external clock source is selected, instruction timing and PWM frequency scale with the external clock
frequency. Nominal external clock frequency is 32.768 kHz.
MODES OF OPERATION
RESET
In the RESET mode all the internal registers are reset to the default values. Reset is initiated if 0xFFh is written
into the RESET register or internal power-up clear (PUC) is activated. PUC will activate when supply voltage is
connected to VDD pin or when the supply voltage drops below the nPUC_VIL level. Once VDD rises above
nPUC_VIH, PUC is released and the chip will continue to the STANDBY mode. CHIP_EN control bit is low after
PUC by default.
SHUTDOWN
Whenever the EN pin is pulled low the device enters SHUTDOWN mode. All functions are disabled, including the
serial interface. This is the lowest power mode.
STANDBY
STANDBY mode is entered if the CHIP_EN bit of the ENABLE register is set to 0 and reset is not active.
Registers can be written to in this mode with the exception of the EXEC bits of the ENABLE register
(R_EXEC[1:0], G_EXEC[1:0], B_EXEC[1:0]). Control bits are effective after start up.
STARTUP
When CHIP_EN bit of the ENABLE register is written 1 and EN pin is high, the chip executes the internal startup
sequence to power up analog blocks (VREF, bias, oscillator etc.). If the chip temperature rises too high, the over
temperature shutdown (OTS) disables the chip and automatically re-enters STARTUP mode, until no thermal
shutdown event is present.
NORMAL
During NORMAL mode the user controls the chip using the control registers. If EN pin is set low, the CHIP_EN
bit is reset to 0.
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POWER SAVE
In POWER SAVE mode analog blocks are disabled to minimize power consumption. See the Power Save Mode
section for further information.
MODE TRANSITIONS
Setting the CHIP_EN bit of the ENABLE register to 0 resets the program counters (PC) but does not change the
LED controller operational mode (see NORMAL MODE settings). Pulling the EN pin low resets the CHIP_EN bit
and PC but does not affect operational mode (see NORMAL MODE settings).
POWER OFF
nPUC=0
RESET = 0xFFh or
nPUC=0
RESET
nPUC=1 and EN pin = Low
nPUC=1 and
EN pin = High
SHUTDOWN
EN pin = Low
EN pin = High
STANDBY
CHIP_EN bit = 0
CHIP_EN bit = 1
STARTUP
TSD=1
TSD=1
TSD=0
TSD RECOVERY
TSD=0
TSD=1
NORMAL
Enable
Power Save
Disable
Power Save
POWER SAVE
Figure 8. Device Startup Flow and Modes of Operation
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POWER SAVE MODE
Automatic power save mode is enabled when PWRSAVE_EN bit in the CONFIG register is set to 1. In power
save mode all analog blocks are powered down with exception of charge pump protection circuits, provided
external clock source is used to run the PWM. If internal clock source has been selected, only charge pump and
LED drivers are disabled and the digital part of the LED controller remains active. In both cases charge pump
enters a special 1x mode to keep the output at battery level. During program execution the device can enter
power save if there is no PWM activity in R, G and B outputs for > 50ms. To prevent the device from entering
power-save mode for short periods of time the device does a command look-ahead. In every instruction cycle R,
G, B commands are analyzed, and if there is sufficient time left with no PWM activity, device will enter power
save mode. In power save mode program execution continues uninterruptedly. When a command that requires
PWM activity is executed, the device starts up automatically. The following table describes commands and
conditions that can activate power save mode. All channels (R, G, and B) need to meet power save condition in
order to enable power save.
POWER SAVE MODE can only be entered when no channel is in the LOAD MODE, all PWM values are zero or
channel is disabled, and C/P mode is either OFF or Automatic.
Table 4. Requirements for Power Save By Command
COMMAND
POWER SAVE REQUIREMENT
WAIT
Enter power save only if PWM is zero and wait is greater then 50 ms.
RAMP
Enter power save only if ramp ends with PWM set to zero and there is 50 ms before the next command.
TRIGGER
Enter power save only if PWM is zero while waiting for trigger.
END
Enter power save only if PWM is zero or reset bit of command is set to 1.
SET
Enter power save only if PWM is set to zero and the next command generates at least a 50-ms wait.
Other
Cannot enter power save mode
LED CONTROLLER OPERATIONAL MODES (NORMAL MODE)
In NORMAL MODE, operation of the red, green, and blue LED controller is defined independently by the
OP_MODE, and respective R/G/B_PC, R/G/B_PWM, and R/G/B_CURRENT registers. The R/G/B CURRENT
registers define the maximum output current for the respective channel. MODE control bits are synchronized to a
32-kHz clock.
In the following, PC denotes either R_PC, G_PC, or B_PC program counter. MODE denotes either R_MODE,
G_MODE, or B_MODE bits of the OP_MODE register.
DISABLED MODE
LED output current is set to 0 and PC counter is reset.
LOAD MODE
The device can store 16 16-bit commands for each channel (R, G, B). Due to the 8-bit format of the I2C protocol
two writes are required to load a single instruction. The device supports auto-increment addressing to reduce
program load time. Register address is incremented after each 8 data bits which allows the whole program
memory to be written in a single I2C write sequence. Program memory is defined in the register table. Read /
write access to program memory is allowed only in LOAD mode and only to the channel in LOAD mode. LOAD
mode resets respective channel’s PC. Program execution on all other channels is halted and PWM value
remains static while at least one channel is in LOAD mode. Program execution continues when all channels are
out of LOAD program mode.
RUN MODE
In RUN mode the LED controller executes instructions stored in program memory. Execution is controlled by the
R, G, and B program counters (R_PC, G_PC, B_PC) and the ENABLE register. For details refer to RUN MODE
OPTIONS section. Program start position can be determined by writing to the PC registers. If program counter
runs to end (15) the next command will be executed from program location 0. If internal PWM clock source is
selected in RUN mode, the LED controller must be disabled (MODE = 00b) before disabling the chip (with
CHIP_EN bit or EN pin) to ensure that the sequence starts from the correct program counter (PC) value when
restarting the sequence. PC registers are synchronized to a 32-kHz clock.
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DIRECT MODE
In DIRECT mode the LED channels can be controlled independently through the I2C interface. For each channel
there is a PWM control register (R_PWM, G_PWM, B_PWM) which contains the PWM duty cycle. If the charge
pump is set to automatic 1x / 1.5x mode selection, PWM values need to be written 0 before disabling the drivers
(MODE = 00b) to ensure proper automatic gain change operation.
MODE TRANSITIONS
A transition between operational modes aborts the instruction being executed (if any), resets the PC and sets the
PWM duty cycle to 0. The channel current setting is not affected.
10b
RUN
10b
10b
10b
00b
01b
11b
DISABLED
11b
01b
00b
00b
00b
DIRECT
LOAD
11b
01b
01b
11b
NORMAL MODE
Bit settings refer to the R/G/B_MODE[1:0] bits of the OP_MODE register.
Figure 9. Operational Modes of LED Controller in NORMAL Mode of Operation
RUN MODE SETTINGS
Run mode is set independently for each channel in the ENABLE register. In the following PC denotes either
R_PC, G_PC, or B_PC program counter. EXEC denotes either R_EXEC, G_EXEC, or B_EXEC bits of the
ENABLE register.
HOLD
Wait until current command is finished then stop while EXEC[1:0] = 00b (Hold). PC can be read or written only in
this mode.
STEP
Execute instruction defined by PC, increment PC and change EXEC[1:0] to 00b (Hold).
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CONTINUE
Start program execution at PC value, increment PC and continue.
EXECUTE
Execute instruction defined by PC, do not update PC, change EXEC[1:0] to 00b (Hold).
MODE TRANSITIONS
A transition between run modes does not abort the instruction being executed. PC is updated before mode
transition. Note that PC is also incremented when transitioning out of EXECUTE mode.
10b
CONTINUE
10b
10b
10b
00b
11b
01b
HOLD
11b
01b
11b
or
00b
EXECUTE
00b
01b
or
00b
STEP
01b
11b
RUN MODE
Bit settings refer to the R/G/B_EXEC[1:0] bits of the ENABLE register.
Figure 10. Run Mode State Diagram
INSTRUCTION DESCRIPTION
The three channels are independent, except for the trigger connections between the channels. The following
table describes the binary format used. In this implementation, there are 16 program steps available per channel.
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0
Int. 32kHz clock
1
Running Counter Value
Increment
Counter
PWM Output
Step Time
Counter
Current value of trigger point
Prescale
Div 16 or
512
Inc / Dec
Ext. clock (CLK32K)
Step time set
G1
Clock for step time counter
Prescale Select
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PWM_HF
Clock Source Select
SLVSA68A – MARCH 2010 – REVISED JANUARY 2011
Comparator
Free
Running
Counter
x2
G1
0
HF PWM clock
1
Figure 11. Simplified Block Diagram of PWM
RAMP / WAIT
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
prescale
0 = 16
1 = 512
sign
0= INC
1= DEC
step time
1 to 63
number of steps
0 to 127
The ramp command generates a PWM ramp starting from the current value. At each ramp step the PWM value
is incremented or decremented by one. Time for one step is defined by prescale and step time bits. The number
of increments executed by the instruction is defined by number of steps which has a maximum value of 127 or
half of full scale. If, during a ramp command, PWM reaches minimum / maximum (0 / 255), the ramp command
will continue for the remaining number of steps without changing the PWM value (PWM value saturates). This
enables the ramp command to be used as combined ramp and wait command in single instruction.
Ramp command can be used as a single step time wait instruction when increment is zero.
SET PWM
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
1
0
0
0
0
0
0
x
x
x
x
x
x
x
x
PWM value
Set PWM output value from 0 to 255 in a single instruction.
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BRANCH
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
loop count
0 to 63 (0 = loop forever)
not used
step number
Loop instruction. Code between (step number) and BRANCH command will be executed (loop count + 1) times.
Set (loop count) = 0 for infinite looping. Nested looping is supported. The number of nested loops is not limited.
GO TO START
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Command resets program counter register and continues executing program from the 00H location.
END
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
1
1
0
INT
RST
x
x
x
x
x
x
x
x
x
x
x
interupt
reset
0 = Keep the current PWM value
1 = Set PWM value to 0
0 = Do not issue interrupt
1 = Issue interrupt and set corresponding status bit high. Interrupt is cleared by reading interrupt status register.
Stops program execution. Set (interrupt) = 1 to issue an interrupt on the INT pin. If INT is used it must be cleared
before pulling the EN pin low or writing CHIP_EN low.
TRIGGER
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
1
1
1
EXT
x
x
B
G
R
EXT
x
x
B
G
R
x
Wait for trigger
R=RED; G=GREEN; B=BLUE; EXT=EXTERNAL
1 = Wait for trigger from specified channel.
Own channel position is ignored.
0 = Continue without wait
Issue trigger
R=RED; G=GREEN; B=BLUE; EXT=EXTERNAL
1 = Issue trigger for specified channel.
Own channel position is ignored.
0 = Continue without issuing trigger
Used to synchronize channels and / or multiple units. The wait for trigger command is executed until all defined
trigger have been received. An external trigger is ignored by the issuing channel / device. External trigger input
signal must be at least two 32-kHz clock cycles long to be recognized. Trigger output signal is three 32-kHz clock
cycles long. External trigger signal is active low, i.e. when trigger is send / received the pin is pulled to GND.
Sent external trigger is masked, i.e. the device which has sent the trigger will not recognize it. If send and wait
external trigger are used on the same command, the send external trigger is executed first, then the wait external
trigger. Channel (R, G, or B) waiting for its own trigger is not allowed.
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Table 5. ADDRESS REGISTER MAP
22
REGISTER
ADDRESS
(HEX)
NAME
DEFAULT
VALUE
0
0
ENABLE
0000 0000
Chip enable and execution control
1
1
OP_MODE
0000 0000
RGB operating mode control
2
2
R_PWM
0000 0000
Red channel PWM value
3
3
G_PWM
0000 0000
Green channel PWM value
4
4
B_PWM
0000 0000
Blue channel PWM value
5
5
R_CURRENT
1010 1111
Red channel current limit value
6
6
G_CURRENT
1010 1111
Green channel current limit value
7
7
B_CURRENT
1010 1111
Blue channel current limit value
8
8
CONFIG
0000 0000
Charge pump configuration
9
9
R_PC
0000 0000
Red channel program counter value
10
0A
G_PC
0000 0000
Green channel program counter value
DESCRIPTION
11
0B
B_PC
0000 0000
Blue channel program counter value
12
0C
STATUS
0000 0000
Clock and interrupt status
13
0D
RESET
0000 0000
Device reset
14
0E
GPO
1000 0000
GPO configuration and value
15
N/A
N/A
N/A
16
10
PROG_MEM_R1_H
0000 0000
Red channel instruction 1 MSB
17
11
PROG_MEM_R1_L
0000 0000
Red channel instruction 1 LSB
...
...
...
...
46
2E
PROG_MEM_R16_H
0000 0000
Red channel instruction 16 MSB
47
2F
PROG_MEM_R16_L
0000 0000
Red channel instruction 16 LSB
48
30
PROG_MEM_G1_H
0000 0000
Green channel instruction 1 MSB
49
31
PROG_MEM_G1_L
0000 0000
Green channel instruction 1 LSB
...
...
...
...
78
4E
PROG_MEM_G16_H
0000 0000
Green channel instruction 16 MSB
79
4F
PROG_MEM_G16_L
0000 0000
Green channel instruction 16 LSB
80
50
PROG_MEM_B1_H
0000 0000
Blue channel instruction 1 MSB
81
51
PROG_MEM_B1_L
0000 0000
Blue channel instruction 1 LSB
...
...
...
...
110
6E
PROG_MEM_B16_H
0000 0000
Blue channel instruction 16 MSB
111
6F
PROG_MEM_B16_L
0000 0000
Blue channel instruction 16 LSB
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Register not implemented
...
...
...
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ENABLE REGISTER (ENABLE)
Address – 0x00h
DATA BIT
FIELD NAME
D7
D6
D5
LOG_EN CHIP_EN
D4
D3
R_EXEC[1:0]
D2
D1
G_EXEC[1:0]
D0
B_EXEC[1:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
D1
D0
FIELD NAME
BIT DEFINITION
LOG_EN
Enable logarithmic current adjustment mode
CHIP_EN
Chip enable: Forcing EN pin low resets CHIP_EN to zero. See state diagram for details.
Program execution control for red channel
00b – Hold: Finish current instruction, then stop until R_EXEC[1:0] changes.
R_EXEC[1:0]
01b – Step: Finish current instruction, increment R_PC and set EXEC to hold
10b – Continue: Execute command indicated by PC, then increment R_PC
11b – Execute: Execute command indicated by R_PC, then set R_EXEC[1:0] to 00b (Hold)
Program execution control for green channel
00b – Hold: Finish current instruction, then stop until G_EXEC[1:0] changes
G_EXEC[1:0]
01b – Step: Finish current instruction, increment R_PC and set EXEC to hold
10b – Continue: Execute command indicated by PC, then increment G_PC
11b – Execute: Execute command indicated by G_PC, then set G_EXEC[1:0] to 00b (Hold)
Program execution control for blue channel
00b – Hold: Finish current instruction, then stop until B_EXEC[1:0] changes
B_EXEC[1:0]
01b – Step: Finish current instruction, increment R_PC and set EXEC to hold
10b – Continue: Execute command indicated by PC, then increment B_PC
11b – Execute: Execute command indicated by B_PC, then set B_EXEC[1:0] to 00b (Hold)
OPERATION MODE REGISTER (OP_MODE)
Address – 0x01h
DATA BIT
D7
D6
FIELD NAME
N/A
N/A
D5
D4
D3
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
R_MODE[1:0]
FIELD NAME
D2
G_MODE[1:0]
B_MODE[1:0]
BIT DEFINITION
Red channel operating mode
00b – Disable
R_MODE[1:0]
01b – Load: Load program to instruction registers and reset R_PC
10b – Run: Execute commands according to R_EXEC[1:0] setting in ENABLE register
11b – Direct: Direct control (through R_PWM register)
Green channel operating mode
00b – Disable
G_MODE[1:0]
01b – Load: Load program to instruction registers and reset G_PC
10b – Run: Execute commands according to G_EXEC[1:0] setting in ENABLE register
11b – Direct: Direct control (through G_PWM register)
Blue channel operating mode
00b – Disable
B_MODE[1:0]
01b – Load: Load program to instruction registers and reset B_PC
10b – Run: Execute commands according to B_EXEC[1:0] setting in ENABLE register
11b – Direct: Direct control (through B_PWM register)
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RED CHANNEL PWM CONTROL REGISTER (R_PWM)
Address – 0x02h
DATA BIT
D7
D6
D5
D4
FIELD NAME
D3
D2
D1
D0
R_PWM[7:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
D2
D1
D0
FIELD NAME
R_PWM[7:0]
BIT DEFINITION
Red channel PWM value used when R_MODE is Direct
GREEN CHANNEL PWM CONTROL REGISTER (G_PWM)
Address – 0x03h
DATA BIT
D7
D6
D5
D4
FIELD NAME
D3
G_PWM[7:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
D2
D1
D0
FIELD NAME
G_PWM[7:0]
BIT DEFINITION
Green channel PWM value used when G_MODE is Direct
BLUE CHANNEL PWM CONTROL REGISTER (B_PWM)
Address – 0x04h
DATA BIT
D7
D6
D5
D4
FIELD NAME
D3
B_PWM[7:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
D2
D1
D0
FIELD NAME
B_PWM[7:0]
BIT DEFINITION
Blue channel PWM value used when B_MODE is Direct
RED CHANNEL CURRENT CONTROL REGISTER (R_CURRENT)
Address – 0x05h
DATA BIT
D7
D6
D5
D4
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1
0
1
0
1
1
1
1
FIELD NAME
D3
R_CURRENT[7:0]
FIELD NAME
BIT DEFINITION
Red channel current setting
0000 0000b - 0.0 mA
0000 0001b - 0.1 mA
0000 0002b - 0.2 mA
R_CURRENT[7:0]
...
1010 1111b - 17.5 mA (default)
...
1111 1101b - 25.3 mA
1111 1110b - 25.4 mA
1111 1111b - 25.5 mA
24
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GREEN CHANNEL CURRENT CONTROL REGISTER (G_CURRENT)
Address – 0x06h
DATA BIT
D7
D6
D5
D4
D3
FIELD NAME
D2
D1
D0
G_CURRENT[7:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1
0
1
0
1
1
1
1
D2
D1
D0
FIELD NAME
BIT DEFINITION
Green channel current setting
0000 0000b - 0.0 mA
0000 0001b - 0.1 mA
0000 0002b - 0.2 mA
G_CURRENT[7:0]
...
1010 1111b - 17.5 mA (default)
...
1111 1101b - 25.3 mA
1111 1110b - 25.4 mA
1111 1111b - 25.5 mA
BLUE CHANNEL CURRENT CONTROL REGISTER (B_CURRENT)
Address – 0x07h
DATA BIT
D7
D6
D5
D4
D3
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1
0
1
0
1
1
1
1
FIELD NAME
B_CURRENT[7:0]
FIELD NAME
BIT DEFINITION
Blue channel current setting
0000 0000b - 0.0 mA
0000 0001b - 0.1 mA
0000 0002b - 0.2 mA
B_CURRENT[7:0]
...
1010 1111b - 17.5 mA (default)
...
1111 1101b - 25.3 mA
1111 1110b - 25.4 mA
1111 1111b - 25.5 mA
CONFIGURATION CONTROL REGISTER (CONFIG)
Address – 0x08h
DATA BIT
D7 (1)
D6
D5
FIELD NAME
N/A
PWM_HF
PWRSAVE_EN
READ/WRITE
N/A
R/W
R/W
R/W
RESET VALUE
0
0
0
0
(1)
D4
D3
D2
D1
D0
R_TO_BATT
CLK_DET_EN
INT_CLK_EN
R/W
R/W
R/W
R/W
0
0
0
0
CP_MODE[1:0]
Bit D7 must be set to 0 at all times. Writing 1 may result in unexpected behavior.
FIELD NAME
BIT DEFINITION
Source clock for PWM blocks
PWM_HF
0b - 256-Hz PWM frequency
1b - 558-Hz PWM frequency
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FIELD NAME
PWRSAVE_EN
BIT DEFINITION
0b - Power save mode disabled
1b – Power save mode enabled
Charge pump operating mode
00b – OFF
CP_MODE[1:0]
01b – Forced 1x mode
10b – Forced 1.5x mode
11b – Automatic mode selection
Red channel source supply
R_TO_BAT
0b – Red channel connected to charge pump output (VOUT)
1b – Red channel connected to battery supply (VDD)
PWM clock source
00b - Use external clock source (CLK_32)
[CLK_DET_EN
INT_CLK_EN]
01b - Use internal clock source, clock detection disabled
10b - Automatically select clock source, clock detection enabled
11b - Use internal clock source, clock detection disabled
RED CHANNEL PROGRAM COUNTER REGISTER (R_PC)
Address – 0x09h
DATA BIT
D7
D6
D5
D4
FIELD NAME
N/A
N/A
N/A
N/A
READ/WRITE
N/A
N/A
N/A
N/A
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
(1)
D3
D2
D1
D0
R_PC[3:0] (1)
R_PC register can only be read or written to when R channel is in HOLD mode (R_EXEC[1:0] = 11b). In STANDBY mode R_PC can be
written to but not read. Value is effective after startup. Any change of the R_MODE[1:0] bits reset the R_PC value. For read access
device must be in NORMAL mode.
FIELD NAME
R_PC[3:0]
BIT DEFINITION
Red channel program counter
GREEN CHANNEL PROGRAM COUNTER REGISTER (G_PC)
Address – 0x0Ah
DATA BIT
D7
D6
D5
D4
D3
D2
D1
FIELD NAME
N/A
N/A
N/A
N/A
READ/WRITE
N/A
N/A
N/A
N/A
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
(1)
G_PC[3:0]
D0
(1)
G_PC register can only be read or written to when G channel is in HOLD mode (G_EXEC[1:0] = 11b). In STANDBY mode G_PC can be
written to but not read. Value is effective after startup. Any change of the G_MODE[1:0] bits reset the G_PC value. For read access
device must be in NORMAL mode.
FIELD NAME
G_PC[3:0]
BIT DEFINITION
Green channel program counter
BLUE CHANNEL PROGRAM COUNTER REGISTER (B_PC)
Address – 0x0Bh
DATA BIT
D7
D6
D5
D4
FIELD NAME
N/A
N/A
N/A
N/A
READ/WRITE
N/A
N/A
N/A
N/A
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
(1)
26
D3
D2
D1
D0
B_PC[3:0] (1)
B_PC register can only be read or written to when B channel is in HOLD mode (B_EXEC[1:0] = 11b). In STANDBY mode B_PC can be
written to but not read. Value is effective after startup. Any change of the B_MODE[1:0] bits reset the B_PC value. For read access
device must be in NORMAL mode.
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SLVSA68A – MARCH 2010 – REVISED JANUARY 2011
FIELD NAME
B_PC[3:0]
BIT DEFINITION
Blue channel program counter
STATUS AND INTERUPT REGISTER (STATUS)
Address – 0x0Ch
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
EXT_CLK_US
ED
R_INT
G_INT
B_INT
FIELD NAME
N/A
N/A
CP_STATUS[1:0]
READ/WRITE
N/A
N/A
R
R
R
R
R
R
RESET VALUE
0
0
0
0
0
0
0
0
FIELD NAME
BIT DEFINITION
Charge pump operating mode
00b – OFF
CP_STATUS[1:0]
01b – Forced 1x mode
10b – Forced 1.5x mode
11b – Power save
External clock selected
EXT_CLK _USED
0b - Internal 32-Hz clock selected
1b - External 32-kHz clock selected
R_INT
(1)
(1)
Red channel interrupt, set upon channel interrupt generation (END instruction), cleared on read
G_INT (1)
Green channel interrupt, set upon channel interrupt generation (END instruction), cleared on read
B_INT (1)
Blue channel interrupt, set upon channel interrupt generation (END instruction), cleared on read
Interrupt bits are cleared and INT output pin will go high-impedance (open drain output) after register read access.
RESET CONTROL REGISTER (RESET)
Address – 0x0Dh
DATA BIT
D7
D6
D5
D4
FIELD NAME
D3
D2
D1
D0
RESET[7:0]
READ/WRITE
W
W
W
W
W
W
W
W
RESET VALUE
0
0
0
0
0
0
0
0
FIELD NAME
BIT DEFINITION
RESET[7:0]
Forced reset state (reset all registers to default values). No I2C acknowledge will be generated when 0xFFh is written to
the RESET register. I2C acknowledge will be generated for any other pattern written to the register.
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GPO CONTROL REGISTER (GPO)
Address – 0x0Eh
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
ID
N/A
N/A
N/A
N/A
INT_AS_GPO
GPO
INT
READ/WRITE
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1
0
0
0
0
0
0
0
FIELD NAME
BIT DEFINITION
INT pin GPO function enable
INT_AS_GPO
0b – INT pin functions as interrupt pin
1b – INT pin functions as GPO
GPO value
GPO
0b – Output low
1b – Output high
INT value (when INT_AS_GPO is set to 1)
INT
0b – Output low
1b – Output high
ID
ID bit
PROGRAM MEMORY REGISTERS (PROGRAM MEMORY R, G, B)
Address – 0x10h to 0x2F in pairs (Red)
– 0x30h to 0x4F in pairs (Green)
– 0x50h to 0x6F in pairs (Blue)
NOTE
Each program command is composed of two consecutive bytes in the register space. The
most significant byte of the command is stored in the lower order address followed by the
least significant byte.
DATA BIT
D7
D6
D5
FIELD NAME
D4
D3
D2
D1
D0
CMD_Rn_H[7:0], CMD_Rn_L[7:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
FIELD NAME
BIT DEFINITION
CMD_Rn_H[7:0]
Red channel program command n, most significant byte; Address is 0x10h + 2n and 0 ≤ n ≤ 15. See program
commands section for details.
CMD_Rn_L[7:0]
Red channel program command n, least significant byte; Address is 0x11h + 2n and 0 ≤ N ≤ 15. See program
commands section for details.
DATA BIT
D7
D6
D5
READ/WRITE
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
FIELD NAME
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
0
0
0
0
CMD_Gn_H[7:0], CMD_Gn_L[7:0]
FIELD NAME
BIT DEFINITION
CMD_Gn_H[7:0]
Green channel program command n, most significant byte; Address is 0x30h + 2n and 0 ≤ n ≤ 15. See program
commands section for details.
CMD_Gn_L[7:0]
Green channel program command n, least significant byte; Address is 0x31h + 2n and 0 ≤ n ≤ 15. See program
commands section for details.
28
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DATA BIT
SLVSA68A – MARCH 2010 – REVISED JANUARY 2011
D7
D6
D5
FIELD NAME
D4
D3
D2
D1
D0
CMD_Bn_H[7:0], CMD_Bn_L[7:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
FIELD NAME
BIT DEFINITION
CMD_Bn_H[7:0]
Blue channel program command n, most significant byte; Address is 0x50h + 2n and 0 ≤ n ≤ 15. See program
commands section for details.
CMD_Bn_L[7:0]
Blue channel program command n, least significant byte; Address is 0x51h + 2n and 0 ≤ n ≤ 15. See program
commands section for details.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS68401C4YFFR
ACTIVE
DSBGA
YFF
20
Green (RoHS
& no Sb/Br)
Call TI
Level-1-260C-UNLIM
-30 to 85
TPS68402A0RHFR
ACTIVE
VQFN
RHF
24
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-30 to 85
68402
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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17-Jan-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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