TPS70351PWPR

TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 D Dual Output Voltages for Split-Supply D D D D D D D D D Applications Selectable Power Up Sequencing for DSP Applications (See TPS704xx for Independent Enabling of Each Output) Output Current Range of 1 A on Regulator 1 and 2 A on Regulator 2 Fast Transient Response Voltage Options Are 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable Outputs Open Drain Power-On Reset With 120-ms Delay Open Drain Power Good for Regulator 1 Ultralow 185 µA (typ) Quiescent Current 2 µA Input Current During Standby Low Noise: 78 µVRMS Without Bypass Capacitor Quick Output Capacitor Discharge Feature Two Manual Reset Inputs 2% Accuracy Over Load and Temperature Undervoltage Lockout (UVLO) Feature 24-Pin PowerPAD TSSOP Package Thermal Shutdown Protection D D D D D D PWP PACKAGE (TOP VIEW) description 1 2 3 4 5 6 7 8 9 10 11 12 TPS703xx family of devices are designed to GND/HEATSINK VIN1 provide a complete power management solution VIN1 for TI DSP, processor power, ASIC, FPGA, and NC digital applications where dual output voltage MR2 regulators are required. Easy programmability of MR1 the sequencing function makes this family ideal EN for any TI DSP applications with power SEQ sequencing requirement. Differentiated features, GND such as accuracy, fast transient response, SVS VIN2 supervisory circuit (power on reset), manual reset VIN2 inputs, and enable function, provide a complete GND/HEATSINK system solution. 24 23 22 21 20 19 18 17 16 15 14 13 GND/HEATSINK VOUT1 VOUT1 VSENSE1/FB1 NC PG1 RESET NC VSENSE2/FB2 VOUT2 VOUT2 GND/HEATSINK NC – No internal connection TPS70351 PWP 5V 0.22 µF 250 kΩ PG1 PG1 MR2 MR2 >2 V 2 V EN 250 kΩ RESET RESET MR1 EN 2 V 2.5 V then VImax = 6 V, VImin = VO + 1 V: Line regulation (mV) + ǒ%ńVǓ V O ǒVImax * ǒVO ) 1ǓǓ 100 3. IO = 1 mA to 1 A for regulator 1 and 1 mA to 2 A for regulator 2. POST OFFICE BOX 655303 1000 • DALLAS, TEXAS 75265 9 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 electrical characteristics over recommended operating junction temperature (TJ = –40°C to 125°C) VIN1 or VIN2 = VOUTX(nom) + 1 V, IOUTX = 1 mA, EN = 0, COUT1 = 22 µF, COUT2 = 47 µF(unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX 1.0 1.3 92% 95% 98% UNIT PG terminal Minimum input voltage for valid PG I(PG) = 300 µA, Trip threshold voltage VO decreasing Hysteresis voltage Measured at VO tr(PG1) Rising edge deglitch Output low voltage VI = 2.7 V, Leakage current V(PG1) = 6 V V(PG1) ≤ 0.8 V I(PG) = 1 mA V VO 0.5% VO 30 µs 0.15 0.4 V 1 µA EN terminal High-level EN input voltage 2 V Low-level EN input voltage Input current (EN) –1 0.7 V 1 µA SEQ terminal High-level SEQ input voltage 2 V Low-level SEQ input voltage 0.7 SEQ pullup current source V µA 6 MR1 / MR2 terminals High-level input voltage 2 V Low-level input voltage 0.7 Pullup current source V µA 6 VOUT2 terminal VOUT2 UV comparator – positive-going input threshold voltage of VOUT1 UV comparator 80% VO VOUT2 UV comparator – hysteresis VOUT2 UV comparator – falling edge deglitch VSENSE2 decreasing below threshold Peak output current 2 ms pulse width Discharge transistor current VOUT2 = 1.5 V 83% VO 86% VO V 3% VO mV 140 µs 3 A 7.5 mA VOUT1 terminal VOUT1 UV comparator – positive-going input threshold voltage of VOUT1 UV comparator 80% VO VOUT1 UV comparator – hysteresis VOUT1 UV comparator – falling edge deglitch Dropout voltage (see Note 4) 83% VO 86% VO V 3% VO mV VSENSE1 decreasing below threshold 140 µs IO = 1 A, 160 VIN1 = 3.2 V, IO = 1 A, TJ = 25°C VIN1 = 3.2 V 250 mV Peak output current 2 ms pulse width 1.2 A Discharge transistor current VOUT1 = 1.5 V 7.5 mA VIN1 / VIN2 terminal UVLO threshold 2.3 UVLO hysteresis 2.65 V 110 mV 1 µA FB1 / FB2 terminals Input current – TPS70302 FB = 1.8 V NOTE 4: Input voltage(VIN1 or VIN2) = VO(Typ) – 100 mV. For the 1.5-V, 1.8-V and 2.5-V regulators, the dropout voltage is limited by input voltage range. The 3.3 V regulator input voltage is set to 3.2 V to perform this test. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VO Output voltage PSRR zo vs Output current 1, 2 vs Junction temperature 3, 4 Ground current vs Junction temperature Power supply rejection ratio vs Frequency 6–9 Output spectral noise density vs Frequency 10 – 13 Output impedance vs Frequency 14 – 17 vs Temperature 18, 19 vs Input voltage 20, 21 Dropout voltage 5 Load transient response 22, 23 Line transient response VO 24, 25 Output voltage and enable voltage vs Time (start-up) 26, 27 Equivalent series resistance vs Output current 29 – 32 TPS70351 TPS70351 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 3.33 1.815 VIN1 = 4.3 V TJ = 25°C VOUT1 3.31 3.30 3.29 3.28 3.27 VIN2 = 2.8V TJ = 25°C VOUT2 1.81 VO – Output Voltage – V VO – Output Voltage – V 3.32 1.805 1.8 1.795 1.79 1.785 0 200 400 600 800 IO – Output Current – mA 1000 0 500 1000 1500 2000 IO – Output Current – mA Figure 1 Figure 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS TPS70351 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 3.354 VIN1 = 4.3 V VOUT1 VO – Output Voltage – V 3.334 3.314 IO = 1 mA 3.294 IO = 1 A 3.274 3.254 3.234 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 3 TPS70351 TPS70351 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE GROUND CURRENT vs JUNCTION TEMPERATURE 210 1.834 Regulator 1 and Regulator 2 VIN2 = 2.8 V VOUT2 200 1.814 1.804 1.794 Ground Current – µ A VO – Output Voltage – V 1.824 IO = 2 A IO = 1 mA IOUT1 = 1 mA IOUT2 = 1 mA 190 170 1.784 160 1.774 1.764 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C 150 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 4 12 IOUT1 = 1 A IOUT2 = 2 A 180 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS TPS70351 TPS70351 POWER SUPPLY REJECTION RATIO vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY 0 VIN1 = 4.3 V VOUT1 = 3.3 V IO = 10 mA Co = 22 µF –20 –30 PSRR – Power Supply Rejection Ratio – dB PSRR – Power Supply Rejection Ratio – dB –10 –40 –50 –60 –70 –80 –90 10 100 1k 10 k 100 k –10 –20 VIN1 = 4.3 V VOUT1 = 3.3 V IO = 1 A Co = 22 µF –30 –40 –50 –60 –70 –80 –90 –100 10 1M 100 f – Frequency – Hz TPS70351 POWER SUPPLY REJECTION RATIO vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY PSRR – Power Supply Rejection Ratio – dB PSRR – Power Supply Rejection Ratio – dB 1M 0 VIN2 = 2.8 V VOUT2 = 1.8 V IO = 10 mA Co = 47 µF –30 –40 –50 –60 –70 –80 –90 –100 10 100 k TPS70351 0 –20 10 k Figure 7 Figure 6 –10 1k f – Frequency – Hz 100 1k 10 k 100 k 1M –10 –20 VIN2 = 2.8 V VOUT2 = 1.8 V IO = 2 A Co = 47 µF –30 –40 –50 –60 –70 –80 –90 –100 10 100 1k 10 k 100 k 1M f – Frequency – Hz f – Frequency – Hz Figure 9 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 1 0.1 0.01 100 1k 10 k f – Frequency – Hz VIN2 = 2.8 V VOUT2 = 1.8 V COUT2 = 47 µF IO = 10 mA TJ = 25°C Hz VIN1 = 4.3 V VOUT1 = 3.3 V COUT1 = 22 µF IO = 10 mA TJ = 25°C Output Spectral Noise Density – µV/ Output Spectral Noise Density – µV/ Hz 10 1 0.1 0.01 100 100 k 1k 10 k f – Frequency – Hz Figure 10 Figure 11 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 VIN1 = 4.3 V VOUT1 = 3.3 V COUT1 = 22 µF IO = 1 A TJ = 25°C Output Spectral Noise Density – µV/ Hz Output Spectral Noise Density – µV/ Hz 10 1 0.1 0.01 100 1k 10 k f – Frequency – Hz 100 k VIN2 = 2.8 V VOUT2 = 1.8 V COUT2 = 47 µF IO = 2 A TJ = 25°C 1 0.1 0.01 100 Figure 12 14 100 k 1k 10 k f – Frequency – Hz Figure 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 k TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY VOUT1 = 3.3 V IO = 1 A Co = 22 µF Z O – Output Impedance – Ω Z O – Output Impedance – Ω VOUT1 = 3.3 V IO = 10 mA Co = 22 µF 1 0.1 0.01 10 100 1k 10 k 100 k 1M 1 0.1 0.01 10 10 M 100 f – Frequency – Hz Figure 15 10 M 1M 10 M VOUT2 = 1.8 V IO = 2 A Co = 47 µF 1 0.1 0.01 1k 1M OUTPUT IMPEDANCE vs FREQUENCY Z O – Output Impedance – Ω Z O – Output Impedance – Ω 100 k Figure 14 VOUT2 = 1.8 V IO = 10 mA Co = 47 µF 100 10 k f – Frequency – Hz OUTPUT IMPEDANCE vs FREQUENCY 10 1k 10 k 100 k 1M 10 M 1 0.1 0.01 10 100 1k 10 k 100 k f – Frequency – Hz f – Frequency – Hz Figure 16 Figure 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS TPS70351 TPS70351 DROPOUT VOLTAGE vs TEMPERATURE DROPOUT VOLTAGE vs TEMPERATURE 25 250 VOUT1 VIN1 = 3.2 V VOUT1 VIN1 = 3.2 V 20 200 Dropout Voltage – mV Dropout Voltage – mV IO = 1 A 150 100 IO = 100 mA 15 10 5 50 IO = 1 mA IO = 10 mA 0 –40 –25 –10 5 20 35 50 65 80 T – Temperature – °C 0 –40 –25 –10 95 110 125 TPS70302 TPS70302 DROPOUT VOLTAGE vs INPUT VOLTAGE DROPOUT VOLTAGE vs INPUT VOLTAGE 300 300 VOUT1 IO = 1 A VOUT2 IO = 2 A 250 TJ = 125°C Dropout Voltage – mV Dropout Voltage – mV 250 200 TJ = 25°C 150 100 TJ= – 40°C 50 TJ = 125°C 200 TJ = 25°C 150 TJ= – 40°C 100 50 3 3.5 4 4.5 5 5.5 0 2.5 VI – Input Voltage – V 3 3.5 4 Figure 21 POST OFFICE BOX 655303 4.5 VI – Input Voltage – V Figure 20 16 95 110 125 Figure 19 Figure 18 0 2.5 5 20 35 50 65 80 T – Temperature – °C • DALLAS, TEXAS 75265 5 5.5 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS LOAD TRANSIENT RESPONSE IO – Output Current – A VIN1 = 4.3 V VOUT1 = 3.3 V Co = 22 µF TJ = 25°C 1 0.5 0 50 ∆ VO – Change in Output Voltage – mV ∆ VO – Change in Output Voltage – mV IO – Output Current – A LOAD TRANSIENT RESPONSE 0 –50 –100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOUT2 = 1.8 V IO = 2 A Co = 47 µF TJ = 25°C 2 1 0 50 0 –50 0 2 0.2 0.4 0.6 0.8 Figure 22 VI – Input Voltage – V 4.3 50 0 –50 –100 20 40 60 80 1.4 1.6 1.8 2 LINE TRANSIENT RESPONSE ∆ VO – Change in Output Voltage – mV VI – Input Voltage – V ∆ VO – Change in Output Voltage – mV VOUT1 = 3.3 V IO = 1 A Co = 22 µF 0 1.2 Figure 23 LINE TRANSIENT RESPONSE 5.3 1 t – Time – ms t – Time – ms 100 120 140 160 180 200 VOUT2 = 1.8 V IO = 2 A Co = 47 µF 3.8 2.8 100 0 –100 –200 0 20 t – Time – µs 40 60 80 100 120 140 160 180 200 t – Time – µs Figure 25 Figure 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) VO – Output Voltage– V 4 3 VOUT1 = 3.3 V IO = 1 A Co = 22 µF VIN1 = 4.3 V SEQ = Low 2 1 0 Enable Voltage – V Enable Voltage – V VO – Output Voltage– V OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 t – Time (Start-Up) – ms 1.6 1.8 2 2 1 0 VOUT2 = 1.8 V IO = 2 A Co = 47 µF VIN2 = 2.8 V SEQ = High 5 0 0 0.2 0.4 Figure 26 VI 0.6 0.8 1 1.2 1.4 t – Time (Start-Up) – ms 1.6 1.8 2 Figure 27 To Load IN OUT + EN RL Co GND ESR Figure 28. Test Circuit for Typical Regions of Stability † Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR)† vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE (ESR)† vs OUTPUT CURRENT 10 VOUT1 = 3.3 V Co = 22 µF ESR – Equivalent Series Resistance – Ω ESR – Equivalent Series Resistance – Ω 10 REGION OF INSTABILITY 1 0.1 50 mΩ 0.01 VOUT1 = 3.3 V Co = 220 µF REGION OF INSTABILITY 1 0.1 15 mΩ 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 IO – Output Current – A Figure 29 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 30 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR)† vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE (ESR)† vs OUTPUT CURRENT 10 10 REGION OF INSTABILITY ESR – Equivalent Series Resistance – Ω REGION OF INSTABILITY ESR – Equivalent Series Resistance – Ω 0.3 IO – Output Current – A VOUT2 = 1.8 V Co = 47 µF 1 0.1 50 mΩ 0.01 VOUT2 = 1.8 V Co = 680 µF 1 0.1 15 mΩ 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 IO – Output Current – A IO – Output Current – A Figure 31 Figure 32 † Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 THERMAL INFORMATION thermally enhanced TSSOP-24 (PWP – PowerPad) The thermally enhanced PWP package is based on the 24-pin TSSOP, but includes a thermal pad [see Figure 33(c)] to provide an effective thermal contact between the IC and the PWB. Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO220-type packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages, however, suffer from several shortcomings: they do not address the very low profile requirements (< 2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough to accommodate increasing integration. On the other hand, traditional low-power surface-mount packages require power-dissipation derating that severely limits the usable range of many high-performance analog circuits. The PWP package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal performance comparable to much larger power packages. The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending) and manufacturing technique to provide the user with direct connection to the heat-generating IC. When this pad is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultrathin, fine-pitch, surface-mount package can be reliably achieved. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) Figure 33. Views of Thermally Enhanced PWP Package Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface), which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference Figure 35(a), 8 cm2 of copper heat sink and natural convection). Increasing the heat-sink size increases the power dissipation range for the component. The power dissipation limit can be further improved by adding airflow to a PWB/IC assembly (see Figures 34 and 35). The line drawn at 0.3 cm2 in Figures 34 and 35 indicates performance at the minimum recommended heat-sink size, illustrated in Figure 36. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 THERMAL INFORMATION thermally enhanced TSSOP-24 (PWP – PowerPad) (continued) The thermal pad is directly connected to the substrate of the IC, which for the TPS703xx series is a secondary electrical connection to device ground. The heat-sink surface that is added to the PWP can be a ground plane or left electrically isolated. In TO220-type surface-mount packages, the thermal connection is also the primary electrical connection for a given terminal which is not always ground. The PWP package provides up to 24 independent leads that can be used as inputs and outputs (Note: leads 1, 12, 13, and 24 are internally connected to the thermal pad and the IC substrate). THERMAL RESISTANCE vs COPPER HEAT-SINK AREA 150 Natural Convection R θ JA – Thermal Resistance – ° C/W 125 50 ft/min 100 ft/min 100 150 ft/min 200 ft/min 75 50 250 ft/min 300 ft/min 25 0 0.3 1 2 3 4 5 6 7 8 Copper Heat-Sink Area – cm2 Figure 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 THERMAL INFORMATION thermally enhanced TSSOP-24 (PWP – PowerPad) (continued) 3.5 3.5 TA = 55°C 300 ft/min 3 PD – Power Dissipation Limit – W PD – Power Dissipation Limit – W TA = 25°C 150 ft/min 2.5 2 Natural Convection 1.5 1 0.5 0 3 300 ft/min 2.5 2 150 ft/min 1.5 Natural Convection 1 0.5 0 0.3 2 4 6 0 8 Copper Heat-Sink Size – cm2 0 0.3 2 4 6 Copper Heat-Sink Size – cm2 (a) (b) 3.5 TA = 105°C PD – Power Dissipation Limit – W 3 2.5 2 1.5 150 ft/min 300 ft/min 1 Natural Convection 0.5 0 0 0.3 2 4 6 8 Copper Heat-Sink Size – cm2 (c) Figure 35. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 THERMAL INFORMATION thermally enhanced TSSOP-24 (PWP – PowerPad) (continued) Figure 36 is an example of a thermally enhanced PWB layout for use with the new PWP package. This board configuration was used in the thermal experiments that generated the power ratings shown in Figure 34 and Figure 35. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. RθJA for this assembly is illustrated in Figure 34 as a function of heat-sink area. A family of curves is included to illustrate the effect of airflow introduced into the system. Heat-Sink Area 1 oz Copper Board thickness Board size Board material Copper trace/heat sink Exposed pad mounting 62 mils 3.2 in. × 3.2 in. FR4 1 oz 63/67 tin/lead solder Figure 36. PWB Layout (Including Copper Heatsink Area) for Thermally Enhanced PWP Package From Figure 34, RθJA for a PWB assembly can be determined and used to calculate the maximum power-dissipation limit for the component/PWB assembly, with the equation: P D(max) + T max * T J A R qJA(system) (1) where TJmax is the maximum specified junction temperature (150°C absolute maximum limit, 125°C recommended operating limit) and TA is the ambient temperature. PD(max) should then be applied to the internal power dissipated by the TPS703xx regulator. The equation for calculating total internal power dissipation of the TPS703xx is: P D(total) ǒ + V IN1 *V Ǔ OUT1 I OUT1 )V I ǒ Ǔ Q ) V *V IN2 OUT2 2 IN1 I OUT2 )V I IN2 Q 2 (2) Since the quiescent current of the TPS703xx is very low, the second term is negligible, further simplifying the equation to: P D(total) ǒ + V IN1 *V Ǔ OUT1 I OUT1 ǒ ) V IN2 *V Ǔ OUT2 I OUT2 (3) For the case where TA = 55°C, airflow = 200 ft /min, copper heat-sink area = 4 cm2, the maximum power-dissipation limit can be calculated. First, from Figure 34, we find the system RθJA is 50°C/W; therefore, the maximum power-dissipation limit is: P D(max) + T max * T ° J A + 125 °C * 55 C + TBD W °CńW R TBD qJA(system) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 (4) 23 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 THERMAL INFORMATION thermally enhanced TSSOP-24 (PWP – PowerPad) (continued) If the system implements a TPS703xx regulator, where VI = 5 V and IO = 800 mA, the internal power dissipation is: P D(total) ǒ + V + (4.3 * 3.3) IN1 *V Ǔ OUT1 I OUT1 0.8 ) (2.8 * 1.8) ǒ ) V IN2 *V Ǔ OUT2 I (5) OUT2 1 + 1.8 W Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the calculated limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing the input voltage or the load current. In either case, the above calculations should be repeated with the new system parameters. This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 2 oz. copper traces on 4-in × 4-in ground layer. Simultaneous and continuous operation of both regulator outputs at full load may exceed the power dissipation rating of the PWP package. mounting information The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted. Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The data included in Figures 34 and 35 is for soldered connections with voiding between 20% and 50%. The thermal analysis shows no significant difference resulting from the variation in voiding percentage. Figure 37 shows the solder-mask land pattern for the PWP package. The minimum recommended heat-sink area is also illustrated. This is simply a copper plane under the body extent of the package, including metal routed under terminals 1, 12, 13, and 24. Minimum Recommended Heat-Sink Area Location of Exposed Thermal Pad on PWP Package Figure 37. PWP Package Land Pattern 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 APPLICATION INFORMATION sequencing timing diagrams The following figures provide a timing diagram of how this device functions in different configurations. application conditions not shown in block diagram: VIN1 and VIN2 are tied to the same fixed input voltage greater than the VUVLO; SEQ is tied to logic low; PG1 is tied to MR2; MR1 is not used and is connected to VIN. TPS703xxPWP (Fixed Output Option) VI VIN1 0.22 µF 22 µF VSENSE1 explanation of timing diagrams: EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic low, when EN is taken to logic low, VOUT1 turns on. VOUT2 turns on after VOUT1 reaches 83% of its regulated output voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to PG1) are at logic high, RESET is pulled to logic high after a 120 ms delay. When EN is returned to logic high, both devices power down and both PG1 (tied to MR2) and RESET return to logic low. VOUT1 VOUT1 250 kΩ PG1 VIN2 0.22 µF >2 V EN EN 2 V 0.7 V (tied to MR2) goes to logic high. When both VOUT1 VSENSE2 2 V (tied to MR2) goes to logic high. When both VOUT1 VSENSE2 2 V 250 kΩ PG1 PG1 VIN2 DSP RESET RESET MR1 EN MR1 VIN 2 V 2.0 V OUT EN VO