Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
TPS717xx 低噪声、高带宽 PSRR、
、
低压降、150mA 线性稳压器
1 特性
•
•
1
•
•
•
•
•
3 说明
输入电压：+2.5V 至 +6.5V
提供多个输出版本：
– 固定输出电压范围：0.9V 至 5V
– 可调节输出电压范围为 0.9V 至 6.2V
超高 PSRR：
– 1kHz 时 70dB，100kHz 时 67dB，1MHz 时
45dB
出色的负载和线路瞬态响应
超低压降：150mA 时为 170mV（典型值）
低噪声：30μVRMS 典型值（100Hz 至 100kHz）
小型 5 引脚 SC-70、2mm × 2mm 晶圆级小外形无
引线 (WSON)-6 封装和 1.5mm × 1.5mm WSON-6
封装
2 应用
•
•
•
•
摄像机传感器电源
移动电话耳机
掌上电脑 (PDA) 和智能手机
无线 LAN， Bluetooth®
TPS717xx 系列低压降 (LDO)、低功耗线性稳压器采用
超小型 5 引脚小外形尺寸晶体管 (SOT) 封装，其具有
非常高的电源抑制比 (PSRR)，同时能够保持 45μA 的
超低接地电流。 该系列稳压器采用先进的双极 CMOS
(BiCMOS) 工艺和功率金属氧化物半导体场效应晶体管
(PMOSFET) 无源器件，可实现快速启动、超低噪声、
优异的瞬态响应以及出色的 PSRR 性能。 TPS717xx
器件与 1μF 陶瓷输出电容一起工作时可保持稳定，并
且使用了一个精确的电压基准和反馈环路，以在所有负
载、线路、过程和温度变化范围内实现至少 3% 的精
度。 该器件系列的额定温度范围为 TJ = -40°C 至
125°C，并且提供小型 SOT (SC70-5) 封装、带有散热
焊盘的
2mm × 2mm WSON-6 封装以及 1.5mm x 1.5mm
WSON-6 封装，非常适合小尺寸便携式设备（例如无
线手持设备和 PDA）。
器件信息(1)
器件型号
封装
TPS717xx
封装尺寸（标称值）
SC70 (5)
2.00mm × 1.25mm
WSON (6)
2.00mm x 2.00mm
WSON (6)
1.50mm x 1.50mm
(1) 如需了解所有可用封装和电压选项，请见数据表末尾的可订购
产品附录。
针对固定电压版本的典型应用电路
VIN
IN
PSRR 与频率间的关系
VOUT
OUT
80
TPS717xx
EN
VEN
GND
0.01 mF
(Optional)
150 mA
70
1 mF
Ceramic
NR
10 mA
60
PSRR (dB)
1 mF
Ceramic
50
40
75 mA
30
20
COUT = 1 mF
CNR = 10 nF
10
0
10
100
1k
100k
10k
Frequency (Hz)
1M
10M
Power-Supply Rejection Ratio (VIN - VOUT = 1 V)
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBVS068
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
13
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Applications ................................................ 16
8.3 Do's and Don'ts ...................................................... 18
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
10.3 Power Dissipation ................................................ 20
11 器件和文档支持 ..................................................... 22
11.1
11.2
11.3
11.4
11.5
器件支持 ...............................................................
文档支持 ...............................................................
商标 .......................................................................
静电放电警告.........................................................
术语表 ...................................................................
22
22
22
22
22
12 机械封装和可订购信息 .......................................... 22
4 修订历史记录
Changes from Revision G (April 2009) to Revision H
Page
•
Changed pin descriptions throughout Pin Functions table ..................................................................................................... 3
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 4
•
Changed load regulation typical specification from 120 µV to 70 µV to better reflect device performance .......................... 5
•
Changed condition for CNR = none for Vn parameter.............................................................................................................. 5
•
Changed Figure 1, Figure 2, Figure 3, and Figure 4: removed legend, added call-outs for clarity ....................................... 6
•
Changed titles of Figure 15, Figure 17, and Figure 25........................................................................................................... 7
•
Corrected input and output symbols in operational amplifiers in Functional Block Diagrams ............................................. 11
•
Changed Undervoltage Lockout (UVLO) section text: reworded for clarity.......................................................................... 13
•
Deleted Reverse Current Protection section ....................................................................................................................... 15
Changes from Revision F (February 2009) to Revision G
Page
•
Changed min and max specs for Output accuracy, VOUT ≥ 1.0V ........................................................................................... 5
2
Copyright © 2006–2015, Texas Instruments Incorporated
TPS717
www.ti.com.cn
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
5 Pin Configuration and Functions
DCK Package
SC70-5
(Top View)
IN
1
GND
2
EN
3
5
4
DRV Package
2-mm × 2-mm WSON
(Top View)
OUT
NR/FB
(1)
OUT
1
NR/FB
2
GND
3
GND
6
IN
5
N/C
4
EN
(1)
N/C = No connection
DSE Package
1.5-mm × 1.5-mm WSON
(Top View)
OUT
1
6
IN
GND
2
5
N/C
NR/FB
3
4
EN
(1)
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DCK
DRV
DSE
EN
3
4
4
I
Driving the enable pin (EN) above VEN(high) turns on the regulator.
Driving this pin below VEN(low) puts the regulator into standby mode,
thereby disabling the output and reducing operating current.
FB
4
2
3
I
Adjustable voltage version only. The voltage at this pin is fed to the
error amplifier. A resistor divider from OUT to FB sets the output
voltage when in regulation.
GND
2
3
2
—
IN
1
6
6
I
N/C
—
5
5
—
Not connected. This pin can be tied to ground to improve thermal
dissipation.
NR
4
2
3
—
Fixed voltage versions only. The noise reduction capacitor filters the
noise generated by the internal band gap, thus lowering output noise.
OUT
5
1
1
O
This pin is the regulated output voltage. A minimum capacitance of
1 μF is required for stability from this pin to ground.
Copyright © 2006–2015, Texas Instruments Incorporated
Ground
Input to the device. A 0.1-μF to 1-μF capacitor is recommended for
better performance.
3
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted), all voltages are with respect to GND (1)
Voltage
MIN
MAX
UNIT
VIN
–0.3
7
V
VFB
–0.3
3.6
V
VNR
–0.3
3.6
V
VEN
–0.3
VIN + 0.3 V (2)
V
VOUT
–0.3
7
V
Current
IOUT
Internally limited
Continuous total power dissipation
PDISS
See Thermal Information
Operating junction temperature
TJ
–55
150
°C
Storage temperature
Tstg
–55
150
°C
(1)
(2)
A
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VEN absolute maximum rating is VIN + 0.3 V or 7 V, whichever is greater.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
6.5
UNIT
VIN
Input voltage
2.5
V
VOUT
Output voltage
0.9
5
IOUT
Output current
0
150
VEN
Enable voltage
0
VIN
V
COUT
Output capacitor
1
100
µF
TJ
Junction temperature
–40
125
°C
V
mA
6.4 Thermal Information
TPS717xx
THERMAL METRIC (1)
DCK
DRV
DSE
5 PINS
6 PINS
6 PINS
190.5
RθJA
Junction-to-ambient thermal resistance
279.2
71.1
RθJC(top)
Junction-to-case (top) thermal resistance
57.5
96.5
94.9
RθJB
Junction-to-board thermal resistance
74.1
40.5
149.3
ψJT
Junction-to-top characterization parameter
0.8
2.7
6.4
ψJB
Junction-to-board characterization parameter
73.1
40.9
152.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
10.7
n/a
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2006–2015, Texas Instruments Incorporated
TPS717
www.ti.com.cn
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
6.5 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater;
IOUT = 0.5 mA, VEN = VIN, COUT = 1.0 μF, CNR = 0.01 μF, unless otherwise noted. For TPS71701, VOUT = 2.8 V.
Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
(1)
VIN
Input voltage range
VFB
Internal reference (TPS71701)
VOUT
VOUT
Output voltage range
V
0.810
V
V
5.0
(TPS71701)
0.9
6.5 – VDO
Output accuracy
Nominal
TJ = 25°C
Output accuracy
(VOUT < 1.0 V)
Over VIN, IOUT,
Temp (2)
VOUT + 0.5 V ≤ VIN ≤ 6.5 V
0 mA ≤ IOUT ≤ 150 mA
–30
+30
Output accuracy
(VOUT ≥ 1.0 V)
Over VIN, IOUT,
Temp (2)
VOUT + 0.5 V ≤ VIN ≤ 6.5 V
0 mA ≤ IOUT ≤ 150 mA
–3.0%
+3.0%
(1)
±2.5
VOUT(nom) + 0.5 V ≤ VIN ≤ 6.5 V,
IOUT = 5 mA
Load regulation
0 mA ≤ IOUT ≤ 150 mA
VDO
Dropout voltage (3)
(VIN = VOUT(nom) – 0.1 V)
IOUT = 150 mA
ILIM (fixed)
Output current limit (fixed output)
VOUT = 0.9 × VOUT(nom)
ILIM (adjustable)
Output current limit (TPS71701)
VOUT = 0.9 × VOUT(nom)
Ground pin current
ISHDN
Shutdown current (IGND)
IFB
Feedback pin current (TPS71701)
Power-supply rejection ratio
Output noise voltage
Startup time
UNIT
V
mV
mV
125
µV/V
70
µV/mA
170
300
mV
200
325
575
mA
200
325
575
mA
IOUT = 0.1 mA
45
80
μA
IOUT = 150 mA
100
VEN ≤ 0.4 V,
TJ = –40°C to
85°C
2.5 V ≤ VIN < 4.5 V
0.20
4.5 V ≤ VIN ≤ 6.5 V
0.90
0.02
VIN = 3.8 V,
VOUT = 2.8 V,
IOUT = 150 mA
μA
1.5
μA
μA
1.0
μA
f = 100 Hz
70
dB
f = 1 kHz
70
dB
f = 10 kHz
67
dB
f = 100 kHz
67
dB
f = 1 MHz
tSTR
6.5
0.800
0.9
ΔVOUT(ΔIOUT)
Vn
MAX
(TPS717xx)
Line regulation
PSRR
TYP
2.5
0.790
ΔVOUT(ΔVIN)
IGND
MIN
45
μVRMS
CNR = none
VOUT = 90%
VOUT(nom),
RL = 19 Ω,
COUT = 1 μF
0.9 V ≤ VOUT ≤ 1.6V, CNR
= 0.001 μF
0.700
1.6 V < VOUT < VMAX,
CNR = 0.01 μF
0.160
CNR = 0.001 μF
dB
95 × VOUT
BW = 100 Hz to
100 kHz,
VIN = 3.8 V,
VOUT = 2.8 V,
IOUT = 10 mA
25 × VOUT
μVRMS
CNR = 0.01 μF
12.5 × VOUT
μVRMS
CNR = 0.1 μF
11.5 × VOUT
μVRMS
VIN ≤ 5.5 V
ms
ms
(4)
V
1.25
6.5
V
0
0.4
V
0.02
1.0
μA
2.45
2.49
1.2
6.5
VEN(high)
Enable high (enabled)
VEN(low)
Enable low (shutdown)
IEN(high)
Enable pin current, enabled
EN = 6.5 V
Undervoltage lockout
VIN rising
Hysteresis
VIN falling
150
mV
Shutdown, temperature increasing
160
°C
Reset, temperature decreasing
140
UVLO
Tsd
Thermal shutdown temperature
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
5.5 V < VIN ≤ 6.5 V
2.41
–40
V
°C
125
°C
Minimum VIN = VOUT + VDO or 2.5 V, whichever is greater.
Does not include external resistor tolerances.
VDO is not measured for devices with VOUT(nom) < 2.6 V because the minimum VINis 2.5 V.
Maximum VEN(high) = VIN + 0.3 or 6.5 V, whichever is smaller.
Copyright © 2006–2015, Texas Instruments Incorporated
5
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
www.ti.com.cn
6.6 Typical Characteristics
50
50
40
40
30
30
20
20
DVOUT (mV)
DVOUT (mV)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT =
0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701,) VOUT = 2.8 V.
Typical values are at TA = 25°C.
10
-40°C
0
25°C
-10
-20
25°C
85°C
10
0
-10
-40°C
125°C
-20
-30
-30
85°C
-40
-40
125°C
-50
0
50
-50
0
150
100
1
3
2
5
4
IOUT (mA)
IOUT (mA)
Figure 2. Load Regulation Under Light Loads
Figure 1. Load Regulation
1.0
3.0
0.8
2.0
0.6
-40°C
0.2
0
85°C
125°C
-0.2
1.0
DVOUT (%)
DVOUT (%)
0.4
85°C
25°C
-40°C
0
-1.0
-0.4
125°C
25°C
-0.6
-2.0
-0.8
-3.0
-1.0
3.5
2.5
4.5
VIN (V)
5.5
2.5
6.5
Figure 3. Line Regulation (IOUT = 5 mA)
3.5
4.5
VIN (V)
5.5
6.5
Figure 4. Line Regulation (IOUT = 150 mA)
250
2.0
TA = 125°C
1.5
200
IOUT = 5mA
0.5
0
-0.5
-1.0
IOUT = 100mA
VDO (mV)
DVOUT (%)
1.0
150
TA = 85°C
100
TA = 25°C
50
IOUT = 150mA
TA = -40°C
-1.5
-2.0
0
-40 -25 -10
5
20
35 50
TJ (°C)
65
80
95 110 125
Figure 5. Output Voltage vs Temperature
6
0
50
100
150
IOUT (mA)
Figure 6. Dropout Voltage vs Output Current
Copyright © 2006–2015, Texas Instruments Incorporated
TPS717
www.ti.com.cn
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT =
0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701,) VOUT = 2.8 V.
Typical values are at TA = 25°C.
150
300
VOUT = 2.8 V
IOUT = 150 mA
250
120
IOUT = 150 mA
150
IGND (mA)
VDO (mV)
200
90
60
100
30
50
IOUT = 10 mA
IOUT = 100 mA
0
0
-40 -25 -10
5
20
35 50
TA (°C)
65
80
2.5
95 110 125
Figure 7. Dropout Voltage vs Temperature
3.5
5.5
4.5
VIN (V)
6.5
Figure 8. Ground Pin Current vs Input Voltage
150
150
120
120
90
90
IGND (mA)
IGND (mA)
IOUT = 150 mA
60
30
60
30
0
IOUT = 100 mA
0
0
100
50
150
-40 -25 -10
5
IOUT (mA)
Figure 9. Ground Pin Current vs Output Current
20
35 50
TA (°C)
65
80
95 110 125
Figure 10. Ground Pin Current vs Temperature (Enabled)
5
600
VEN = 0.4 V
TA = -40°C
500
3
IGND (mA)
IGND (mA)
4
2
TA = 25°C
TA = 85°C
400
VIN = 4.5 V
VIN = 6.5 V
300
1
TA = 125°C
VIN = 3.3 V
0
200
-40 -25 -10
5
20
35 50
TA (°C)
65
80
95 110 125
Figure 11. Ground Pin Current vs Temperature (Disabled)
Copyright © 2006–2015, Texas Instruments Incorporated
2.5
3.5
4.5
VIN (V)
5.5
6.5
Figure 12. Current Limit vs Input Voltage
7
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
www.ti.com.cn
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT =
0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701,) VOUT = 2.8 V.
Typical values are at TA = 25°C.
80
80
150mA
70
10mA
60
50
PSRR (dB)
PSRR (dB)
60
40
75mA
30
20
75mA
150mA
50
40
30
20
COUT = 1mF
CNR = 10nF
10
COUT = 1mF
CNR = 10nF
10
0
0
10
100
1k
100k
10k
Frequency (Hz)
1M
10M
10
100
1k
100k
10k
Frequency (Hz)
10M
1M
Figure 13. Power-Supply Ripple Rejection vs Frequency
(VIN – VOUT = 1 V)
Figure 14. Power-Supply Ripple Rejection vs Frequency
(VIN – VOUT = 0.5 V)
80
80
70
70
10mA
60
50
10mA
60
75mA
PSRR (dB)
PSRR (dB)
10mA
70
40
150mA
30
20
50
40
150mA
30
20
COUT = 1mF
CNR = 10nF
10
0
10
100
1k
100k
10k
Frequency (Hz)
1M
COUT = 10mF
CNR = 10nF
10
0
10M
10
Figure 15. Power-Supply Ripple Rejection vs Frequency in
Dropout Conditions (VIN – VOUT = 0.25 V)
100
1k
100k
10k
Frequency (Hz)
10M
1M
Figure 16. Power-Supply Ripple Rejection vs Frequency
(VIN – VOUT = 1 V)
80
80
70
70
10mA
60
50
50
PSRR (dB)
PSRR (dB)
10mA
60
40
150mA
30
20
150mA
30
20
COUT = 10mF
CNR = 10nF
10
0
COUT = 10mF
CNR = 0nF
10
0
10
100
1k
100k
10k
Frequency (Hz)
1M
10M
Figure 17. Power-Supply Ripple Rejection vs Frequency in
Dropout Conditions (VIN – VOUT = 0.25 V)
8
40
10
100
1k
100k
10k
Frequency (Hz)
1M
10M
Figure 18. Power-Supply Ripple Rejection vs Frequency
(VIN – VOUT = 1 V)
Copyright © 2006–2015, Texas Instruments Incorporated
TPS717
www.ti.com.cn
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT =
0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701,) VOUT = 2.8 V.
Typical values are at TA = 25°C.
80
80
1kHz
70
10kHz
100kHz
50
1MHz
40
30
20
60
40
1MHz
30
IOUT = 75mA
COUT = 1mF
CNR = 10nF
10
0
0
0
0.5
2.5
1.5
2.0
VIN - VOUT (V)
1.0
3.0
3.5
4.0
0
Figure 19. Power-Supply Ripple Rejection vs (VIN – VOUT)
60
10kHz
50
40
1MHz
30
20
IOUT = 150mA
COUT = 1mF
CNR = 10nF
10
0
0
0.5
2.5
1.5
2.0
VIN - VOUT (V)
1.0
3.0
3.5
3.5
4.0
IOUT = 10mA
10
8
6
4
2
0
100
10
COUT = 1mF
6
4
2
0
10k
1k
Frequency (Hz)
Figure 23. Output Spectral Noise Density vs
Output Capacitance
Copyright © 2006–2015, Texas Instruments Incorporated
10k
1k
100k
Figure 22. Output Spectral Noise Density vs
Output Current
100k
Output Spectral Noise Density (mV/ÖHz)
COUT = 10mF
COUT = 1mF
CNR = 10nF
Frequency (Hz)
IOUT = 10mA
CNR = 10nF
14
100
3.0
12
4.0
16
8
2.5
1.5
2.0
VIN - VOUT (V)
IOUT = 150mA
14
Figure 21. Power-Supply Ripple Rejection vs (VIN – VOUT)
12
1.0
16
1kHz
100kHz
70
0.5
Figure 20. Power-Supply Ripple Rejection vs (VIN – VOUT)
Output Noise Density (mV/ÖHz)
80
PSRR (dB)
50
20
IOUT = 10mA
COUT = 1mF
CNR = 10nF
10
10kHz
100kHz
PSRR (dB)
PSRR (dB)
60
Output Noise Density (mV/ÖHz)
1kHz
70
30
IOUT = 10mA
COUT = 1mF
25
20
15
10
CNR = 0nF
CNR = 10nF
CNR = 1nF
CNR = 100nF
5
0
100
10k
1k
100k
Frequency (Hz)
Figure 24. Output Spectral Noise Density vs
Noise Reduction
9
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
www.ti.com.cn
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT =
0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701,) VOUT = 2.8 V.
Typical values are at TA = 25°C.
50
300
IOUT = 10mA
COUT = 1mF
270
40
Total Noise (mVRMS)
240
Total Noise (mVRMS)
VOUT = 2.8V, CNR = 10nF
VOUT = 1.3V, CNR = 1nF
45
210
180
150
120
90
35
30
25
20
15
60
10
30
5
0
0
0
10
1
0
100
5
CNR (nF)
Figure 25. Total Output Noise vs Noise Reduction Capacitor
10
15
COUT (mF)
20
25
Figure 26. Total Output Noise vs Output Capacitance
VIN = 3.3 V
COUT = 1 mF
10 mV/div
VOUT
dVIN
= 1 V/ms
dt
50 mV/div
COUT = 1 mF
VOUT
6.5 V
1 V/div
150 mA
3.3 V
VIN
40 mV/div
Figure 27. Line Transient Response
COUT = 10mF
1V/div
Figure 28. Load Transient Response
VOUT
VIN
IOUT = 150 mA
6
5
VOUT
Volts
COUT = 1mF
4
3
VOUT
2
1V/div
1
6.5V
VIN
0
0V
50ms/div
Figure 29. Turn-On Response
10
IOUT
100 ms/div
100 ms/div
4V/div
1 mA
50 ms/div
Figure 30. Power-Up and Power-Down
Copyright © 2006–2015, Texas Instruments Incorporated
TPS717
www.ti.com.cn
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
7 Detailed Description
7.1 Overview
The TPS717xx family of low-dropout (LDO) regulators combines the high performance required by many RF and
precision analog applications with ultra-low current consumption. High PSRR is provided by a high-gain, highbandwidth error loop with good supply rejection with very low headroom (VIN – VOUT). Fixed voltage versions
provide a noise reduction pin to bypass noise generated by the band-gap reference and to improve PSRR. A
quick-start circuit fast-charges this capacitor at startup. The combination of high performance and low ground
current also make the TPS717xx family of devices an excellent choice for battery-powered applications. All
versions have thermal and overcurrent protection.
7.2 Functional Block Diagrams
OUT
IN
2.5 mA
Current
Limit
EN
Thermal
Shutdown
UVLO
Quick-Start
1.20-V
Band Gap
VOUT > 1.6 V
NR
360 kW
0.8 V
250 kW
VOUT £ 1.6 V
640 kW
GND
Figure 31. Fixed Voltage Versions
Copyright © 2006–2015, Texas Instruments Incorporated
11
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
www.ti.com.cn
Functional Block Diagrams (continued)
OUT
IN
Current
Limit
EN
Thermal
Shutdown
3.3 MW
UVLO
1.20-V
Band Gap
360 kW
FB
0.8 V
250 kW
640 kW
GND
Figure 32. Adjustable Voltage Version
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS717xx internal current limit helps protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, do
not operate the device in a current-limit state for extended periods of time.
The PMOS pass element in the TPS717xx has a built-in body diode that conducts current when the voltage at
OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting may be appropriate.
7.3.2 Shutdown
The enable pin (EN) is active high and compatible with standard and low voltage, TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to IN.
7.3.3 Startup and Noise Reduction Capacitor
Fixed voltage versions of the TPS717xx use a quick-start circuit to fast-charge the noise reduction capacitor,
CNR, if present (see Figure 31). This circuit allows the combination of very low output noise and fast start-up
times. The NR pin is high impedance, so a low-leakage CNR capacitor must be used; most ceramic capacitors
are appropriate in this configuration.
Note that for fastest startup, apply VIN first, then the enable pin (EN) driven high. If EN is tied to IN, startup is
somewhat slower. Refer to Figure 29 in Typical Characteristics. The quick-start switch is closed for approximately
135 μs. To ensure that CNR is fully charged during the quick-start time, use a 0.01-μF or smaller capacitor.
12
Copyright © 2006–2015, Texas Instruments Incorporated
TPS717
www.ti.com.cn
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
Feature Description (continued)
For output voltages below 1.6 V, a voltage divider on the band-gap reference voltage is employed to optimize
output regulation performance for lower output voltages. This configuration results in an additional resistor in the
quick-start path and combined with the noise reduction capacitor (CNR) results in slower start-up times for output
voltages below 1.6 V.
Equation 1 approximates the start-up time as a function of CNR for output voltages below 1.6 V:
ms
tSTART = 160ms + (540
x CNRnF)ms
nF
(1)
7.3.4 Undervoltage Lockout (UVLO)
The TPS717xx uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is
operating properly. The UVLO circuit has a limited glitch immunity so undershoot transients are typically ignored
on the input if these transients are less than 5 μs in duration.
7.3.5 Minimum Load
The TPS717xx is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at
very light output loads. The TPS717xx employs an innovative low-current mode circuit to increase loop gain
under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero
output current.
7.3.6 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety
in a complete design (including heatsink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°C
above the maximum expected ambient condition of a particular application. This configuration produces a worstcase junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS717xx is designed to protect against overload conditions. This circuitry
is not intended to replace proper heatsinking. Continuously running the TPS717xx into thermal shutdown
degrades device reliability.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
•
•
The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO
falling threshold.
The input voltage is greater than the nominal output voltage added to the dropout voltage.
The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
The output current is less than the current limit.
The device junction temperature is less than the maximum specified junction temperature.
Copyright © 2006–2015, Texas Instruments Incorporated
13
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
www.ti.com.cn
Device Functional Modes (continued)
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
VEN
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO and VIN > UVLO
VEN > VEN(high)
I OUT < ILIM
T J < 125°C
Dropout mode
UVLO < VIN < VOUT(nom) + VDO
VEN > VEN(high)
—
TJ < 125°C
VIN < UVLO – Vhys
VEN < VEN(low)
—
TJ > 165°C
Disabled mode
(any true condition disables the device)
14
Copyright © 2006–2015, Texas Instruments Incorporated
TPS717
www.ti.com.cn
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS717xx belongs to a family of new generation LDO regulators that use innovative circuitry to achieve
ultra-wide bandwidth and high loop gain, resulting in extremely high PSRR at very low headroom (VIN – VOUT).
Fixed voltage versions provide a noise reduction pin to bypass noise generated by the band-gap reference and
to improve PSRR while a quick-start circuit fast-charges this capacitor. These features, combined with low noise,
enable, low ground pin current, and ultra-small packaging, make this part ideal for automotive applications. This
family of regulators offers sub-band-gap output voltages, current limit, and thermal protection, and is fully
specified from –40°C to 125°C.
8.1.1 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot or undershoot magnitude but
increases duration of the transient. The TPS717xx has an ultra-wide loop bandwidth that allows it to respond
quickly to load transient events. As with any regulator, the loop bandwidth is finite and the initial transient voltage
peak is controlled by the sizing of the output capacitor. Typically, larger output capacitors reduce the peak while
also reducing the bandwidth of the LDO, slowing the response time.
8.1.2 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF or
larger low equivalent series resistance (ESR) capacitor from IN to GND near the regulator. This capacitor
counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A
higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if the device is
located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input
capacitor may be necessary to ensure stability.
The TPS717xx is designed to be stable with ceramic output capacitors of values 1 μF or larger. The X5R- and
X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. The
maximum ESR of the output capacitor must be less than 1 Ω.
8.1.3 Dropout Voltage
The TPS717xx uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the
RDSon of the PMOS pass element. VDO scales approximately with output current because the PMOS device
functions as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded when (VIN – VOUT) approaches dropout.
This effect is illustrated in Figure 15 through Figure 17 in Typical Characteristics.
Copyright © 2006–2015, Texas Instruments Incorporated
15
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
www.ti.com.cn
Application Information (continued)
8.1.4 Output Noise
In most LDOs, the band gap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the
TPS717xx, the band gap does not contribute significantly to noise. Instead, noise is dominated by the output
resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01-μF (minimum)
noise reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce
noise. A parallel combination that gives 2.5 μA of divider current has the same noise performance as a fixed
voltage version.
Equation 2 approximates the total noise referred to the feedback point (FB pin) when CNR = 0.01 μF:
mVRMS
x VOUT
VN = 11.5
V
(2)
8.2 Typical Applications
8.2.1 Application for Fixed Voltage Versions and Adjustable Voltage Version
Figure 33 shows the basic circuit connections for the fixed voltage options. Figure 34 gives the connections for
the adjustable output version (TPS71701). Note that the NR pin is not available on the adjustable version.
Optional 1-mF input
capacitor. May improve
source impedance, noise
or PSRR.
Optional 1-mF input
capacitor. May improve
source impedance, noise
or PSRR.
VIN
IN
VIN
VOUT
OUT
IN
TPS717xx
EN
GND
NR
1 mF
Ceramic
VOUT
OUT
TPS71701
EN
GND
R1
FB
1 mF
Ceramic
R2
VEN
VEN
Optional 0.01-mF bypass
capacitor to reduce
output noise and
increase PSRR.
Figure 33. Typical Application Circuit
(Fixed Voltage Versions)
Figure 34. Typical Application Circuit
(Adjustable Voltage Version)
8.2.1.1 Design Requirements
Table 2 summarizes the design requirements for Figure 36.
Table 2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
3.3 V, ±10%
Output voltage
2.8 V, ±5%
Output current
100 mA typical, 150 mA peak
Output voltage transient deviation
5%
Maximum ambient temperature
85°C
8.2.1.2 Detailed Design Procedure
For the adjustable version (TPS71701), the NR pin is replaced with a feedback (FB) pin. The voltage on this pin
sets the output voltage and is determined by the values of R1 and R2. The values of R1 and R2 can be calculated
for any voltage using the formula given in Equation 3:
R1 R2 * (VOUT / VREF 1)
(3)
The value of R2 directly impacts the operation of the device and must be chosen in the range of approximately
160 kΩ to 320 kΩ. Sample resistor values for common output voltages are shown in Table 3.
16
Copyright © 2006–2015, Texas Instruments Incorporated
TPS717
www.ti.com.cn
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
Table 3. Sample 1% Resistor Values for Common
Output Voltages
VOUT
R1
R2
1
80.6 kΩ
324 kΩ
1.2
162 kΩ
324 kΩ
1.5
294 kΩ
332 kΩ
1.8
402 kΩ
324 kΩ
2.5
665 kΩ
316 kΩ
3.3
1.02 MΩ
324 kΩ
5
1.74 MΩ
332 kΩ
8.2.1.3 Application Curve
VIN = 3.3 V
50 mV/div
COUT = 1 mF
VOUT
150 mA
1 mA
40 mV/div
IOUT
100 ms/div
Figure 35. Load Transient Response
8.2.2 Powering a PLL Integrated on an SOC
Figure 36 shows the TPS71701 powering a phase-locked loop (PLL) that is integrated into a system-on-a-chip
(SOC).
3.3 V
IN
2.8 V
OUT
CIN
PLL
COUT
TPS71701
Buck Regulator
R1
SOC
EN
FB
GND
R2
Figure 36. Typical Application Circuit: PLL on an SOC
Use the input and output capacitors to ensure the voltage transient requirements. A 1-µF input and 1-µF output
capacitor are selected to maximize the capacitance and minimize capacitor size.
R2 is chosen to be 158 kΩ for optimal noise and PSRR, and by Equation 4, R1 is selected to be 402 kΩ. Both R1
and R2 must be 1% tolerance resistors to meet the dc accuracy specification over line, load, and temperature.
Copyright © 2006–2015, Texas Instruments Incorporated
17
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
www.ti.com.cn
8.3 Do's and Don'ts
Do place at least one 1-µF ceramic capacitor as close as possible in the range of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Do not place any components in the feedback loop except for the output capacitor and feedback resistors.
Do not exceed the device absolute maximum ratings.
Do not float the enable (EN) pin.
9 Power Supply Recommendations
The TPS717xx is designed to operate from an input voltage between 2.5 V and 6.5 V. The input supply must
provide adequate headroom for the device to operate in a normal mode of operation.
Connect a low output impedance power supply directly to the IN pin of the TPS717xx. Inductive impedances
between the input supply and the IN pin can create significant voltage excursions at the IN pin during startup or
load transient events. If inductive impedances are unavoidable, use an input capacitor. To increase the overall
PSRR of the power solution, use a pi-filter before the input of the LDO or after the FB network of the LDO.
18
Copyright © 2006–2015, Texas Instruments Incorporated
TPS717
www.ti.com.cn
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close to the GND pin as possible, connected by wide, component-side,
copper surface area. The use of vias and long traces to create LDO component connections is strongly
discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive
parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground
reference plane is also recommended and is either embedded in the printed circuit board (PCB) itself or located
on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the
output voltage, shields the LDO from noise, and functions similar to a thermal plane to spread (or sink) heat from
the LDO device when connected to the thermal pad. In most applications, this ground plane is necessary to meet
thermal requirements.
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the
board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the
GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to the
GND pin of the device.
10.2 Layout Example
GND
NR
COUT
OUT
CNR
(1)
(1)
EN
CIN
N/C
IN
Thermal Pad
Circles within thermal pad area indicate vias to other layers on the board, for electrical connections or thermal
conduction.
Figure 37. Fixed Voltage Layout
Copyright © 2006–2015, Texas Instruments Incorporated
19
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
www.ti.com.cn
Layout Example (continued)
NR
OUT
COUT
GND
R2
R1
(1)
(1)
EN
CIN
N/C
IN
Thermal Pad
Circles within thermal pad area indicate vias to other layers on the board, for electrical connections or thermal
conduction.
Figure 38. Adjustable Voltage Layout
10.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in
Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 4:
PD VIN VOUT u IOUT
(4)
A better method of estimating the thermal measure comes from using the thermal metrics ΨJT and ΨJB, shown in
Thermal Information. These metrics are a more accurate representation of the heat transfer characteristics of the
die and the package than RθJA. The junction temperature can be estimated with Equation 5.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
20
PD is the power dissipation shown by Equation 4,
TT is the temperature at the center-top of the IC package,
TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface.
(5)
版权 © 2006–2015, Texas Instruments Incorporated
TPS717
www.ti.com.cn
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
Power Dissipation (接
接下页)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the application note Using New Thermal Metrics
(SBVA025), available for download at www.ti.com.
版权 © 2006–2015, Texas Instruments Incorporated
21
TPS717
ZHCSAL2H – FEBRUARY 2006 – REVISED JANUARY 2015
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 评估模块
评估模块 (EVM) 可与 TPS717 配套使用，帮助评估初始电路性能。 TPS717xxEVM-134 评估模块（和相关的用户
指南）可在德州仪器 (TI) 网站上的产品文件夹中获取，也可直接从 TI 网上商店购买。
11.1.2 器件命名规则
表 4. 器件命名规则 (1)
产品
TPS717xx(x)yyyz
(1)
VOUT
xx(x) 为标称输出电压。 对于分辨率为 100mV 的输出电压，订货编号中使用两位数字；否则，使用三位
数字（例如，28 = 2.8V；125 = 1.25V）。 01 表示可调电压版本。
yyy 为封装标识符。
z 为封装数量。 R 表示卷（3000 片），T 表示带（250 片）。
要获得最新的封装和订货信息，请参见本文档末尾的封装选项附录，或者访问器件产品文件夹（www.ti.com）。
11.2 文档支持
11.2.1 相关文档
《TPS717xxEVM-134 评估模块用户指南》，SLVU148
11.3 商标
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
版权 © 2006–2015, Texas Instruments Incorporated
重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
产品
应用
数字音频
www.ti.com.cn/audio
通信与电信
www.ti.com.cn/telecom
放大器和线性器件
www.ti.com.cn/amplifiers
计算机及周边
www.ti.com.cn/computer
数据转换器
www.ti.com.cn/dataconverters
消费电子
www.ti.com/consumer-apps
DLP® 产品
www.dlp.com
能源
www.ti.com/energy
DSP - 数字信号处理器
www.ti.com.cn/dsp
工业应用
www.ti.com.cn/industrial
时钟和计时器
www.ti.com.cn/clockandtimers
医疗电子
www.ti.com.cn/medical
接口
www.ti.com.cn/interface
安防应用
www.ti.com.cn/security
逻辑
www.ti.com.cn/logic
汽车电子
www.ti.com.cn/automotive
电源管理
www.ti.com.cn/power
视频和影像
www.ti.com.cn/video
微控制器 (MCU)
www.ti.com.cn/microcontrollers
RFID 系统
www.ti.com.cn/rfidsys
OMAP应用处理器
www.ti.com/omap
无线连通性
www.ti.com.cn/wirelessconnectivity
德州仪器在线技术支持社区
www.deyisupport.com
IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS71701DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMT
TPS71701DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMT
TPS71701DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMT
TPS71701DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMT
TPS71709DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FY
TPS71709DSERG4
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FY
TPS71709DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FY
TPS71709DSETG4
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FY
TPS71710DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMU
TPS71710DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMU
TPS71710DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMU
TPS71710DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMU
TPS71710DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMU
TPS71710DRVRG4
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMU
TPS71710DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMU
TPS71711DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BRL
TPS71711DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BRL
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-Jun-2016
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS71711DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BRL
TPS71711DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BRL
TPS71712DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CKE
TPS71712DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CKE
TPS71712DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CKE
TPS71712DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CKE
TPS71713DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMW
TPS71713DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMW
TPS71713DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMW
TPS71715DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAA
TPS71715DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAA
TPS71715DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAA
TPS717185DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KB
TPS717185DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KB
TPS71718DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMX
TPS71718DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMX
TPS71718DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMX
TPS71718DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMX
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-Jun-2016
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS71718DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
G6
TPS71718DSERG4
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
G6
TPS71718DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
G6
TPS71719DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CCZ
TPS71719DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CCZ
TPS71719DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CCZ
TPS71719DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CCZ
TPS71721DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
NXL
TPS71721DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
NXL
TPS71725DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAF
TPS71725DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAF
TPS71725DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAF
TPS71726DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BRK
TPS71726DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BRK
TPS71726DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BRK
TPS71727DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BSC
TPS71727DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BSC
TPS71727DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BSC
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-Jun-2016
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS71727DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KU
TPS71727DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
KU
TPS717285DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BRJ
TPS717285DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BRJ
TPS71728DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMZ
TPS71728DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMZ
TPS71728DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMZ
TPS71728DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BMZ
TPS71728DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FU
TPS71728DSERG4
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FU
TPS71728DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FU
TPS71728DSETG4
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FU
TPS71729DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CJR
TPS71729DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CJR
TPS71730DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNA
TPS71730DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNA
TPS71730DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNA
TPS71730DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNA
Addendum-Page 4
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-Jun-2016
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS71733DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNB
TPS71733DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNB
TPS71733DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNB
TPS71733DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNB
TPS71733DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNB
TPS71733DRVRG4
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNB
TPS71733DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNB
TPS71733DRVTG4
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BNB
TPS71733DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FV
TPS71733DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
FV
TPS71745DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
GL
TPS71745DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
GL
TPS71750DSER
ACTIVE
WSON
DSE
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
PD
TPS71750DSET
ACTIVE
WSON
DSE
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
PD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 5
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2016
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS717 :
• Automotive: TPS717-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 6
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS71701DCKR
Package Package Pins
Type Drawing
SC70
DCK
5
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71701DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71709DSER
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71709DSET
WSON
DSE
6
250
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71710DCKR
SC70
DCK
5
3000
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71710DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71710DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71710DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71710DRVR
WSON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS71710DRVT
WSON
DRV
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS71711DCKR
SC70
DCK
5
3000
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71711DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71711DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71711DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71712DCKR
SC70
DCK
5
3000
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71712DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71712DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71712DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS71713DCKR
SC70
DCK
5
3000
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71713DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71713DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71713DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71715DCKR
SC70
DCK
5
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TPS71715DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71715DCKT
SC70
DCK
5
250
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TPS71715DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS717185DSER
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS717185DSET
WSON
DSE
6
250
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71718DCKR
SC70
DCK
5
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TPS71718DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71718DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71718DCKT
SC70
DCK
5
250
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TPS71718DSER
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71718DSET
WSON
DSE
6
250
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71719DCKR
SC70
DCK
5
3000
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71719DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71719DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71719DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71721DCKR
SC70
DCK
5
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TPS71721DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71721DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71721DCKT
SC70
DCK
5
250
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TPS71725DCKR
SC70
DCK
5
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TPS71725DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71725DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71725DCKT
SC70
DCK
5
250
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TPS71726DCKR
SC70
DCK
5
3000
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71726DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71726DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71726DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71727DCKR
SC70
DCK
5
3000
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71727DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71727DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71727DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71727DSER
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71727DSET
WSON
DSE
6
250
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS717285DCKR
SC70
DCK
5
3000
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS717285DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS717285DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS717285DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71728DCKR
SC70
DCK
5
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS71728DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71728DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71728DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71728DSER
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71728DSET
WSON
DSE
6
250
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71729DCKR
SC70
DCK
5
3000
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71729DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71729DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71729DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71730DCKR
SC70
DCK
5
3000
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71730DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71730DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71730DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71733DCKR
SC70
DCK
5
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
TPS71733DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71733DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
TPS71733DCKT
SC70
DCK
5
250
179.0
8.4
2.25
2.4
1.22
4.0
8.0
Q3
TPS71733DRVR
WSON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS71733DRVT
WSON
DRV
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS71733DSER
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71733DSET
WSON
DSE
6
250
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71745DSER
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71745DSET
WSON
DSE
6
250
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71750DSER
WSON
DSE
6
3000
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
TPS71750DSET
WSON
DSE
6
250
179.0
8.4
1.8
1.8
1.0
4.0
8.0
Q2
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS71701DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71701DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71709DSER
WSON
DSE
6
3000
203.0
203.0
35.0
TPS71709DSET
WSON
DSE
6
250
203.0
203.0
35.0
TPS71710DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71710DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71710DCKT
SC70
DCK
5
250
340.0
340.0
38.0
TPS71710DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71710DRVR
WSON
DRV
6
3000
203.0
203.0
35.0
TPS71710DRVT
WSON
DRV
6
250
203.0
203.0
35.0
TPS71711DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71711DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71711DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71711DCKT
SC70
DCK
5
250
340.0
340.0
38.0
TPS71712DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71712DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71712DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71712DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71713DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71713DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS71713DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71713DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71715DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71715DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71715DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71715DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS717185DSER
WSON
DSE
6
3000
203.0
203.0
35.0
TPS717185DSET
WSON
DSE
6
250
203.0
203.0
35.0
TPS71718DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71718DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71718DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71718DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71718DSER
WSON
DSE
6
3000
203.0
203.0
35.0
TPS71718DSET
WSON
DSE
6
250
203.0
203.0
35.0
TPS71719DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71719DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71719DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71719DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71721DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71721DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71721DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71721DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71725DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71725DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71725DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71725DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71726DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71726DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71726DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71726DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71727DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71727DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71727DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71727DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71727DSER
WSON
DSE
6
3000
203.0
203.0
35.0
TPS71727DSET
WSON
DSE
6
250
203.0
203.0
35.0
TPS717285DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS717285DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS717285DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS717285DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71728DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71728DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71728DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71728DCKT
SC70
DCK
5
250
180.0
180.0
18.0
Pack Materials-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS71728DSER
WSON
DSE
6
3000
203.0
203.0
35.0
TPS71728DSET
WSON
DSE
6
250
203.0
203.0
35.0
TPS71729DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71729DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71729DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71729DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71730DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71730DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71730DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71730DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71733DCKR
SC70
DCK
5
3000
203.0
203.0
35.0
TPS71733DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
TPS71733DCKT
SC70
DCK
5
250
180.0
180.0
18.0
TPS71733DCKT
SC70
DCK
5
250
203.0
203.0
35.0
TPS71733DRVR
WSON
DRV
6
3000
203.0
203.0
35.0
TPS71733DRVT
WSON
DRV
6
250
203.0
203.0
35.0
TPS71733DSER
WSON
DSE
6
3000
203.0
203.0
35.0
TPS71733DSET
WSON
DSE
6
250
203.0
203.0
35.0
TPS71745DSER
WSON
DSE
6
3000
203.0
203.0
35.0
TPS71745DSET
WSON
DSE
6
250
203.0
203.0
35.0
TPS71750DSER
WSON
DSE
6
3000
203.0
203.0
35.0
TPS71750DSET
WSON
DSE
6
250
203.0
203.0
35.0
Pack Materials-Page 6
IMPORTANT NOTICE
重要声明
德州仪器 (TI) 公司有权按照最新发布的 JESD46 对其半导体产品和服务进行纠正、增强、改进和其他修改，并不再按最新发布的 JESD48 提
供任何产品和服务。买方在下订单前应获取最新的相关信息，并验证这些信息是否完整且是最新的。
TI 公布的半导体产品销售条款 (http://www.ti.com/sc/docs/stdterms.htm) 适用于 TI 已认证和批准上市的已封装集成电路产品的销售。另有其
他条款可能适用于其他类型 TI 产品及服务的使用或销售。
复制 TI 数据表上 TI 信息的重要部分时，不得变更该等信息，且必须随附所有相关保证、条件、限制和通知，否则不得复制。TI 对该等复制文
件不承担任何责任。第三方信息可能受到其它限制条件的制约。在转售 TI 产品或服务时，如果存在对产品或服务参数的虚假陈述，则会失去
相关 TI 产品或服务的明示或暗示保证，且构成不公平的、欺诈性商业行为。TI 对此类虚假陈述不承担任何责任。
买方和在系统中整合 TI 产品的其他开发人员（总称“设计人员”）理解并同意，设计人员在设计应用时应自行实施独立的分析、评价和判断，且
应全权 负责并确保 应用的安全性， 及设计人员的 应用 （包括应用中使用的所有 TI 产品）应符合所有适用的法律法规及其他相关要求。设计
人员就自己设计的 应用声明，其具备制订和实施下列保障措施所需的一切必要专业知识，能够 (1) 预见故障的危险后果，(2) 监视故障及其后
果，以及 (3) 降低可能导致危险的故障几率并采取适当措施。设计人员同意，在使用或分发包含 TI 产品的任何 应用前， 将彻底测试该等 应用
和 该等应用中所用 TI 产品的 功能。
TI 提供技术、应用或其他设计建议、质量特点、可靠性数据或其他服务或信息，包括但不限于与评估模块有关的参考设计和材料（总称“TI 资
源”），旨在帮助设计人员开发整合了 TI 产品的 应用， 如果设计人员（个人，或如果是代表公司，则为设计人员的公司）以任何方式下载、
访问或使用任何特定的 TI 资源，即表示其同意仅为该等目标，按照本通知的条款使用任何特定 TI 资源。
TI 所提供的 TI 资源，并未扩大或以其他方式修改 TI 对 TI 产品的公开适用的质保及质保免责声明；也未导致 TI 承担任何额外的义务或责任。
TI 有权对其 TI 资源进行纠正、增强、改进和其他修改。除特定 TI 资源的公开文档中明确列出的测试外，TI 未进行任何其他测试。
设计人员只有在开发包含该等 TI 资源所列 TI 产品的 应用时， 才被授权使用、复制和修改任何相关单项 TI 资源。但并未依据禁止反言原则或
其他法理授予您任何TI知识产权的任何其他明示或默示的许可，也未授予您 TI 或第三方的任何技术或知识产权的许可，该等产权包括但不限
于任何专利权、版权、屏蔽作品权或与使用TI产品或服务的任何整合、机器制作、流程相关的其他知识产权。涉及或参考了第三方产品或服务
的信息不构成使用此类产品或服务的许可或与其相关的保证或认可。使用 TI 资源可能需要您向第三方获得对该等第三方专利或其他知识产权
的许可。
TI 资源系“按原样”提供。TI 兹免除对资源及其使用作出所有其他明确或默认的保证或陈述，包括但不限于对准确性或完整性、产权保证、无屡
发故障保证，以及适销性、适合特定用途和不侵犯任何第三方知识产权的任何默认保证。TI 不负责任何申索，包括但不限于因组合产品所致或
与之有关的申索，也不为或对设计人员进行辩护或赔偿，即使该等产品组合已列于 TI 资源或其他地方。对因 TI 资源或其使用引起或与之有关
的任何实际的、直接的、特殊的、附带的、间接的、惩罚性的、偶发的、从属或惩戒性损害赔偿，不管 TI 是否获悉可能会产生上述损害赔
偿，TI 概不负责。
除 TI 已明确指出特定产品已达到特定行业标准（例如 ISO/TS 16949 和 ISO 26262）的要求外，TI 不对未达到任何该等行业标准要求而承担
任何责任。
如果 TI 明确宣称产品有助于功能安全或符合行业功能安全标准，则该等产品旨在帮助客户设计和创作自己的 符合 相关功能安全标准和要求的
应用。在应用内使用产品的行为本身不会 配有 任何安全特性。设计人员必须确保遵守适用于其应用的相关安全要求和 标准。设计人员不可将
任何 TI 产品用于关乎性命的医疗设备，除非已由各方获得授权的管理人员签署专门的合同对此类应用专门作出规定。关乎性命的医疗设备是
指出现故障会导致严重身体伤害或死亡的医疗设备（例如生命保障设备、心脏起搏器、心脏除颤器、人工心脏泵、神经刺激器以及植入设
备）。此类设备包括但不限于，美国食品药品监督管理局认定为 III 类设备的设备，以及在美国以外的其他国家或地区认定为同等类别设备的
所有医疗设备。
TI 可能明确指定某些产品具备某些特定资格（例如 Q100、军用级或增强型产品）。设计人员同意，其具备一切必要专业知识，可以为自己的
应用选择适合的 产品， 并且正确选择产品的风险由设计人员承担。设计人员单方面负责遵守与该等选择有关的所有法律或监管要求。
设计人员同意向 TI 及其代表全额赔偿因其不遵守本通知条款和条件而引起的任何损害、费用、损失和/或责任。
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2017 德州仪器半导体技术（上海）有限公司
工商网监
湘ICP备2023018690号
