TPS71733DSER

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 TPS717 Low-Noise, High-Bandwidth PSRR, Low-Dropout, 150-mA Linear Regulator 1 Features 3 Description • • The TPS717 family of low-dropout (LDO), low-power linear regulators offers very high power-supply rejection (PSRR) while maintaining very low 45-μA ground current in an ultra-small, five-pin SOT package. The family uses an advanced BiCMOS process and a PMOS pass device to achieve fast start-up, very low noise, excellent transient response, and excellent PSRR performance. The TPS717 is stable with a 1-μF ceramic output capacitor and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations. The device family is fully specified from TJ = –40°C to 125°C and is offered in a small SOT (SC70-5) package, a 2-mm × 2-mm WSON-6 package with a thermal pad, and a 1.5-mm × 1.5-mm WSON-6 package, which are ideal for small form factor portable equipment (such as wireless handsets and PDAs). 1 • • • • • Input Voltage: 2.5 V to 6.5 V Available in Multiple Output Versions: – Fixed Output with Voltages from 0.9 V to 5 V – Adjustable Output Voltage from 0.9 V to 6.2 V Ultra-High PSRR: – 70 dB at 1 kHz, 67 dB at 100 kHz, and 45 dB at 1 MHz Excellent Load and Line Transient Response Very Low Dropout: 170 mV typical at 150 mA Low Noise: 30 μVRMS typical (100 Hz to 100 kHz) Small 5-pin SC-70, 2-mm × 2-mm WSON-6, and 1.5-mm × 1.5-mm WSON-6 Packages 2 Applications • • • • Camera Sensor Power Mobile Phone Handsets PDAs and Smartphones Wireless LAN, Bluetooth® Device Information(1) PART NUMBER PACKAGE TPS717 BODY SIZE (NOM) SC70 (5) 2.00 mm × 1.25 mm WSON (6) 2.00 mm × 2.00 mm WSON (6) 1.50 mm × 1.50 mm (1) For all available package and voltage options, see the orderable addendum at the end of the datasheet. Typical Application Circuit for Fixed-Voltage Versions VIN IN PSRR vs Frequency 80 VOUT OUT 150 mA 70 TPS717xx EN VEN GND 1 mF Ceramic NR 0.01 mF (Optional) 10 mA 60 PSRR (dB) 1 mF Ceramic 50 40 75 mA 30 20 COUT = 1 mF CNR = 10 nF 10 0 10 100 1k 100k 10k Frequency (Hz) 1M 10M Power-Supply Rejection Ratio (VIN - VOUT = 1 V) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagrams ..................................... Feature Description................................................. Device Functional Modes........................................ 12 12 13 14 8 Application and Implementation ........................ 16 8.1 Application Information............................................ 16 8.2 Typical Applications ................................................ 17 8.3 Do's and Don'ts ...................................................... 19 9 Power Supply Recommendations...................... 19 10 Layout................................................................... 20 10.1 Layout Guidelines ................................................. 20 10.2 Layout Examples................................................... 20 10.3 Power Dissipation ................................................ 21 11 Device and Documentation Support ................. 23 11.1 11.2 11.3 11.4 11.5 11.6 Device Support .................................................... Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 24 24 24 12 Mechanical, Packaging, and Orderable Information ........................................................... 24 4 Revision History Changes from Revision H (January 2015) to Revision I Page • Added TI Design .................................................................................................................................................................... 1 • Changed PMOSFET to PMOS in Description section ........................................................................................................... 1 • Added footnote to the Recommended Operating Conditions table........................................................................................ 5 • Changed VFB parameter in Electrical Characteristics table ................................................................................................... 6 • Changed units of Vn parameter in Electrical Characteristics table ......................................................................................... 6 • Deleted UVLO parameter minimum specification from Electrical Characteristics table......................................................... 6 • Changed TA to TJ in x-axis of Figure 7, Figure 10, and Figure 11 ........................................................................................ 8 • Changed second paragraph of Startup and Noise Reduction Capacitor section................................................................. 13 • Changed last bullet in Normal Operation section ................................................................................................................ 14 • Changed value of the TJ column in last row of Table 1 ...................................................................................................... 15 • Added last sentence to Input and Output Capacitor Requirements section......................................................................... 16 • Changed VREF to VFB in Equation 3 ..................................................................................................................................... 17 • Changed definition of z in Table 4 ....................................................................................................................................... 23 2 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 TPS717 www.ti.com SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 Changes from Revision G (April 2009) to Revision H Page • Changed pin descriptions throughout Pin Functions table ..................................................................................................... 4 • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 5 • Changed load regulation typical specification from 120 µV to 70 µV to better reflect device performance .......................... 6 • Changed condition for CNR = none for Vn parameter.............................................................................................................. 6 • Changed Figure 1, Figure 2, Figure 3, and Figure 4: removed legend, added call-outs for clarity ....................................... 7 • Changed titles of Figure 15, Figure 17, and Figure 25........................................................................................................... 8 • Corrected input and output symbols in operational amplifiers in Functional Block Diagrams ............................................. 12 • Changed Undervoltage Lockout (UVLO) section text: reworded for clarity.......................................................................... 14 • Deleted Reverse Current Protection section ....................................................................................................................... 16 Changes from Revision F (February 2009) to Revision G • Page Changed min and max specs for Output accuracy, VOUT ≥ 1.0V ........................................................................................... 6 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 3 TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 5 Pin Configuration and Functions DCK Package 5-Pin SC70 Top View IN 1 GND 2 EN 3 5 4 DRV Package 2-mm × 2-mm, 6-Pin WSON Top View OUT NR/FB OUT 1 NR/FB 2 GND 3 GND 6 IN 5 N/C 4 EN (1) DSE Package 1.5-mm × 1.5-mm, 6-Pin WSON Top View (1) OUT 1 6 IN GND 2 5 N/C NR/FB 3 4 EN (1) N/C = No connection Pin Functions PIN DCK (SC70) DRV (WSON) DSE (WSON) I/O EN 3 4 4 I Driving the enable pin (EN) above VEN(high) turns on the regulator. Driving this pin below VEN(low) puts the regulator into standby mode, thereby disabling the output and reducing operating current. FB 4 2 3 I Adjustable voltage version only. The voltage at this pin is fed to the error amplifier. A resistor divider from OUT to FB sets the output voltage when in regulation. GND 2 3 2 — IN 1 6 6 I N/C — 5 5 — Not connected. This pin can be tied to ground to improve thermal dissipation. NR 4 2 3 — Fixed voltage versions only. The noise reduction capacitor filters the noise generated by the internal band gap, thus lowering output noise. OUT 5 1 1 O This pin is the regulated output voltage. A minimum capacitance of 1 μF is required for stability from this pin to ground. NAME 4 DESCRIPTION Ground Input to the device. A 0.1-μF to 1-μF capacitor is recommended for better performance. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 TPS717 www.ti.com SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 6 Specifications 6.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted), all voltages are with respect to GND (1) Voltage MIN MAX VIN –0.3 7 UNIT VFB –0.3 3.6 VNR –0.3 3.6 VEN –0.3 VIN + 0.3 V (2) VOUT –0.3 V 7 Current IOUT Internally limited Continuous total power dissipation PDISS See Thermal Information Operating junction temperature TJ –55 150 °C Storage temperature Tstg –55 150 °C (1) (2) A Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. VEN absolute maximum rating is VIN + 0.3 V or 7 V, whichever is greater. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 2.5 6.5 VOUT Output voltage 0.9 5 IOUT Output current 0 150 VEN Enable voltage 0 VIN V COUT Output capacitor 1 (1) 100 µF TJ Junction temperature –40 125 °C (1) V V mA When using feedback resistors that are smaller than recommended, the minimum output capacitance must be greater than 5 µF. 6.4 Thermal Information TPS717 THERMAL METRIC (1) DCK (SC70) DRV (WSON) DSE (WSON) 5 PINS 6 PINS 6 PINS UNIT 190.5 °C/W RθJA Junction-to-ambient thermal resistance 279.2 71.1 RθJC(top) Junction-to-case (top) thermal resistance 57.5 96.5 94.9 °C/W RθJB Junction-to-board thermal resistance 74.1 40.5 149.3 °C/W ψJT Junction-to-top characterization parameter 0.8 2.7 6.4 °C/W ψJB Junction-to-board characterization parameter 73.1 40.9 152.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 10.7 n/a °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 5 TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 6.5 Electrical Characteristics Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT = 0.5 mA, VEN = VIN, COUT = 1.0 μF, CNR = 0.01 μF, unless otherwise noted. For TPS71701, VOUT = 2.8 V. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS VIN Input voltage range VFB Feedback pin voltage (TPS71701) VOUT Output voltage range VOUT –2% 6.5 V 0.793 2% V 0.9 5.0 (TPS71701) 0.9 6.5 – VDO Output accuracy Nominal TJ = 25°C Output accuracy (VOUT < 1.0 V) Over VIN, IOUT, temperature (2) VOUT + 0.5 V ≤ VIN ≤ 6.5 V 0 mA ≤ IOUT ≤ 150 mA –30 30 Output accuracy (VOUT ≥ 1.0 V) Over VIN, IOUT, temperature (2) VOUT + 0.5 V ≤ VIN ≤ 6.5 V 0 mA ≤ IOUT ≤ 150 mA –3.0% 3.0% ΔVOUT(ΔIOUT) Load regulation 0 mA ≤ IOUT ≤ 150 mA VDO Dropout voltage (3) (VIN = VOUT(nom) – 0.1 V) IOUT = 150 mA ILIM (fixed) Output current limit (fixed output) VOUT = 0.9 × VOUT(nom) ILIM (adjustable) Output current limit (TPS71701) VOUT = 0.9 × VOUT(nom) IGND Ground pin current ISHDN Shutdown current (IGND) IFB Feedback pin current (TPS71701) Power-supply rejection ratio UNIT V ±2.5 VOUT(nom) + 0.5 V ≤ VIN ≤ 6.5 V, IOUT = 5 mA mV 125 µV/V 70 µV/mA 170 300 mV 200 325 575 mA 200 325 575 mA IOUT = 0.1 mA 45 80 IOUT = 150 mA 100 VEN ≤ 0.4 V, TJ = –40°C to 85°C 2.5 V ≤ VIN < 4.5 V 0.20 4.5 V ≤ VIN ≤ 6.5 V 0.90 0.02 VIN = 3.8 V, VOUT = 2.8 V, IOUT = 150 mA f = 100 Hz 70 f = 1 kHz 70 f = 10 kHz 67 f = 100 kHz 67 f = 1 MHz tSTR MAX (TPS717xx) Line regulation (1) Vn TYP 2.5 IOUT = 5 mA ΔVOUT(ΔVIN) PSRR MIN (1) μA 1.5 μA 1.0 μA dB 45 CNR = none Output noise voltage BW = 100 Hz to 100 kHz, VIN = 3.8 V, VOUT = 2.8 V, IOUT = 10 mA 95 × VOUT 0.9 V ≤ VOUT ≤ 1.6V, CNR = 0.001 μF 0.700 Startup time VOUT = 90% VOUT(nom), RL = 19 Ω, COUT = 1 μF 1.6 V < VOUT < VMAX, CNR = 0.01 μF 0.160 CNR = 0.001 μF 25 × VOUT CNR = 0.01 μF 12.5 × VOUT CNR = 0.1 μF 11.5 × VOUT VIN ≤ 5.5 V μVRMS/V ms 1.2 6.5 (4) 1.25 6.5 VEN(high) Enable high (enabled) VEN(low) Enable low (shutdown) 0.4 V IEN(high) Enable pin current, enabled EN = 6.5 V 0.02 1.0 μA Undervoltage lockout VIN rising 2.45 2.49 Hysteresis VIN falling 150 Shutdown, temperature increasing 160 Reset, temperature decreasing 140 UVLO Tsd Thermal shutdown temperature TJ Operating junction temperature (1) (2) (3) (4) 6 5.5 V < VIN ≤ 6.5 V 0 –40 V V mV °C 125 °C Minimum VIN = VOUT + VDO or 2.5 V, whichever is greater. Does not include external resistor tolerances. VDO is not measured for devices with VOUT(nom) < 2.6 V because the minimum VIN is 2.5 V. Maximum VEN(high) = VIN + 0.3 or 6.5 V, whichever is smaller. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 TPS717 www.ti.com SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 6.6 Typical Characteristics 50 50 40 40 30 30 20 20 DVOUT (mV) DVOUT (mV) Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT = 0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701,) VOUT = 2.8 V. Typical values are at TA = 25°C. 10 -40°C 0 25°C -10 -20 25°C 85°C 10 0 -10 -40°C 125°C -20 -30 -30 85°C -40 -40 125°C -50 0 50 -50 0 150 100 1 3 2 5 4 IOUT (mA) IOUT (mA) Figure 2. Load Regulation Under Light Loads Figure 1. Load Regulation 1.0 3.0 0.8 2.0 0.6 -40°C 0.2 0 85°C 125°C -0.2 1.0 DVOUT (%) DVOUT (%) 0.4 85°C 25°C -40°C 0 -1.0 -0.4 125°C 25°C -0.6 -2.0 -0.8 -3.0 -1.0 3.5 2.5 4.5 VIN (V) 5.5 3.5 2.5 6.5 Figure 3. Line Regulation (IOUT = 5 mA) 4.5 VIN (V) 5.5 6.5 Figure 4. Line Regulation (IOUT = 150 mA) 250 2.0 TA = 125°C 1.5 200 IOUT = 5mA 0.5 0 -0.5 -1.0 IOUT = 100mA VDO (mV) DVOUT (%) 1.0 150 TA = 85°C 100 TA = 25°C 50 IOUT = 150mA TA = -40°C -1.5 -2.0 0 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 95 110 125 50 0 100 150 IOUT (mA) Figure 5. Output Voltage vs Temperature Figure 6. Dropout Voltage vs Output Current Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 7 TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT = 0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701,) VOUT = 2.8 V. Typical values are at TA = 25°C. 150 300 VOUT = 2.8 V IOUT = 150 mA 250 120 IOUT = 150 mA 150 IGND (mA) VDO (mV) 200 90 60 100 30 50 IOUT = 10 mA IOUT = 100 mA 0 0 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 95 110 125 2.5 Figure 7. Dropout Voltage vs Temperature 3.5 5.5 4.5 VIN (V) 6.5 Figure 8. Ground Pin Current vs Input Voltage 150 150 120 120 90 90 IGND (mA) IGND (mA) IOUT = 150 mA 60 30 60 30 IOUT = 100 mA 0 0 0 100 50 150 -40 -25 -10 5 IOUT (mA) Figure 9. Ground Pin Current vs Output Current 80 95 110 125 TA = -40°C 500 IGND (mA) IGND (mA) 4 TA = 25°C TA = 85°C 400 VIN = 4.5 V VIN = 6.5 V 300 1 TA = 125°C VIN = 3.3 V 0 200 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 95 110 125 2.5 Figure 11. Ground Pin Current vs Temperature (Disabled) 8 65 600 VEN = 0.4 V 2 35 50 TJ (°C) Figure 10. Ground Pin Current vs Temperature (Enabled) 5 3 20 Submit Documentation Feedback 3.5 4.5 VIN (V) 5.5 6.5 Figure 12. Current Limit vs Input Voltage Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 TPS717 www.ti.com SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 Typical Characteristics (continued) Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT = 0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701,) VOUT = 2.8 V. Typical values are at TA = 25°C. 80 80 150mA 70 10mA 60 50 PSRR (dB) PSRR (dB) 60 40 75mA 30 20 75mA 150mA 50 40 30 20 COUT = 1mF CNR = 10nF 10 COUT = 1mF CNR = 10nF 10 0 0 10 100 1k 100k 10k Frequency (Hz) 1M 10M 10 100 1k 100k 10k Frequency (Hz) 10M 1M Figure 13. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 1 V) Figure 14. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 0.5 V) 80 80 70 70 10mA 60 50 10mA 60 75mA PSRR (dB) PSRR (dB) 10mA 70 40 150mA 30 20 50 40 150mA 30 20 COUT = 1mF CNR = 10nF 10 0 10 100 1k 100k 10k Frequency (Hz) 1M COUT = 10mF CNR = 10nF 10 0 10M 10 Figure 15. Power-Supply Ripple Rejection vs Frequency in Dropout Conditions (VIN – VOUT = 0.25 V) 100 1k 100k 10k Frequency (Hz) 10M 1M Figure 16. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 1 V) 80 80 70 70 10mA 60 50 50 PSRR (dB) PSRR (dB) 10mA 60 40 150mA 30 20 40 150mA 30 20 COUT = 10mF CNR = 10nF 10 0 COUT = 10mF CNR = 0nF 10 0 10 100 1k 100k 10k Frequency (Hz) 1M 10M Figure 17. Power-Supply Ripple Rejection vs Frequency in Dropout Conditions (VIN – VOUT = 0.25 V) 10 100 1k 100k 10k Frequency (Hz) 1M 10M Figure 18. Power-Supply Ripple Rejection vs Frequency (VIN – VOUT = 1 V) Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 9 TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com Typical Characteristics (continued) Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT = 0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701,) VOUT = 2.8 V. Typical values are at TA = 25°C. 80 80 1kHz 70 10kHz 100kHz 50 1MHz 40 30 20 60 40 1MHz 30 IOUT = 75mA COUT = 1mF CNR = 10nF 10 0 0 0 0.5 2.5 1.5 2.0 VIN - VOUT (V) 1.0 3.0 3.5 4.0 0 Figure 19. Power-Supply Ripple Rejection vs (VIN – VOUT) 60 10kHz 50 40 1MHz 30 20 IOUT = 150mA COUT = 1mF CNR = 10nF 10 0 0 0.5 2.5 1.5 2.0 VIN - VOUT (V) 1.0 3.0 3.5 4.0 10 COUT = 1mF 6 4 2 10k 1k COUT = 1mF CNR = 10nF IOUT = 10mA 10 8 6 4 2 0 100 10k 1k 100k Figure 22. Output Spectral Noise Density vs Output Current 100k Output Spectral Noise Density (mV/ÖHz) COUT = 10mF 0 30 IOUT = 10mA COUT = 1mF 25 20 15 10 CNR = 0nF CNR = 10nF CNR = 1nF CNR = 100nF 5 0 100 Frequency (Hz) 10k 1k 100k Frequency (Hz) Figure 23. Output Spectral Noise Density vs Output Capacitance 10 3.5 Frequency (Hz) IOUT = 10mA CNR = 10nF 14 100 3.0 12 4.0 16 8 2.5 1.5 2.0 VIN - VOUT (V) IOUT = 150mA 14 Figure 21. Power-Supply Ripple Rejection vs (VIN – VOUT) 12 1.0 16 1kHz 100kHz 70 0.5 Figure 20. Power-Supply Ripple Rejection vs (VIN – VOUT) Output Noise Density (mV/ÖHz) 80 PSRR (dB) 50 20 IOUT = 10mA COUT = 1mF CNR = 10nF 10 10kHz 100kHz PSRR (dB) PSRR (dB) 60 Output Noise Density (mV/ÖHz) 1kHz 70 Figure 24. Output Spectral Noise Density vs Noise Reduction Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 TPS717 www.ti.com SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 Typical Characteristics (continued) Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT = 0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701,) VOUT = 2.8 V. Typical values are at TA = 25°C. 50 300 IOUT = 10mA COUT = 1mF 270 40 Total Noise (mVRMS) 240 Total Noise (mVRMS) VOUT = 2.8V, CNR = 10nF VOUT = 1.3V, CNR = 1nF 45 210 180 150 120 90 35 30 25 20 15 60 10 30 5 0 0 0 10 1 0 100 5 CNR (nF) Figure 25. Total Output Noise vs Noise Reduction Capacitor 10 15 COUT (mF) 20 25 Figure 26. Total Output Noise vs Output Capacitance VIN = 3.3 V COUT = 1 mF 10 mV/div VOUT dVIN = 1 V/ms dt 50 mV/div COUT = 1 mF VOUT 6.5 V 1 V/div 150 mA 3.3 V VIN 40 mA/div IOUT 100 ms/div 100 ms/div Figure 27. Line Transient Response COUT = 10mF 1V/div Figure 28. Load Transient Response VOUT VIN IOUT = 150 mA 6 5 VOUT Volts COUT = 1mF 4 3 VOUT 2 1V/div 1 6.5V VIN 4V/div 1 mA 0 0V 50ms/div 50 ms/div Figure 30. Power-Up and Power-Down Figure 29. Turn-On Response Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 11 TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 7 Detailed Description 7.1 Overview The TPS717 family of low-dropout (LDO) regulators combines the high performance required by many RF and precision analog applications with ultra-low current consumption. High PSRR is provided by a high-gain, highbandwidth error loop with good supply rejection with very low headroom (VIN – VOUT). Fixed voltage versions provide a noise reduction pin to bypass noise generated by the band-gap reference and to improve PSRR. A quick-start circuit fast-charges this capacitor at startup. The combination of high performance and low ground current also make the TPS717 family of devices an excellent choice for battery-powered applications. All versions have thermal and overcurrent protection. 7.2 Functional Block Diagrams OUT IN 2.5 mA Current Limit EN Thermal Shutdown UVLO Quick-Start 1.20-V Band Gap VOUT > 1.6 V NR 360 kW 0.8 V 250 kW VOUT £ 1.6 V 640 kW GND Figure 31. Fixed Voltage Versions 12 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 TPS717 www.ti.com SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 Functional Block Diagrams (continued) OUT IN Current Limit EN Thermal Shutdown 3.3 MW UVLO 1.20-V Band Gap 360 kW FB 0.8 V 250 kW 640 kW GND Figure 32. Adjustable Voltage Version 7.3 Feature Description 7.3.1 Internal Current Limit The TPS717 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, do not operate the device in a current-limit state for extended periods of time. The PMOS pass element in the TPS717 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate. 7.3.2 Shutdown The enable pin (EN) is active high and compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN. 7.3.3 Startup and Noise Reduction Capacitor Fixed voltage versions of the TPS717 use a quick-start circuit to fast-charge the noise reduction capacitor, CNR, if present (see Figure 31). This circuit allows the combination of very low output noise and fast start-up times. The NR pin is high impedance, so a low-leakage CNR capacitor must be used; most ceramic capacitors are appropriate in this configuration. Note that for fastest startup, apply VIN first, then drive the enable pin high. If EN is tied to IN, startup is somewhat slower. The quick-start switch is closed for approximately 135 μs. To ensure that CNR is fully charged during the quick-start time, use a 0.01-μF or smaller capacitor. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 13 TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) For output voltages below 1.6 V, a voltage divider on the band-gap reference voltage is employed to optimize output regulation performance for lower output voltages. This configuration results in an additional resistor in the quick-start path and combined with the noise reduction capacitor (CNR) results in slower start-up times for output voltages below 1.6 V. Equation 1 approximates the start-up time as a function of CNR for output voltages below 1.6 V: ms tSTART = 160ms + (540 x CNRnF)ms nF (1) 7.3.4 Undervoltage Lockout (UVLO) The TPS717 uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a limited glitch immunity so undershoot transients are typically ignored on the input if these transients are less than 5 μs in duration. When the input is lower than 1.4 V, the UVLO circuit may not have enough headroom to keep the output fully off. 7.3.5 Minimum Load The TPS717 is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS717 employs an innovative low-current mode circuit to increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current. 7.3.6 Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°C above the maximum expected ambient condition of a particular application. This configuration produces a worstcase junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS717 is designed to protect against overload conditions. This circuitry is not intended to replace proper heatsinking. Continuously running the TPS717 into thermal shutdown degrades device reliability. 7.4 Device Functional Modes 7.4.1 Normal Operation The device regulates to the nominal output voltage under the following conditions: • • • • • 14 The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO falling threshold The input voltage is greater than the nominal output voltage added to the dropout voltage The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold The output current is less than the current limit The device junction temperature is less than or equal to the maximum specified operating junction temperature Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 TPS717 www.ti.com SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 Device Functional Modes (continued) 7.4.2 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line or load transients in dropout can result in large output voltage deviations. 7.4.3 Disabled The device is disabled under the following conditions: • The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold. • The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold. • The device junction temperature is greater than the thermal shutdown temperature. Table 1 shows the conditions that lead to the different modes of operation. Table 1. Device Functional Mode Comparison PARAMETER OPERATING MODE VIN VEN IOUT TJ Normal mode VIN > VOUT(nom) + VDO and VIN > UVLO VEN > VEN(high) I OUT < ILIM T J < 125°C Dropout mode UVLO < VIN < VOUT(nom) + VDO VEN > VEN(high) — TJ < 125°C VIN < UVLO – Vhys VEN < VEN(low) — TJ > 160°C Disabled mode (any true condition disables the device) Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 15 TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS717 belongs to a family of new generation LDO regulators that use innovative circuitry to achieve ultrawide bandwidth and high loop gain, resulting in extremely high PSRR at very low headroom (VIN – VOUT). Fixed voltage versions provide a noise reduction pin to bypass noise generated by the band-gap reference and to improve PSRR when a quick-start circuit fast-charges this capacitor. These features, combined with low noise, enable, low ground pin current, and ultra-small packaging, make this part ideal for many applications. This family of regulators offers sub-band-gap output voltages, current limit, and thermal protection, and is fully specified from –40°C to 125°C. 8.1.1 Transient Response As with any regulator, increasing the size of the output capacitor reduces overshoot or undershoot magnitude but increases duration of the transient. The TPS717 has an ultra-wide loop bandwidth that allows it to respond quickly to load transient events. As with any regulator, the loop bandwidth is finite and the initial transient voltage peak is controlled by the sizing of the output capacitor. Typically, larger output capacitors reduce the peak and also reduce the bandwidth of the LDO, thus slowing the response time. 8.1.2 Input and Output Capacitor Requirements Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF or larger low equivalent series resistance (ESR) capacitor from IN to GND near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability. The TPS717 is designed to be stable with ceramic output capacitors of values 1 μF or larger. The X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. The maximum ESR of the output capacitor must be less than 1 Ω. The minimum output capacitance is increased to 5 μF or larger if using an R2 value outside of the range of 160 kΩ to 320 kΩ. 8.1.3 Dropout Voltage The TPS717 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the RDSon of the PMOS pass element. VDO scales approximately with output current because the PMOS device functions as a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded when (VIN – VOUT) approaches dropout. This effect is illustrated in Figure 15 through Figure 17 in the Typical Characteristics section. 16 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 TPS717 www.ti.com SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 Application Information (continued) 8.1.4 Output Noise In most LDOs, the band gap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the TPS717, the band gap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01-μF (minimum) noise reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce noise. A parallel combination that gives 2.5 μA of divider current has the same noise performance as a fixed voltage version. Equation 2 approximates the total noise referred to the feedback point (FB pin) when CNR = 0.01 μF: mVRMS x VOUT VN = 11.5 V (2) 8.2 Typical Applications 8.2.1 Application for Fixed Voltage Versions and Adjustable Voltage Version Figure 33 shows the basic circuit connections for the fixed voltage options. Figure 34 gives the connections for the adjustable output version (TPS71701). Note that the NR pin is not available on the adjustable version. Optional 1-mF input capacitor. May improve source impedance, noise or PSRR. Optional 1-mF input capacitor. May improve source impedance, noise or PSRR. VIN IN VIN VOUT OUT IN TPS717xx EN GND NR 1 mF Ceramic VOUT OUT TPS71701 GND EN R1 FB 1 mF Ceramic R2 VEN VEN Optional 0.01-mF bypass capacitor to reduce output noise and increase PSRR. Figure 33. Typical Application Circuit (Fixed Voltage Versions) Figure 34. Typical Application Circuit (Adjustable Voltage Version) 8.2.1.1 Design Requirements Table 2 summarizes the design requirements for Figure 36. Table 2. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 3.3 V, ±10% Output voltage 2.8 V, ±5% Output current 100 mA typical, 150 mA peak Output voltage transient deviation 5% Maximum ambient temperature 85°C 8.2.1.2 Detailed Design Procedure For the adjustable version (TPS71701), the NR pin is replaced with a feedback (FB) pin. The voltage on this pin sets the output voltage and is determined by the values of R1 and R2. The values of R1 and R2 can be calculated for any voltage using the formula given in Equation 3: R1 § V · R2 u ¨ OUT ¸ © VFB 1 ¹ (3) Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 17 TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com The value of R2 directly impacts the operation of the device and must be chosen in the range of approximately 160 kΩ to 320 kΩ. Sample resistor values for common output voltages are shown in Table 3. Table 3. Sample 1% Resistor Values for Common Output Voltages VOUT R1 R2 1 80.6 kΩ 324 kΩ 1.2 162 kΩ 324 kΩ 1.5 294 kΩ 332 kΩ 1.8 402 kΩ 324 kΩ 2.5 665 kΩ 316 kΩ 3.3 1.02 MΩ 324 kΩ 5 1.74 MΩ 332 kΩ 8.2.1.3 Application Curve VIN = 3.3 V 50 mV/div COUT = 1 mF VOUT 150 mA 1 mA 40 mA/div IOUT 100 ms/div Figure 35. Load Transient Response 8.2.2 Powering a PLL Integrated on an SOC Figure 36 shows the TPS71701 powering a phase-locked loop (PLL) that is integrated into a system-on-a-chip (SOC). 3.3 V IN 2.8 V OUT CIN PLL COUT TPS71701 Buck Regulator R1 SOC EN FB GND R2 Figure 36. Typical Application Circuit: PLL on an SOC Use the input and output capacitors to ensure the voltage transient requirements. A 1-µF input and 1-µF output capacitor are selected to maximize the capacitance and minimize capacitor size. R2 is chosen to be 158 kΩ for optimal noise and PSRR, and by Equation 4, R1 is selected to be 402 kΩ. Both R1 and R2 must be 1% tolerance resistors to meet the dc accuracy specification over line, load, and temperature. 18 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 TPS717 www.ti.com SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 8.3 Do's and Don'ts Do place at least one 1-µF ceramic capacitor as close as possible in the range of the regulator. Do not place the output capacitor more than 10 mm away from the regulator. Do not place any components in the feedback loop except for the output capacitor and feedback resistors. Do not exceed the device absolute maximum ratings. Do not float the enable (EN) pin. 9 Power Supply Recommendations The TPS717 is designed to operate from an input voltage between 2.5 V and 6.5 V. The input supply must provide adequate headroom for the device to operate in a normal mode of operation. Connect a low output impedance power supply directly to the IN pin of the TPS717. Inductive impedances between the input supply and the IN pin can create significant voltage excursions at the IN pin during startup or load transient events. If inductive impedances are unavoidable, use an input capacitor. To increase the overall PSRR of the power solution, use a pi-filter before the input of the LDO or after the feedback network of the LDO. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 19 TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 10 Layout 10.1 Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to the GND pin as possible, connected by wide, component-side, copper surface area. The use of vias and long traces to create LDO component connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the printed circuit board (PCB) itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shields the LDO from noise, and functions similar to a thermal plane to spread (or sink) heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal requirements. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to the GND pin of the device. 10.2 Layout Examples GND NR COUT OUT CNR (1) (1) EN CIN N/C IN Thermal Pad Circles within thermal pad area indicate vias to other layers on the board, for electrical connections or thermal conduction. Figure 37. Fixed Voltage Layout 20 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 TPS717 www.ti.com SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 Layout Examples (continued) NR OUT COUT GND R2 R1 (1) (1) EN CIN N/C IN Thermal Pad Circles within thermal pad area indicate vias to other layers on the board, for electrical connections or thermal conduction. Figure 38. Adjustable Voltage Layout 10.3 Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT), and is approximated in Equation 4: PD VIN VOUT u IOUT (4) Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 21 TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com Power Dissipation (continued) A better method of estimating the thermal measure comes from using the thermal metrics ΨJT and ΨJB; see the Thermal Information table. These metrics are a more accurate representation of the heat transfer characteristics of the die and the package than RθJA. The junction temperature can be estimated with Equation 5. YJT: TJ = TT + YJT · PD YJB: TJ = TB + YJB · PD where • • • PD is the power dissipation given by Equation 4, TT is the temperature at the center-top of the device package, TB is the PCB temperature measured 1 mm away from the device package on the PCB surface. (5) NOTE Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring TT and TB, see the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com. 22 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 TPS717 www.ti.com SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Evaluation Module An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS717. The TPS717xxEVM-134 evaluation module (and related user's guide) can be requested at the Texas Instruments website through the product folders or purchased directly from the TI eStore. 11.1.2 Device Nomenclature Table 4. Device Nomenclature (1) (1) PRODUCT VOUT TPS717xx(x)yyyz xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). An 01 denotes an adjustable voltage version. yyy is the package designator. z is the package quantity. R is for a large reel (3000 pieces), T is for a small reel (250 pieces). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. 11.2 Documentation Support 11.2.1 Related Documentation PMP10651 Test Results, TIDUAE4 TPS717xxEVM-134 Evaluation Module User's Guide, SLVU148 Using New Thermal Metrics, SBVA025 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 23 TPS717 SBVS068I – FEBRUARY 2006 – REVISED JANUARY 2016 www.ti.com 11.4 Trademarks E2E is a trademark of Texas Instruments. Bluetooth is a registered trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 24 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Product Folder Links: TPS717 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS71701DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMT Samples TPS71701DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMT Samples TPS71701DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMT Samples TPS71701DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMT Samples TPS71709DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 FY Samples TPS71709DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 FY Samples TPS71709DSETG4 ACTIVE WSON DSE 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 FY Samples TPS71710DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMU Samples TPS71710DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMU Samples TPS71710DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMU Samples TPS71710DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 BMU Samples TPS71710DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 BMU Samples TPS71711DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BRL Samples TPS71711DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BRL Samples TPS71711DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BRL Samples TPS71712DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CKE Samples TPS71712DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CKE Samples TPS71712DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CKE Samples TPS71712DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CKE Samples TPS71713DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMW Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS71713DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMW Samples TPS71715DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CAA Samples TPS71715DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CAA Samples TPS71715DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CAA Samples TPS717185DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 KB Samples TPS717185DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 KB Samples TPS71718DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMX Samples TPS71718DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMX Samples TPS71718DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMX Samples TPS71718DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMX Samples TPS71718DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 G6 Samples TPS71718DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 G6 Samples TPS71719DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CCZ Samples TPS71719DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CCZ Samples TPS71719DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CCZ Samples TPS71721DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 NXL Samples TPS71721DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 NXL Samples TPS71725DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CAF Samples TPS71725DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CAF Samples TPS71725DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CAF Samples TPS71726DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BRK Samples Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS71726DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BRK Samples TPS71727DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BSC Samples TPS71727DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BSC Samples TPS71727DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 KU Samples TPS71727DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 KU Samples TPS717285DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BRJ Samples TPS717285DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BRJ Samples TPS71728DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMZ Samples TPS71728DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMZ Samples TPS71728DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 FU Samples TPS71728DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 FU Samples TPS71729DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CJR Samples TPS71729DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CJR Samples TPS71730DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BNA Samples TPS71730DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BNA Samples TPS71730DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BNA Samples TPS71733DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BNB Samples TPS71733DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BNB Samples TPS71733DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BNB Samples TPS71733DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BNB Samples TPS71733DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BNB Samples Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS71733DRVRG4 ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BNB Samples TPS71733DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 BNB Samples TPS71733DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 FV Samples TPS71733DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 FV Samples TPS71745DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 GL Samples TPS71745DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 GL Samples TPS71750DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 PD Samples TPS71750DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 PD Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of