TPS72727DSET

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 TPS727 250-mA, Ultralow IQ, Fast Transient Response, RF Low-Dropout Linear Regulator 1 Features 3 Description • The TPS727 family of low-dropout (LDO) linear regulators are ultralow quiescent current LDOs with excellent line and ultra-fast load transient performance and are designed for power-sensitive applications. The LDO output voltage level is preset by the use of innovative factory EEPROM programming. A precision band-gap and error amplifier provides overall 2% accuracy over load, line, and temperature extremes. The TPS727 family is available in 1.5-mm × 1.5-mm SON and wafer chipscale (WCSP) packages that make the devices ideal for handheld applications. This family of devices is fully specified over a temperature range of TJ = –40°C to +125°C. 1 • • • • • • • • Very Low Dropout: – 65 mV Typical at 100 mA – 130 mV Typical at 200 mA – 163 mV Typical at 250 mA 2% Accuracy Over Load, Line, Temperature Ultralow IQ: 7.9 μA Excellent Load Transient Performance:±50 mV for 200 mA Loading and Unloading Transient Available in Fixed-Output Voltages From 0.9 V to 5 V Using Innovative Factory EEPROM Programming High PSRR: 70 dB at 1 kHz Stable with a 1.0-μF Ceramic Capacitor Thermal Shutdown and Overcurrent Protection Available in 4-Ball, 0.4-mm Pitch Wafer-Level Chip Scale and 1.5-mm × 1.5-mm SON Packages Device Information PART NUMBER 2 Applications • • • • • PACKAGE BODY SIZE (NOM) TPS727xxDSE WSON (6) 1.50 mm × 1.50 mm TPS727xxYFF DSBGA (4) 1.20 mm × 0.80 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Wireless Handsets, Smart Phones, PDAs MP3 Players and Other Handheld Products Wireless LAN, Bluetooth®, Zigbee® Remote Controls Portable Consumer Products TYPICAL APPLICATION CIRCUIT VIN IN OUT CIN COUT VOUT 1mF Ceramic TPS727xx On EN Off GND GROUND PIN CURRENT vs TEMPERATURE PSRR vs FREQUENCY 15 90 12 80 VIN = 2.1V IOUT = 0mA 70 IOUT = 10mA 60 IGND (mA) Power-Supply Rejection Ratio (dB) 100 50 40 9 6 30 20 3 10 IOUT = 200mA 0 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configurations and Functions ....................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 11 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 12 8 Applications and Implementation ...................... 13 8.1 Application Information............................................ 13 8.2 Typical Application .................................................. 13 8.3 Do's and Don'ts ....................................................... 17 9 Power-Supply Recommendations...................... 17 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Example .................................................... 18 11 Device and Documentation Support ................. 22 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (September 2014) to Revision F • Page Changed DSBGA body size in Device Information table ...................................................................................................... 1 Changes from Revision D (February 2014) to Revision E Page • Added TPS727105 to document ............................................................................................................................................ 1 • Changed terminal to pin throughout document ...................................................................................................................... 1 • Updated Device Information table to current standards ......................................................................................................... 1 • Changed Pin Configurations note .......................................................................................................................................... 4 • Changed Pin Functions table: reordered table by pin name, added I/O column ................................................................... 4 • Updated Handling Ratings table to current standard ............................................................................................................. 5 • Changed Thermal Information table: updated symbols.......................................................................................................... 5 • Deleted new generation from first sentence of Overview section ........................................................................................ 11 • Added note to Applications and Implementation section...................................................................................................... 13 Changes from Revision C (January, 2011) to Revision D Page • Changed format to meet latest data sheet standards; added new sections and moved existing sections............................ 1 • Deleted pinout diagrams from front page; see Pin Configurations and Functions section. ................................................... 1 • Changed Pin Configurations section and moved to Pin Configurations and Functions section ............................................ 4 • Changed note in Pin Configurations and Functions section. ................................................................................................. 4 • Deleted Figure 26 and Figure 27.......................................................................................................................................... 17 Changes from Revision B (April, 2010) to Revision C Page • Updated YFF front page pin drawing to show pin locations................................................................................................... 1 • Revised Pin Configurations section ....................................................................................................................................... 4 • Changed graph title for Figure 6............................................................................................................................................. 7 2 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 Changes from Revision A (September, 2009) to Revision B Page • Updated Features list ............................................................................................................................................................. 1 • Changed title of data sheet..................................................................................................................................................... 1 • Changed footnote 2 to Absolute Maximum Ratings table ...................................................................................................... 5 • Revised numerous specifications and parameters in Electrical Characteristics table ........................................................... 6 • Revised operating parameters for Figure 4............................................................................................................................ 7 • Replaced Figure 5 .................................................................................................................................................................. 7 • Added operating parameters to Figure 6................................................................................................................................ 7 • Updated Figure 9.................................................................................................................................................................... 7 Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com 5 Pin Configurations and Functions TPS72715, TPS72718, TPS72728, TPS72748 YFF Package DSBGA-4 Top View OUT GND B2 B1 A2 All Other TPS727 Devices YFF Package DSBGA-4 Top View OUT GND B2 B1 A2 A1 IN EN A1 IN EN See note. See note. DSE Package 1,5mm × 1,5mm WSON-6 Top View OUT 1 6 IN NC 2 5 NC GND 3 4 EN Tape and Reel Sprocket Holes Top Dot Mark Tape and Reel Sprocket Holes Top Dot Mark TPS72715YFF, TPS72718YFF TPS72728YFF, TPS72748YFF TPS727xxDSE TPS72711YFF (Example) See Note See Note NOTE The EN pin is marked with a dot for the 1.5-V, 1.8-V, 2.8-V, and 4.8-V versions of the YFF package. The GND pin is marked with a dot for all other voltage versions of the YFF package. Refer to YFF0004 Package Outline page included at the end of this document for dimensions of the YFF package. On the package outline, the shaded box indicates the location of ball A1 and does not correlate to any marking on the topside of the physical package. Pin Functions PIN NAME YFF DSE I/O DESCRIPTION Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode, thus reducing the operating current to 120 nA, nominal. EN A1 4 I GND B1 3 — IN A2 6 I NC — 2, 5 — No connection. This pin can be tied to ground to improve thermal dissipation. OUT B2 1 O Regulated output voltage pin. A small 1-μF ceramic capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. 4 Ground pin. Input pin. A small capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 6 Specifications 6.1 Absolute Maximum Ratings at TJ = –40°C to +125°C (unless otherwise noted); all voltages are with respect to GND (1) Input voltage range, VIN MIN MAX UNIT –0.3 +6.0 V Enable voltage range, VEN –0.3 Output voltage range, VOUT –0.3 +6.0 (2) V +6.0 Maximum output current, IOUT V Internally limited Output short-circuit duration Indefinite Operating junction temperature, TJ –55 +150 °C Storage temperature, Tstg –55 +150 °C (1) (2) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. VEN absolute maximum rating is VIN or 6.0 V, whichever is less. 6.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN VIN Input voltage IOUT Output current TJ Operating junction temperature range NOM MAX 2 UNIT 5.5 V 0 250 mA –40 +125 °C 6.4 Thermal Information TPS727 THERMAL METRIC (1) DSE (WSON) YFF (DSBGA) UNITS 6 PINS 4 PINS RθJA Junction-to-ambient thermal resistance 190.5 160 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.9 75 °C/W RθJB Junction-to-board thermal resistance 149.3 76 °C/W ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter RθJC(bot) Junction-to-case (bottom) thermal resistance (2) (1) (2) 6.4 3 °C/W 152.8 74 °C/W N/A N/A °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. θJCbot is not applicable because there is no thermal pad. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com 6.5 Electrical Characteristics Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = 0.9 V, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C. PARAMETER VIN Input voltage range VO Output voltage range TEST CONDITIONS MIN TJ = +25°C VOUT (1) DC output accuracy VOUT + 0.3 V ≤ VIN ≤ 5.5 V, 0 mA ≤ IOUT ≤ 200 mA Load transient ΔVO/ΔVIN Line regulation ΔVO/ΔIOUT Load regulation Dropout voltage (2) VDO ICL Output current limit IGND ISHDN PSRR VN Ground pin current Shutdown current (IGND) Power-supply rejection ratio Output noise voltage (3) UNIT V 0.9 5.0 V +2.5 mV –2.0% ±1.0% +2.0% ±1.0% ±50.0 1 mA to 250 mA or 250 mA to 1 mA in 1 μs, COUT = 1 μF ±65 mV VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA 8 μV/V 0 mA ≤ IOUT ≤ 250 mA 20 μV/mA VIN = 0.98 × VOUT(NOM), IOUT = 10 mA 6.5 VIN = 0.98 × VOUT(NOM), IOUT = 50 mA 32.5 VIN = 0.98 × VOUT(NOM), IOUT = 100 mA 65 VIN = 0.98 × VOUT(NOM), IOUT = 200 mA 130 VIN = 0.98 × VOUT(NOM), IOUT = 250 mA 162.5 VOUT = 0.9 × VOUT(NOM) 300 mV 200 400 550 IOUT = 0 mA, TJ = –40°C to +125°C 7.9 12 IOUT = 200 mA 110 IOUT = 250 mA 130 VEN ≤ 0.4 V, VIN = 2 V, TJ = +25°C 0.12 VEN ≤ 0.4 V, 2.0 V < VIN ≤ 4.5 V, TJ = –40°C to +85°C 0.55 VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA f = 10 Hz 85 f = 100 Hz 75 f = 1 kHz 70 f = 10 kHz 55 f = 100 kHz 40 f = 1 MHz 45 BW = 100 Hz to 100 kHz, VIN = 2.1 V, VOUT = 1.8 V, IOUT = 10 mA Enable pin high (enabled) VLO Enable pin low (disabled) IEN Enable pin current EN = 5.5 V UVLO Undervoltage lock-out VIN rising TSD Thermal shutdown temperature TJ Operating junction temperature 2 μVRMS μs VIN 0 1.85 V 0.4 V 40 500 nA 1.90 1.95 V Shutdown, temperature increasing +160 Reset, temperature decreasing +140 –40 µA dB 100 0.9 mA µA 33.5 COUT = 1.0 μF, 0 ≤ IOUT ≤ 250 mA Startup time VHI 6 5.5 1 mA to 200 mA or 200 mA to 1 mA in 1 μs, COUT = 1 μF tSTR (1) (2) (3) MAX –2.5 VOUT + 0.3 V ≤ VIN ≤ 5.5 V, 0 mA ≤ IOUT ≤ 250 mA ΔVOUT TYP 2.0 °C +125 °C The output voltage is programmed at the factory. VDO is measured for devices with VOUT(NOM) ≥ 2.35 V so that VIN ≥ 2.3 V. Startup time: time from EN assertion to 0.98 × VOUT(NOM). Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 6.6 Typical Characteristics 1.90 1.90 1.88 1.88 1.86 1.86 1.84 1.84 1.82 1.82 VOUT (V) VOUT (V) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C. 1.80 1.78 1.76 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 2.1 2.6 3.1 3.6 4.1 4.6 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 5.1 5.6 2.1 2.6 3.1 3.6 VIN (V) IOUT = 10 mA 5.1 5.6 Figure 2. Line Regulation (TPS72718) 1.90 1.90 1.88 1.88 1.86 1.86 1.84 1.84 1.82 1.82 VOUT (V) VOUT (V) 4.6 IOUT = 200 mA Figure 1. Line Regulation (TPS72718) 1.80 1.78 1.80 1.78 1.76 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 0 1 2 3 4 5 6 7 8 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 9 0 10 25 50 Figure 4. Load Regulation (TPS72718) Figure 3. Load Regulation Under Light Loads (TPS72718) 160 140 140 120 120 100 100 VDO (mV) 160 80 60 50 100 150 200 60 +125°C +85°C +25°C -40°C 20 0 0 80 40 +125°C +85°C +25°C -40°C 20 100 125 150 175 200 225 250 0 mA ≤ IOUT ≤ 250 mA 0 mA ≤ IOUT ≤ 10 mA 40 75 IOUT (mA) IOUT (mA) VDO (mV) 4.1 VIN (V) 250 IOUT (mA) 0 2.25 2.75 3.25 3.75 4.25 4.75 VIN (V) IOUT = 200 mA Figure 5. Dropout Voltage vs Output Current (TPS72750) Copyright © 2009–2015, Texas Instruments Incorporated Figure 6. Dropout Voltage vs Input Voltage Submit Documentation Feedback 7 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com Typical Characteristics (continued) 1.90 12.0 1.88 11.5 1.86 11.0 1.84 10.5 IOUT = 10 mA 1.82 IGND (mA) VOUT (V) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C. 1.80 1.78 IOUT = 200 mA 1.76 +125°C +85°C +25°C -40°C 10.0 9.5 9.0 8.5 1.74 8.0 1.72 7.5 1.70 7.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.1 2.6 3.1 3.6 Temperature (°C) 4.1 4.6 5.1 5.6 VIN (V) IOUT = 0 mA Figure 7. Output Voltage vs Temperature (TPS72718) Figure 8. Ground Pin Current vs Input Voltage (TPS72718) 15 140 120 12 IGND (mA) IGND (mA) 100 80 60 +125°C +85°C +25°C -40°C 40 20 9 6 3 0 0 0 25 50 75 100 125 150 175 200 225 250 -40 -25 -10 5 35 50 65 80 95 110 125 VIN = 2.1 V, IOUT = 0 mA 0 mA ≤ IOUT ≤ 250 mA Figure 10. Ground Pin Current vs Temperature (TPS72718) Figure 9. Ground Pin Current vs Load (TPS72718) 550 2.0 +125°C +85°C +25°C -40°C 1.6 500 1.2 ILIM (mA) IGND (mA) 20 Temperature (°C) IOUT (mA) 0.8 450 400 0.4 350 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) Figure 11. Shutdown Current vs Input Voltage (TPS72718) 8 Submit Documentation Feedback 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) Figure 12. Current Limit vs Input Voltage (TPS72718) Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 Typical Characteristics (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C. 100 90 80 70 IOUT = 10 mA 60 50 40 30 20 10 IOUT = 200 mA Power-Supply Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 100 90 80 70 60 40 30 20 10 0 IOUT = 200 mA 0 10 100 1k 10k 100k 1M 10 10M 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) Figure 13. PSRR vs Frequency (VIN – VOUT = 0.5 V, TPS72718) Figure 14. PSRR vs Frequency (VIN – VOUT = 0.3 V, TPS72718) 80 10M 10.00 Noise Spectral Density (mV/ÖHz) Power-Supply Rejection Ratio (dB) IOUT = 10 mA 50 70 60 50 40 30 20 1 kHz 10 kHz 100 kHz 10 1.00 0.10 0.01 0 0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 10 2.8 100 1k VIN (V) 10k 100k 1M 10M Frequency (Hz) IOUT = 10 mA, CIN = COUT = 1 µF Figure 15. PSRR vs Input Voltage (TPS72718) Figure 16. Output Spectral Noise Density vs Output Voltage (TPS72718) 200 mA 100 mA/div IOUT 0.1 mA 50 mV/div VOUT IOUT 1 mA 50 mV/div 100 mA/div 200 mA VOUT 100 ms/div 50 ms/div VIN = 2.3 V, tR = tF = 1 µs VIN = 2.3 V, tR = tF = 1 µs Figure 17. Load Transient Response: 0.1 mA to 200 mA (TPS72718) Copyright © 2009–2015, Texas Instruments Incorporated Figure 18. Load Transient Response: 1 mA to 200 mA (TPS72718) Submit Documentation Feedback 9 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com Typical Characteristics (continued) Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater; IOUT = 10 mA, VEN = VIN, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C. 2 mV/div IOUT 10 mA 50 mV/div VOUT VOUT 2.7 V VIN 0.5 V/div 100 mA/div 200 mA 2.1 V 1 ms/div 50 ms/div Slew rate = 1 V/µs, IOUT = 100 µA VIN = 2.3 V, tR = tF = 1 µs Figure 20. Line Transient Response (TPS72718) Figure 19. Load Transient Response: 10 mA to 200 mA (TPS72718) 1 V/div 1 V/div EN 5 mV/div VOUT VOUT 2.7 V 50 mA/div 0.5 V/div VIN 2.1 V 100 ms/div IIN 20 ms/div Slew rate = 1 V/µs, IOUT = 200 µA VIN = 2.1 V, VOUT = 1.8 V, IOUT = 100 µA Figure 21. Line Transient Response (TPS72718) Figure 22. VIN Inrush Current (TPS72718) 100 mA/div VIN VOUT 1 V/div 1 V/div 1 V/div EN VOUT IIN 20 ms/div VIN = 2.1 V, VOUT = 1.8 V, IOUT = 200 mA Figure 23. VIN Inrush Current (TPS72718) 10 Submit Documentation Feedback 200 ms/div IOUT = 200 mA Figure 24. VIN Ramp Up, Ramp Down Response (TPS72718) Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 7 Detailed Description 7.1 Overview The TPS727 devices belong to a family of LDO regulators that consume extremely low quiescent current while simultaneously delivering excellent PSRR with very little headroom (VIN – VOUT differential voltage), and very good transient response. These features, combined with low noise without a noise reduction pin in an ultrasmall package, make these devices ideal for portable applications. This family of regulators offers sub-band-gap output voltages, current limit and thermal protection, and is fully specified from –40°C to +125°C. 7.2 Functional Block Diagram IN OUT Current Limit Thermal Shutdown UVLO EEPROM EN Bandgap LOGIC 7.3 Feature Description 7.3.1 Internal Current Limit The TPS727 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output voltage is not regulated and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device is turned off. As the device cools down, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Protection section for more details. The PMOS pass element in the TPS727 has a built-in body diode that conducts current when the voltage at the OUT pin exceeds the voltage at the IN pin. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of rated output current is recommended. 7.3.2 Soft Start The startup current is given by Equation 1: ISOFT START (mA) = COUT(mF) ´ 0.07(V/ms) + ILOAD(mA) (1) Equation 1 shows that soft-start current is directly proportional to COUT. The output voltage ramp rate is independent of COUT and load current, and has a typical value of 0.07 V/μs. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com Feature Description (continued) The TPS727 automatically adjusts the soft-start current to supply both the load current and the COUT charge current. For example, if ILOAD = 0 mA upon enabling the LDO, ISOFT START = 1 μF × 0.07 V/μs + 0 mA = 70 mA, the current that charges the output capacitor. If ILOAD = 200 mA, ISOFT START = 1 μF × 0.07 V/μs + 200 mA = 270 mA, the current required for charging output capacitor and supplying the load current. If the output capacitor and load are increased such that the soft-start current exceeds the output current limit, the current is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF and IOUT = 200 mA, 10 μF × 0.07 V/μs + 200 mA = 900 mA is not supplied. Instead, the current is clamped at 400 mA. 7.3.3 Shutdown The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to the IN pin. 7.3.4 Dropout Voltage The TPS727 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO approximately scales with output current because the PMOS device functions like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is illustrated in Figure 15 in the Typical Characteristics section. 7.3.5 Undervoltage Lock-out (UVLO) The TPS727 uses an undervoltage lock-out circuit that keeps the output shut off until the input voltage reaches the UVLO threshold voltage. 7.3.6 Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, limit junction temperature to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection triggers at least +35°C above the maximum expected ambient condition of a particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS727 is designed to protect against overload conditions. This circuitry is not intended to replace proper heatsinking. Continuously running the TPS727 into thermal shutdown degrades device reliability. 7.4 Device Functional Modes 7.4.1 Operation with EN Control Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode, thus reducing the operating current to 120 nA, nominal. 12 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 8 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS727 family of low-dropout (LDO) linear regulators are utralow quiescent current LDOs with excellent line and ultra-fast load transient performance and are designed for power-sensitive applications. 8.2 Typical Application Figure 25. TPS72718YFF 2.5 VIN to 1.8 VOUT at 200 mA Schematic 8.2.1 Design Requirements 8.2.1.1 Input and Output Capacitor Requirements Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability. The TPS727 is designed to be stable with standard ceramic capacitors with values of 1.0 μF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR must be less than 200 mΩ. 8.2.1.2 Transient Response As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but increases duration of the transient response. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com Typical Application (continued) 8.2.2 Detailed Design Procedure Select the desired device based on the output voltage. Provide an input supply with adequate headroom to include dropout and output current to account for the GND pin current and to power the load. Select adequate input and output capacitors. The startup current is given by Equation 2: ISOFT START (mA) = COUT(mF) ´ 0.07(V/ms) + ILOAD(mA) (2) Equation 2 shows that soft-start current is directly proportional to COUT. The output voltage ramp rate is independent of COUT and load current and has a typical value of 0.07 V/μs. The TPS727 automatically adjusts the soft-start current to supply both the load current and the COUT charge current. For example, if ILOAD = 0 mA upon enabling the LDO, ISOFT START = 1 μF × 0.07 V/μs + 0 mA = 70 mA, the current that charges the output capacitor. If ILOAD = 200 mA, ISOFT START = 1 μF × 0.07 V/μs + 200 mA = 270 mA, the current required for charging output capacitor and supplying the load current. If the output capacitor and load are increased such that the soft-start current exceeds the output current limit, the current is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF and IOUT = 200 mA, 10 μF × 0.07 V/μs + 200 mA = 900 mA is not supplied. Instead, the current is clamped at 400 mA. 14 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 Typical Application (continued) 8.2.3 Application Curves 10.00 90 80 70 IOUT = 10 mA 60 50 40 30 20 10 IOUT = 200 mA Noise Spectral Density (mV/ÖHz) Power-Supply Rejection Ratio (dB) 100 1.00 0.10 0.01 0 0 10 100 1k 10k 100k 1M 10 10M 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) IOUT = 10 mA, CIN = COUT = 1 µF Figure 26. PSRR vs Frequency (VIN – VOUT = 0.5 V, TPS72718) Figure 27. Output Spectral Noise Density vs Output Voltage (TPS72718) 200 mA 100 mA/div 0.1 mA IOUT 50 mV/div VOUT VOUT 100 ms/div 50 ms/div VIN = 2.3 V, tR = tF = 1 µs VIN = 2.3 V, tR = tF = 1 µs Figure 28. Load Transient Response: 0.1 mA to 200 mA (TPS72718) Figure 29. Load Transient Response: 1 mA to 200 mA (TPS72718) IOUT 2 mV/div 200 mA 10 mA 50 mV/div VOUT 50 ms/div VIN = 2.3 V, tR = tF = 1 µs Figure 30. Load Transient Response: 10 mA to 200 mA (TPS72718) Copyright © 2009–2015, Texas Instruments Incorporated VOUT 2.7 V VIN 0.5 V/div 100 mA/div 1 mA 50 mV/div 100 mA/div 200 mA IOUT 2.1 V 1 ms/div Slew rate = 1 V/µs, IOUT = 100 µA Figure 31. Line Transient Response (TPS72718) Submit Documentation Feedback 15 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com Typical Application (continued) 1 V/div 1 V/div EN 5 mV/div VOUT VOUT 2.7 V 50 mA/div 0.5 V/div VIN 2.1 V 100 ms/div IIN 20 ms/div Slew rate = 1 V/µs, IOUT = 200 µA VIN = 2.1 V, VOUT = 1.8 V, IOUT = 100 µA Figure 32. Line Transient Response (TPS72718) Figure 33. VIN Inrush Current (TPS72718) 100 mA/div VIN VOUT 1 V/div 1 V/div 1 V/div EN VOUT IIN 20 ms/div VIN = 2.1 V, VOUT = 1.8 V, IOUT = 200 mA Figure 34. VIN Inrush Current (TPS72718) 16 Submit Documentation Feedback 200 ms/div IOUT = 200 mA Figure 35. VIN Ramp Up, Ramp Down Response (TPS72718) Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 8.3 Do's and Don'ts Do place at least one 1.0-µF ceramic capacitor as close as possible to the OUT pin of the regulator. Do not place the output capacitor more than 10 mm away from the regulator. For DSE devices, do tie the NC pins to ground to improve thermal dissipation. Do connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the regulator. Do not exceed the absolute maximum ratings. 9 Power-Supply Recommendations These devices are designed to operate from an input voltage supply range between 2.0 V and 5.5 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. 10 Layout 10.1 Layout Guidelines 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor must be connected directly to the GND pin of the device. High ESR capacitors may degrade PSRR. 10.1.2 Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 3: PD = (VIN - VOUT) ´ IOUT (3) 10.1.3 Package Mounting Solder pad footprint recommendations and recommended land patterns are attached to the end of this document. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com 10.2 Layout Example 10.2.1 DSE EVM Board Layout This section provides the TPS727xxDSEEVM-406 board layout and illustrations. Figure 36. Top Layer Assembly Figure 37. Top Layer Routing 18 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 Layout Example (continued) Figure 38. Bottom Layer Routing Figure 39. Bottom Layer Assembly Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com Layout Example (continued) 10.2.2 YFF EVM Board Layout This section provides the TPS727xxYFFEVM-407 board layout and illustrations. Figure 40. Top Layer Assembly Figure 41. Top Layer Routing 20 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 Layout Example (continued) Figure 42. Bottom Layer Routing Figure 43. Bottom Layer Assembly Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation Application report SLAA414, LDO PSRR Measurement Simplified. Application report SLAA412, LDO Noise Demystified. User guide SLVU323, TPS727xxYFF EVM User guide SLVU325, TPS727xxDSE EVM 11.1.2 Device Nomenclature Table 1. Device Nomenclature (1) PRODUCT TPS727xxx yyy z (1) (2) VOUT (2) XXX is the nominal output voltage. YYY is package designator. Z is package tape and reel quantity (R = 3000, T = 250). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Output voltages from 0.9 V to 5.0 V in 50-mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. Bluetooth is a registered trademark of Bluetooth SIG. Zigbee is a registered trademark of Zigbee Alliance. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com Copyright © 2009–2015, Texas Instruments Incorporated SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 Submit Documentation Feedback 23 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 24 Submit Documentation Feedback www.ti.com Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 PACKAGE OUTLINE TPS727xxYFF YFF0004 DSBGA - 0.625 mm max height SCALE 13.000 DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER D 0.625 MAX C SEATING PLANE 0.30 0.12 BALL TYP 0.4 TYP B SYMM 0.4 TYP D: Max = 0.82 mm, Min = 0.76 mm E: Max = 1.19 mm, Min = 1.13 mm A 4X 0.015 C A 0.3 0.2 1 2 SYMM B 02/2014 NOTES: NanoFree Is a trademark of Texas Instruments. 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. TM 3. NanoFree package configuration. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 25 TPS727 SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 www.ti.com TPS727xxYFF EXAMPLE BOARD LAYOUT YFF0004 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 4 0.23 0.02 2 1 A SYMM (0.4) TYP B SYMM LAND PATTERN EXAMPLE SCALE:50X 0.05 MAX ( 0.23) METAL METAL UNDER MASK 0.05 MIN ( 0.23) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 02/2014 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments Literature No. SBVA017 (www.ti.com/lit/sbva017). 26 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated TPS727 www.ti.com SBVS128F – JUNE 2009 – REVISED DECEMBER 2015 EXAMPLE STENCIL DESIGN TPS727xxYFF YFF0004 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 4X ( 0.25) (R0.05) TYP 1 2 A SYMM (0.4) TYP B METAL TYP SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:50X 02/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 27 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS727105YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 GA TPS727105YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 GA TPS72710DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 UR TPS72710DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 UR TPS72711YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 QL TPS72711YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 QL TPS72715DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 GS TPS72715DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 GS TPS72715YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 GS TPS72715YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 GS TPS727185YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 RW TPS727185YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 RW TPS72718DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 GT TPS72718DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 GT TPS72718YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 GT TPS72718YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 GT TPS72719DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CB TPS72719DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CB TPS72719YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 AA TPS72719YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 AA Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Dec-2020 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS72725DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 QA TPS72725DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 QA TPS72727DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 TS TPS72727DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 TS TPS727285DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 QK TPS727285DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 QK TPS72728DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 GU TPS72728DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 GU TPS72728YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 GU TPS72728YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 GU TPS72730DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 QB TPS72730DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 QB TPS72730YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 ZZ TPS72730YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 ZZ TPS72733DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 QC TPS72733DSET ACTIVE WSON DSE 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 QC TPS72733YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 ZY TPS72733YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 ZY TPS72748DSER ACTIVE WSON DSE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 KA TPS72748YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 EY TPS72748YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 EY Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Dec-2020 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS72750YFFR ACTIVE DSBGA YFF 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 CA TPS72750YFFT ACTIVE DSBGA YFF 4 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 CA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of