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TPS730
SBVS054J – NOVEMBER 2004 – REVISED APRIL 2015
TPS730 Low-Noise, High PSRR, RF, 200-mA Low-Dropout Linear Regulators
1 Features
3 Description
•
The TPS730 family of low-dropout (LDO) low-power
linear voltage regulators features high power-supply
rejection ratio (PSRR), low noise, fast start-up, and
excellent line and load transient responses in a small
SOT-23 package. NanoStar™ packaging gives an
ultrasmall footprint as well as an ultralow profile and
package weight, making it ideal for portable
applications such as handsets and PDAs. Each
device in the family is stable, with a small, 2.2-μF
ceramic capacitor on the output. The TPS730 family
uses an advanced, proprietary BiCMOS fabrication
process to yield low dropout voltages (for example,
120 mV at 200 mA, TPS73030). Each device
achieves fast start-up times (approximately 50 μs with
a 0.001-μF bypass capacitor) while consuming low
quiescent current (170 μA typical). Moreover, when
the device is placed in standby mode, the supply
current is reduced to less than 1 μA. The TPS73018
exhibits approximately 33 μVRMS of output voltage
noise at 1.8 V output with a 0.01-μF bypass
capacitor. Applications with analog components that
are noise-sensitive, such as portable RF electronics,
benefit from the high PSRR and low-noise features
as well as the fast response time.
1
•
•
•
•
•
•
•
•
200-mA RF Low-Dropout Regulator
With Enable
Available in Fixed Voltages from 1.8 V to 3.3 V
and Adjustable Voltages (1.22 V to 5.5 V)
High PSRR (68 dB at 100 Hz)
Low Noise (33 μVRMS, TPS73018)
Fast Start-Up Time (50 μs)
Stable With a 2.2-μF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage (120 mV at 200 mA)
5- and 6-Pin SOT-23 (DBV), and Wafer Chip
Scale (YZQ) Packages
2 Applications
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Cellular and Cordless Telephones
Bluetooth®, Wireless LAN
Handheld Organizers, PDAs
Device Information(1)
PART NUMBER
TPS730
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SOT-23 (6)
2.90 mm × 1.60 mm
DSBGA (5)
1.35 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VIN
Ripple Rejection vs Frequency
VOUT
VIN
IN
100
VOUT
OUT
90
TPS730xx
EN
GND
NR
2.2µF
0.01µF(1)
NOTE: (1) This capacitor is optional.
IOUT = 200 mA
80
Ripple Rejection (dB)
0.1µF
70
60
50
40
IOUT = 10 mA
30
20
VIN = 3.8 V
COUT = 10 mF
CNR = 0.01 mF
10
0
10
100
1k
10 k
100 k
1M
10 M
Frequency (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS730
SBVS054J – NOVEMBER 2004 – REVISED APRIL 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Typical Characteristics ..............................................
Overview ................................................................... 9
Functional Block Diagrams ....................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application .................................................. 13
8.3 Do's and Don'ts ....................................................... 14
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Considerations ........................................
Power Dissipation .................................................
15
15
16
16
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
12.1 TPS730YZQ Nanostar™ Wafer Chip Scale
Information ............................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (February, 2011) to Revision J
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed fourth bullet of Features list to low noise ............................................................................................................... 1
•
Changed front-page figure ..................................................................................................................................................... 1
•
Added Pin Configuration and Functions section .................................................................................................................... 3
•
Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement ................... 4
•
Deleted Dissipation Ratings table; added Thermal Information table ................................................................................... 4
•
Added condition statement to Typical Characteristics ........................................................................................................... 6
•
Moved Ordering Information to Device Nomenclature section ............................................................................................ 18
Changes from Revision H (October, 2007) to Revision I
•
2
Page
Corrected units in y-axis of Figure 5....................................................................................................................................... 6
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
IN
1
GND
2
EN
3
5
DBV Package
6-Pin SOT-23
Top View
OUT
IN
1
6
OUT
GND
2
5
FB
EN
3
4
NR
NR
4
Fixed Voltage Versions
Adjustable Voltage Version
YZQ Package
5-Pin DSBGA
Top View
IN
C3
A3
EN
C1
B2
A1
OUT
NR
GND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
SOT-23
DSBGA
EN
3
A3
I
Enable pin. Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts
the regulator into shutdown mode. EN can be connected to IN if not used.
FB
5
N/A
I
Feedback pin. This terminal is the feedback input pin for the adjustable device. Fixed-voltage
versions in the DBV package do not have this pin.
GND
2
A1
—
Regulator ground.
IN
1
C3
I
Input to the device.
OUT
6
C1
O
Output of the regulator.
NR
4
B2
—
Noise Reduction pin. Connecting an external capacitor to this pin filters noise generated by
the internal bandgap. This configuration improves power-supply rejection and reduces output
noise.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
Voltage
Current
MIN
MAX
Input range, VIN
–0.3
6
Enable range, VEN
–0.3
6
Output range, VOUT
–0.3
6
Peak output, IOUT(max)
See Thermal Information
Junction, TJ
DBV package
–40
150
YZQ package
–40
125
–65
150
Storage, Tstg
(1)
V
Internally limited
Continuous total power dissipation
Temperature
UNIT
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).
MIN
NOM
MAX
UNIT
VIN
Input supply voltage
VEN
Enable supply voltage
VOUT
Output voltage
IOUT
Output current
0
200
TJ
Operating junction temperature
–40
CIN
Input capacitor
0.1
1
µF
COUT
Output capacitor
2.2 (1)
10
µF
CNR
Noise reduction capacitor
0
10
nF
CFF
Feed-forward capacitor
R2
Lower feedback resistor
(1)
2.7
5.5
V
0
VIN
V
VFB
5
125
V
mA
°C
15
pF
30.1
kΩ
If CFF is not used or VOUT(nom) < 1.8 V, the minimum recommended COUT = 4.7 µF.
6.4 Thermal Information
TPS73001
THERMAL METRIC
(1)
DBV (SOT-23)
YZQ (DSBGA)
6 PINS
5 PINS
178.5
RθJA
Junction-to-ambient thermal resistance
225.1
RθJC(top)
Junction-to-case (top) thermal resistance
78.4
1.4
RθJB
Junction-to-board thermal resistance
54.7
62.1
ψJT
Junction-to-top characterization parameter
3.3
0.9
ψJB
Junction-to-board characterization parameter
53.8
62.1
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Over recommended operating temperature range TJ = –40 to +125°C, VEN = VIN, VIN = VOUT(nom) + 1 V (1), IOUT = 1 mA, COUT =
10 μF, CNR = 0.01 μF (unless otherwise noted). Typical values are at 25°C.
PARAMETER
TEST CONDITIONS
VIN
Input voltage range (1)
IOUT
Continuous output current
VFB
Internal reference (TPS73001)
VOUT
Output voltage
range
MIN
TYP
2.7
0
1.201
TPS73001
1.225
VFB
Output voltage accuracy
0 µA ≤ IOUT ≤ 200 mA, 2.75 V ≤ VIN ≤ 5.5 V
ΔVOUT(ΔVIN)
Line regulation (1)
VOUT + 1 V ≤ VIN ≤ 5.5 V
ΔVOUT(ΔIOUT)
Load regulation
0 µA ≤ IOUT ≤ 200 mA, TJ = 25°C
–2% VOUT(nom)
MAX
UNIT
5.5
V
200
mA
1.25
V
5.5 – VDO
V
2%
V
0.05
%/V
5
mV
(2)
VDO
Dropout voltage
(VIN = VOUT(nom) – 0.1 V)
IOUT = 200 mA
ICL
Output current limit
VOUT = 0 V
IGND
Ground pin current
0 µA < IOUT < 200 mA
170
VEN = 0 V, 2.7 V ≤ VIN ≤ 5.5 V
0.07
(3)
120
285
210
mV
600
mA
250
μA
1
μA
1
μA
ISHUTDOWN
Shutdown current
IFB
FB pin current
PSRR
Power-supply
rejection ratio
TPS73028 f = 100 Hz, IOUT = 200 mA, TJ = 25°C
Vn
Output noise
voltage
TPS73018
tSTR
Start-up time
TPS73018 RL = 14 Ω, COUT = 1 µF, CNR = 0.001 μF
VEN(high)
High-level enable input voltage
2.7 V ≤ VIN ≤ 5.5 V
1.7
VIN
VEN(low)
Low-level enable input voltage
2.7 V ≤ VIN ≤ 5.5 V
0
0.7
V
IEN
EN pin current
VEN = 0 V
–1
1
μA
VFB = 1.8 V
UVLO
(1)
(2)
(3)
BW = 200 Hz to 100 kHz, IOUT = 200 mA,
CNR = 0.01 μF
Threshold, VCC rising
Hysteresis
68
dB
33
μVRMS
50
μs
2.25
2.65
100
V
V
mV
Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.
Dropout is not measured for the TPS73018 and TPS73025 since minimum VIN = 2.7 V.
For adjustable versions, this applies only after VIN is applied; then VEN transitions high to low.
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6.6 Typical Characteristics
Over recommended operating temperature range TJ = –40°C to +125°C, VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT =
10 μF, CNR = 0.01 μF, VOUT(nom) = 2.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
2.805
2.805
VIN = 3.8 V
COUT = 10 mF
TJ = 25°C
2.804
2.803
2.800
IOUT = 1 mA
2.802
2.795
VOUT (V)
VOUT (V)
2.801
2.800
2.799
2.790
IOUT = 200 mA
2.785
2.798
2.797
2.780
VIN = 3.8 V
COUT = 10 mF
2.796
2.795
2.775
0
50
100
150
−40 −25 −10 5
200
20 35 50 65 80 95 110 125
IOUT (mA)
TJ (°C)
Figure 1. TPS73028 Output Voltage vs Output Current
Figure 2. TPS73028 Output Voltage vs Junction
Temperature
1.6
VIN = 3.8 V
COUT = 10 mF
Output Spectral Noise Density (mV/√Hz)
250
IOUT = 1 mA
IGND (mA)
200
IOUT = 200 mA
150
100
50
0
−40 −25 −10 5
VIN = 3.8 V
IOUT = 200 mA
COUT = 10 mF
1.4
1.2
CNR = 0.001 mF
1.0
CNR = 0.0047 mF
0.8
CNR = 0.01 mF
0.6
CNR = 0.1 mF
0.4
0.2
0
100
20 35 50 65 80 95 110 125
1k
10 k
100 k
TJ (°C)
Frequency (Hz)
Figure 3. TPS73028 Ground Current vs Junction
Temperature
Figure 4. TPS73028 Output Spectral Noise Density vs
Frequency
180
VOUT = 2.8 V
IOUT = 200 mA
COUT = 10 mF
50
160
VIN = 2.7 V
COUT = 10 mF
140
40
120
VDO (mV)
RMS Output Noise (mVRMS)
60
30
20
IOUT = 200 mA
100
80
60
40
10
IOUT = 10 mA
20
BW = 100 Hz to 100 kHz
0
0.001
0.01
CNR (mF)
20 35 50 65 80 95 110 125
TJ (°C)
Figure 5. Root Mean Square Output Noise vs CNR
6
0
−40 −25 −10 5
0.1
Figure 6. TPS73028 Dropout Voltage vs Junction
Temperature
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Typical Characteristics (continued)
Over recommended operating temperature range TJ = –40°C to +125°C, VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT =
10 μF, CNR = 0.01 μF, VOUT(nom) = 2.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
100
90
4
VEN (V)
IOUT = 200 mA
Ripple Rejection (dB)
80
70
VIN = 3.8 V
VOUT = 2.8 V
IOUT = 200 mA
COUT = 2.2 mF
TJ = 25°C
2
0
60
50
CNR = 0.001 mF
40
3
IOUT = 10 mA
20
VOUT (V)
30
VIN = 3.8 V
COUT = 10 mF
CNR = 0.01 mF
10
0
10
100
2
CNR = 0.0047 mF
1
CNR = 0.01 mF
0
1k
10 k
100 k
1M
0
10 M
20 40
60 80 100 120 140 160 180 200
Time (ms)
Frequency (Hz)
Figure 7. TPS73028 Ripple Rejection vs Frequency
Figure 8. TPS73028 Output Voltage, Enable Voltage vs Time
(Start-Up)
3.8
IOUT = 200 mA
COUT = 2.2 mF
CNR = 0.01 mF
0
−20
−40
dv
0.4 V
= ms
dt
0
-20
200
10
20
30 40
50 60
70 80
1mA
100
0
0
di
0.02A
= ms
dt
300
IOUT (mA)
20
VIN (mV)
VIN = 3.8 V
COUT = 10 mF
20
DVOUT (mV)
VOUT (mV)
4.8
90 100
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
Time (ms)
Figure 9. TPS73028 Line Transient Response
Figure 10. TPS73028 Load Transient Response
250
VOUT = 3 V
RL = 15 W
200
VDO (mV)
500 mV/div
TJ = 125°C
VIN
150
TJ = 25°C
100
VOUT
TJ = −55°C
50
0
0
1s/div
20 40 60 80 100 120 140 160 180 200
IOUT (mA)
Figure 11. Power Up and Power Down
Figure 12. Dropout Voltage vs Output Current
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Typical Characteristics (continued)
Over recommended operating temperature range TJ = –40°C to +125°C, VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT =
10 μF, CNR = 0.01 μF, VOUT(nom) = 2.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
100
COUT = 2.2 µF
VIN = 5.5 V, VOUT ≥ 1.5 V
TJ = −40°C to 125°C
ESR, Equivalent Series Resistance (Ω)
ESR, Equivalent Series Resistance (Ω)
100
10
Region of Instability
1
0.1
Region of Stability
0.01
10
Region of Instability
1
0.1
Region of Stability
0.01
0
8
COUT = 10 µF
VIN = 5.5 V
TJ = −40°C to 125°C
0.02
0.04
0.06
0.08
0.20
0
0.02
0.04
0.06
0.08
0.20
IOUT (A)
IOUT (A)
Figure 13. Typical Regions of Stability Equivalent Series
Resistance (ESR) vs Output Current
Figure 14. Typical Regions of Stability Equivalent Series
Resistance (ESR) vs Output Current
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7 Detailed Description
7.1 Overview
The TPS730 family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive, batteryoperated equipment. The device features extremely low dropout voltages, high PSRR, ultra-low output noise, low
quiescent current (170 μA typically), and enable-input to reduce supply currents to less than 1 μA when the
regulator is turned off.
7.2 Functional Block Diagrams
IN
OUT
UVLO
2.45V
59 k
Current
Sense
ILIM
GND
R1
SHUTDOWN
_
+
FB
EN
R2
UVLO
Thermal
Shutdown
IN
External to
the Device
QuickStart
Bandgap
Reference
1.22V
250 kW
Vref
NR
Figure 15. TPS730 Block Diagram (Adjustable-Voltage Version)
IN
OUT
UVLO
2.45V
Current
Sense
GND
SHUTDOWN
ILIM
_
EN
R1
+
UVLO
R2
Thermal
Shutdown
R2 = 40 kW
QuickStart
IN
Bandgap
Reference
1.22V
250 kW
Vref
NR
Figure 16. TPS730 Block Diagram (Fixed-Voltage Versions)
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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TPS730 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is
greater than the rising UVLO voltage. This circuit ensures that the device does not exhibit any unpredictable
behavior when the supply voltage is lower than the operational range of the internal circuitry, VIN(min).
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(high) (1.7 V, minimum).
Turn off the device by forcing the EN pin to drop below 0.7 V. If shutdown capability is not required, connect EN
to IN.
7.3.3 Foldback Current Limit
The TPS730 features internal current limiting and thermal protection. During normal operation, the TPS730 limits
output current to approximately 400 mA. When current limiting engages, the output voltage scales back linearly
until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, do not
exceed the power dissipation ratings of the package or the absolute maximum voltage ratings of the device.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as VIN(min).
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage is greater than VEN(min).
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device is in the linear region and no longer controls the current
through the LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
• The input voltage is less than UVLOfalling.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO and
VIN > VIN(min)
VEN > VEN(high)
IOUT < ILIM
TJ < 125°C
Dropout mode
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(high)
—
TJ < 125°C
VIN < UVLOfalling
VEN < VEN(low)
—
TJ > 165°C (1)
Disabled mode
(any true condition disables the
device)
(1)
Approximate value for thermal shutdown.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS730 family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive batteryoperated equipment. The device features extremely low dropout voltages, high PSRR, ultra-low output noise, low
quiescent current (170 μA typically), and enable-input to reduce supply currents to less than 1 μA when the
regulator is turned off.
8.1.1 Adjustable Operation
The output voltage of the TPS73001 adjustable regulator is programmed using an external resistor divider as
shown in Figure 17. The output voltage is calculated using Equation 1:
§
R1 ·
VR E F u ¨ 1
¸
R2 ¹
©
VO U T
Where:
•
VREF = 1.225 V typical (the internal reference voltage)
(1)
Resistors R1 and R2 should be chosen for approximately 50-μA divider current. Lower value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistors values can cause
accuracy issues and other problems. The recommended design procedure is to choose R2 = 30.1 kΩ to set the
divider current at 50 μA, C1 = 15 pF for stability, and then calculate R1 using Equation 2:
VOUT
R1 =
VREF
- 1 ´ R2
(2)
To improve the stability of the adjustable version, TI suggests placing a small compensation capacitor between
OUT and FB. For output voltages < 1.8 V, the value of this capacitor should be 100 pF. For output voltages > 1.8
V, use Equation 3 to calculate the approximate value of this capacitor.
C1
(3 u 1 0
7
) u (R 1 R 2 )
(R 1 u R 2 )
(3)
Figure 17 shows the suggested value of this capacitor for several resistor ratios. If this capacitor is not used
(such as in a unity-gain configuration) or if an output voltage < 1.8 V is chosen, then the minimum recommended
output capacitor is 4.7 μF instead of 2.2 μF.
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VIN
IN
1mF
OUT
TPS73001
EN
NR
GND
VOUT
R1
C1
2.2mF
FB
0.01mF
R2
OUTPUT
VOLTAGE
R1
R2
C1
1.22V
short
open
0pF
2.5V
31.6kW
30.1kW
22pF
3.3V
51kW
30.1kW
15pF
3.6V
59kW
30.1kW
15pF
Figure 17. TPS73001 Adjustable LDO Regulator Programming
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Application Information (continued)
8.1.2 Capacitor Recommendations
Low equivalent series resistance (ESR) capacitors should be used for the input, output, noise reduction, and
bypass capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more
stable characteristics. Ceramic X7R capacitors offer improved overtemperature performance, while ceramic X5R
capacitors are more cost-effective and are available in higher values.
8.1.3 Input and Output Capacitor Requirements
A 0.1-μF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS730, is required for stability and improves transient response, noise rejection, and ripple rejection. A highervalue input capacitor may be necessary if large, fast-rise-time load transients are anticipated or the device is
located several inches from the power source.
Like most low-dropout regulators, the TPS730 requires an output capacitor connected between OUT and GND to
stabilize the internal control loop. The minimum recommended capacitance is 2.2 μF. Any 2.2-μF or larger
ceramic capacitor is suitable, provided the capacitance does not vary significantly over temperature. If load
current is not expected to exceed 100 mA, a 1-μF ceramic capacitor can be used. If a feed-forward capacitor is
not used (such as in a unity-gain configuration) or if an output voltage less than 1.8 V is chosen, then the
minimum recommended output capacitor is 4.7 μF instead of 2.2 μF. Table 2 lists the recommended output
capacitor sizes for several common configurations.
Table 2. Output Capacitor Sizing
CONDITION
COUT (µF)
VOUT < 1.8 V or CFF = 0 nF
4.7
VOUT > 1.8 V, IOUT > 100 mA
2.2
VOUT > 1.8 V, IOUT < 100 mA
1
8.1.4 Noise Reduction and Feed-Forward Capacitor Requirements
The internal voltage reference is a key source of noise in an LDO regulator. The TPS730 has an NR pin which is
connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in
conjunction with an external bypass capacitor connected to the NR pin, creates a low-pass filter to reduce the
voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate
properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR
drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor should be no more than 0.1 μF to ensure that it is fully charged
during the quick-start time provided by the internal switch shown in the Functional Block Diagram section.
As an example, the TPS73018 exhibits only 33 μVRMS of output voltage noise using a 0.01-μF ceramic bypass
capacitor and a 2.2-μF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance
increases due to the RC time constant at the NR pin that is created by the internal 250-kΩ resistor and external
capacitor.
A feed-forward capacitor is recommended to improve the stability of the device. If R2 = 30.1 kΩ, set C1 to 15 pF
for optimal performance. For voltages less than 1.8 V, the value of this capacitor should be 100 pF. For voltages
greater than 1.8 V, the approximate value of this capacitor can be calculated as shown in Equation 3.
8.1.5 Reverse Current Operation
The TPS730 PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (for example, during power-down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting
might be appropriate. If extended reverse voltage operation in anticipated, external limiting to 5% of the rated
output current is recommended.
12
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8.2 Typical Application
A typical application circuit is shown in Figure 18.
VOUT
VIN
VIN
IN
VOUT
OUT
TPS730xx
0.1µF
EN
GND
NR
2.2µF
0.01µF(1)
NOTE: (1) This capacitor is optional.
Figure 18. Typical Application Circuit
8.2.1 Design Requirements
Table 3 lists the design requirements.
Table 3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
4.2 V to 3 V (Lithium Ion battery)
Output voltage
1.8 V, ±1%
DC output current
10 mA
Peak output current
75 mA
Maximum ambient temperature
65°C
8.2.2 Detailed Design Procedure
Pick the desired output voltage option. An input capacitor of 0.1 µF is used as the battery is connected to the
input through a via and a short 10-mil (0.01-in) trace. An output capacitor of 10 µF is used to provide optimal
response time for the load transient. Verify that the maximum junction temperature is not exceed by referring to
Figure 24.
8.2.3 Application Curves
2
0
CNR = 0.001 mF
VOUT (mV)
VEN (V)
4
VIN = 3.8 V
VOUT = 2.8 V
IOUT = 200 mA
COUT = 2.2 mF
TJ = 25°C
3.8
IOUT = 200 mA
COUT = 2.2 mF
CNR = 0.01 mF
20
VIN (mV)
3
VOUT (V)
4.8
2
CNR = 0.0047 mF
1
dv
0.4 V
= ms
dt
0
-20
CNR = 0.01 mF
0
0
20 40
60 80 100 120 140 160 180 200
0
Time (ms)
10
20
30 40
50 60
70 80
90 100
Time (ms)
Figure 19. TPS73028 Output Voltage, Enable Voltage vs
Time (Start-Up)
Figure 20. TPS73028 Line Transient Response
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100
DVOUT (mV)
ESR, Equivalent Series Resistance (Ω)
VIN = 3.8 V
COUT = 10 mF
20
0
−20
−40
di
0.02A
= ms
dt
IOUT (mA)
300
200
1mA
100
0
0
COUT = 10 µF
VIN = 5.5 V
TJ = −40°C to 125°C
10
Region of Instability
1
0.1
Region of Stability
0.01
50 100 150 200 250 300 350 400 450 500
0
Time (ms)
0.02
0.04
0.06
0.08
0.20
IOUT (A)
Figure 21. TPS73028 Load Transient Response
Figure 22. Typical Regions of Stability Equivalent Series
Resistance (ESR) vs Output Current
8.3 Do's and Don'ts
Do place at least one, low-ESR, 2.2-μF capacitor as close as possible between the OUT pin of the regulator and
the GND pin.
Do place at least one, low-ESR, 0.1-μF capacitor as close as possible between the IN pin of the regulator and
the GND pin.
Do provide adequate thermal paths away from the device.
Do not place the input or output capacitor more than 10 mm away from the regulator.
Do not exceed the absolute maximum ratings.
Do not float the Enable (EN) pin.
Do not resistively or inductively load the NR pin.
Do not let the output voltage get more than 0.3 V above the input voltage.
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9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range from 2.7 V to 5.5 V. The input voltage
range must provide adequate headroom in order for the device to have a regulated output. This input supply
must be well-regulated and stable. A 0.1-µF input capacitor is required for stability; if the input supply is noisy,
additional input capacitors with low ESR can help improve the output noise performance.
10 Layout
10.1 Layout Guidelines
Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade
the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with
a low ESR ceramic bypass capacitor with an X5R or X7R dielectric.
Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized to maximize
performance and ensure stability. Every capacitor (CIN, COUT, CNR/SS, CFF) must be placed as close as possible to
the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use
of vias and long traces is strongly discouraged because these circuits may impact system performance
negatively, and even cause instability.
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve AC measurements like PSRR, output noise, and transient response, TI recommends designing the
board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of
the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of
the device.
10.2 Layout Example
Output Ground
Output Plane
Input Plane
IN
OUT
GND
FB
EN
NR
Input Ground
NR and FB
Ground
Denotes via
Figure 23. Layout Example (DBV Package)
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10.3 Thermal Considerations
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits regulator dissipation, protecting the device from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature must be limited to 125°C maximum. To estimate the margin
of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection
is triggered; use worst-case loads and signal conditions.
The TPS730 internal protection circuitry is designed to protect against overload conditions. This circuitry is not
intended to replace proper heatsinking. Continuously running the TPS730 into thermal shutdown degrades
device reliability.
10.4 Power Dissipation
Specified regulator operation is assured to a junction temperature of +125°C; the maximum junction temperature
should be restricted to +125°C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or
equal to PD(max).
The maximum power dissipation limit is determined using Equation 4:
PD (m a x )
TJm a x T A
R 4 JA
Where:
•
•
•
TJmax is the maximum allowable junction temperature.
RθJA is the thermal resistance junction-to-ambient for the package (see the Thermal Information table).
TA is the ambient temperature.
(4)
The regulator dissipation is calculated using Equation 5:
PD
( V IN V O U T ) u IO U T
(5)
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal
protection circuit.
Figure 24 shows the maximum ambient temperature versus the power dissipation of the TPS730. This figure
assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board
thermal impedances vary widely. If the application requires high power dissipation, having a thorough
understanding of the board temperature and thermal impedances is helpful to ensure the TPS730 does not
operate above a junction temperature of 125°C.
Maximum Ambient Temperature (qC)
125
DBV Package
YZQ Package
100
75
50
0
0.1
0.2
0.3
Power Dissapation (W)
0.4
0.5
Figure 24. Maximum Ambient Temperature vs Power Dissipation
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Power Dissipation (continued)
Estimating the junction temperature can be done by using the thermal metrics ΨJT and ΨJB, shown in the
Thermal Information table. These metrics are a more accurate representation of the heat transfer characteristics
of the die and the package than RθJA. The junction temperature can be estimated with Equation 6.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
PD is the power dissipation shown by Equation 5,
TT is the temperature at the center-top of the IC package,
TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface.
(6)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the application note Using New Thermal Metrics
(SBVA025), available for download at www.ti.com.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS730 is available through the product folders under Tools
& Software.
11.1.2 Device Nomenclature
Table 4. Ordering Information (1) (2)
PRODUCT
TPS730xxyyyz
(1)
(2)
VOUT
XX(X) is the nominal output voltage (for example, 28 = 2.8 V; 285 = 2.85 V; 01 = adjustable version).
YYY is the package designator.
Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 1.2 V to 4.8 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
•
•
Using New Thermal Metrics, SBVA025
Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator, SBVA042
11.3 Trademarks
NanoStar is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth Sig, Inc.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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12.1 TPS730YZQ Nanostar™ Wafer Chip Scale Information
0,79
0,84
1,30
1,34
0.625 Max
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoStar package configuration.
D. This package is tin-lead (SnPb); consult the factory for availability of lead-free material.
NanoStar is a trademark of Texas Instruments.
Figure 25. Nanostar™ Wafer Chip Scale Package
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS73001DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGVI
Samples
TPS73001DBVRG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGVI
Samples
TPS73001DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGVI
Samples
TPS73001DBVTG4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGVI
Samples
TPS73018DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHHI
Samples
TPS73018DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHHI
Samples
TPS73018DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHHI
Samples
TPS73018DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHHI
Samples
TPS73025DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGWI
Samples
TPS73025DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGWI
Samples
TPS73025DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGWI
Samples
TPS73025DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGWI
Samples
TPS73025YZQR
LIFEBUY
DSBGA
YZQ
5
3000
TBD
Call TI
Call TI
-40 to 125
E4
TPS73025YZQT
LIFEBUY
DSBGA
YZQ
5
250
TBD
Call TI
Call TI
-40 to 125
E4
TPS730285DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHII
Samples
TPS730285DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHII
Samples
TPS73028DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGXI
Samples
TPS73028DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGXI
Samples
TPS73028DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGXI
Samples
TPS73028DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGXI
Samples
TPS73028YZQR
LIFEBUY
DSBGA
YZQ
5
3000
TBD
Call TI
Call TI
-40 to 125
E2
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS73028YZQT
ACTIVE
DSBGA
YZQ
5
250
TBD
Call TI
Call TI
-40 to 125
E2
Samples
TPS73030DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGYI
Samples
TPS73030DBVT
LIFEBUY
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PGYI
TPS73033DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHUI
Samples
TPS73033DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHUI
Samples
TPS73033DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHUI
Samples
TPS73033DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PHUI
Samples
TPS73047DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PETI
Samples
TPS73047DBVT
LIFEBUY
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PETI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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