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TPS732-Q1
SGLS303F – MAY 2005 – REVISED APRIL 2016
TPS732-Q1 Cap-Free NMOS 250-mA Low-Dropout Regulator
With Reverse-Current Protection
1 Features
2 Applications
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results
– Device Temperature Grade 0: –40°C to 150°C
Ambient Operating Temperature Range
– Device HBM Classification Level 2
– Device CDM Classification Level C4B
– Device MM Classification Level M2
Stable With No Output Capacitor or Any Value or
Type of Capacitor
Input Voltage Range: 1.7 V to 5.5 V
Ultra-Low Dropout Voltage: 40-mV Typical at
250 mA
Excellent Load Transient Response—With or
Without Optional Output Capacitor
New NMOS Topology Provides Low Reverse
Leakage Current
Low Noise: 30-μVRMS Typical (10 kHz to 100 kHz)
0.5% Initial Accuracy
1% Overall Accuracy (Line, Load, and
Temperature)
Less Than 1-μA Maximum IQ in Shutdown Mode
Thermal Shutdown and Specified Minimum and
Maximum Current Limit Protection
Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.2 V, 1.5 V, 1.6 V, 1.8 V,
2.5 V, 3 V, 3.3 V, and 5 V
– Adjustable Outputs From 1.2 V to 5.5 V
– Custom Outputs Available
Portable and Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry Such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
3 Description
The TPS732-Q1 family of low-dropout (LDO) voltage
regulators uses a new topology: an NMOS pass
element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
The topology also provides high reverse blockage
(low reverse current) and ground pin current that is
nearly constant over all values of output current.
The TPS732-Q1 family of devices uses an advanced
BiCMOS process to yield high precision while
delivering low dropout voltages and low ground pin
current. Current consumption, when not enabled, is
under 1 μA and ideal for portable applications. The
extremely low output noise (30 μVRMS with 0.1-µF
CNR) is ideal for powering VCOs. These devices are
protected by thermal shutdown and foldback current
limit.
Device Information(1)
PART NUMBER
TPS73201-Q1
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
VSON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Circuit for Fixed Voltage Versions
Optional
VIN
Optional
IN
VOUT
OUT
TPS732xx-Q1
EN
GND
NR
Optional
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS732-Q1
SGLS303F – MAY 2005 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Power Dissipation .................................................
Package Mounting ................................................
17
18
18
18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Revision E (August 2013) to Revision F
•
Added Device Information table, Table of Contents, Specifications section, ESD Ratings table, Recommended
Operating Conditions table, Detailed Description section, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
Changes from Revision D (March 2009) to Revision E
•
2
Page
Page
Deleted TPS73215-Q1, TPS73216-Q1, TPS73218-Q1, TPS73230-Q1, TPS73233-Q1, and TPS73250-Q1 from the
data sheet ............................................................................................................................................................................... 1
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SGLS303F – MAY 2005 – REVISED APRIL 2016
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
IN
1
GND
2
EN
3
DRB Package
8-Pin VSON With Exposed Thermal Pad
Top View
5
OUT
OUT
1
NC
2
8
IN
7
NC
Pad
4
NR/FB
3
6
NC
GND
4
5
EN
NR/FB
NC: No internal connection
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
SOT-23
VSON
EN
3
5
I
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator
into shutdown mode. See Shutdown for more details. EN can be connected to IN if not used.
FB (1)
4
3
I
Input to the control loop error amplifier, and is used to set the output voltage of the device.
GND
2
4
—
IN
1
8
I
4
3
—
Connecting an external capacitor to this pin bypasses noise generated by the internal
bandgap. This allows output noise to be reduced to low levels.
NR
(2)
Ground
Unregulated input supply
OUT
5
1
O
Output of the regulator. There are no output capacitor requirements for stability.
Pad
—
Pad
—
Ground
NC
—
2, 6, 7
—
No internal connection
(1)
(2)
Adjustable voltage versions only.
Fixed voltage versions only.
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SGLS303F – MAY 2005 – REVISED APRIL 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN
–0.3
6
V
VEN
–0.3
6
V
VOUT
–0.3
5.5
V
Peak output current
Internally limited
Output short-circuit duration
Indefinite
Junction temperature, TJ
–55
150
°C
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1000
Machine model (MM)
±200
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
Input voltage (1)
IOUT
Output current
TJ
Operating junction temperature
(1)
MIN
MAX
1.7
5.5
UNIT
V
0
250
mA
–40
125
°C
Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
6.4 Thermal Information
TPS732-Q1
THERMAL METRIC (1)
DBV (SOT-23)
DRB (VSON)
5 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
180
47.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
64
83
°C/W
RθJB
Junction-to-board thermal resistance
35
—
°C/W
ψJT
Junction-to-top characterization parameter
—
2.1
°C/W
ψJB
Junction-to-board characterization parameter
—
17.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
12.1
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V (1), IOUT = 10 mA, VEN = 1.7 V, and
COUT = 0.1 μF, unless otherwise noted. Typical values are at TJ = 25°C
PARAMETER
VFB
MIN
TYP
MAX
UNIT
TJ = 25°C
TEST CONDITIONS
1.198
1.2
1.21
V
VFB
5.5 – VDO
V
Nominal
TJ = 25°C
–0.5%
0.5%
VIN, IOUT, and TJ
(VOUT + 0.5 V) ≤ VIN ≤ 5.5 V,
10 mA ≤ IOUT ≤ 250 mA
Internal reference (TPS73201-Q1)
Output voltage range (TPS73201-Q1)
VOUT
Accuracy (1)
ΔVOUT%/ΔVIN
Line regulation (1)
(2)
–1%
(VOUT(nom) + 0.5 V) ≤ VIN ≤ 5.5 V
±0.5%
1%
0.06
1 mA ≤ IOUT ≤ 250 mA
0.002
10 mA ≤ IOUT ≤ 250 mA
0.0008
%/V
ΔVOUT%/ΔIOUT
Load regulation
VDO
Dropout voltage
(VIN = VOUT (nom) – 0.1 V)
IOUT = 250 mA
ZO(DO)
Output impedance in dropout
1.7 V ≤ VIN ≤ (VOUT + VDO)
ICL
Output current limit
VOUT = 0.9 × VOUT(nom)
ISC
Short-circuit current
VOUT = 0 V
300
IREV
Reverse leakage current (3) (–IIN)
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
0.1
10
IOUT = 10 mA (IQ)
400
550
IOUT = 250 mA
650
950
0.02
1
40
150
mV
600
mA
Ω
0.25
250
425
IGND
Ground pin current
ISHDN
Shutdown current (IGND)
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5
PSRR
Power-supply rejection ratio
(ripple rejection)
f = 100 Hz, IOUT = 250 mA
58
f = 10 kHz, IOUT = 250 mA
37
VN
Output noise voltage
BW = 10 Hz – 100 kHz
COUT = 10 μF, No CNR
27 × VOUT
COUT = 10 μF, CNR = 0.01 μF
8.5 × VOUT
VEN(HI)
Enable high (enabled)
VEN(LO)
Enable low (shutdown)
IEN(HI)
Enable pin current (enabled)
TSD
Thermal shutdown temperature
(1)
(2)
(3)
%/mA
1.7
mA
0
0.02
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
μA
μA
dB
μVRMS
VIN
VEN = 5.5 V
μA
V
0.5
V
0.1
μA
°C
Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
TPS73201-Q1 is tested at VOUT = 2.5 V.
Fixed-voltage versions only; see Reverse Current for more information.
6.6 Switching Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V (1), IOUT = 10 mA, VEN = 1.7 V, and
COUT = 0.1 μF, unless otherwise noted. Typical values are at TJ = 25°C
PARAMETER
tSTR
(1)
Start-Up time
TEST CONDITIONS
VOUT = 3 V, RL = 30 Ω COUT = 1 μF, CNR = 0.01 μF
MIN
TYP
MAX
600
UNIT
μs
Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
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6.7 Typical Characteristics
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted
0.5
0.20
Referred to IOUT = 10mA
0.4
0.2
Change in VOUT (%)
0.3
Change in VOUT (%)
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
0.15
–40°C
25°C
125°C
0.1
0
- 0.1
- 0.2
- 0.3
0.10
25°C
125°C
0.05
0
- 0.05
–40°C
- 0.10
- 0.15
- 0.4
- 0.5
- 0.20
0
50
100
150
200
250
0
0.5
1.0
1.5
IOUT (mA)
2.0
2.5
3.0
3.5
4.0
4.5
VIN - VOUT (V)
Figure 1. Load Regulation
Figure 2. Line Regulation
100
100
TPS73225DBV
TPS73225DBV
80
80
125°C
VDO (mV)
VDO (mV)
60
25°C
40
20
60
50
20
–40°C
0
0
0
50
100
150
200
250
–50
–25
IOUT (mA)
25
50
75
100
125
Temperature (°C)
Figure 3. Dropout Voltage vs Output Current
Figure 4. Dropout Voltage vs Temperature
18
30
IOUT = 10mA
16
Percent of Units (%)
25
Percent of Units (%)
0
20
15
10
I OUT = 10mA
All Voltage Versions
14
12
10
8
6
4
5
2
6
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/°C)
Figure 5. Output Voltage Accuracy Histogram
Figure 6. Output Voltage Drift Histogram
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Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted
1000
800
900
700
800
600
700
600
I GND (µA)
I GND (µA)
IOUT = 250mA
500
400
300
100
50
100
150
200
300
VIN = 5.5V
VIN = 4V
VIN = 2V
100
0
0
400
200
VIN = 5.5V
VIN = 4V
VIN = 2V
200
500
0
- 50
250
- 25
0
25
IOUT (mA)
Figure 7. Ground Pin Current vs Output Current
75
100
125
Figure 8. Ground Pin Current vs Temperature
500
1
450
VENABLE = 0.5V
VIN = VOUT + 0.5V
ICL
400
350
300
IGND (µA)
Current Limit (mA)
50
Temperature (°C)
ISC
250
200
0.1
150
100
50
TPS73233
0
0.5
1.0
1.5
2.0
2.5
3.0
0.01
- 50
3.5
- 25
0
25
50
75
100
125
VOUT (V)
Temperature (°C)
Figure 9. Current Limit vs VOUT (FOLDBACK)
Figure 10. Ground Pin Current in Shutdown vs Temperature
600
600
550
550
500
500
Current Limit (mA)
Current Limit (mA)
0
450
400
350
450
400
350
300
300
250
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
250
- 50
- 25
0
25
50
75
100
125
Temperature (°C)
VIN (V)
Figure 11. Current Limit vs VIN
Figure 12. Current Limit vs Temperature
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Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted
40
90
IOUT = 100mA
COUT = Any
Ripple Rejection (dB)
70
35
30
IOUT = 1mA
COUT = 10µF
60
50
IO = 100mA
CO = 1µF
IOUT = 1mA
C OUT = Any
40
PSRR (dB)
80
IOUT = 1mA
COUT = 1µF
30
20
0
10
100
1k
10k
20
15
10
I OUT = 100mA
COUT = 10µF
IOUT = Any
COUT = 0µF
10
25
Frequency = 100kHz
COUT = 10 µF
CNR = 0.01 µF
5
0
100k
1M
0
10M
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VIN - VOUT (V)
Frequency (Hz)
Figure 14. PSRR (Ripple Rejection) vs VIN – VOUT
Figure 13. PSRR (Ripple Rejection) vs Frequency
1
1
COUT = 0µF
0.1
COUT = 10µF
eN (µV/√Hz)
eN (µV/√Hz)
C OUT = 1µF
COUT = 1µF
0.1
COUT = 0µF
COUT = 10µF
IOUT = 150mA
IOUT = 150mA
0.01
0.01
10
100
1k
10k
100k
10
100
Frequency (Hz)
1k
10k
100k
Frequency (Hz)
Figure 15. Noise Spectral Density vs CNR = 0 μF
Figure 16. Noise Spectral Density vs CNR = 0.01 μF
60
140
50
120
VOUT = 5.0V
VOUT = 5.0V
100
VN (RMS)
VN (RMS)
40
30 VOUT = 3.3V
20
0
0.1
8
20
CNR = 0.01 µF
10Hz < Frequency < 100kHz
0
1
10
VOUT = 3.3V
60
40
VOUT = 1.5V
10
80
VOUT = 1.5V
COUT = 0 µF
10Hz < Frequency < 100kHz
1p
10p
100p
1n
COUT (µF)
CNR (F)
Figure 17. RMS Noise Voltage vs COUT
Figure 18. RMS Noise Voltage vs CNR
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Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted
VIN = 3.8V
IOUT = 250mA
COUT = 0µF
50mV/tick
VOUT
COUT = 0µF
50mV/div
COUT = 1µF
50mV/tick
COUT = 10µF
50mV/tick
VOUT
VOUT
VOUT
C OUT = 100µF
50mV/div
5.5V
250mA
dt
50mA/tick
= 0.5V/µs
4.5V
1V/div
10mA
VIN
I OUT
10µs/div
10µs/div
Figure 20. TPS73233-Q1 – Line Transient Response
Figure 19. TPS73233-Q1 – Load Transient Response
RL = 1 kΩ
COUT = 0 µF
RL = 20 Ω
COUT = 10 µF
VOUT
R L = 20 Ω
C OUT = 1 µF
1V/div
VOUT
dVIN
R L = 20 Ω
C OUT = 1 µF
1V/div
RL = 1 kΩ
COUT = 0 µF
RL = 20 Ω
COUT = 10 µF
VOUT
2V
2V
VEN
1V/div
1V/div
0V
0V
VEN
100 µs/div
100 µs/div
Figure 21. TPS73233-Q1 – Turnon Response
Figure 22. TPS73233-Q1 – Turnoff Response
6
10
5
VIN
4
VOUT
IENABLE (nA)
Volts
3
2
1
1
0.1
0
-1
-2
0.01
- 50
50ms/div
- 25
0
25
50
75
100
125
Temperature (°C)
Figure 23. TPS73233-Q1 – Power Up and Power Down
Figure 24. IENABLE vs Temperature
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Typical Characteristics (continued)
60
160
55
140
50
120
45
100
I FB (nA)
VN (rms)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted
40
60
35
30
25
80
VOUT = 2.5V
COUT = 0 µF
R1 = 39.2 kΩ
10Hz < Frequency < 100kHz
20
10p
100p
40
20
1n
10n
0
- 50
- 25
0
25
50
75
100
125
CFB (F)
Temperature (°C)
Figure 25. TPS73201-Q1 – RMS Noise Voltage vs CADJ
Figure 26. TPS73201-Q1 – IFB vs Temperature
CFB = 10nF
R1 = 39.2kΩ
COUT = 0µF
100mV/div
100mV/div
VOUT
100mV/div
C OUT = 10µF
100mV/div
COUT = 0µF
VOUT
VOUT = 2.5V
CFB = 10nF
COUT = 10µF
VOUT
VOUT
4.5V
250mA
3.5V
10mA
10
VIN
IOUT
10µs/div
5µs/div
Figure 27. TPS73201-Q1 – Load Transient,
Adjustable Version
Figure 28. TPS73201-Q1 – Line Transient,
Adjustable Version
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7 Detailed Description
7.1 Overview
The TPS732-Q1 low-dropout linear regulator devices operate with an input voltage down to 1.7 V and support
output voltages down to 1.2 V while sourcing up to 500 mA of load current. These linear regulators use an
NMOS pass element with an integrated 4-MHz charge pump to provide a dropout voltage of less than 250 mV at
full load current. This unique architecture also permits stable regulation over a wide range of output capacitors. In
fact, the TPS732-Q1 family of devices does not require any output capacitor for stability. The increased
insensitivity to the output capacitor value and type makes this family of linear regulators an ideal choice when
powering a load where the effective capacitance is unknown. The TPS732-Q1 family of devices also features a
noise reduction (NR) pin that allows for additional reduction of the output noise. The low noise output featured by
the TPS732-Q1 family makes the device well-suited for powering VCOs or any other noise-sensitive load.
7.2 Functional Block Diagram
IN
Charge
Pump
EN
Thermal
Protection
Ref
Servo
27kW
Bandgap
Error
Amp
Current
Limit
OUT
8kW
GND
R1
R1 + R2 = 80kW
R2
Copyright © 2016, Texas Instruments Incorporated
NR
Fixed voltage version.
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS732-Q1 internal current limit helps protect the regulator during fault conditions. Foldback helps to protect
the regulator from damage during output short-circuit conditions by reducing current limit when VOUT drops below
0.5 V. See Figure 9.
7.3.2 Shutdown
The enable pin is active high and is compatible with standard TTL-CMOS levels. VEN below 0.5 V (maximum)
turns the regulator off and drops the ground pin current to approximately 10 nA. When shutdown capability is not
required, the Enable pin can be connected to VIN. When a pullup resistor is used, and operation down to 1.8 V is
required, use pullup resistor values below 50 kΩ.
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Feature Description (continued)
7.3.3 Dropout Voltage
The TPS732-Q1 family of devices uses an NMOS pass transistor to achieve extremely low dropout. When (VIN –
VOUT) is less than the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS pass element.
For large step changes in load current, the TPS732-Q1 family of devices requires a larger voltage drop from VIN
to VOUT to avoid degraded transient response. The boundary of this transient dropout region is approximately
twice the dc dropout. Values of VIN – VOUT above this line ensure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recover
from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load
current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale
instantaneous load change with (VIN – VOUT) close to dc dropout levels], the TPS732-Q1 family of devices can
take a couple of hundred microseconds to return to the specified regulation accuracy.
7.3.4 Transient Response
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration
allows operation without an output capacitor for many applications. As with any regulator, the addition of a
capacitor (nominal value 1 μF) from the output pin to ground will reduce undershoot magnitude but increase
duration. In the adjustable version, the addition of a capacitor, CFB, from the output to the adjust pin will also
improve the transient response.
The TPS732-Q1 family of devices does not have active pulldown when the output is over-voltage. This allows
applications that connect higher voltage sources, such as alternate power supplies, to the output. This also
results in an output overshoot of several percent if the load current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot can be reduced by adding a load resistor. The overshoot
decays at a rate determined by output capacitor COUT and the internal and external load resistance. The rate of
decay is given by Equation 1 and Equation 2:
(Fixed voltage version)
VOUT
dV / dt =
C OUT ´ 80 kW
(1)
(Adjustable voltage version)
VOUT
dV / dt =
C OUT ´ 80 kW || (R 1 + R 2 )
(2)
7.3.5 Reverse Current
The NMOS pass element of the TPS732-Q1 family of devices provides inherent protection against current flow
from the output of the regulator to the input when the gate of the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element, the enable pin must be driven low before the input voltage
is removed. If this is not done, the pass element may be left on due to stored charge on the gate.
After the enable pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that
reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There
will be additional current flowing into the OUT pin due to the 80-kΩ internal resistor divider to ground (see the
Functional Block Diagram and Figure 31).
For the TPS73201-Q1, reverse current may flow when VFB is more than 1 V above VIN.
12
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Feature Description (continued)
7.3.6 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of your application. This produces a worstcase junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS732-Q1 family of devices has been designed to protect against
overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS732-Q1
family of devices into thermal shutdown will degrade device reliability.
7.4 Device Functional Modes
7.4.1 Normal Operation
The TPS632-Q1 family of devices require an input voltage of at least 1.7 V to function properly and attempt to
maintain regulation.
When operating the device near 5.5 V, take care to suppress any transient spikes that may exceed the 6-V
absolute maximum voltage rating. The device must never operate at a DC voltage greater than 5.5 V.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS732-Q1 belongs to a family of new generation LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints.
These features, combined with low noise and an enable input, make the TPS732-Q1 family of devices ideal for
portable applications. This regulator family offers a wide selection of fixed output voltage versions and an
adjustable output version. All versions have thermal and overcurrent protection, including foldback current limit.
8.2 Typical Application
Figure 29 shows the basic circuit connections for the fixed voltage models. Figure 30 gives the connections for
the adjustable output version (TPS73201-Q1).
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
Optional output capacitor.
May improve load transient,
noise, or PSRR.
IN
VOUT
OUT
TPS732xx-Q1
EN
GND
NR
Optional bypass
capacitor to reduce
output noise.
Copyright © 2016, Texas Instruments Incorporated
Figure 29. Typical Application Circuit for Fixed-Voltage Versions
Optional output capacitor.
May improve load transient,
noise, or PSRR.
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
VOUT
OUT
TPS732xx-Q1
EN
GND
R1
CFB
FB
R2
VOUT =
(R1 + R 2 )
R2
´ 1.204
Optional capacitor
reduces output noise.
Copyright © 2016, Texas Instruments Incorporated
Figure 30. Typical Application Circuit for Adjustable-Voltage Versions
14
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Typical Application (continued)
8.2.1 Design Requirements
R1 and R2 can be calculated for any output voltage using the formula shown in Figure 30. Sample resistor values
for common output voltages are shown in Figure 31. For best accuracy, make the parallel combination of R1 and
R2 approximately 19 kΩ.
IN
Charge
Pump
EN
Thermal
Protection
Ref
Servo
27kW
Bandgap
Error
Amp
OUT
Current
Limit
GND
80kW
8kW
R1
FB
R2
Copyright © 2016, Texas Instruments Incorporated
VOUT = ( R1 + R2 ) / R2 × 1.204
R1 || R2 ≅ 19 kΩ for best accuracy.
Figure 31. Adjustable Voltage Version
Table 1. Standard 1% Resistor Values for Common
Output Voltages
VOUT
R1
R2
1.2 V
Short
Open
1.5 V
23.2 kW
95.3 kW
1.8 V
28 kW
56.2 kW
2.5 V
39.2 kW
36.5 kW
2.8 V
44.2 kW
33.2 kW
3V
46.4 kW
30.9 kW
3.3 V
52.3 kW
30.1 kW
5V
78.7 kW
24.9 kW
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8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to
1‑μF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and
improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if
large, fast rise-time load transients are anticipated or the device is located several inches from the power source.
The TPS732-Q1 family of devices does not require an output capacitor for stability and has maximum phase
margin with no capacitor. It is designed to be stable for all available types and values of capacitors. In
applications where VIN – VOUT < 0.5 V and multiple low ESR capacitors are in parallel, ringing may occur when
the product of COUT and total ESR drops below 50 nF. Total ESR includes all parasitic resistances, including
capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.
8.2.2.2 Output Noise
A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the
dominant noise source within the TPS732-Q1 family of devices and it generates approximately 32 μVRMS (10 Hz
to 100 kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same
gain as the reference voltage, so that the noise voltage of the regulator is approximately given by:
VOUT
(R1 ) R2)
V N + 32mVRMS
+ 32mVRMS
R2
VREF
(3)
Because the value of VREF is 1.2 V, this relationship reduces to:
ǒmVV Ǔ
V N(mVRMS) + 27
RMS
V OUT(V)
where
•
CNR does not exist
(4)
An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF,
the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the
approximate relationship:
æ µV
ö
VN (µVRMS ) = 8.5 ç RMS ÷ ´ VOUT (V)
è V ø
where
•
CNR = 10 nF
(5)
This noise reduction effect is shown as RMS Noise Voltage vs CNR in Typical Characteristics.
The TPS73201-Q1 adjustable version does not have the noise-reduction pin available. However, connecting a
feedback capacitor, CFB, from the output to the FB pin will reduce output noise and improve load transient
performance.
The TPS732-Q1 family of devices uses an internal charge pump to develop an internal supply voltage sufficient
to drive the gate of the NMOS pass element above VOUT. The charge pump generates approximately 250 μV of
switching noise at approximately 2 MHz; however, charge-pump noise contribution is negligible at the output of
the regulator for most values of IOUT and COUT.
16
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8.2.3 Application Curves
Figure 32. Start-Up
Figure 33. Shutdown
9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range from 1.7 V to 5.5 V. The input voltage
range provides adequate headroom for the device to have a regulated output. This input supply must be well
regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise
performance.
10 Layout
10.1 Layout Guidelines
To improve ac performance such as PSRR, output noise, and transient response, TI recommends designing the
PCB with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the
device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the
device.
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10.2 Layout Example
GND PLANE
COUT
VIN
TPS732xx-Q1
VOUT
NC
NR/FB
CNR
1
8
2
7
NC
3
6
NC
4
5
CIN
EN
GND PLANE
Copyright © 2016, Texas Instruments Incorporated
Figure 34. Layout Diagram
10.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Using heavier copper will increase the effectiveness in removing heat from the device.
The addition of plated through-holes to heat-dissipating layers will also improve the heat-sink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of the
output current times the voltage drop across the output pass element (VIN to VOUT):
PD = (VIN - VOUT )´ IOUT
(6)
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required
output voltage.
10.4 Package Mounting
Solder pad footprint recommendations for the TPS732-Q1 family of devices are presented in the Solder Pad
Recommendations for Surface-Mount Devices (SBFA015) application bulletin.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Solder Pad Recommendations for Surface-Mount Devices, SBFA015
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS73201QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
PJOQ
TPS73201QDRBRQ1
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
PSAQ
TPS73218QDCQRQ1
ACTIVE
SOT-223
DCQ
6
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
73218Q
TPS73250QDCQRQ1
ACTIVE
SOT-223
DCQ
6
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
73250Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS732-Q1 :
• Catalog: TPS732
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS73201QDBVRQ1
Package Package Pins
Type Drawing
SPQ
SOT-23
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DBV
5
3000
179.0
8.4
3.2
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
1.4
4.0
8.0
Q3
TPS73201QDRBRQ1
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS73218QDCQRQ1
SOT-223
DCQ
6
2500
330.0
12.4
7.1
7.45
1.88
8.0
12.0
Q3
TPS73250QDCQRQ1
SOT-223
DCQ
6
2500
330.0
12.4
7.1
7.45
1.88
8.0
12.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS73201QDBVRQ1
SOT-23
DBV
5
3000
203.0
203.0
35.0
TPS73201QDRBRQ1
SON
DRB
8
3000
367.0
367.0
35.0
TPS73218QDCQRQ1
SOT-223
DCQ
6
2500
346.0
346.0
29.0
TPS73250QDCQRQ1
SOT-223
DCQ
6
2500
346.0
346.0
29.0
Pack Materials-Page 2
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and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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