TPS73433-Q1
TPS73401-Q1
SBVS185 – DECEMBER 2011
www.ti.com
250mA, Low Quiescent Current, Ultra-Low Noise, High PSRR
Low-Dropout Linear Regulator
Check for Samples: TPS73433-Q1, TPS73401-Q1
FEATURES
DESCRIPTION
•
•
•
•
The TPS734xx-Q1 family of low-dropout (LDO),
low-power linear regulators offers excellent ac
performance with very low ground current. High
power-supply rejection ratio (PSRR), low noise, fast
start-up, and excellent line and load transient
response are provided while consuming a very low
44μA (typical) ground current. The TPS734xx-Q1 is
stable with ceramic capacitors and uses an advanced
BiCMOS fabrication process to yield a typical dropout
voltage of 125mV at 250mA output. The
TPS734xx-Q1 uses a precision voltage reference and
feedback loop to achieve overall accuracy of 2% over
all load, line, process, and temperature variations. It
is fully specified from TA = –40°C to +105°C and is
offered in a low-profile ThinSOT-23 package that are
ideal for wireless handsets, printers, and WLAN
cards.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
250mA Low Dropout Regulator with EN
Low IQ: 44μA
Multiple Output Voltage Versions Available:
– Fixed 3.3V Outputs
– Adjustable Outputs from 1.25V to 6.2V
High PSRR: 60dB at 1kHz
Ultra-Low Noise: 28μVRMS
Fast Start-Up Time: 45μs
Stable with a Low-ESR, 2.0μF Typical Output
Capacitance
Excellent Load/Line Transient Response
2% Overall Accuracy (Load/Line/Temp)
ThinSOT-23 Package
TPS73433TDDCRQ1
TSOT23-5
(TOP VIEW)
IN
1
GND
2
EN
3
5
4
TPS73401TDDCRQ1
TSOT23-5
(TOP VIEW)
OUT
NR
IN
1
GND
2
EN
3
5
OUT
4
FB
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS73433-Q1
TPS73401-Q1
SBVS185 – DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION (1)
PRODUCT
(1)
VOUT
PACKAGE MARKING
TPS73433TDDCRQ1
3.3V
PXTQ
TPS73401TDDCRQ1
Adjustable
Preview
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating temperature range (unless otherwise noted).
TPS734xx-Q1
UNIT
VIN range
PARAMETER
–0.3 to +7.0
V
VEN range
–0.3 to VIN +0.3
V
VOUT range
–0.3 to VIN +0.3
V
–0.3 to VFB (TYP) +0.3
V
VFB range
Peak output current
Internally limited
Continuous total power dissipation
See Dissipation Ratings Table
Junction temperature range, TJ
–55 to +150
Storage junction temperature range, TSTG
–55 to +150
°C
2
kV
1
kV
100
V
ESD rating, HBM
ESD rating, CDM
ESD rating, MM
(1)
°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
DISSIPATION RATINGS
BOARD
PACKAGE
RθJC
RθJA
DERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
TA = +70°C
TA = +85°C
Low-K (1)
DDC
90°C/W
280°C/W
3.6mW/°C
360mW
200mW
145mW
High-K (2)
DDC
90°C/W
200°C/W
5.0mW/°C
500mW
275mW
200mW
(1)
(2)
2
The JEDEC low-K (1s) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), two-layer board with 2-ounce (56,699g)
copper traces on top of the board.
The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), multilayer board with 1-ounce (28,35g)
internal power and ground planes and 2-ounce (56,699g) copper traces on top and bottom of the board
Copyright © 2011, Texas Instruments Incorporated
TPS73433-Q1
TPS73401-Q1
SBVS185 – DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TA = –40°C to +105°C), VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA,
VEN = VIN, COUT = 2.2μF, CNR = 0.01μF, unless otherwise noted. For TPS73401-Q1, VOUT = 3.0V.
Typical values are at TA = +25°C.
PARAMETER
TEST CONDITIONS
VIN
Input voltage range (1)
VFB
Internal reference (TPS73401-Q1)
TYP
2.7
1.184
1.208
MAX
UNIT
6.5
V
1.232
V
VOUT
Output voltage range (TPS73401-Q1)
VFB
6.3
V
VOUT
Output accuracy
Nominal
TA = +25°C
–1.0
+1.0
%
VOUT
Output accuracy (1)
Over VIN,
IOUT, Temp
VOUT + 0.3V ≤ VIN ≤ 6.5V
1mA ≤ IOUT ≤ 250mA
–2.0
+2.0
%
ΔVOUT%/ ΔVIN
Line regulation (1)
VOUT(NOM) + 0.3V ≤ VIN ≤ 6.5V
ΔVOUT%/ ΔIOUT
Load regulation
500μA ≤ IOUT ≤ 250mA
VDO
Dropout voltage
(VIN = VOUT(NOM) – 0.1V)
IOUT = 250mA
ICL
Output current limit
VOUT = 0.9 × VOUT(NOM)
IGND
Ground pin current
500μA ≤ IOUT ≤ 250mA
ISHDN
Shutdown current (IGND)
VEN ≤ 0.4V
IFB
PSRR
VN
TSTR
Power-supply rejection ratio
VIN = 3.85V, VOUT = 2.85V,
CNR = 0.01μF, IOUT = 100mA
Output noise voltage
BW = 10Hz to 100kHz, VOUT = 2.8V
Startup time,
VOUT = 0 ~ 90%,
VOUT = 2.85V,
RL = 14Ω, COUT = 2.2μF
Enable high (enabled)
VEN(LO)
Enable low (shutdown)
Enable pin current, enabled
TSD
Thermal shutdown temperature
TA
Operating temperature
UVLO
300
±1.0
0.02
%/V
0.005
%/mA
125
219
mV
580
900
mA
45
65
μA
0.15
1.0
μA
0.5
μA
–0.5
Feedback pin current (TPS73401-Q1)
VEN(HI)
IEN(HI)
(1)
MIN
f = 100Hz
60
dB
f = 1kHz
56
dB
f = 10kHz
41
dB
f = 100kHz
28
dB
CNR = 0.01μF
11 x VOUT
μVRMS
CNR = none
95 x VOUT
μVRMS
CNR = none
45
μs
CNR = 0.001μF
45
μs
CNR = 0.01μF
50
μs
CNR = 0.047μF
50
μs
1.2
VIN
V
0
0.4
V
1.0
μA
VEN = VIN = 6.5V
0.03
Shutdown, temperature increasing
165
°C
Reset, temperature decreasing
145
°C
–40
Undervoltage lock-out
VIN rising
Hysteresis
VIN falling
1.90
+105
2.20
70
2.65
°C
V
mV
Minimum VIN = VOUT + VDO or 2.7V, whichever is greater.
Copyright © 2011, Texas Instruments Incorporated
3
TPS73433-Q1
TPS73401-Q1
SBVS185 – DECEMBER 2011
www.ti.com
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAMS
IN
OUT
IN
OUT
400W
400W
2mA
Current
Limit
Overshoot
Detect
Thermal
Shutdown
EN
3.3MW
Current
Limit
Thermal
Shutdown
EN
Overshoot
Detect
UVLO
UVLO
Quickstart
1.208V
Bandgap
1.208V
Bandgap
NR
500kW
FB
500kW
GND
GND
Figure 1. Fixed Voltage Versions
Figure 2. Adjustable Voltage Versions
PIN CONFIGURATIONS
TPS73401TDDCRQ1
TSOT23-5
(TOP VIEW)
TPS73433TDDCRQ1
TSOT23-5
(TOP VIEW)
IN
1
GND
2
EN
3
5
4
OUT
NR
IN
1
GND
2
EN
3
5
OUT
4
FB
PIN DESCRIPTIONS
TPS734xx-Q1
4
NAME
DDC
DESCRIPTION
IN
1
Input supply.
GND
2
Ground. The pad must be tied to GND.
EN
3
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. EN can be connected to IN if not used.
NR
4
Fixed voltage versions only; connecting an external capacitor to this pin bypasses noise generated by the
internal bandgap. This allows output noise to be reduced to very low levels.
FB
4
Adjustable version only; this is the input to the control loop error amplifier, and is used to set the output voltage
of the device.
OUT
5
Output of the regulator. A small capacitor (total typical capacitance ≥ 2.0μF ceramic) is needed from this pin to
ground to assure stability.
Copyright © 2011, Texas Instruments Incorporated
TPS73433-Q1
TPS73401-Q1
SBVS185 – DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
Over operating temperature range (TA = –40°C to +105°C); VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA, VEN = VIN,COUT
= 2.2μF, CNR = 0.01μF, unless otherwise noted. For TPS73401-Q1, VOUT = 3.0V. Typical values are at TA = +25°C.
TPS73401-Q1 LINE REGULATION
TPS73401-Q1 LOAD REGULATION
0.5
Y-axis range is ±2% of 2.8V
2.85
2.84
0.3
TJ = -40°C
0.2
2.83
TJ = 0°C
2.82
0.1
VOUT (V)
Change in VOUT (%)
2.86
IOUT = 100mA
0.4
0
-0.1
TJ = +25°C
-0.2
2.79
TJ = +85°C
2.77
TJ = +125°C
2.76
TJ = +125°C
-0.4
2.80
2.78
TJ = +85°C
-0.3
TJ = -40°C
2.81
2.75
-0.5
2.74
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0
50
100
250
Figure 4.
TPS73401-Q1 DROPOUT VOLTAGE vs
OUTPUT CURRENT
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
(VIN – VOUT = 1.0V)
400
90
350
80
IOUT = 1mA
70
TJ = +125°C
250
PSRR (dB)
VDO (mV)
200
Figure 3.
300
TJ = +85°C
200
TJ = +25°C
150
IOUT = 250mA
60
IOUT =
100mA
50
40
30
100
20
TJ = 0°C
TJ = -40°C
50
10
0
0
0
50
100
150
200
COUT = 10mF
CNR = 0.01mF
10
250
100
IOUT = 200mA
10k
1k
100k
1M
10M
IOUT (mA)
Frequency (Hz)
Figure 5.
Figure 6.
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
(VIN – VOUT = 0.5V)
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
(VIN – VOUT = 0.3V)
90
90
80
PSRR (dB)
IOUT =
100mA
50
40
30
IOUT = 200mA
60
IOUT =
100mA
50
40
30
20
0
IOUT = 1mA
70
IOUT = 200mA
60
10
80
IOUT = 1mA
70
PSRR (dB)
150
Load (mA)
VIN (V)
20
COUT = 2.2mF
CNR = 0.01mF
10
100
10
IOUT = 250mA
1k
10k
100k
0
1M
10M
COUT = 2.2mF
CNR = 0.01mF
10
100
IOUT =
200mA
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 7.
Figure 8.
Copyright © 2011, Texas Instruments Incorporated
1M
10M
5
TPS73433-Q1
TPS73401-Q1
SBVS185 – DECEMBER 2011
www.ti.com
APPLICATION INFORMATION
The TPS734xx-Q1 family of LDO regulators
combines the high performance required of many RF
and precision analog applications with ultra-low
current consumption. High PSRR is provided by a
high gain, high bandwidth error loop with good supply
rejection at very low headroom (VIN – VOUT). Fixed
voltage versions provide a noise reduction pin to
bypass noise generated by the bandgap reference
and to improve PSRR while a quick-start circuit
fast-charges this capacitor at startup. The
combination of high performance and low ground
current also make the TPS734xx-Q1 an excellent
choice for portable applications. All versions have
thermal and over-current protection and are fully
specified from –40°C to +105°C.
Figure 9 shows the basic circuit connections for fixed
voltage models. Figure 10 gives the connections for
the adjustable output version (TPS73401-Q1). R1 and
R2 can be calculated for any output voltage using the
formula in Figure 10.
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
VOUT
OUT
TPS73433-Q1
EN
VEN
GND
2.2mF
Ceramic
NR
Optional bypass capacitor
to reduce output noise
and increase PSRR.
Figure 9. Typical Application Circuit for
FIxed Voltage Versions
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
VOUT =
(R1 + R2)
R2
VOUT
OUT
TPS73401-Q1
EN
GND
´ 1.208
R1
FB
CFB
2.2mF
Ceramic
R2
VEN
Figure 10. Typical Application Circuit for
Adjustable Voltage Versions
space
space
6
Input and Output Capacitor Requirements
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1μF to 1μF low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. The ground of this capacitor should be
connected as close as the ground of output capacitor;
a capacitor value of 0.1μF is enough in this condition.
When it is difficult to place these two ground points
close together, a 1μF capacitor is recommended.
This capacitor counteracts reactive input sources and
improves transient response, noise rejection, and
ripple rejection. A higher-value capacitor may be
necessary if large, fast rise-time load transients are
anticipated, or if the device is located several inches
from the power source. If source impedance is not
sufficiently low, a 0.1μF input capacitor may be
necessary to ensure stability.
The TPS734xx-Q1 is designed to be stable with
standard ceramic output capacitors of values 2.2μF
or larger. X5R and X7R type capacitors are best
because they have minimal variation in value and
ESR over temperature. Maximum ESR of the output
capacitor should be < 1.0Ω, so output capacitor type
should be either ceramic or conductive polymer
electrolytic.
Feedback Capacitor Requirements
(TPS73401-Q1 only)
The feedback capacitor, CFB, shown in Figure 10 is
required for stability. For a parallel combination of R1
and R2 equal to 250kΩ, any value from 3pF to 1nF
can be used. Fixed voltage versions have an internal
30pF feedback capacitor that is quick-charged at
start-up. The adjustable version does not have this
quick-charge circuit, so values below 5pF should be
used to ensure fast startup; values above 47pF can
be used to implement an output voltage soft-start.
Larger value capacitors also improve noise slightly.
The TPS73401-Q1 is stable in unity-gain
configuration (OUT tied to FB) without CFB.
Output Noise
In most LDOs, the bandgap is the dominant noise
source. If a noise reduction capacitor (CNR) is used
with the TPS734xx-Q1, the bandgap does not
contribute significantly to noise. Instead, noise is
dominated by the output resistor divider and the error
amplifier input. To minimize noise in a given
application, use a 0.01μF noise reduction capacitor;
for the adjustable version, smaller value resistors in
the output resistor divider reduce noise. A parallel
combination that gives 2μA of divider current has the
same noise performance as a fixed voltage version.
Copyright © 2011, Texas Instruments Incorporated
TPS73433-Q1
TPS73401-Q1
SBVS185 – DECEMBER 2011
www.ti.com
To further optimize noise, equivalent series
resistance of the output capacitor can be set to
approximately 0.2Ω. This configuration maximizes
phase margin in the control loop, reducing total
output noise by up to 10%.
Noise can be referred to the feedback point (FB pin)
such that with CNR = 0.01μF, total noise is given
approximately by Equation 1:
11mVRMS
VN =
x VOUT
V
(1)
The TPS73401-Q1 adjustable version does not have
the noise-reduction pin available, so ultra-low noise
operation is not possible. Noise can be minimized
according to the above recommendations.
Board Layout Recommendations to Improve
PSRR and Noise Performance
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
Internal Current Limit
The TPS734xx-Q1 internal current limit helps protect
the regulator during fault conditions. During current
limit, the output sources a fixed amount of current
that is largely independent of output voltage. For
reliable operation, the device should not be operated
in current limit for extended periods of time.
The PMOS pass element in the TPS734xx-Q1 has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting may be
appropriate.
Shutdown
The enable pin (EN) is active high and is compatible
with standard and low voltage TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to IN.
Dropout Voltage
The TPS734xx-Q1 uses a PMOS pass transistor to
achieve low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the PMOS pass device is
in its linear region of operation and the input-to-output
resistance is the RDS, ON of the PMOS pass element.
Because the PMOS device behaves like a resistor in
dropout, VDO approximately scales with output
current.
Copyright © 2011, Texas Instruments Incorporated
As with any linear regulator, PSRR and transient
response are degraded as (VIN – VOUT) approaches
dropout. This effect is shown in the Typical
Characteristics section.
Startup and Noise Reduction Capacitor
Fixed voltage versions of the TPS734xx-Q1 use a
quick-start circuit to fast-charge the noise reduction
capacitor, CNR, if present (see the Functional Block
Diagrams). This architecture allows the combination
of very low output noise and fast start-up times. The
NR pin is high impedance so a low leakage CNR
capacitor must be used; most ceramic capacitors are
appropriate in this configuration.
Note that for fastest startup, VIN should be applied
first, then the enable pin (EN) driven high. If EN is
tied to IN, startup is somewhat slower. Refer to the
Typical Characteristics section. The quick-start switch
is closed for approximately 135μs. To ensure that
CNR is fully charged during the quick-start time, a
0.01μF or smaller capacitor should be used.
Transient Response
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response. In
the adjustable version, adding CFB between OUT and
FB improves stability and transient response. The
transient response of the TPS734xx-Q1 is enhanced
by an active pull-down that engages when the output
overshoots by approximately 5% or more when the
device is enabled. When enabled, the pull-down
device behaves like a 400Ω resistor to ground.
Undervoltage Lock-Out (UVLO)
The TPS734xx-Q1 utilizes an undervoltage lock-out
circuit to keep the output shut off until internal
circuitry is operating properly. The UVLO circuit has a
de-glitch feature so that it typically ignores
undershoot transients on the input if they are less
than 50μs duration.
Minimum Load
The TPS734xx-Q1 is stable and well-behaved with no
output load. To meet the specified accuracy, a
minimum load of 1mA is required. Below 1mA at
junction temperatures near +125°C, the output can
drift up enough to cause the output pull-down to turn
on. The output pull-down limits voltage drift to 5%
typically but ground current could increase by
approximately 50μA. In typical applications, the
junction cannot reach high temperatures at light loads
because there is no appreciable dissipated power.
The specified ground current would then be valid at
no load conditions in most applications.
7
TPS73433-Q1
TPS73401-Q1
SBVS185 – DECEMBER 2011
www.ti.com
Thermal Information
Thermal Protection
Thermal protection disables the output when the
junction temperature rises to approximately +165°C,
allowing the device to cool. When the junction
temperature cools to approximately +145°C the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your particular application. This
configuration produces a worst-case junction
temperature of +125°C at the highest expected
ambient temperature and worst-case load.
The internal protection circuitry of the TPS734xx-Q1
has been designed to protect against overload
conditions. It was not intended to replace proper
heatsinking. Continuously running the TPS734xx-Q1
into thermal shutdown degrades device reliability.
Power Dissipation
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are given in the Dissipation Ratings table. Using
heavier copper increases the effectiveness in
removing heat from the device. The addition of plated
through-holes to heat-dissipating layers also
improves the heatsink effectiveness.
Power dissipation depends on input voltage and load
conditions. Power dissipation is equal to the product
of the output current time the voltage drop across the
output pass element, as shown in Equation 2:
P D + ǒVIN*V OUTǓ @ I OUT
(2)
Package Mounting
Solder pad footprint recommendations for the
TPS734xx-Q1 are available from the Texas
Instruments web site at www.ti.com.
8
Copyright © 2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS73433TDDCRQ1
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
PXTQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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