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TPS736
SBVS038U – SEPTEMBER 2003 – REVISED JANUARY 2015
TPS736xx Cap-Free, NMOS, 400-mA Low-Dropout Regulator with Reverse Current
Protection
1 Features
3 Description
•
The TPS736xx family of low-dropout (LDO) linear
voltage regulators uses a new topology: an NMOS
pass element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly constant
over all values of output current.
1
•
•
•
•
•
•
•
•
•
•
Stable with No Output Capacitor or Any Value or
Type of Capacitor
Input Voltage Range of 1.7 V to 5.5 V
Ultra-Low Dropout Voltage: 75 mV typ
Excellent Load Transient Response—with or
without Optional Output Capacitor
New NMOS Topology Delivers Low Reverse
Leakage Current
Low Noise: 30 μVRMS typ (10 Hz to 100 kHz)
0.5% Initial Accuracy
1% Overall Accuracy Over Line, Load, and
Temperature
Less Than 1 μA max IQ in Shutdown Mode
Thermal Shutdown and Specified Min/Max
Current Limit Protection
Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.20 V to 5.0 V
– Adjustable Output from 1.20 V to 5.5 V
– Custom Outputs Available
The TPS736xx uses an advanced BiCMOS process
to yield high precision while delivering very low
dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1 μA and
ideal for portable applications. The extremely low
output noise (30 μVRMS with 0.1-μF CNR) is ideal for
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
Device Information(1)
PART NUMBER
TPS736xx
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm x 1.60 mm
SOT-223 (6)
6.50 mm x 3.50 mm
VSON (8)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
PACKAGE
Portable/Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
Typical Application Circuit for Fixed-Voltage Versions
Optional
VIN
Optional
IN
VOUT
OUT
TPS736xx
EN
GND
NR
ON
OFF
Optional
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS736
SBVS038U – SEPTEMBER 2003 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Applications ................................................ 15
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 20
10.1
10.2
10.3
10.4
10.5
Layout Guidelines .................................................
Layout Examples...................................................
Power Dissipation .................................................
Thermal Protection................................................
Package Mounting ................................................
20
20
21
22
22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision T (August 2010) to Revision U
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement ................... 4
•
Changed "free-air temperature" to "junction temperature" in Recommended Operating Conditions condition
statement ............................................................................................................................................................................... 4
•
Changed Thermal Information table; updated thermal resistance values for all packages .................................................. 5
Changes from Revision S (August, 2009) to Revision T
•
Page
Replaced Dissipation Ratings Table with Thermal Information Table.................................................................................... 4
Changes from Revision R (May, 2008) to Revision S
Page
•
Changed Figure 10 ................................................................................................................................................................ 7
•
Added paragraph about recommended start-up sequence to Internal Current Limit section .............................................. 14
•
Added paragraph about current foldback and device start-up to Enable Pin and Shutdown section .................................. 14
2
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SBVS038U – SEPTEMBER 2003 – REVISED JANUARY 2015
5 Pin Configuration and Functions
DBV Package
5-Pin SOT23
(Top View)
IN
1
GND
2
EN
3
5
DCQ Package
6-Pin SOT223
(Top View)
OUT
6
4
NR/FB
1
2
IN
3
4
GND
OUT
5
EN
NR/FB
DRB Package
8-Pin VSON
(Top View)
1
8
IN
N/C 2
7
N/C
OUT
NR/FB 3
6
N/C
GND 4
5
EN
Pin Functions
PIN
NO.
I/O
DESCRIPTION
SOT23
SOT22
3
VSON
IN
1
1
8
I
GND
2
3, 6
4, Pad
—
EN
3
5
5
I
NR
4
4
3
—
Fixed-voltage versions only. Connecting an external capacitor to this noise reduction
pin bypasses noise generated by the internal bandgap, reducing output noise to very
low levels.
FB
4
4
3
I
Adjustable-voltage version only. This pin is the input to the control loop error amplifier,
and sets the output voltage of the device.
OUT
5
2
1
O
Output of the regulator. There are no output capacitor requirements for stability.
NAME
Input supply
Ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the
regulator into shutdown mode. Refer to the Shutdown section for more details. EN can
be connected to IN if not used.
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SBVS038U – SEPTEMBER 2003 – REVISED JANUARY 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
Voltage
Peak output current
(1)
MIN
MAX
UNIT
VIN
–0.3
+6.0
V
VEN
–0.3
+6.0
V
VOUT
–0.3
+5.5
V
VNR, VFB
–0.3
+6.0
V
IOUT
Internally limited
Output short-circuit duration
Indefinite
Continuous total power
dissipation
PDISS
TJ
Junction temperature range
–55
150
°C
Tstg
Storage temperature range
–65
150
°C
(1)
See Thermal Information
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Electrical
Characteristics Exposure to absolute maximum rated conditions for extended periods may affect device reliability
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VIN
Input supply voltage range
IOUT
Output current
TJ
Operating junction temperature
4
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NOM
MAX
UNIT
1.7
5.5
V
0
500
mA
–40
125
°C
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SBVS038U – SEPTEMBER 2003 – REVISED JANUARY 2015
6.4 Thermal Information
TPS736 (3)
THERMAL METRIC
RθJA
(1) (2)
Junction-to-ambient thermal resistance (4)
(5)
DRB/SON
DCQ/SOT223
DBV/SOT23
8 PINS
6 PINS
5 PINS
52.8
118.7
221.9
RθJC(top)
Junction-to-case (top) thermal resistance
60.4
64.9
74.9
RθJB
Junction-to-board thermal resistance (6)
28.4
65.0
51.9
ψJT
Junction-to-top characterization parameter (7)
2.1
14.0
2.8
ψJB
Junction-to-board characterization parameter (8)
28.6
63.8
51.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance (9)
12.0
N/A
N/A
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
. ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
. iii. DBV: There is no exposed pad with the DBV package.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
. ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
. iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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SBVS038U – SEPTEMBER 2003 – REVISED JANUARY 2015
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6.5 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V (1), IOUT = 10 mA, VEN = 1.7 V, and
COUT = 0.1 μF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
VIN
Input voltage range (1) (2)
VFB
Internal reference (TPS73601)
TEST CONDITIONS
Nominal
Accuracy (1) (4) over VIN, IOUT,
and T
(1)
TYP
1.7
TJ = 25°C
Output voltage range
(TPS73601) (3)
VOUT
MIN
TJ = 25°C
VOUT + 0.5 V ≤ VIN ≤ 5.5 V;
10 mA ≤ IOUT ≤ 400 mA
ΔVOUT(ΔVIN)
Line regulation
ΔVOUT(ΔIOUT)
Load regulation
VDO
Dropout voltage (5)
(VIN = VOUT(nom) – 0.1 V)
IOUT = 400 mA
ZO(do)
Output impedance in dropout
1.7 V ≤ VIN ≤ VOUT + VDO
MAX
UNIT
5.5
V
1.210
V
VFB
5.5 – VDO
V
–0.5
+0.5
1.198
–1.0%
VO(nom) + 0.5 V ≤ VIN ≤ 5.5 V
1.20
±0.5%
+1.0%
0.01
1 mA ≤ IOUT ≤ 400 mA
0.002
10 mA ≤ IOUT ≤ 400 mA
0.0005
75
%/V
%/mA
200
mV
800
mA
800
mA
Ω
0.25
VOUT = 0.9 × VOUT(nom)
400
3.6 V ≤ VIN ≤ 4.2 V, 0°C ≤ TJ ≤ 70°C
500
650
ICL
Output current limit
ISC
Short-circuit current
VOUT = 0 V
450
IREV
Reverse leakage current (6) (–IIN)
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
0.1
10
IOUT = 10 mA (IQ)
400
550
IOUT = 400 mA
800
1000
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5,
–40°C ≤ TJ ≤ 100°C
0.02
1
μA
0.1
0.3
μA
IGND
GND pin current
ISHDN
Shutdown current (IGND)
IFB
FB pin current (TPS73601)
PSRR
Power-supply rejection ratio
(ripple rejection)
f = 100 Hz, IOUT = 400 mA
58
f = 10 kHz, IOUT = 400 mA
37
Vn
Output noise voltage
BW = 10Hz – 100KHz
COUT = 10 μF, No CNR
27 × VOUT
COUT = 10 μF, CNR = 0.01 μF
8.5 × VOUT
tSTR
Startup time
VEN(high)
EN pin high (enabled)
VEN(low)
EN pin low (shutdown)
IEN(high)
EN pin current (enabled)
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
(5)
(6)
6
VOUT = 3 V, RL = 30 Ω COUT = 1 μF,
CNR = 0.01 μF
mA
μVRMS
μs
VIN
0
VEN = 5.5 V
0.02
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
–40
μA
dB
600
1.7
μA
V
0.5
V
0.1
μA
°C
125
°C
Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
For VOUT(nom) < 1.6 V, when VIN ≤ 1.6 V, the output locks to VIN and may result in a damaging over-voltage level on the output. To avoid
this situation, disable the device before powering down the VIN.
TPS73601 is tested at VOUT = 2.5 V.
Tolerance of external resistors not included in this specification.
VDO is not measured for fixed output versions with VOUT(nom) < 1.8 V.
Fixed-voltage versions only; refer to Application Information section for more information.
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6.6 Typical Characteristics
For all voltage versions, at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
0.20
0.5
Referred to IOUT = 10mA
−40_C
+25_C
+125_ C
Change in VOUT (%)
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
0.15
Change in VOUT (%)
0.4
0.10
0
−0.05
−40_ C
−0.10
−0.15
−0.4
−0.20
−0.5
0
50
100
150
200
250
300
350
0
400
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN − VOUT (V)
IOUT (mA)
Figure 1. Load Regulation
Figure 2. Line Regulation
100
100
TPS73625DBV
+125_ C
80
80
60
VDO (mV)
VDO (mV)
+25_ C
+125_C
0.05
+25_ C
40
−40_C
20
50
100
150
200
250
300
60
40
20
0
−50
0
0
TPS73625DBV
I OUT = 400mA
350
400
IOUT (mA)
−25
0
25
50
75
100
125
Temperature (_ C)
Figure 3. Dropout Voltage vs Output Current
Figure 4. Dropout Voltage vs Temperature
30
18
IOUT = 10mA
IOUT = 10mA
All Voltage Versions
16
25
Percent of Units (%)
Percent of Units (%)
14
20
15
10
12
10
8
6
4
5
2
0
−1.0
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
100
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/_C)
Figure 5. Output Voltage Accuracy Histogram
Figure 6. Output Voltage Drift Histogram
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Typical Characteristics (continued)
For all voltage versions, at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
900
800
800
700
700
600
600
I GND (µA)
1000
900
IGND (µA)
1000
500
400
300
IOUT = 400mA
500
400
300
VIN = 5.5V
VIN = 4V
VIN = 2V
200
100
100
0
0
100
200
300
VIN = 5.5V
VIN = 3V
VIN = 2V
200
0
−50
400
−25
0
IOUT (mA)
Figure 7. Ground Pin Current vs Output Current
50
75
100
125
Figure 8. Ground Pin Current vs Temperature
800
1
TPS73633
VENABLE = 0.5V
VIN = VO + 0.5V
700
Output Current (mA)
IGND (µA)
25
Temperature (_C)
0.1
ICL
600
500
ISC
400
300
200
100
0.01
−50
−25
0
25
50
75
100
0
-0.5
125
0
0.5
800
800
750
750
700
700
Current Limit (mA)
Current Limit (mA)
1.5
2.0
2.5
3.0
3.5
Figure 10. Current Limit vs VOUT(Foldback)
Figure 9. Ground Pin Current In Shutdown vs Temperature
650
600
550
500
450
650
600
550
500
450
400
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
400
−50
VIN (V)
−25
0
25
50
75
100
125
Temperature (_C)
Figure 11. Current Limit vs VIN
8
1.0
Output Voltage (V)
Temperature (_C)
Figure 12. Current Limit vs Temperature
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Typical Characteristics (continued)
For all voltage versions, at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
90
40
IOUT = 100mA
COUT = Any
Ripple Rejection (dB)
70
IOUT = 1mA
COUT = 1µF
35
30
IOUT = 1mA
COUT = 10µF
60
50
IO = 100mA
CO = 1µF
IOUT = 1mA
C OUT = Any
40
25
PSRR (dB)
80
20
15
30
20
IOUT = Any
COUT = 0µF
10
VIN = VOUT + 1V
0
10
100
1k
10k
Frequency = 10kHz
COUT = 10mF
VOUT = 2.5V
IOUT = 100mA
10
I OUT = 100mA
COUT = 10µF
5
0
100k
1M
0
10M
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VIN - VOUT (V)
Frequency (Hz)
Figure 14. PSRR (Ripple Rejection) vs VIN – VOUT
Figure 13. PSRR (Ripple Rejection) vs Frequency
1
1
COUT = 0µF
0.1
COUT = 10µF
eN (µV/√Hz)
eN (µV/√Hz)
C OUT = 1µF
COUT = 1µF
0.1
COUT = 0µF
COUT = 10µF
IOUT = 150mA
IOUT = 150mA
0.01
0.01
10
100
1k
10k
100k
10
100
Frequency (Hz)
1k
10k
100k
Frequency (Hz)
Figure 15. Noise Spectral Density cNR = 0 μF
Figure 16. Noise Spectral Density cNR = 0.01 μF
60
140
50
120
VOUT = 5.0V
VOUT = 5.0V
100
30
VN (RMS)
VN (RMS)
40
VOUT = 3.3V
80
VOUT = 3.3V
60
20
40
VOUT = 1.5V
10
0
20
CNR = 0.01µF
10Hz < Frequency < 100kHz
0.1
0
1
10
VOUT = 1.5V
COUT = 0µF
10Hz < Frequency < 100kHz
1p
10p
100p
1n
COUT (µF)
CNR (F)
Figure 17. RMS Noise Voltage vs COUT
Figure 18. RMS Noise Voltage vs CNR
10n
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Typical Characteristics (continued)
For all voltage versions, at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
VIN = 3.8V
COUT = 0µF
100mV/tick
IOUT = 400mA
VOUT
COUT = 0µF
50mV/div
COUT = 1µF
50mV/tick
COUT = 10µF
20mV/tick
VOUT
VOUT
VOUT
COUT = 100µF
50mV/div
VOUT
dVIN
5.5V
400mA
IOUT
50mA/tick
10mA
1V/div
VIN
10µs/div
10µs/div
Figure 19. TPS73633 Load Transient Response
RL = 1kΩ
CO UT = 0µF
Figure 20. TPS73633 Line Transient Response
R L = 20Ω
C OUT = 10µF
VOUT
RL = 20Ω
COUT = 1µF
1V/div
R L = 20Ω
C OUT = 1µF
1V/div
R L = 1kΩ
C OUT = 0µF
RL = 20Ω
COUT = 10µF
VOUT
2V
2V
VEN
1V/div
1V/div
0V
0V
VEN
100µs/div
100µs/div
Figure 21. TPS73633 Turn-On Response
Figure 22. TPS73633 Turn-Off Response
10
6
5
4
VIN
VOUT
IENABLE (nA)
3
Volts
= 0.5V/µs
dt
4.5V
2
1
1
0.1
0
−1
−2
0.01
−50
50ms/div
−25
0
25
50
75
100
125
Temperature (_ C)
Figure 23. TPS73633 Power Up / Power Down
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Typical Characteristics (continued)
60
160
55
140
50
120
45
100
IFB (nA)
VN (rms)
For all voltage versions, at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
40
60
35
30
25
80
VOUT = 2.5V
COUT = 0µF
R1 = 39.2kΩ
10Hz < Frequency < 100kHz
20
10p
100p
40
20
1n
10n
0
−50
−25
0
25
50
75
100
CFB (F)
Temperature (_C)
Figure 25. TPS73601 RMS Noise Voltage vs CFB
Figure 26. TPS73601 IFB vs Temperature
CFB = 10nF
R1 = 39.2kΩ
COUT = 0µF
200mV/div
VOUT
COUT = 0µF
200mV/div
VOUT = 2.5V
CFB = 10nF
100mV/div
COUT = 10µF
100mV/div
COUT = 10µF
125
VOUT
VOUT
VOUT
4.5V
400mA
3.5V
VIN
10mA
IOUT
25µs/div
5µs/div
Figure 27. TPS73601 Load Transient, Adjustable Version
Figure 28. TPS73601 Line Transient, Adjustable Version
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7 Detailed Description
7.1 Overview
The TPS736xx family of low-dropout linear regulators operates down to an input voltage of 1.7 V and supports
output voltages down to 1.2 V while sourcing up to 500 mA of load current. This linear regulator utilizes an
NMOS pass element with an integrated 4-MHz charge pump to provide a dropout voltage of less than 200 mV at
full load current. This unique architecture also permits stable regulation over a wide range of output capacitors. In
fact, the TPS736xx family of devices does not require any output capacitor for stability. The increased
insensitivity to the output capacitor value and type makes this family of linear regulators an ideal choice when
powering a load where the effective capacitance is unknown.
The TPS736xx family of devices also features a noise reduction (NR) pin that allows for additional reduction of
the output noise. With a noise reduction capacitor of 0.01 µF connected from the NR pin to GND, the TPS73615
output noise can be as low as 12.75 µVRMS. The low noise output featured by the TPS736xx family makes it wellsuited for powering VCOs or any other noise sensitive load.
7.2 Functional Block Diagram
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27kW
Bandgap
Error
Amp
Current
Limit
OUT
8kW
GND
R1
R1 + R2 = 80kW
R2
NR
Figure 29. Fixed-Voltage Version
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Functional Block Diagram (continued)
IN
Standard 1%
Resistor Values for
Common Output Voltages
4MHz
Charge Pump
EN
VO
Thermal
Protection
Ref
Servo
27kW
Bandgap
Error
Amp
OUT
Current
Limit
GND
80kW
8kW
R1
R1
R2
1.2V
Short
Open
1.5V
23.2kW
95.3kW
1.8V
28.0kW
56.2kW
2.5V
39.2kW
36.5kW
2.8V
44.2kW
33.2kW
3.0V
46.4kW
30.9kW
3.3V
52.3kW
30.1kW
NOTE: VOUT = (R1 + R2)/R2 × 1.204;
R1||R 2 @ 19kW for best
accuracy.
FB
R2
Figure 30. Adjustable-Voltage Version
7.3 Feature Description
7.3.1 Output Noise
A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the
dominant noise source within the TPS736xx and it generates approximately 32 μVRMS (10 Hz to 100 kHz) at the
reference output (NR). The regulator control loop gains up the reference noise with the same gain as the
reference voltage, so that the noise voltage of the regulator is approximately given by:
(R1 ) R2)
+ 32mVRMS
R2
V N + 32mVRMS
VOUT
VREF
(1)
Since the value of VREF is 1.2 V, this relationship reduces to:
ǒmVV Ǔ
RMS
V N(mVRMS) + 27
V OUT(V)
(2)
for the case of no CNR.
An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF,
the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of ~3.2, giving the approximate
relationship:
ǒmVV Ǔ
V N(mVRMS) + 8.5
RMS
V OUT(V)
(3)
for CNR = 10 nF.
This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section.
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Feature Description (continued)
The TPS73601 adjustable version does not have the NR pin available. However, connecting a feedback
capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improves load transient
performance.
The TPS736xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of
the NMOS pass element above VOUT. The charge pump generates ~250 μV of switching noise at ~4 MHz;
however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and
COUT.
7.3.2 Internal Current Limit
The TPS736xx internal current limit helps protect the regulator during fault conditions. Foldback current limit
helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when
VOUT drops below 0.5 V. See Figure 10 in the Typical Characteristics section.
Note from Figure 10 that approximately –0.2 V of VOUT results in a current limit of 0 mA. Therefore, if OUT is
forced below –0.2 V before EN goes high, the device may not start up. In applications that work with both a
positive and negative voltage supply, the TPS736xx should be enabled first.
7.3.3 Enable Pin and Shutdown
The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. VEN below 0.5 V (max)
turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to shutdown the
regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated VOUT
(see Figure 19).
When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after
VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster
ramp times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output may
overshoot upon power-up.
Note that current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit
section for more information.
7.3.4 Reverse Current
The NMOS pass element of the TPS736xx provides inherent protection against current flow from the output of
the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed
from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is
not done, the pass element may be left on due to stored charge on the gate.
After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that
reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There
is additional current flowing into the OUT pin due to the 80-kΩ internal resistor divider to ground (see Figure 29
and Figure 30).
For the TPS73601, reverse current may flow when VFB is more than 1.0 V above VIN.
7.4 Device Functional Modes
7.4.1 Normal Operation with 1.7 V ≤ VIN ≤ 5.5 V and VEN ≥ 1.7 V
The TPS736xx family requires an input voltage of at least 1.7 V to function properly and attempt to maintain
regulation. Please note that if the device output voltage is greater than 1.5 V when the input voltage is at 1.7 V,
the device is operating in dropout and regulation cannot be maintained. Due the NMOS architecture used in the
TPS736xx devices, the dropout voltage is not a strong function of the input voltage.
When operating the device near 5.5 V, take care to suppress any transient spikes that may exceed the 6.0-V
absolute maximum voltage rating. The device should never operate at a dc voltage greater than 5.5 V.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS736xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints.
These features, combined with low noise and an enable input, make the TPS736xx ideal for portable
applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable
output version. All versions have thermal and over-current protection, including foldback current limit.
8.2 Typical Applications
Figure 31 shows the basic circuit connections for the fixed voltage models. Figure 32 gives the connections for
the adjustable output version (TPS73601).
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
Optional output capacitor.
May improve load transient,
noise, or PSRR.
IN
VOUT
OUT
TPS736xx
EN
GND
NR
ON
OFF
Optional bypass
capacitor to reduce
output noise.
Figure 31. Typical Application Circuit for Fixed-Voltage Versions
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
Optional output capacitor.
May improve load transient,
noise, or PSRR.
TPS73601
EN
OFF
VOUT
OUT
GND
R1
CFB
FB
ON
R2
VOUT =
(R1 + R2)
R2
x 1.204
Optional capacitor
reduces output noise
and improves
transient response.
Figure 32. Typical Application Circuit for Adjustable-Voltage Version
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Typical Applications (continued)
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 below as the input parameters.
Table 1. Design Parameters (Fixed-Voltage Version)
PARAMETER
DESIGN REQUIREMENT
Input voltage
5 V, ±3%
Output voltage
3.3 V, ±1%
Output current
500 mA (maximum), 20 mA (minimum)
RMS noise, 10 Hz to 100 kHz
< 30 μVRMS
Ambient temperature
55°C (Maximum)
Table 2. Design Parameters (Adjustable-Voltage Version)
PARAMETER
DESIGN REQUIREMENT
Input voltage
5 V, ±3%, provided by the dc/dc converter switching at 1 MHz
Output voltage
2.5 V, ±1%
Output current
0.4 A (maximum), 10 mA (minimum)
RMS noise, 10 Hz to 100 kHz
< 35 μVRMS
Ambient temperature
55°C (Maximum)
8.2.2 Detailed Design Procedure
The first step when designing with a linear regulator is to examine the maximum load current along with the input
and output voltage requirements to determine if the device thermal and dropout voltage requirements can be
met. At 0.5 A, the dropout voltage of the TPS73633 is a maximum of 200 mV over temperature; thus, the dropout
headroom is sufficient for operation over both input and output voltage accuracy.
The maximum power dissipated in the linear regulator is the maximum voltage dropped across the pass element
from the input to the output times the maximum load current. In this example, the maximum voltage drop across
in the pass element is 5 V + 3% (5.15 V) minus 3.3 V – 1% (3.267 V) or 1.883 V. The power dissipated in the
pass element is calculated by taking this voltage drop multiplied by the maximum load current. For this example,
the maximum power dissipated in the linear regulator is 942 mW. Once the power dissipated in the linear
regulator is known, the corresponding junction temperature rise can be calculated. To calculate the junction
temperature rise above ambient, the power dissipated must be multiplied by the junction-to-ambient thermal
resistance. For thermal resistance information please refer to Thermal Protection. For this example, using the
DRB package, the maximum junction temperature rise is calculated to be 45°C. The maximum junction
temperature rise is calculated by adding junction temperature rise to the maximum ambient temperature. In this
example, the maximum junction temperature is 100°C. Keep in mind the maximum junction temperate must be
below 125°C for reliable operation. Addition ground planes, added thermal vias, and air flow all help to lower the
maximum junction temperature. Using the DCQ or DBV packages are not recommended for this application due
to the excessive junction temperature rise that would be incurred.
To get the noise level below 30 µVRMS, a noise reduction capacitance (CNR) of 10 nF is selected along with an
output capacitance of 10 μF. Referencing the Output Noise section, the RMS noise can be calculated to be
28 µVRMS.
Use of an input capacitor is optional. However, in systems where the input supply is located several inches away
from the LDO, a small 0.1-µF input capacitor is recommended to negate the adverse effects that input supply
inductance has on stability and ac performance.
In the same way as with designing with a fixed output voltage, the first step is to examine the maximum load
current along with the input and output voltage requirements to determine if the device thermal and dropout
voltage requirements are met. At 0.4 A, the maximum dropout voltage can be approximated by assuming a linear
characteristic of the dropout voltage with load current. The maximum dropout voltage can be estimated to be
200 mV times the ratio of the load current to specified dropout voltage load current. For this example, the dropout
can be estimated to be 200 mV × 400 mA/500 mA or 160 mV. Since the input voltage is 5 V and the output
voltage is 2.5 V, there is more than sufficient voltage headroom to avoid dropout and maintain good PSRR.
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The maximum power dissipated in the linear regulator is the maximum voltage dropped across the pass element
from the input to the output times the maximum load current. In this example, the maximum voltage drop across
in the pass element is 5 V + 3% (5.15 V) minus 2.5 V – 1% (2.475 V) or 2.675 V. The power dissipated in the
pass element is calculated by taking this voltage drop multiplied by the maximum load current. For this example,
the maximum power dissipated in the linear regulator is 1.07 W. Once the power dissipated in the linear regulator
is known, the corresponding junction temperature rise can be calculated. To calculate the junction temperature
rise above ambient, the power dissipated must be multiplied by the junction-to-ambient thermal resistance. For
thermal resistance information, refer to Thermal Information. For this example, using the DRB package, the
maximum junction temperature rise is calculated to be 51°C. The maximum junction temperature rise is
calculated by adding junction temperature rise to the maximum ambient temperature. In this example, the
maximum junction temperature is 106°C. Keep in mind the maximum junction temperate must be below 125°C
for reliable operation. Addition ground planes, added thermal vias, and air flow all help to lower the maximum
junction temperature. Using the DCQ or DBV packages are not recommended for this application due to the
excessive junction temperature rise that would be incurred.
R1 and R2 can be calculated for any output voltage using the formula shown in Figure 32. Sample resistor values
for common output voltages are shown in Figure 30.
For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19 kΩ. This 19 kΩ, in
addition to the internal 8-kΩ resistor, presents the same impedance to the error amp as the 27-kΩ bandgap
reference output. This impedance helps compensate for leakages into the error amp terminals.
Using the values shown in Figure 40xx for a 2.5-V output results in a values of 39.2 kΩ for R1 and 36.5 kΩ for
R2.
To get the noise level below 35 µVRMS, a noise reduction capacitance (CFF) of 10 nF is selected. Figure 25
should be used as a reference when selecting optimal value for CFF.
A 10-µF, low equivalent series resistance (ESR) ceramic X5R capacitor was used on the output of this design to
minimize the output voltage droop during a low transient. Use of an input capacitor is optional. However, in
systems where the input supply is located several inches away from the LDO, a small 0.1-µF input capacitor is
recommended to negate the adverse effects that input supply inductance has on stability and ac performance.
Refer to Input and Output Capacitor Requirements for additional information about input and output capacitor
selection.
8.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to
1-μF, low ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input
sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be
necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the
power source.
The TPS736xx does not require an output capacitor for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available types and values of capacitors. In applications where
multiple low ESR capacitors are in parallel, ringing may occur when the product of COUT and total ESR drops
below 50 nΩF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and
solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance meets this
requirement.
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8.2.2.2 Dropout Voltage
The TPS736xx uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS(on) of the NMOS pass element.
For large step changes in load current, the TPS736xx requires a larger voltage drop from VIN to VOUT to avoid
degraded transient response. The boundary of this transient dropout region is approximately twice the dc
dropout. Values of VIN – VOUT above this line ensure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recover
from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load
current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale
instantaneous load change with (VIN – VOUT) close to dc dropout levels], the TPS736xx can take a couple of
hundred microseconds to return to the specified regulation accuracy.
8.2.2.3 Transient Response
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration
allows operation without an output capacitor for many applications. As with any regulator, the addition of a
capacitor (nominal value 1 μF) from the OUT pin to ground reduces undershoot magnitude but increase its
duration. In the adjustable version, the addition of a capacitor, CFB, from the OUT pin to the FB pin also improves
the transient response.
The TPS736xx does not have active pull-down when the output is over-voltage. This feature allows applications
that connect higher voltage sources, such as alternate power supplies, to the output. This feature also results in
an output overshoot of several percent if load current quickly drops to zero when a capacitor is connected to the
output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate
determined by output capacitor COUT and the internal/external load resistance. The rate of decay is given by:
(Fixed Voltage Version)
dVńdt +
C OUT
VOUT
80kW ø R LOAD
(4)
(Adjustable Voltage Version)
dVńdt +
18
C OUT
V OUT
80kW ø (R 1 ) R 2) ø R LOAD
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8.2.3 Application Curves
RL = 1kΩ
CO UT = 0µF
1V/div
VOUT
VIN = 3.8V
COUT = 0µF
100mV/tick
VOUT
RL = 20Ω
COUT = 1µF
COUT = 1µF
50mV/tick
RL = 20Ω
COUT = 10µF
2V
VEN
COUT = 10µF
20mV/tick
VOUT
VOUT
1V/div
400mA
0V
IOUT
50mA/tick
10mA
100µs/div
10µs/div
Figure 33. TPS73633 Turn-On Response
Figure 34. TPS73633 Load Transient Response
60
CFB = 10nF
R1 = 39.2kΩ
55
VN (rms)
COUT = 0µF
200mV/div
50
VOUT
45
40
30
25
COUT = 10µF
200mV/div
35
VOUT = 2.5V
COUT = 0µF
R1 = 39.2kΩ
10Hz < Frequency < 100kHz
20
10p
100p
VOUT
400mA
10mA
1n
IOUT
25µs/div
10n
CFB (F)
Figure 35. TPS73601 RMS Noise Voltage vs CFB
Figure 36. TPS73601 Load Transient, Adjustable Version
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9 Power Supply Recommendations
This device is designed to operate with an input supply range of 1.7 V to 5.5 V. If the input supply is noisy,
additional input capacitors with low ESR can help improve output noise performance.
10 Layout
10.1 Layout Guidelines
To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the
board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the
GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the
GND pin of the device.
10.2 Layout Examples
GND PLANE
COUT
VIN
TPS736xxDRB
VOUT
CNR
1
8
N/C
2
7
N/C
NR/FB
3
6
N/C
4
5
EN
CIN
GND PLANE
Figure 37. Fixed Output Voltage Option Layout (DRB Package)
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Layout Examples (continued)
GND PLANE
COUT
VOUT
VIN
TPS73601DRB
CFF
R1
N/C
NR/FB
R2
1
8
2
7
N/C
3
6
N/C
4
5
EN
CIN
GND PLANE
Figure 38. Adjustable Output Voltage Option Layout (DRB Package)
10.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Thermal
Information table. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heat-sink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current times the voltage drop across the output pass element (VIN to VOUT):
space
P D + (VIN * VOUT)
I OUT
(6)
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required
output voltage.
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10.4 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of your application. This produces a worstcase junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS736xx has been designed to protect against overload conditions. It
was not intended to replace proper heat sinking. Continuously running the TPS736xx into thermal shutdown
degrades device reliability.
10.5 Package Mounting
Solder pad footprint recommendations for the TPS736xx are presented in Application Note Solder Pad
Recommendations for Surface-Mount Devices (SBFA015), available from the Texas Instruments web site at
www.ti.com.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS736xx. The TPS73601DRBEVM-518 evaluation module (and related user guide) can be requested at the
Texas Instruments website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS736 is available through the product folders under
Simulation Models.
11.1.2 Device Nomenclature
Table 3. Device Nomenclature (1)
PRODUCT
TPS736xx yyy z
(1)
VOUT
XX is the nominal output voltage (for example, 25 = 2.5 V; 01 = Adjustable).
YYY is the package designator.
Z is the tape and reel quantity (R = 3000, T = 250).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
• Application note. Regulating VOUT Below 1.2 V Using an External Reference. Literature number SLVA216.
• TPS73x01DRBEVM-518 User's Guide. Literature number SBVU014.
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: TPS736
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS73601DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PJFQ
Samples
TPS73601DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PJFQ
Samples
TPS73601DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PJFQ
Samples
TPS73601DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PJFQ
Samples
TPS73601DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS73601
Samples
TPS73601DCQG4
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73601
Samples
TPS73601DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS73601
Samples
TPS73601DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PJFQ
Samples
TPS73601DRBRG4
ACTIVE
SON
DRB
8
3000
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
PJFQ
Samples
TPS73601DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PJFQ
Samples
TPS73601DRBTG4
ACTIVE
SON
DRB
8
250
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
PJFQ
Samples
TPS736125DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T49
Samples
TPS736125DRBT
LIFEBUY
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T49
TPS73615DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T44
Samples
TPS73615DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T44
Samples
TPS73615DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73615
Samples
TPS73615DCQR
LIFEBUY
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS73615
TPS73615DCQRG4
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73615
Samples
TPS73615DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T44
Samples
TPS73615DRBT
LIFEBUY
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T44
TPS73615DRBTG4
LIFEBUY
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T44
Addendum-Page 1
NIPDAU
NIPDAU
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS73616DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OCQ
Samples
TPS73616DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OCQ
Samples
TPS73618DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T43
Samples
TPS73618DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T43
Samples
TPS73618DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T43
Samples
TPS73618DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T43
Samples
TPS73618DCQ
LIFEBUY
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73618
TPS73618DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS73618
Samples
TPS73618DCQRG4
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73618
Samples
TPS73619DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BYY
Samples
TPS73619DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BYY
Samples
TPS73625DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T42
Samples
TPS73625DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T42
Samples
TPS73625DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T42
Samples
TPS73625DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T42
Samples
TPS73625DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73625
Samples
TPS73625DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS73625
Samples
TPS73630DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T45
Samples
TPS73630DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T45
Samples
TPS73630DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T45
Samples
TPS73630DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T45
Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS73630DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73630
Samples
TPS73630DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73630
Samples
TPS73632DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T53
Samples
TPS73632DBVT
LIFEBUY
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T53
TPS73633DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T46
Samples
TPS73633DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T46
Samples
TPS73633DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T46
Samples
TPS73633DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T46
Samples
TPS73633DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73633
Samples
TPS73633DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73633
Samples
TPS73633DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T46
Samples
TPS73633DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T46
Samples
TPS73633DRBTG4
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T46
Samples
TPS73643DBVR
LIFEBUY
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T54
TPS73643DBVRG4
LIFEBUY
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T54
TPS73643DBVT
LIFEBUY
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T54
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2022
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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