Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
TPS737xx 1-A Low-Dropout Regulator With Reverse Current Protection
1 Features
3 Description
•
The TPS737xx family of linear low-dropout (LDO)
voltage regulators uses an NMOS pass element in a
voltage-follower configuration. This topology is
relatively insensitive to output capacitor value and
ESR, allowing a wide variety of load configurations.
Load transient response is excellent, even with a
small 1-μF ceramic output capacitor. The NMOS
topology also allows very low dropout.
1
•
•
•
•
•
•
•
•
•
Stable With 1-μF or Larger Ceramic Output
Capacitor
Input Voltage Range: 2.2 V to 5.5 V
Ultralow Dropout Voltage: 130 mV Typical at 1 A
Excellent Load Transient Response—Even With
Only 1-μF Output Capacitor
NMOS Topology Delivers Low Reverse Leakage
Current
1% Initial Accuracy
3% Overall Accuracy Over Line, Load, and
Temperature
Less Than 20 nA Typical IQ in Shutdown Mode
Thermal Shutdown and Current Limit for Fault
Protection
Available in Multiple Output Voltage Versions
– Adjustable Output: 1.20 V to 5.5 V
– Custom Outputs Available Using Factory
Package-Level Programming
The TPS737xx family uses an advanced BiCMOS
process to yield high precision while delivering very
low dropout voltages and low ground pin current.
Current consumption, when not enabled, is less than
20 nA and ideal for portable applications. These
devices are protected by thermal shutdown and
foldback current limit.
For applications that require higher output voltage
accuracy, consider TI's TPS7A37xx family of 1%
overall accuracy, 1-A low-dropout voltage regulators.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
TPS737xx
Point-of-Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
Post-Regulation for Switching Supplies
Portable and Battery-Powered Equipment
space
PACKAGE
BODY SIZE (NOM)
VSON (8)
3.00 mm × 3.00 mm
SOT-223 (6)
6.50 mm × 3.50 mm
WSON (6)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
Optional
VIN
IN
OUT
1.0mF
TPS737xx
EN
OFF
GND
VOUT
FB
ON
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
13
13
14
15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application .................................................. 16
8.3 What To Do and What Not To Do........................... 18
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision Q (May 2015) to Revision R
Page
•
Changed WSON to VSON and VSON to WSON in header row of Pin Functions table ....................................................... 4
•
Changed unit from V to % in VOUT parameter of Electrical Characteristics table .................................................................. 7
Changes from Revision P (July 2013) to Revision Q
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement ................... 5
•
Changed "free-air temperature" to "junction temperature" in Recommended Operating Conditions condition
statement ............................................................................................................................................................................... 5
•
Changed Internal Reference parameter (VFB) typical values from 1.2 V to 1.204 V.............................................................. 7
Changes from Revision O (June 2012) to Revision P
•
Page
Added last paragraph to Description section.......................................................................................................................... 1
Changes from Revision N (June 2011) to Revision O
Page
•
Changed Thermal Information table data and footnote 2b..................................................................................................... 6
•
Changed VFB Internal reference parameter in Electrical Characteristics table....................................................................... 7
•
Changed title of Figure 6 ........................................................................................................................................................ 8
2
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
TPS737
www.ti.com
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
Changes from Revision M (October, 2010) to Revision N
Page
•
Added footnote (3) to Thermal Information table.................................................................................................................... 7
•
Added footnote to Figure 38 ................................................................................................................................................. 21
Changes from Revision L (August, 2010) to Revision M
•
Page
Corrected typo in Figure 38 .................................................................................................................................................. 21
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
3
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
www.ti.com
5 Pin Configuration and Functions
DCQ Package
6-Pin SOT-223
Top View
6
1
IN
2
3
DRB Package
8-Pin VSON
Top View
TAB IS GND
4
5
OUT
1
8
IN
N/C
2
7
N/C
NR/FB
3
6
N/C
GND
4
5
EN
GND
EN
OUT NR/FB
DRV Package(1)
6-Pin WSON
Top View
(1)
OUT
1
6
IN
NR/FB
2
5
N/C
GND
3
4
EN
Power dissipation may limit operating range. Check Thermal Information table.
Pin Functions
PIN
NAME
4
SOT-223
VSON
WSON
I/O
IN
1
8
6
I
GND
3, 6
4, Pad
3, Pad
—
DESCRIPTION
Unregulated input supply
Ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low
puts the regulator into shutdown mode. Refer to the Enable Pin and
Shutdown section under Application Information for more details. EN must not
be left floating and can be connected to IN if not used.
EN
5
5
4
I
NR
4
3
2
—
FB
4
3
2
OUT
2
1
1
NC
—
2, 6, 7
5
Fixed voltage versions only—connecting an external capacitor to this pin
bypasses noise generated by the internal bandgap, reducing output noise to
very low levels.
I
Adjustable voltage version only—this is the input to the control loop error
amplifier, and is used to set the output voltage of the device.
O
Regulator output. A 1.0-μF or larger capacitor of any type is required for
stability.
—
Not connected
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
TPS737
www.ti.com
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
Voltage
Peak output current
(1)
MIN
MAX
VIN
–0.3
6
VEN
–0.3
6
VOUT
–0.3
5.5
VNR, VFB
–0.3
6
IOUT
Temperature
(1)
V
Internally limited
Output short-circuit duration
Continuous total power
dissipation
UNIT
Indefinite
PDISS
See Thermal Information
Junction range, TJ
–55
150
Storage range, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VIN
Input supply voltage range
IOUT
Output current
TJ
Operating junction temperature
2.2
NOM
MAX
UNIT
5.5
0
1
A
–40
125
°C
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
V
5
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
www.ti.com
6.4 Thermal Information
TPS737xx (2)
THERMAL METRIC (1)
(4)
DRB [VSON]
DCQ
[SOT-223]
DRV
[WSON] (3)
8 PINS
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
49.5
53.1
67.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance (5)
58.9
35.2
87.6
°C/W
RθJB
Junction-to-board thermal resistance (6)
25.1
7.8
36.8
°C/W
(7)
ψJT
Junction-to-top characterization parameter
1.7
2.9
1.8
°C/W
ψJB
Junction-to-board characterization parameter (8)
25.2
7.7
37.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance (9)
8.6
N/A
7.7
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.
. ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3 × 2 thermal via array.
. iii. DRV: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array. Due to size limitation of thermal
pad, 0.8-mm pitch array is used which is off the JEDEC standard.
(b) The top copper layer has a detailed copper trace pattern. The bottom copper layer is assumed to have a 20% thermal conductivity of
copper, representing a 20% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch × 3-inch copper area.
To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction
Temperature sections of this data sheet.
Power dissipation may limit operating range.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
TPS737
www.ti.com
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
6.5 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 1 V (1), IOUT = 10 mA, VEN = 2.2 V, and
COUT = 2.2 μF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
Input voltage range (1) (2)
VIN
VFB
MAX
TJ = 25°C
1.198
1.204
1.21
Internal reference
(DRB and DRV packages)
TJ = 25°C
1.192
1.204
1.216
VOUT
Accuracy (1), (4)
Over VIN, IOUT,
and T
VFB
5.5 – VDO
TJ = 25°C
–1
1
5.36 V < VIN < 5.5 V, VOUT = 5.08
V,
10 mA < IOUT < 800 mA,
–40°C < TJ < 85°C,
TPS73701 (DCQ)
–2
2
VOUT + 0.5 V ≤ VIN ≤ 5.5 V;
10 mA ≤ IOUT ≤ 1 A
–3
Line regulation (1)
ΔVOUT(ΔIOUT)
Load regulation
VDO
Dropout voltage (5)
(VIN = VOUT(nom) – 0.1 V)
IOUT = 1 A
ZOUT(DO)
Output impedance in dropout
2.2 V ≤ VIN ≤ VOUT + VDO
ICL
Output current limit
VOUT = 0.9 × VOUT(nom)
IOS
Short-circuit current
VOUT = 0 V
IREV
Reverse leakage current (6) (–IIN)
GND pin current
ISHDN
Shutdown current [IGND]
IFB
FB pin current (TPS73701)
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V
0.002
0.0005
3
130
%/V
%/mA
500
mV
Ω
0.25
1.05
1.6
2.2
A
mA
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
0.1
μA
IOUT = 10 mA
400
IOUT = 1 A
20
0.1
f = 100 Hz, IOUT = 1 A
58
f = 10 kHz, IOUT = 1 A
37
COUT = 10 μF
tSTR
Start-up time
VOUT = 3 V, RL = 30 Ω, COUT = 1
μF
VEN(HI)
EN pin high (enabled)
VEN(LO)
EN pin low (shutdown)
IEN(HI)
EN pin current (enabled)
μA
1300
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5
Output noise voltage
BW = 10 Hz to 100 kHz
Operating junction temperature
%
450
Vn
TJ
V
0.01
10 mA ≤ IOUT ≤ 1 A
Power-supply rejection ratio
(ripple rejection)
Thermal shutdown temperature
±0.5%
1 mA ≤ IOUT ≤ 1 A
PSRR
Tsd
V
V
ΔVOUT(ΔVIN)
IGND
UNIT
5.5
Internal reference
(DCQ package)
Nominal
(3)
(4)
(5)
(6)
TYP
2.2
Output voltage range
(TPS73701) (3)
(1)
(2)
MIN
nA
0.6
μA
dB
27 × VOUT
μVRMS
600
μs
1.7
VIN
V
0
0.5
V
VEN = 5.5 V
20
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
–40
nA
°C
125
°C
Minimum VIN = VOUT + VDO or 2.2 V, whichever is greater.
For VOUT(nom) < 1.6 V, when VIN ≤ 1.6V, the output locks to VIN and may result in an over-voltage condition on the output. To avoid this
situation, disable the device before powering down VIN.
TPS73701 is tested at VOUT = 1.2 V.
Tolerance of external resistors not included in this specification.
VDO is not measured for fixed output versions with VOUT(nom) < 2.3 V because minimum VIN = 2.2 V.
Fixed-voltage versions only; refer to the Application Information section for more information.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
7
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
www.ti.com
6.6 Typical Characteristics
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF, unless otherwise
noted.
0.5
Referred to VIN = VOUT + 1.0V at IOUT = 10mA
-40°C
+25°C
+125°C
0.2
0.1
0
-0.1
-0.2
Change in VOUT (%)
0.15
0.3
Change in VOUT (%)
0.20
Referred to IOUT = 10mA
0.4
-0.3
0.10
0
-0.05
-40°C
-0.10
-0.15
-0.4
-0.5
-0.20
0
100 200
300 400
500 600 700
800 900 1000
0
0.5
1.0
IOUT (mA)
2.0
2.5
3.0
3.5
4.0
4.5
Figure 2. Line Regulation
200
VOUT = 2.5V
180
1.5
VIN - VOUT (V)
Figure 1. Load Regulation
200
180
160
160
+125°C
+25°C
140
120
140
VDO (mV)
VDO (mV)
+25°C
+125°C
0.05
100
80
120
100
80
60
60
-40°C
40
40
20
20
0
0
0
100 200 300
400 500
600 700
800 900 1000
-50
-25
IOUT (mA)
0
25
50
75
100
125
150
Temperature (°C)
Figure 3. Dropout Voltage vs Output Current
Figure 4. Dropout Voltage vs Temperature
30
18
IOUT = 10mA
16
IOUT = 10mA
25
Percent of Units (%)
Percent of Units (%)
14
20
15
10
12
10
8
6
4
5
2
8
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/°C)
Figure 5. Output Voltage Histogram
Figure 6. Output Voltage Drift Histogram
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
TPS737
www.ti.com
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF, unless otherwise
noted.
3000
2500
IOUT = 1A
VIN = 5.0V
2500
2000
IGND (mA)
VIN = 5.0V
IGND (mA)
1500
VIN = 3.3V
2000
VIN = 3.3V
1500
1000
1000
VIN = 2.2V
VIN = 2.2V
500
500
0
0
0
200
400
600
800
-50
1000
0
-25
50
75
100
125
Figure 8. Ground Pin Current vs Temperature
Figure 7. Ground Pin Current vs Output Current
1
2.00
VENABLE = 0.5V
VIN = VOUT + 0.5V
1.80
ICL
1.60
Output Current (A)
IGND (mA)
25
Temperature (°C)
IOUT (mA)
0.1
1.40
1.20
1.00
0.80
0.60
ISC
0.40
0.20
0.01
-50
-25
0
25
50
75
100
0
-0.5
125
VOUT = 3.3V
0
0.5
Figure 9. Ground Pin Current in Shutdown vs Temperature
1.5
2.0
2.5
3.0
3.5
Figure 10. Current Limit vs VOUT (Foldback)
2.0
2.0
1.9
1.9
1.8
1.8
1.7
1.7
Current Limit (A)
Current Limit (A)
1.0
Output Voltage (V)
Temperature (°C)
1.6
1.5
1.4
1.3
1.6
1.5
1.4
1.3
1.2
1.2
1.1
1.1
1.0
VOUT = 1.2V
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
-25
0
25
50
75
100
VIN (V)
Temperature (°C)
Figure 11. Current Limit vs VIN
Figure 12. Current Limit vs Temperature
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
125
9
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
www.ti.com
Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF, unless otherwise
noted.
90
40
IOUT = 100mA
COUT = Any
70
IOUT = 1mA
COUT = 1mF
35
30
IOUT = 1mA
COUT = 10mF
60
50
IO = 100mA
CO = 1mF
IOUT = 1mA
COUT = Any
40
PSRR (dB)
Ripple Rejection (dB)
80
30
20
20
15
Frequency = 10kHz
COUT = 10mF
VOUT = 2.5V
IOUT = 100mA
10
IOUT = 100mA
COUT = 10mF
10
25
5
0
0
10
100
1k
10k
100k
1M
0
10M
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VIN - VOUT (V)
Frequency (Hz)
Figure 13. PSRR (Ripple Rejection) vs Frequency
Figure 14. PSRR (Ripple Rejection) vs (VIN – VOUT)
1
60
COUT = 1mF
55
0.1
VN (uVrms)
eN (mV/ÖHz)
50
COUT = 10mF
45
40
35
VOUT = 2.5V
COUT = 0μF
R1 = 39.2kΩ
10Hz < Frequency < 100kHz
30
25
IOUT = 150mA
0.01
10
100
1k
10k
20
10p
100k
100p
1n
10n
Frequency (Hz)
CFF (F)
Figure 15. Noise Spectral Density
Figure 16. TPS73701 RMS Noise Voltage vs CFB
60
140
50
120
VOUT = 5.0V
100
40
30
VN (uVrms)
VN (uVrms)
VOUT = 5.0V
VOUT = 3.3V
20
0.1
10
20
CNR = 0.01μF
10Hz < Frequency < 100kHz
0
1
10
VOUT = 3.3V
60
40
VOUT = 1. 5V
10
0
80
VOUT = 1.5V
COUT = 0μF
10Hz < Frequency < 100kHz
1p
10p
100p
1n
COUT (mF)
CNR (F)
Figure 17. RMS Noise Voltage vs COUT
Figure 18. RMS Noise Voltage vs CNR
Submit Documentation Feedback
10n
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
TPS737
www.ti.com
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF, unless otherwise
noted.
CNR = 10nF
CNR = 10nF
COUT = 10mF
VOUT
200mV/div
COUT = 10mF
100mV/div
VOUT
1A
5.3V
10mA
4.3V
IOUT
VIN
10ms/div
10ms/div
Figure 19. TPS73733 Load Transient Response
Figure 20. TPS73733 Line Transient Response
RL = 20W
COUT = 10mF
VOUT
RL = 20W
COUT = 1mF
1V/div
RL = 20W
COUT = 1mF
1V/div
RL = 20W
COUT = 10mF
VOUT
2V
2V
VEN
1V/div
1V/div
0V
0V
VEN
100ms/div
100ms/div
Figure 21. TPS73701 Turnon Response
Figure 22. TPS73701 Turnoff Response
10
6
5
4
VIN
VOUT
IENABLE (nA)
Volts
3
2
1
1
0.1
0
-1
0.01
-50
-2
50ms/div
-25
0
25
50
75
100
125
Temperature (°C)
Figure 23. TPS73701, VOUT = 3.3-V Power Up and Power
Down
Figure 24. IEN vs Temperature
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
11
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
www.ti.com
Typical Characteristics (continued)
60
160
55
140
50
120
45
100
IFB (nA)
VN (VRMS)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 10 mA, VEN = 2.2 V, and COUT = 2.2 μF, unless otherwise
noted.
40
60
35
30
25
80
VOUT = 2.5V
COUT = 0mF
R1 = 39.2kW
10Hz < Frequency < 100kHz
20
10p
100p
40
20
1n
10n
0
-50
-25
0
25
50
75
100
CFB (F)
Temperature (°C)
Figure 25. TPS73701 RMS Noise Voltage vs CFB
Figure 26. TPS73701 IFB vs Temperature
CFB = 10nF
R1 = 39.2kW
COUT = 10mF
100mV/div
VOUT
COUT = 10mF
100mV/div
125
VOUT = 2.5V
CFB = 10nF
VOUT
4.5V
250mA
3.5V
10mA
12
IOUT
VIN
10ms/div
5ms/div
Figure 27. TPS73701 Load Transient, Adjustable Version
Figure 28. TPS73701 Line Transient, Adjustable Version
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
TPS737
www.ti.com
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
7 Detailed Description
7.1 Overview
The TPS737xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to
achieve ultralow dropout performance, reverse current blockage, and freedom from output capacitor constraints.
These features combined with an enable input make the TPS737xx ideal for portable applications. This regulator
family offers a wide selection of fixed-output voltage versions and an adjustable-output version. All versions have
thermal and overcurrent protection, including foldback current-limit.
7.2 Functional Block Diagrams
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27kΩ
Bandgap
Error
Amp
Current
Limit
OUT
8kΩ
GND
R1
R1 + R2 = 80kΩ
R2
NR
Figure 29. Fixed-Voltage Version
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
13
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
www.ti.com
Functional Block Diagrams (continued)
IN
Standard 1% Resistor Values
for Common Output Voltages
VOUT
4-MHZ
Charge Pump
EN
Thermal
Protection
Ref
Servo
27 kW
Bandgap
Error
Amp
GND
80 kW
8 kW
R2
1.2 V
Short
Open
1.5 V
23.2 kW
95.3 kW
1.8 V
28.0 kW
56.2 kW
2.5 V
39.2 kW
36.5 kW
2.8 V
44.2 kW
33.2 kW
3.0 V
46.4 kW
30.9 kW
3.3 V
52.3 kW
30.1 kW
NOTE: VOUT = (R1 + R2)/R2 ´ 1.204;
R1 || R2 @ 19 kW for best
accuracy.
OUT
Current
Limit
R1
R1
FB
R2
Figure 30. Adjustable-Voltage Version
7.3 Feature Description
7.3.1 Output Noise
A precision bandgap reference is used to generate the internal reference voltage, Vref. This reference is
dominant noise source within the TPS737xx and it generates approximately 32 μVRMS (10 Hz to 100 kHz) at
reference output (NR). The regulator control loop gains up the reference noise with the same gain as
reference voltage, so that the noise voltage of the regulator is approximately given by:
V
(R + R2 )
= 32mVRMS ´ OUT
VN = 32mVRMS ´ 1
R2
VREF
Because the value of VR is 1.2 V, this relationship reduces to:
æ mV
ö
VN (mVRMS ) = 27 ç RMS ÷ ´ VOUT (V)
V
è
ø
the
the
the
(1)
(2)
for the case of no CNR.
An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF,
the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the
approximate relationship:
mVRMS
VN(mVRMS) = 8.5
x VOUT(V)
V
(3)
(
)
for CNR = 10 nF.
This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section.
14
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
TPS737
www.ti.com
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
Feature Description (continued)
The TPS73701 adjustable version does not have the NR pin available. However, connecting a feedback
capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improve load transient
performance. This capacitor should be limited to 0.1 µF.
The TPS737xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of
the NMOS pass element above VOUT. The charge pump generates approximately 250 μV of switching noise at
approximately 4 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for
most values of IOUT and COUT.
7.3.2 Internal Current Limit
The TPS737xx internal current limit helps protect the regulator during fault conditions. Foldback current-limit
helps to protect the regulator from damage during output short-circuit conditions by reducing current-limit when
VOUT drops below 0.5 V. See Figure 10 in the Typical Characteristics section.
Note from Figure 10 that approximately –0.2 V of VOUT results in a current-limit of 0 mA. Therefore, if OUT is
forced below –0.2 V before EN goes high, the device may not start up. In applications that work with both a
positive and negative voltage supply, the TPS737xx should be enabled first.
7.3.3 Enable Pin and Shutdown
The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. VEN below 0.5 V
(maximum) turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to
shutdown the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a
regulated VOUT (see Figure 21).
When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after
VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster
ramp times upon power up. In addition, for VIN ramp times slower than a few milliseconds, the output may
overshoot upon power up.
Note that current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit
section for more information.
7.3.4 Reverse Current
The NMOS pass element of the TPS737xx provides inherent protection against current flow from the output of
the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed
from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If the EN
pin is not driven low, the pass element may be left on because of stored charge on the gate.
After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Reverse current
is specified as the current flowing out of the IN pin because of voltage applied on the OUT pin. There is
additional current flowing into the OUT pin as a result of the 80-kΩ internal resistor divider to ground (see
Figure 29 and Figure 30).
For the TPS73701, reverse current may flow when VFB is more than 1.0 V above VIN.
7.4 Device Functional Modes
Driving the EN pin over 1.7 V turns on the regulator. Driving the EN pin below 0.5 V causes the regulator to enter
shutdown mode. In shutdown, the current consumption of the device is reduced to 20 nA, typically.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
15
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS737xx family of LDO regulators use an NMOS pass transistor to achieve ultra-low-dropout performance,
reverse current blockage, and freedom from output capacitor constraints. These features, combined with low
noise and an enable input, make the TPS737xx ideal for portable applications. This regulator family offers a wide
selection of fixed-output voltage versions and an adjustable-output version. All versions have thermal and
overcurrent protection, including foldback current-limit.
8.2 Typical Application
Figure 31 shows the basic circuit connections for the fixed-voltage models. Figure 32 gives the connections for
the adjustable output version (TPS73701).
VIN
IN
VOUT
OUT
TPS737xx
EN
GND
ON
OFF
Figure 31. Typical Application Circuit for Fixed-Voltage Versions
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
Output capacitor
must be ³ 1.0mF.
TPS73701
EN
OFF
VOUT
OUT
GND
R1
CFB
FB
ON
R2
VOUT =
(R1 + R2)
x 1.204
R2
Optional capacitor
reduces output noise
and improves
transient response.
Figure 32. Typical Application Circuit for Adjustable-Voltage Version
8.2.1 Design Requirements
R1 and R2 can be calculated for any output voltage using the formula shown in Figure 32. Sample resistor values
for common output voltages are shown in Figure 30.
For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19 kΩ. This 19 kΩ, in
addition to the internal 8-kΩ resistor, presents the same impedance to the error amp as the 27-kΩ bandgap
reference output. This impedance helps compensate for leakages into the error amp terminals.
8.2.2 Detailed Design Procedure
Provide an input supply with adequate headroom to account for dropout and output current to compensate for
the GND terminal current and to power the load. Further, select adequate input and output capacitors as
discussed in Input and Output Capacitor Requirements.
16
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
TPS737
www.ti.com
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
Typical Application (continued)
8.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability if input impedance is very low, it is good analog design
practice to connect a 0.1-μF to 1-μF low equivalent series resistance (ESR) capacitor across the input supply
near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise
rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients
are anticipated or the device is located several inches from the power source.
The TPS737xx requires a 1-μF output capacitor for stability. It is designed to be stable for all available types and
values of capacitors. In applications where multiple low-ESR capacitors are in parallel, ringing may occur when
the product of COUT and total ESR drops below 50 nF. Total ESR includes all parasitic resistances, including
capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and
trace resistance meets this requirement.
8.2.2.2 Dropout Voltage
The TPS737xx uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS(on) of the NMOS pass element.
For large step changes in load current, the TPS737xx requires a larger voltage drop from VIN to VOUT to avoid
degraded transient response. The boundary of this transient dropout region is approximately twice the DC
dropout. Values of (VIN – VOUT) above this line ensure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recover
from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load
current, and the available headroom (VIN-to-VOUT voltage drop). Under worst-case conditions [full-scale
instantaneous load change with (VIN – VOUT) close to DC dropout levels], the TPS737xx can take a couple of
hundred microseconds to return to the specified regulation accuracy.
8.2.2.3 Transient Response
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration
allows operation without a 1-µF output capacitor. As with any regulator, the addition of additional capacitance
from the OUT pin to ground reduces undershoot magnitude but increases its duration. In the adjustable version,
the addition of a capacitor, CFB, from the OUT pin to the FB pin will also improve the transient response.
The TPS737xx does not have active pulldown when the output is over-voltage. This architecture allows
applications that connect higher voltage sources, such as alternate power supplies, to the output. This
architecture also results in an output overshoot of several percent if the load current quickly drops to zero when a
capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output capacitor COUT and the internal/external load resistance. The
rate of decay is given by:
(Fixed voltage version)
VOUT
dV
=
dT COUT ´ 80kW P RLOAD
(4)
(Adjustable voltage version)
VOUT
dV
=
dT COUT ´ 80kW P (R1 + R2 ) P RLOAD
(5)
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
17
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
www.ti.com
Typical Application (continued)
8.2.3 Application Curves
1
90
IOUT = 100mA
COUT = Any
70
IOUT = 1mA
COUT = 10mF
60
50
40
IOUT = 1mA
COUT = 1mF
COUT = 1mF
eN (mV/ÖHz)
Ripple Rejection (dB)
80
IO = 100mA
CO = 1mF
IOUT = 1mA
COUT = Any
30
20
0.1
COUT = 10mF
IOUT = 100mA
COUT = 10mF
10
IOUT = 150mA
0.01
0
10
100
1k
10k
100k
1M
10
10M
100
1k
10k
Frequency (Hz)
Frequency (Hz)
Figure 33. PSRR (Ripple Rejection) vs Frequency
Figure 34. Noise Spectral Density
100k
6
5
VIN
4
VOUT
Volts
3
2
1
0
-1
-2
50ms/div
Figure 35. TPS73701, VOUT = 3.3-V Power Up and Power Down
8.3 What To Do and What Not To Do
Place at least one 1-μF ceramic capacitor as close as possible to the OUT terminal of the regulator.
Do not place the output capacitor more than 10-mm away from the regulator.
Connect a 1-μF low equivalent series resistance (ESR) capacitor across the IN terminal and GND input of the
regulator for improved transient performance.
Do not exceed the absolute maximum ratings.
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.2 V and 5.5 V. The input
voltage range provides adequate headroom in order for the device to have a regulated output. This input supply
must be well regulated. If the input supply is noisy, additional input capacitors with low ESR help improve the
output noise performance.
18
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
TPS737
www.ti.com
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
10 Layout
10.1 Layout Guidelines
To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the
printed-circuit-board (PCB) with separate ground planes for VIN and VOUT, with each ground plane connected
only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect
directly to the GND pin of the device.
10.1.1 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions and can be calculated using
Equation 6:
PD
VIN VOUT u IOUT
(6)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On both SON (DRB) and SON (DRV) packages, the primary conduction path for heat is through the exposed pad
to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be
attached to an appropriate amount of copper PCB area to ensure the device does not overheat. On the SOT-223
(DCQ) package, the primary conduction path for heat is through the tab to the PCB. That tab should be
connected to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient
temperature, maximum device junction temperature, and power dissipation of the device and can be calculated
using Equation 7:
125qC TA
RTJA
PD
(7)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 36.
160
DCQ
DRV
DRB
140
qJA (°C/W)
120
100
80
60
40
20
0
0
Note:
1
2
4
5
7
3
6
Board Copper Area (in2)
8
9
10
θJA value at board size of 9 in2 (that is, 3 in × 3 in) is a JEDEC standard.
Figure 36. θJA vs Board Size
Figure 36 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as
a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate
actual thermal performance in real application environments.
NOTE
When the device is mounted on an application PCB, TI strongly recommends using ΨJT
and ΨJB, as explained in the section.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
19
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
www.ti.com
Layout Guidelines (continued)
10.1.2 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of your application. This produces a worstcase junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS737xx has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TPS737xx into thermal shutdown
degrades device reliability.
10.1.3 Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can
be estimated with corresponding formulas (given in Equation 8). For backward compatibility, an older θJC,Top
parameter is listed as well.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
(8)
Where PD is the power dissipation shown by Equation 6, TT is the temperature at the center-top of the IC
package, and TB is the PCB temperature measured 1-mm away from the IC package on the PCB surface (as
Figure 38 shows).
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the application note, Using New Thermal Metrics
(SBVA025), available for download at www.ti.com.
By looking at Figure 37, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That
is, using ΨJT or ΨJB with Equation 8 is a good way to estimate TJ by simply measuring TT or TB, regardless of the
application board size.
35
YJT and YJB (°C/W)
30
DRV
DCQ YJB
DRB
25
20
DRV
DCQ YJT
DRB
15
10
5
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
Figure 37. ΨJT and ΨJB vs Board Size
20
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
TPS737
www.ti.com
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
Layout Guidelines (continued)
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
refer to application report, Using New Thermal Metrics (SBVA025), available for download at www.ti.com. For
further information, refer to application report, IC Package Thermal Metrics (SPRA953), also available on the TI
website.
TB
1mm
TT on top
of IC
X
TT on top
of IC
TB on PCB
surface
TB on PCB
surface
TT
X
1mm
1mm
See note (1)
(a) Example DRB (SON) Package Measurement
(1)
(b) Example DRV (SON) Package Measurement
(c) Example DCQ (SOT-223) Package Measurement
Power dissipation may limit operating range. Check Thermal Information table.
Figure 38. Measuring Points for TT and TB
10.2 Layout Example
GND PLANE
COUT
VOUT
VIN
TPS73701
DRV
1
6
2
5
3
4
R1
CFF
R2
N/C
CIN
GND PLANE
Figure 39. Layout Example
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
21
TPS737
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS737xx. The TPS73701DRVEVM-529 evaluation module (and related user's guide) can be requested at the
Texas Instruments website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS737 is available through the product folders under Tools
& Software.
11.1.2 Device Nomenclature
Table 1. Ordering Information (1)
VOUT (1)
PRODUCT
xx is nominal output voltage (for example, 25 = 2.5 V, 01 = Adjustable
TPS737xx yy yz
(2)
).
yyy is the package designator.
z is the package quantity.
(1)
(2)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
For fixed 1.20-V operation, tie FB to OUT.
11.2 Documentation Support
11.2.1 Related Documentation
•
•
•
•
Texas
Texas
Texas
Texas
Instruments, Using New Thermal Metrics application report
Instruments, TPS73701DRVEVM-529 User's Guide user guide
Instruments, TMS320DM644x Power Reference Design application report
Instruments, TPS73x01DRBEVM-518 User's Guide user guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
22
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
TPS737
www.ti.com
SBVS067R – JANUARY 2006 – REVISED DECEMBER 2019
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: TPS737
23
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS73701DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS
& no Sb/Br)
SN
Level-2-260C-1 YEAR
-40 to 125
TPS73701
TPS73701DCQG4
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS73701
TPS73701DCQR
ACTIVE
SOT-223
DCQ
6
2500
Green (RoHS
& no Sb/Br)
SN
Level-2-260C-1 YEAR
-40 to 125
TPS73701
TPS73701DCQRG4
ACTIVE
SOT-223
DCQ
6
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS73701
TPS73701DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BZN
TPS73701DRBRG4
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BZN
TPS73701DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BZN
TPS73701DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QTN
TPS73701DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QTN
TPS73718DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS
& no Sb/Br)
SN
Level-2-260C-1 YEAR
-40 to 125
TPS73718
TPS73718DCQG4
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS73718
TPS73718DCQR
ACTIVE
SOT-223
DCQ
6
2500
Green (RoHS
& no Sb/Br)
SN
Level-2-260C-1 YEAR
-40 to 125
TPS73718
TPS73718DCQRG4
ACTIVE
SOT-223
DCQ
6
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS73718
TPS73718DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAL
TPS73718DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAL
TPS73725DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS73725
TPS73725DCQR
ACTIVE
SOT-223
DCQ
6
2500
Green (RoHS
& no Sb/Br)
SN
Level-2-260C-1 YEAR
-40 to 125
TPS73725
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
6-Feb-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS73725DCQRG4
ACTIVE
SOT-223
DCQ
6
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS73725
TPS73730DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CVT
TPS73730DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CVT
TPS73733DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS
& no Sb/Br)
SN
Level-2-260C-1 YEAR
-40 to 125
TPS73733
TPS73733DCQG4
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS73733
TPS73733DCQR
ACTIVE
SOT-223
DCQ
6
2500
Green (RoHS
& no Sb/Br)
SN
Level-2-260C-1 YEAR
-40 to 125
TPS73733
TPS73733DCQRG4
ACTIVE
SOT-223
DCQ
6
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS73733
TPS73733DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SIJ
TPS73733DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SIJ
TPS73734DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCH
TPS73734DCQR
ACTIVE
SOT-223
DCQ
6
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
