Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
TPS74901 3-A Low Dropout Linear Regulator With Programmable Soft-Start
1 Features
3 Description
•
•
•
•
•
The TPS74901 low-dropout (LDO) linear regulator
provides an easy-to-use, robust power management
solution for a wide variety of applications. Userprogrammable soft-start minimizes stress on the input
power source by reducing capacitive inrush current
during start-up. The soft-start is monotonic and wellsuited for powering many different types of
processors and ASICs. The enable input and powergood output allow easy sequencing with external
regulators. This complete flexibility permits the user to
configure a solution that meets the sequencing
requirements of FPGAs, DSPs, and other
applications with special start-up requirements.
1
•
•
•
•
•
•
VOUT Range: 0.8 V to 3.6 V
Ultralow VIN Range: 0.8 V to 5.5 V
VBIAS Range: 2.7 V to 5.5 V
Low Dropout: 120 mV (Typical) at 3 A
Power-Good (PG) Output Allows Supply
Monitoring or Provides a Sequencing Signal for
Other Supplies
2% Accuracy Over Line, Load, and Temperature
Adjustable Start-Up In-Rush Control
VBIAS Permits Low VIN Operation With Good
Transient Response
Stable with Any Output Capacitor ≥ 2.2 µF
Packages:
– Small, 3-mm × 3-mm × 1-mm VSON
– 5-mm × 5-mm × 1-mm VQFN and DDPAK-7
Active High Enable
2 Applications
•
•
•
•
•
FPGA Applications
DSP Core and I/O Voltages
Servers
Post-Regulation Applications
Applications with Special Start-Up Time or
Sequencing Requirements
SPACE
A precision reference and error amplifier deliver 2%
accuracy over load, line, temperature, and process.
The device is stable with any type of capacitor
≥ 2.2 µF, and the device is fully specified from –40°C
to 125°C. The TPS74901 is offered in a small (3 mm
× 3 mm) VSON package and a small (5-mm × 5-mm)
VQFN package, yielding a highly compact total
solution size. The device is also available in a
DDPAK-7 package.
Device Information(1)
PART
NUMBER
PACKAGE
TPS74901
IN
CIN
VBIAS
TPS74901
VSON (10)
3.00 mm × 3.00 mm
CSS = 0mF
VOUT
R1
GND
CSS
8.89 mm × 10.10 mm
Turnon Response
R3
OUT
SS
CBIAS
5.00 mm × 5.00 mm
DDPAK/TO-263 (7)
PG
BIAS
EN
VQFN (20)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit (Adjustable)
VIN
BODY SIZE (NOM)
FB
COUT
CSS = 0.001mF
VOUT
CSS = 0.0047mF
1V/div
R2
1.2V
Copyright © 2016, Texas Instruments Incorporated
1V/div
VEN
0V
Time (1ms/div)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Typical Characteristics: IOUT = 50 mA ...................... 7
Typical Characteristics: IOUT = 1 A ......................... 10
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
12
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 18
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Power Dissipation .................................................
Thermal Considerations ........................................
20
20
20
21
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (November 2015) to Revision I
Page
•
Added DRC package to document ........................................................................................................................................ 1
•
Changed Packages Features bullet ...................................................................................................................................... 1
•
Added DRC package to Description section .......................................................................................................................... 1
•
Added DRC (VSON) package to Device Information table .................................................................................................... 1
•
Added DRC package to Pin Configuration and Functions section......................................................................................... 3
•
Added DRC package to Thermal Information table ............................................................................................................... 5
Changes from Revision G (November 2010) to Revision H
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Deleted nonimal values from VIN, VEN, and VBIAS rows .......................................................................................................... 4
•
Changed values in the Thermal Information table.................................................................................................................. 5
•
Changed values for VBIAS column on Normal mode, Dropout mode, and Disabled mode rows ...................................... 13
•
Changed VIN(min) to VIN(UVLO) under VIN column in Disabled mode row ................................................................................. 13
Changes from Revision F (August, 2010) to Revision G
•
Page
Corrected equation for and updated values for Table 2....................................................................................................... 16
Changes from Revision E (January, 2010) to Revision F
Page
•
Revised Layout Recommendations and Power Dissipation section .................................................................................... 20
•
Added Estimating Junction Temperature ............................................................................................................................. 21
2
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
TPS74901
www.ti.com
SBVS082I – JUNE 2007 – REVISED MAY 2016
5 Pin Configuration and Functions
RGW Package
20-Pin VQFN
Top View
IN
NC
NC
NC
OUT
5
4
3
2
1
KTW Package
7-Pin DDPAK/TO-263
Top View
OUT
PG
9
17
NC
BIAS
10
16
FB
1 2 3 4 5 6 7
SS
FB
OUT
GND
IN
BIAS
EN
18
15
8
SS
IN
14
OUT
NC
19
13
7
NC
IN
12
OUT
GND
20
11
6
EN
IN
DRC Package
10-Pin VSON with Thermal Pad
Top View
IN 1
10 OUT
9 OUT
IN 2
PG 3
Thermal
Pad
BIAS 4
EN 5
8 FB
7 SS
6 GND
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DDPAK/TO-263
VQFN
VSON
BIAS
6
10
4
I
Bias input voltage for error amplifier, reference, and internal control
circuits.
EN
7
11
5
I
Enable pin. Driving this pin high enables the regulator. Driving this pin
low puts the regulator into shutdown mode. This pin must not be left
floating.
FB
2
16
8
I
This pin is the feedback connection to the center tap of an external
resistor divider network that sets the output voltage. This pin must not
be left floating.
GND
4
12
6
—
IN
5
5, 6, 7, 8
1, 2
I
NC
—
2, 3, 4, 13,
14, 17
—
—
No connection. This pin can be left floating or connected to GND to
allow better thermal contact to the top-side plane.
OUT
3
1, 18, 19,
20
9, 10
O
Regulated output voltage. A small capacitor (total typical capacitance
≥ 2.2 µF, ceramic) is needed from this pin to ground to assure stability.
Ground
Unregulated input to the device.
PG
—
9
3
O
Power-Good (PG) is an open-drain, active-high output that indicates
the status of VOUT. When VOUT exceeds the PG trip threshold, the PG
pin goes into a high-impedance state. When VOUT is below this
threshold the pin is driven to a low-impedance state. A pullup resistor
from 10 kΩ to 1 MΩ must be connected from this pin to a supply up to
5.5 V. The supply can be higher than the input voltage. Alternatively,
the PG pin can be left floating if output monitoring is not necessary.
SS
1
15
7
—
Soft-Start pin. A capacitor connected on this pin to ground sets the
start-up time. If this pin is left floating, the regulator output soft-start
ramp time is typically 100 µs.
—
Solder to the ground plane for increased thermal performance.
Thermal Pad
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
3
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
At TJ = –40°C to 125°C, unless otherwise noted. All voltages are with respect to GND. (1)
MIN
MAX
UNIT
Input voltage
–0.3
6
V
VEN
Enable voltage
–0.3
6
V
VPG
Power-good voltage
–0.3
6
V
IPG
PG sink current
0
1.5
mA
VSS
SS pin voltage
–0.3
6
V
VFB
Feedback pin voltage
–0.3
6
V
VOUT
Output voltage
–0.3
VIN + 0.3
V
IOUT
Maximum output current
VIN,
VBIAS
Internally limited
Output short circuit duration
Indefinite
PDISS
Continuous total power dissipation
TJ
Operating junction temperature
–40
125
°C
Tstg
Storage junction temperature
–55
150
°C
(1)
See Thermal Information
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VIN
Input supply voltage
VEN
Enable supply voltage
VBIAS
(1)
MAX
UNIT
5.5
V
0
5.5
V
(2)
5.5
V
VOUT
Output voltage
0.8
3.3
V
IOUT
Output current
0
3
COUT
Output capacitor
CIN
Input capacitor (3)
CBIAS
Bias capacitor
0.1
TJ
Operating junction temperature
–40
(1)
(2)
(3)
4
BIAS supply voltage
NOM
VOUT + VDO (VIN)
VOUT + VDO (VBIAS)
2.2
A
µF
1
µF
1
µF
125
°C
BIAS supply is required when VIN is below VOUT + 1.62 V.
VBIAS has a minimum voltage of 2.7 V or VOUT + VDO (VBIAS), whichever is higher.
If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 µF.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
TPS74901
www.ti.com
SBVS082I – JUNE 2007 – REVISED MAY 2016
6.4 Thermal Information
TPS74901
THERMAL METRIC (1)
RGW (VQFN)
KTW (TO-263)
DRC (VSON)
20 PINS
7 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
38.1
33.8
48.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
36.3
35.9
60.3
°C/W
RθJB
Junction-to-board thermal resistance
17.5
25
22.4
°C/W
ψJT
Junction-to-top characterization parameter
0.7
6
1.0
°C/W
ψJB
Junction-to-board characterization parameter
17.6
23.6
22.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.2
N/A
4.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
5
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
6.5 Electrical Characteristics
At TJ = –40°C to 125°C, VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 1 nF, IOUT = 50 mA, and
VBIAS = 5 V, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
Input voltage
VBIAS
Bias pin voltage
VREF
Internal reference (Adj.)
TJ = 25°C
Output voltage
VIN = 5 V, IOUT = 3 V
VREF
Accuracy
(RGW package) (1)
VOUT + 2.2 V ≤ VBIAS ≤ 5.5 V,
50 mA ≤ IOUT ≤ 3 A
–2%
±0.5%
2%
Accuracy
(KTW package) (1)
VOUT + 2.4 V ≤ VBIAS ≤ 5.5 V,
50 mA ≤ IOUT ≤ 3 A
–2%
±0.5%
2%
VOUT/VIN
Line regulation
VOUT (NOM) + 0.3 ≤ VIN ≤ 5.5 V
0.03
%/V
VOUT/IOUT
Load regulation
50 mA ≤ IOUT ≤ 3 A
0.09
%/A
IOUT = 3 A,
VBIAS – VOUT (NOM) ≥ 3.25 V (3)
120
280
mV
IOUT = 3 A, VIN = VBIAS
1.31
1.75
V
VOUT
VIN dropout voltage
VDO
VOUT + VDO
MAX
VIN
2.7
(2)
VBIAS dropout voltage (2)
ICL
Current limit
IBIAS
Bias pin current
ISHDN
Shutdown supply current
(IGND)
IFB
Feedback pin current
Power-supply rejection
(VIN to VOUT)
PSRR
Power-supply rejection
(VBIAS to VOUT)
0.798
0.802
5.5
V
5.5
V
0.806
V
3.6
V
VOUT = 80% × VOUT (NOM), RGW
Package
3.9
4.6
5.5
VOUT = 80% × VOUT (NOM), KTW
Package
3.8
4.6
5.5
1
2
mA
1
50
µA
0.150
1
µA
A
VEN ≤ 0.4 V
–1
1 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V
60
300 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V
30
1 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V
50
300 kHz, IOUT = 1.5 A,
VIN = 1.8 V, VOUT = 1.5 V
30
dB
dB
Noise
Output noise voltage
100 Hz to 100 kHz,
IOUT = 3 A, CSS = 0.001 μF
tSTR
Minimum start-up time
RLOAD for IOUT = 1 A, CSS = open
200
µs
ISS
Soft-start charging current
VSS = 0.4 V
440
nA
VEN,
HI
Enable input high level
VEN,
LO
Enable input low level
VEN,
HYS
Enable pin hysteresis
VEN,
DG
Enable pin deglitch time
1.1
5.5
0
0.4
VEN = 5 V
VIT
PG trip threshold
VOUT decreasing
VHYS
PG trip hysteresis
VPG, LO
PG output low voltage
IPG = 1 mA (sinking), VOUT < VIT
IPG, LKG
PG leakage current
VPG = 5.25 V, VOUT > VIT
TJ
Operating junction
temperature
TSD
Thermal shutdown
temperature
85
V
V
mV
20
Enable pin current
6
µVRMS
50
IEN
(1)
(2)
(3)
25 × VOUT
µs
0.1
1
µA
90
94
%VOUT
3
0.1
–40
Shutdown, temperature increasing
165
Reset, temperature decreasing
140
%VOUT
0.3
V
1
µA
125
°C
°C
Adjustable devices tested at 0.8 V; resistor tolerance is not considered.
Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
3.25 V is a test condition of this device and can be adjusted by referring to Figure 6.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
TPS74901
www.ti.com
SBVS082I – JUNE 2007 – REVISED MAY 2016
6.6 Typical Characteristics: IOUT = 50 mA
0.20
0.5
0.15
0.4
0.3
0.10
Change in VOUT (%)
Change in VOUT (%)
At TJ = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 µF, CBIAS = 4.7 µF, and COUT = 10 µF,
unless otherwise noted.
-40°C
0.05
0
+25°C
-0.05
+125°C
-0.01
0.2
-40°C
0.1
0
-0.1
+125°C
-0.2
+25°C
-0.3
-0.15
-0.4
-0.20
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.5
5.0
1.0
1.5
2.0
VIN - VOUT (V)
Figure 1. VIN Line Regulation
3.0
3.5
4.0
Figure 2. VBIAS Line Regulation
1.0
0.5
0.4
0.8
-40°C
03
0.6
Change in VOUT (%)
Change in VOUT (%)
2.5
VBIAS - VOUT (V)
-40°C
0.4
+25°C
+125°C
0.2
+25°C
0.2
0.1
0
-0.1
-0.2
+125°C
-0.3
0
-0.4
-0.2
-0.5
0
10
20
30
40
0
50
0.5
1.0
1.5
IOUT (mA)
2.5
3.0
IOUT (A)
Figure 3. Load Regulation
Figure 4. Load Regulation
180
400
160
350
IOUT = 3A
140
VDO (VIN - VOUT) (mV)
VDO (VIN - VOUT) (mV)
2.0
120
100
+125°C
80
60
+25°C
40
250
+125°C
200
150
100
+25°C
-40°C
20
300
50
-40°C
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VBIAS - VOUT (V)
IOUT (A)
Figure 5. VIN Dropout Voltage vs
IOUT and Temperature (TJ)
Figure 6. VIN Dropout Voltage vs
VIN Dropout Voltage vs IOUT and Temperature (TJ)
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
7
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
Typical Characteristics: IOUT = 50 mA (continued)
At TJ = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 µF, CBIAS = 4.7 µF, and COUT = 10 µF,
unless otherwise noted.
2200
200
IOUT = 0.5A
2000
160
VDO (VBIAS - VOUT) (mV)
VDO (VIN - VOUT) (mV)
180
140
120
100
+25°C
80
+125°C
60
40
-40°C
1800
1600
+125°C
1400
1200
+25°C
1000
-40°C
800
20
600
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
4.5
0.5
1.0
2.5
3.0
90
80
IOUT = 0.1A
70
IOUT = 1.5A
60
50
40
IOUT = 0.5A
30
VIN = 1.8V
VOUT = 1.2V
VBIAS = 5V
CSS = 1nF
20
10
0
10
100
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
90
80
70
IOUT = 100mA
60
IOUT = 500mA
50
40
30
20
VIN = 1.8V
VOUT = 1.2V
CSS = 1nF
10
0
1k
10k
100k
1M
10
10M
100
IOUT = 1500mA
1k
Frequency (Hz)
70
1kHz
60
10kHz
50
40
500kHz
30
100kHz
20
10
0
0
0.25
0.50
0.75
1.00
1.25
100k
1M
10M
1.50
1.75
2.00 2.25
Figure 10. VIN PSRR vs Frequency
Output Spectral Noise Density (mV/ÖHz)
VOUT = 1.2V
IOUT = 1.5A
CSS = 1nF
80
10k
IOUT = 300mA
Frequency (Hz)
Figure 9. VBIAS PSRR vs Frequency
90
Power-Supply Rejection Ratio (dB)
2.0
Figure 8. VBIAS Dropout Voltage vs
IOUT and Temperature (TJ)
Figure 7. VIN Dropout Voltage vs
(VBIAS – VOUT) and Temperature (TJ)
1
IOUT = 100mA
VOUT = 1.2V
CSS = 0nF
0.1
CSS = 10nF
CSS = 1nF
0.01
100
VIN - VOUT (V)
1k
10k
100k
Frequency (Hz)
Figure 11. VIN PSRR vs (VIN – VOUT)
8
1.5
IOUT (A)
VBIAS - VOUT (V)
Submit Documentation Feedback
Figure 12. Noise Spectral Density
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
TPS74901
www.ti.com
SBVS082I – JUNE 2007 – REVISED MAY 2016
Typical Characteristics: IOUT = 50 mA (continued)
At TJ = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 µF, CBIAS = 4.7 µF, and COUT = 10 µF,
unless otherwise noted.
2.0
2.0
1.8
1.8
+125°C
1.6
1.4
IBIAS (mA)
IBIAS (mA)
1.4
1.2
1.0
0.8
-40°C
0.6
1.2
+25°C
1.0
0.8
0.6
+25°C
0.4
0.4
0.2
0.2
0
-40°C
0
0
0.5
1.0
1.5
2.0
2.5
2.0
3.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
IOUT (A)
VBIAS (V)
Figure 13. BIAS Pin Current vs IOUT and Temperature (TJ)
Figure 14. BIAS Pin Current vs VBIAS and Temperature (TJ)
1.0
500
VOL Low-Level PG Voltage (V)
475
450
ISS (nA)
+125°C
1.6
425
400
375
350
325
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
300
-50
-25
0
25
50
75
100
125
0
2
4
Junction Temperature (°C)
8
10
12
PG Current (mA)
Figure 15. Soft-Start Charging Current (ISS) vs
Temperature (TJ)
5.0
6
Figure 16. Low-Level PG Voltage vs Current
-40°C
4.5
Current Limit (A)
4.0
+125°C
3.5
3.0
+25°C
2.5
Drive capability of output FET limits
IOUT when VBIAS - VOUT is under 2.0V.
2.0
1.5
VOUT = 0.8V
1.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VBIAS - VOUT (V)
Figure 17. Current Limit vs (VBIAS – VOUT)
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
9
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
6.7 Typical Characteristics: IOUT = 1 A
At TJ = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V, CIN = 1 µF, CBIAS = 4.7 µF, and
COUT = 10 µF, unless otherwise noted.
CSS = 1nF
COUT = 10mF (Ceramic)
COUT = 10mF (Ceramic)
100mV/div
100mV/div
COUT = 2.2mF (Ceramic)
100mV/div
CSS = 1nF
3.8V
5.0V
1V/div
1V/div
1V/ms
3.3V
1V/ms
1.8V
Time (50ms/div)
Time (50ms/div)
Figure 18. VBIAS Line Transient
Figure 19. VIN Line Transient
COUT = 470mF (OSCON)
CSS = 0nF
100mV/div
COUT = 100mF (Ceramic)
CSS = 1nF
0.5V/div
100mV/div
VOUT
CSS = 2.2nF
COUT = 22mF (Ceramic)
100mV/div
1.2V
3A
2A/div
CSS = 1nF
1V/div
VEN
0V
1A/ms
50mA
Time (50ms/div)
Time (1ms/div)
Figure 20. Output Load Transient Response
Figure 21. Turnon Response
VIN = VBIAS = VEN
1V/div
VPG (500mV/div)
VOUT
Time (20ms/div)
Figure 22. Power Up and Power Down
10
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
TPS74901
www.ti.com
SBVS082I – JUNE 2007 – REVISED MAY 2016
7 Detailed Description
7.1 Overview
The TPS74901 belongs to a family of low-dropout regulators that feature soft-start capabilities. These regulators
use a low-current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate
very-low input and output voltages.
The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology
device, the output capacitor has little effect on loop stability. This architecture allows the TPS74901 to be stable
with any capacitor with a value of 2.2 µF or greater. Transient response is also superior to PMOS topologies,
particularly for low VIN applications.
The TPS74901 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic
start-up and limits start-up inrush currents that may be caused by large capacitive loads. A power-good (PG)
output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with
hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT
capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply
voltages often present in processor-intensive systems.
7.2 Functional Block Diagram
IN
Current
Limit
BIAS
UVLO
OUT
Thermal
Limit
0.44mA
VOUT
R1
SS
CSS
Soft-Start
Discharge
0.8V
Reference
FB
PG
EN
Hysteresis
and Deglitch
R2
0.9 ´ VREF
GND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Enable and Shutdown
The enable (EN) pin is active high and is compatible with standard digital-signaling levels. VEN below 0.4 V turns
the regulator off and VEN above 1.1 V turns the regulator on. Unlike many regulators, the enable circuitry has
hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration allows the
TPS74901 to be enabled by connecting the output of another supply to the EN pin. The enable circuitry typically
has 50 mV of hysteresis and a deglitch circuit to help avoid ON-OFF cycling because of small glitches in the VEN
signal.
The enable threshold is typically 0.8 V and varies with temperature and process variations. Temperature
variation is approximately –1 mV/°C; process variation accounts for most of the rest of the variation to the 0.4-V
and 1.1-V limits. If precise turnon timing is required, a fast rise-time signal must be used to enable the
TPS74901.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
11
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
Feature Description (continued)
If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, then connect EN as close as
possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the enable
circuit.
7.3.2 Power-Good
The power-good (PG) pin is an open-drain output and can be connected to any 5.5 V or lower rail through an
external pullup resistor. This pin requires at least 1.1 V on VBIAS to have a valid output. The PG output is highimpedance when VOUT is greater than VIT + VHYS. If VOUT drops below VIT or if VBIAS drops below 1.9 V, the opendrain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled. The
recommended operating condition of PG pin sink current is up to 1 mA, so the pullup resistor for PG must be in
the range of 10 kΩ to 1 MΩ. PG is only provided on the VQFN package. If output voltage monitoring is not
needed, the PG pin can be left floating.
7.3.3 Internal Current Limit
The TPS74901 features a factory-trimmed, accurate current limit that is flat over temperature and supply voltage.
The current limit allows the device to supply surges of up to 4 A and maintain regulation. The current limit
responds in about 10 µs to reduce the current during a short circuit fault.
The internal current limit protection circuitry of the TPS74901 is designed to protect against overload conditions.
This circuitry is not intended to allow operation above the rated current of the device. Continuously running the
TPS74901 above the rated current degrades device reliability.
7.3.4 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may
cycle ON and OFF. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For
reliable operation, junction temperature must be limited to 125°C maximum. To estimate the margin of safety in a
complete design (including heatsink), increase the ambient temperature until thermal protection is triggered; use
worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least 40°C above
the maximum expected ambient condition of the application. This condition produces a worst-case junction
temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS74901 is designed to protect against overload conditions. This circuitry
is not intended to replace proper heatsinking. Continuously running the TPS74901 into thermal shutdown
degrades device reliability.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
•
12
The input voltage and bias voltage are both at least at the respective minimum specifications.
The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
The output current is less than the current limit.
The device junction temperature is less than the maximum specified junction temperature.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
TPS74901
www.ti.com
SBVS082I – JUNE 2007 – REVISED MAY 2016
Device Functional Modes (continued)
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The input or bias voltages are below the respective minimum specifications.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 lists the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
VEN
VBIAS
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO (VIN)
VEN > VEN(high)
VBIAS ≥ VOUT +
VDO(VBIAS)
I OUT < ICL
T J < 125°C
Dropout mode
VIN < VOUT(nom) + VDO (VIN)
VEN > VEN(high)
VBIAS < VOUT +
VDO(VBIAS)
—
TJ < 125°C
VEN < VEN(low)
VBIAS < VBIAS(UVLO)
—
TJ > 165°C
Disabled mode
(any true condition disables
the device)
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
13
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input, Output, and BIAS Capacitor Requirements
The device is designed to be stable for all available types of and values of output capacitors ≥ 2.2 µF. The device
is also stable with multiple capacitors in parallel, which can be of any type or value.
The capacitance required on the IN and BIAS pin strongly depends on the input supply source impedance. To
counteract any inductance in the input, the minimum recommended capacitor for VIN and VBIAS is 1 µF. If VIN and
VBIAS are connected to the same supply, the recommended minimum capacitor for VBIAS is 4.7 µF. Good quality,
low-ESR capacitors must be used on the input; ceramic X5R and X7R capacitors are preferred. These capacitors
must be placed as close as possible to the pins for optimum performance.
8.1.2 Transient Response
The TPS74901 is designed to have excellent transient response for most applications with a small amount of
output capacitance. In some cases, the transient response may be limited by the transient response of the input
supply. This limitation is especially true in applications where the difference between the input and output is less
than 300 mV. In this case, adding additional input capacitance improves the transient response much more than
just adding additional output capacitance would do. With a solid input supply, adding additional output
capacitance reduces undershoot and overshoot during a transient event; see Figure 20 in the Typical
Characteristics: IOUT = 50 mA section. Because the TPS74901 is stable with output capacitors as low as 2.2 µF,
many applications may need very little capacitance at the LDO output. For these applications, local bypass
capacitance for the powered device may be sufficient to meet the transient requirements of the application. This
design reduces the total solution cost by avoiding the need to use expensive high-value capacitors at the LDO
output.
8.1.3 Dropout Voltage
The TPS74901 offers very low dropout performance, making the device well-suited for high-current low VIN and
low VOUT applications. The low dropout of the TPS74901 allows the device to be used in place of a DC-DC
converter and still achieve good efficiencies. This provides designers with the power architecture for their
applications to achieve the smallest, simplest, and lowest-cost solution.
There are two different specifications for dropout voltage with the TPS74901. The first specification (see
Figure 23) is referred to as VIN Dropout and is used when an external bias voltage is applied to achieve low
dropout. This specification assumes that VBIAS is at least 3.25 V above VOUT, which is the case for VBIAS when
powered by a 5-V rail with 5% tolerance and with VOUT = 1.5 V (3.25 V is a test condition of this device and can
be adjusted by referring to Figure 6). If VBIAS is higher than VOUT + 3.25 V, VIN dropout is less than specified.
14
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
TPS74901
www.ti.com
SBVS082I – JUNE 2007 – REVISED MAY 2016
Application Information (continued)
BIAS
IN
Reference
VBIAS = 5V ±5%
VIN = 1.8V
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 83%
OUT
VOUT
COUT
FB
Simplified Block Diagram
Figure 23. Typical Application of the TPS74901 Using an Auxiliary Bias Rail
The second specification (shown in Figure 24) is referred to as VBIAS Dropout and applied to applications where
IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias
voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because
VBIAS provides the gate drive to the pass FET; therefore, VBIAS must be 1.75 V above VOUT. Dropout is limited by
BIAS in these applications because VBIAS provides the gate drive to the pass FET; therefore, VBIAS must be
1.75 V above VOUT. Because of this usage, IN and BIAS tied together easily consume huge power. Pay attention
not to exceed the power rating of the IC package.
VIN
BIAS
Reference
IN
VBIAS = 3.3V ±5%
VIN = 3.3V ± 5V
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 45%
OUT
VOUT
COUT
FB
Simplified Block Diagram
Figure 24. Typical Application of the TPS74901 Without an Auxiliary Bias
8.1.4 Output Noise
The TPS74901 provides low-output noise when a soft start capacitor is used. When the device reaches the end
of the soft start cycle, the soft start capacitor serves as a filter for the internal reference. By using a 0.001-µF soft
start capacitor, the output noise is reduced by half and is typically 30 µVRMS for a 1.2-V output (10 Hz to
100 kHz). Further increasing CSS has little effect on noise. Because most of the output noise is generated by the
internal reference, the noise is a function of the set output voltage. The RMS noise with a 0.001-µF soft-start
capacitor is given in Equation 1.
VN(mVRMS) = 25
mVRMS
x VOUT(V)
V
(1)
The low-output noise of the TPS74901 makes the device a good choice for powering transceivers, PLLs, or other
noise-sensitive circuitry.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
15
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
Application Information (continued)
8.1.5 Programmable Soft Start
The TPS74901 features a programmable, monotonic, voltage-controlled soft start that is set with an external
capacitor (CSS). This feature is important for many applications because power-up initialization problems are
eliminated when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also
reduces peak inrush current during start-up, minimizing start-up transient events to the input power bus.
To achieve a linear and monotonic soft start, the TPS74901 error amplifier tracks the voltage ramp of the
external soft start capacitor until the voltage exceeds the internal reference. The soft start ramp time is
dependent on the soft start charging current (ISS), soft start capacitance (CSS), and the internal reference voltage
(VREF), and can be calculated using Equation 2.
tSS =
(VREF x CSS)
ISS
(2)
If large output capacitors are used, the device current limit (ICL) and the output capacitor may set the start-up
time. In this case, the start-up time is given by Equation 3:
tSSCL =
(VOUT(NOM) x COUT)
ICL(MIN)
where
•
•
•
VOUT(NOM) is the nominal set output voltage.
COUT is the output capacitance.
ICL(MIN) is the minimum current limit for the device.
(3)
In applications where monotonic start-up is required, the soft start time given by Equation 2 must be set to be
greater than Equation 3.
The maximum recommended soft start capacitor is 0.015 µF. Larger soft start capacitors can be used and do not
damage the device; however, the soft start capacitor discharge circuit may not be able to fully discharge the soft
start capacitor when enabled. Soft start capacitors larger than 0.015 µF could be a problem in applications where
the user must rapidly pulse the enable pin and still requires the device to soft start from ground. CSS must be
low-leakage; X7R, X5R, or C0G dielectric materials are preferred. See Table 2 for suggested soft-start capacitor
values.
Table 2. Standard Capacitor Values for Programming the Soft-Start Time (1)
tSS(s) =
(1)
16
CSS
SOFT START TIME
Open
0.1 ms
270 pF
0.5 ms
560 pF
1 ms
2.7 nF
5 ms
5.6 nF
10 ms
0.01 µF
18 ms
VREF × CSS 0.8V × CSS(F)
=
0.44mA where tSS(s) = soft-start time in seconds.
ISS
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
TPS74901
www.ti.com
SBVS082I – JUNE 2007 – REVISED MAY 2016
8.1.6 Sequencing Requirements
VIN, VBIAS, and VEN can be sequenced in any order without causing damage to the device. However, for the softstart function to work as intended, certain sequencing rules must be applied. Connecting EN to IN is acceptable
for most applications as long as VIN is greater than 1.1 V, and the ramp rate of VIN and VBIAS is faster than the
set soft start ramp rate. If the ramp rate of the input sources is slower than the set soft start time, the output
tracks the slower supply minus the dropout voltage until the set output voltage is reached. If EN is connected to
BIAS, the device soft-starts as programmed, provided that VIN is present before VBIAS. If VBIAS and VEN are
present before VIN is applied and the set soft start time has expired, then VOUT tracks VIN. If the soft start time
has not expired, the output tracks VIN until VOUT reaches the value set by the charging soft start capacitor.
Figure 25 shows the use of an RC-delay circuit to hold off VEN until VBIAS has ramped. This technique can also
be used to drive EN from VIN. An external control signal can also be used to enable the device after VIN and
VBIAS are present.
NOTE
When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately
50 µA of current from OUT. Although this condition will not cause any damage to the
device, the output current may charge up the OUT node if total resistance between OUT
and GND (including external feedback resistors) is greater than 10 kΩ.
VIN
IN
VOUT
OUT
R1
CIN
BIAS TPS74901
COUT
FB
R2
R
VBIAS
EN
CBIAS
C
GND
SS
CSS
Figure 25. Soft-Start Delay Using an RC Circuit on Enable
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
17
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
8.2 Typical Application
Figure 26 illustrates the typical application circuit for the TPS74901 adjustable output device.
R1 and R2 can be calculated for any output voltage using the formula shown in Figure 26. See Table 3 for
sample resistor values of common output voltages. To achieve the maximum accuracy specifications, R2 must be
≤ 4.99 kΩ.
VIN
IN
CIN
1mF
PG
R3
BIAS
EN
VBIAS
R1
SS
CBIAS
1mF
VOUT
OUT
TPS74901
FB
GND
CSS
COUT
10mF
R2
(
VOUT = 0.8 ´ 1 +
R1
R2
)
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Typical Application Circuit for the TPS74901 (Adjustable)
Table 3. Standard 1% Resistor Values for Programming the Output Voltage (1)
(1)
R1 (kΩ)
R2 (kΩ)
VOUT (V)
Short
Open
0.8
0.619
4.99
0.9
1.13
4.53
1
1.37
4.42
1.05
1.87
4.99
1.1
2.49
4.99
1.2
4.12
4.75
1.5
3.57
2.87
1.8
3.57
1.69
2.5
3.57
1.15
3.3
VOUT = 0.8 × (1 + R1 / R2)
8.2.1 Design Requirements
The goal of this design is to create a 1.2-V rail at 3 A with minimal external components from a 1.5-V rail.
8.2.2 Detailed Design Procedure
First choose the bias, which must be at least 1.75-V above the output voltage. A 3.3-V rail is used to achieve this
minimum voltage. For a minimal external component count and size, select the minimum capacitor sizes.
CIN = 1 µF, CBIAS = 1 µF, and a COUT = 10 µF. The COUT value was chosen to improve transient response. Using
Table 3, R1 is set to 2.49 kΩ and R2 is set to 4.99 kΩ to create a 1.2-V rail. The pullup resistor for PG is set to
10 kΩ.
18
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
TPS74901
www.ti.com
SBVS082I – JUNE 2007 – REVISED MAY 2016
Power-Supply Rejection Ratio (dB)
90
VOUT = 1.2V
IOUT = 1.5A
CSS = 1nF
80
70
1kHz
60
10kHz
50
40
500kHz
30
100kHz
20
10
0
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00 2.25
Output Spectral Noise Density (mV/ÖHz)
8.2.3 Application Curves
1
IOUT = 100mA
VOUT = 1.2V
CSS = 0nF
0.1
CSS = 10nF
CSS = 1nF
0.01
100
VIN - VOUT (V)
1k
10k
100k
Frequency (Hz)
Figure 27. VIN PSRR vs (VIN – VOUT)
Figure 28. Noise Spectral Density
9 Power Supply Recommendations
The TPS74901 is designed to operate from an input voltage from 1.1 V to 5.5 V, provided the bias rail is at least
1.75-V higher than the input supply. The bias rail and the input supply must both provide adequate headroom
and current for the device to operate normally.
Connect a low-output impedance power supply directly to the IN pin of the TPS74901. This supply must have at
least 1 µF of capacitance near the IN pin for stability. A supply with similar requirements must also be connected
directly to the bias rail with a separate 1-µF or larger capacitor.
If the IN pin is tied to the bias pin, a minimum 4.7 µF of capacitance is needed for stability.
To increase the overall PSRR of the solution at higher frequencies, use a PI-filter or ferrite bead before the input
capacitor.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
19
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
10 Layout
10.1 Layout Guidelines
An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage droop
on the input of the device during load transients, connect the capacitance on IN and BIAS as close as possible to
the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source
and can therefore improve stability. To achieve optimal transient performance and accuracy, connect the top side
of R1 in Figure 26 as close as possible to the load. If BIAS is connected to IN, TI recommends connecting BIAS
as close to the sense point of the input supply as possible. This connection minimizes the voltage droop on BIAS
during transient conditions and can improve the turnon response.
10.2 Layout Example
Input GND Plane
IN
NC
NC
NC
OUT
Cin
5
4
3
2
1
Vin Plane
R(pull-up)
Vout Plane
IN
6
20 OUT
IN
7
19 OUT
IN
8
PG
9
17
NC
BIAS
10
16
FB/
SNS
18 OUT
Thermal Pad
Cout
11
12
13
14
14
15
GND
NC
NC
SS
Cbias
EN
R1
R1 & R2 should be
connected close to the load,
Cout should be as near to
the LDO as possible
R2
Css
Keep the ground planes on
the same side of the PCB if
possible to improve thermal
disappation
Output GND Plane
Figure 29. Layout Schematic (RGW Package)
10.3 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions, and can be calculated using
Equation 4:
PD = (VIN - VOUT ) ´ IOUT
(4)
20
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
TPS74901
www.ti.com
SBVS082I – JUNE 2007 – REVISED MAY 2016
Power Dissipation (continued)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On the VQFN (RGW) package, the primary conduction path for heat is through the exposed pad to the PCB. The
pad can be connected to ground or left floating; however, the pad must be attached to an appropriate amount of
copper PCB area to ensure the device does not overheat. On the DDPAK (KTW) package, the primary
conduction path for heat is through the tab to the PCB. Connect that tab to ground. The maximum junction-toambient thermal resistance depends on the maximum ambient temperature, maximum device junction
temperature, and power dissipation of the device and can be estimated using Equation 5:
( +125°C - TA )
RqJA =
PD
(5)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 30.
120
100
qJA (°C/W)
80
60
qJA (RGW)
40
20
qJA (KTW)
0
0
1
2
3
4
5
7
6
8
9
10
2
Board Copper Area (in )
Note:
2
θJA value at board size of 9 in (that is, 3 inches × 3 innches) is a JEDEC standard.
Figure 30. θJA versus Board Size
Figure 30 shows the variation of θJA as a function of ground plane copper area in the board. Figure 30 is
intended only as a guideline to demonstrate the affects of heat spreading in the ground plane; do not use
Figure 30 to estimate actual thermal performance in real application environments.
NOTE
When the device is mounted on an application PCB, TI strongly recommends using ΨJT
and ΨJB, as explained in the section.
10.4 Thermal Considerations
A better method of estimating the thermal measure comes from using the thermal metrics ΨJT and ΨJB, as
shown in Equation 6. These metrics are a more accurate representation of the heat transfer characteristics of the
die and the package than RθJA. The junction temperature can be estimated with the corresponding formulas
given in Equation 6.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
PD is the power dissipation shown by Equation 4
TT is the temperature at the center-top of the IC package
TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface (see Figure 31) (6)
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
21
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
Thermal Considerations (continued)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the application note Using New Thermal Metrics
(SBVA025), available for download at www.ti.com.
TT on top of IC
TB on PCB
TT on top of IC
(1)
1mm
TB on PCB
surface
(2)
1mm
(a) Example RGW (VQFN) Package Measurement
(1)
TT is measured at the center of both the X- and Y-dimensional axes.
(2)
TB is measured below the package lead on the PCB surface.
(b) Example KTW (DDPAK) Package Measurement
Figure 31. Measuring Points for TT and TB
22
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
TPS74901
www.ti.com
SBVS082I – JUNE 2007 – REVISED MAY 2016
Compared with θJA, the thermal metrics ΨJT and ΨJB are less independent of board size but do have a small
dependency on board size and layout. Figure 32 shows characteristic performance of ΨJT and ΨJB versus board
size.
Referring to Figure 32, the RGW package thermal performance has negligible dependency on board size. The
KTW package, however, does have a measurable dependency on board size. This dependency exists because
the package shape is not point symmetric to an IC center. In the KTW package, for example (see Figure 31),
silicon is not beneath the measuring point of TT which is the center of the X and Y dimension, so that ΨJT has a
dependency. Also, because of that non-point symmetry, device heat distribution on the PCB is not point
symmetric either, so that ΨJB has a greater dependency on board size and layout.
12
YJT and YJB (°C/W)
10
YJB (RGW)
8
YJB (KTW)
6
4
YJT (KTW)
2
YJT (RGW)
0
0
2
4
6
8
10
2
Board Copper Area (in )
Figure 32. ΨJT and ΨJB versus Board Size
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
see the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com. Also,
see the application note IC Package Thermal Metrics (SPRA953) (also available on the TI website) for further
information.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
23
TPS74901
SBVS082I – JUNE 2007 – REVISED MAY 2016
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS48.
The TPS74901EVM-210 evaluation module and related user's guide (SLVU190) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS748 is available through the product folders under Tools
& Software.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Using New Thermal Metrics, SBVA025
• IC Package Thermal Metrics, SPRA953
• Ultimate Regulation of with Fixed Output Versions of the TPS742xx, TPS743xx, and TPS744xx, SBVA024
• Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator, SBVA042
• TPS74901EVM-210 Evaluation Module User Guide, SLVU190
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: TPS74901
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS74901DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11S
TPS74901DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11S
TPS74901KTWR
ACTIVE
DDPAK/
TO-263
KTW
7
500
RoHS & Green
Call TI | SN
Level-2-260C-1 YEAR
-40 to 125
TPS74901
TPS74901RGWR
ACTIVE
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
74901
TPS74901RGWT
ACTIVE
VQFN
RGW
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
74901
TPS74901RGWTG4
ACTIVE
VQFN
RGW
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
74901
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
