TPS767D301-EP
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SGLS327A – FEBRUARY 2006 – REVISED APRIL 2010
DUAL-OUTPUT LOW-DROPOUT LINEAR REGULATOR
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FEATURES
1
•
•
•
•
•
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
•
•
•
•
PWP PACKAGE
(TOP VIEW)
•
•
•
•
•
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC
NC
1GND
1EN
1IN
1IN
NC
NC
2GND
2EN
2IN
2IN
NC
NC
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification testing
should not be viewed as justifying use of this component beyond
specified
performance and environmental limits.
•
1-mA Quiescent Current During Shutdown
Dual Open-Drain Power-On Reset With
200-ms Delay for Each Regulator
28-Pin PowerPAD™ TSSOP Package
Thermal Shutdown Protection for Each
Regulator
Dual Output Voltages for Split-Supply
Applications
Output Current Range of 0 mA to 1.0 A Per
Regulator
3.3-V/Adjustable Output
Fast Transient Response
3% Tolerance Over Load and Temperature
Dropout Voltage Typically 350 mV at 1 A
Ultra-Low 85-mA Typical Quiescent Current
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1RESET
NC
NC
1FB/NC
1OUT
1OUT
2RESET
NC
NC
NC
2OUT
2OUT
NC
NC
NC − No internal connection
DESCRIPTION/ORDERING INFORMATION
The TPS767D301-EP dual-voltage regulator offers fast transient response, low dropout (LDO) voltages, and dual
outputs in a compact package and incorporates stability with 10-mF low-ESR output capacitors.
The TPS767D301-EP dual-voltage regulator is designed primarily for DSP applications. This device can be used
in any mixed-output voltage application, with each regulator supporting up to 1 A. Dual active-low reset (RESET)
signals allow resetting of core logic and I/O separately.
Table 1. ORDERING INFORMATION
TJ
–55°C to 125°C
REGULATOR 1
VO
Adjustable (1.5 V to 5.5 V)
REGULATOR 2
VO
3.3 V
TSSOP (PWP)
TPS767D301MPWPREP
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2010, Texas Instruments Incorporated
TPS767D301-EP
SGLS327A – FEBRUARY 2006 – REVISED APRIL 2010
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
LOAD TRANSIENT RESPONSE
103
VO = 3.3 V
CL =100 µF
TA = 25°C
50
IO = 1 A
102
VDO − Dropout Voltage − mV
I O − Output Current − A
∆ VO − Change in
Output Voltage − mV
100
0
−50
−100
1
0.5
101
IO = 10 mA
100
10−1
0
VO = 3.3 V
CO = 10 µF
0
20
40
60
10−2
−60 −40 −20
80 100 120 140 160 180 200
t − Time − µs
IO = 0
0
20
40
60
80 100 120 140
TA − Free-Air Temperature − °C
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low and is directly
proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the
quiescent current is very low and independent of output loading (typically 85 mA over the full range of output
current, 0 mA to 1 A). These two key specifications yield a significant improvement in operating life for
battery-powered systems. This LDO device also features a sleep mode; applying a TTL high signal to enable
(EN) shuts down the regulator, reducing the quiescent current to 1 mA at TJ = 25°C.
The RESET output of the TPS767D301-EP initiates a reset in microcomputer and microprocessor systems in the
event of an undervoltage condition. An internal comparator in the TPS767D301-EP monitors the output voltage
of the regulator to detect an undervoltage condition on the regulated output voltage.
The TPS767D301-EP is offered in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output
voltage tolerance is specified as a maximum of 3% over line, load, and temperature ranges. The
TPS767D301-EP is available in a 28-pin PWP (TSSOP) package. The device operates over a junction
temperature range of –55°C to 125°C.
TPS767D3xx
VI
5
6
C1
0.1 µF
50 V
IN
RESET
RESET
250 kΩ
IN
OUT
4
28
EN
OUT
24
VO
23
+
GND
CO
10 µF
3
Figure 1. Typical Application Circuit (Fixed Versions) for Single Channel
2
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SGLS327A – FEBRUARY 2006 – REVISED APRIL 2010
FUNCTIONAL BLOCK DIAGRAM
Adjustable Version (for Each LDO)
IN
EN
RESET
_
+
OUT
+
_
200-ms Delay
R1
Vref = 1.1834 V
R2
GND
FUNCTIONAL BLOCK DIAGRAM
Fixed-Voltage Version (for Each LDO)
IN
EN
RESET
_
+
OUT
+
_
R1
200-ms Delay
Vref = 1.1834 V
FB/NC
R2
GND
External to the device
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TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
1GND
3
I/O
DESCRIPTION
Regulator 1 ground
1EN
4
I
Regulator 1 enable
1IN
5, 6
I
Regulator 1 input supply voltage
2GND
9
2EN
10
2IN
2OUT
Regulator 2 ground
I
Regulator 2 enable
11, 12
I
Regulator 2 input supply voltage
17, 18
O
Regulator 2 output voltage
22
O
Regulator 2 reset
23, 24
O
Regulator 1 output voltage
1FB/NC
25
I
Regulator 1 output voltage feedback for adjustable version and no connect for fixed-output
version
1RESET
28
O
Regulator 1 reset
2RESET
1OUT
1, 2, 7, 8, 13–16,
19–21, 26, 27
NC
No connection
TIMING DIAGRAM
VI
Vres
See Note A.
Vres
t
VO
VIT +
See Note B.
VIT +
See Note B.
Threshold
Voltage
VIT −
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
RESET
Output
Output
Undefined
4
Less than 5% of the
output voltage
VIT −
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
t
200-ms
Delay
200-ms
Delay
Output
Undefined
t
A.
Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC
standards for semiconductor symbology.
B.
VIT – Trip voltage typically is 5% lower than the output voltage (95% VO).
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Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VI
Input voltage range (2)
VI
Input voltage range
VO
(1)
1IN, 2IN, EN
MIN
MAX
UNIT
–0.3
13.5
V
–0.3
VI + 0.3
V
1OUT, 2OUT
Output voltage
7
RESET
Peak output current
HBM
V
16.5
Internally limited
ESD rating
2
Continuous total power dissipation
kV
See Dissipation Rating Table
TJ
Operating virtual junction temperature range
–55
150
°C
Tstg
Storage temperature range
–65
150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Table 2. DISSIPATION RATING TABLE
PACKAGE
AIR FLOW
(CFM)
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
0
3.58 W
35.8 mW/°C
1.97 W
1.43 W
250
5.07 W
50.7 mW/°C
2.79 W
2.03 W
PWP (1)
(1)
This parameter is measured with the recommended copper heat-sink pattern on a four-layer PCB, 1-oz copper on 4-in × 4-in ground
layer. For more information, refer to TI technical brief literature number SLMA002.
Recommended Operating Conditions
VI
Input voltage (1)
IO
Output current for each LDO (2)
VO
Output voltage range
TJ
Operating virtual junction temperature
(1)
(2)
1IN, 2IN
1OUT, 2OUT
MIN
MAX
2.7
10
UNIT
V
0
1
A
1.5
5.5
V
–55
125
°C
To calculate the minimum input voltage for maximum output current, use the following equation:
VI(min) = VO(max) + VDO(max load)
Continuous output current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that
the device operate under conditions beyond those specified in this table for extended periods of time.
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Electrical Characteristics
Vi = VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 10 mF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Adjustable
VO
Output voltage
1.5 V ≤ VO ≤ 5.5 V,
10 mA < IO < 1 A
(1)
4.3 V < VI < 10 V,
3.3-V output
10 mA < IO < 1 A
TYP
TJ = –55°C to
125°C
0.97VO
TJ = 25°C
TJ = –55°C to
125°C
3.201
3.366
85
125
VO + 1 V < VI ≤ 10 V, TJ = 25°C
Output noise voltage
BW = 200 Hz to 100 kHz, VO = 1.8 V,
IC = 1 A, CO = 10 mF, TJ = 25°C
55
Output current limit for each LDO
VO = 0 V
1.7
0.01
Thermal shutdown junction temperature
FB input current
Adjustable
TJ = –55°C to
125°C
FB = 1.5
2
nA
V
0.8
V
f = 1 KHz, TJ = 25°C, CO = 10 mF
60
dB
IO(RESET) = 300 mA
1.1
V
Trip threshold voltage
VO decreasing
Hysteresis voltage
Measured at VO
Output low voltage
VI = 2.7 V,
Leakage current
V(RESET) = 7 V
92
EN
IO(RESET ) = 1 mA
0.15
–1
EN = VI
–1
0
V
1
mA
mV
1
1
3
VO = 3.3 V, IO = 1 A
%/VO
0.4
200
EN = 0 V
TJ = 25°C
Dropout voltage (3)
98
0.5
Load regulation
6
mA
Minimum input voltage
for valid RESET
Input current
(3)
A
°C
10
RESET time-out delay
(1)
(2)
2
1
Low-level enable input voltage
Reset
µVRMS
2
(1)
mA
%/V
150
TJ = 25°C
High-level enable input voltage
Power-supply ripple rejection
V
3.3
Output voltage line regulation
for each LDO (1) (2)
2.7 V < VI < 10 V,
EN = VI
UNIT
1.02VO
IO = 1 A, TJ = –55°C to 125°C
Standby current for each LDO
MAX
VO
10 µA < IO < 1 A, TJ = 25°C
Quiescent current (GND current)
for each LDO (1)
ΔVO/VO
MIN
TJ = 25°C
mA
mV
350
TJ = –55°C to
125°C
575
mV
The minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. The maximum IN voltage is 10 V.
If VO ≤ 1.8 V then VI(min) = 2.7 V, VI(max) = 10 V:
VOǒV I(max) * 2.7 VǓ
Line regulator (mV) + ǒ%ńVǓ
1000
100
If VO ≥ 2.5 V, then VI(min) = VO + 1 V, and VI(max) = 10 V:
VOƪV I(max) * ǒVO ) 1 VǓƫ
Line regulator (mV) + ǒ%ńVǓ
1000
100
IN voltage equals VO(typ) – 100 mV; adjustable output voltage set to 3.3 V nominal with external resistor divider. Dropout voltage of 1.8 V
and 2.5 V is limited by input voltage-range limitations.
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TYPICAL CHARACTERISTICS
Table 3. TABLE OF GRAPHS
FIGURE
Output voltage
vs Output current
3, 4, 5
vs Free-air temperature
6, 7, 8
Ground current
vs Free-air temperature
9, 10
Power-supply ripple rejection
vs Frequency
11
Output spectral noise density
vs Frequency
12
Output impedance
vs Frequency
13
Dropout voltage
vs Free-air temperature
14
Line transient response
15, 17
Load transient response
16, 18
Output voltage
vs Time
19
Dropout voltage
vs Input voltage
20
vs Output current, TA = 25°C
22
vs Output current, TJ = 125°C
23
vs Output Current, TA = 25°C
24
vs Output current, TJ = 125°C
25
Equivalent series resistance (ESR)
18
16
Years Estimated Life
14
12
10
8
6
4
2
0
80
90
100
110
120
130
140
150
Continuous TJ (5C)
Figure 2. TPS767D301MPWPREP Estimated Device Life at
Elevated Temperatures Wirebond Voiding Fail Mode
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TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.2835
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
2.4960
1.7965
VO = 1.8 V
VI = 2.8V
TA = 25°C
VO = 3.3 V
VI = 4.3 V
TA = 25°C
3.2830
VO = 2.5 V
VI = 3.5 V
TA = 25°C
2.4955
3.2820
3.2815
3.2810
2.4950
VO − Output Voltage − V
VO − Output Voltage − V
VO − Output Voltage − V
1.7960
3.2825
1.7955
1.7950
2.4945
2.4940
2.4935
2.4930
1.7945
3.2805
2.4925
1.7940
3.2800
0
0.1
0.2 0.3
0.4
0.5
0.6 0.7
0.8
0.9
1
0
0.1
0.2 0.3
IO − Output Current − A
0.8
0.9
2.4920
1
0
0.1 0.2 0.3
0.4 0.5
0.6 0.7
0.8 0.9
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
1.815
VO = 3.3 V
VI = 4.3 V
2.515
VO = 1.8 V
VI = 2.8 V
2.510
3.29
IO = 1 A
IO = 1 mA
3.28
3.27
VO − Output Voltage − V
1.810
3.30
1.805
IO = 1 A
1.800
IO = 1 mA
1.795
1.790
3.25
−60 −40 −20
0
20
40
60
80
100 120 140
TA − Free-Air Temperature − °C
Figure 6.
1
IO − Output Current − A
Figure 5.
VO − Output Voltage − V
VO − Output Voltage − V
0.6 0.7
Figure 4.
3.26
8
0.5
Figure 3.
3.32
3.31
0.4
IO − Output Current − A
VO = 2.5 V
VI = 3.5 V
2.505
2.500
IO = 1 A
2.495
IO = 1 mA
2.490
2.485
1.785
−60 −40 −20
0
20
40
60
80
100 120 140
TA − Free-Air Temperature − °C
Figure 7.
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2.480
−60 −40
−20
0
20
40
60
80
100 120
TA − Free-Air Temperature − °C
Figure 8.
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SGLS327A – FEBRUARY 2006 – REVISED APRIL 2010
TYPICAL CHARACTERISTICS (continued) (continued)
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
92
88
92
86
90
84
82
IO = 1 mA
80
IO = 1 A
78
IO = 1 mA
88
86
IO = 500 mA
84
82
80
IO = 500 mA
76
PSRR − Power Supply Ripple Rejection − dB
VO = 1.8 V
VI = 2.8 V
94
Ground Current − µ A
78
74
76
72
−60 −40 −20
74
−60 −40 −20
0
20
40
60
80
100 120 140
IO = 1 A
TA − Free-Air Temperature − °C
0
20
40
60
80
40
30
20
10
0
100 120 140
100
1k
10k
100k
OUTPUT SPECTRAL NOISE
DENSITY
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
103
0
VI = 4.3 V
CO = 10 µF
TA = 25°C
IO = 1 A
10−7
IO = 1 A
102
VDO − Dropout Voltage − mV
Zo − Output Impedance − Ω
IO = 7 mA
10−6
IO = 1 mA
10−1
IO = 1 A
101
IO = 10 mA
100
10−1
VO = 3.3 V
CO = 10 µF
103
104
10−2
101
105
102
f − Frequency − Hz
103
104
f − Frequency − kHz
Figure 12.
LINE TRANSIENT RESPONSE
105
∆ VO − Change in
Output Voltage − mV
2.8
VO = 1.8 V
IL = 10 mA
CL = 10 µF
TA = 25°C
40
60
80 100 120 140 160 180 200
t − Time − µs
Figure 15.
20
40
60
80 100 120 140
Figure 14.
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
VO = 1.8 V
VI = 2.8 V
CL = 100 µF
TA = 25°C
50
0
−50
VO = 3.3 V
CL = 10 µF
TA = 25°C
5.3
4.3
1
0.5
0
0
0
Figure 13.
∆ VO − Change in
Output Voltage − mV
I O − Output Current − A
−20
IO = 0
TA − Free-Air Temperature − °C
−100
0
20
10−2
−60 −40 −20
106
100
3.8
1M
f − Frequency − Hz
Figure 11.
102
VI − Input Voltage − V
50
Figure 10.
10−8
∆ VO − Change in
Output Voltage − mV
60
Figure 9.
VI = 4.3 V
CO = 10 µF
TA = 25°C
0
70
TA − Free-Air Temperature − °C
10−5
20
VO = 3.3 V
VI = 4.3 V
CO = 10 µF
IO = 1 A
TA = 25°C
80
−10
10
VI − Input Voltage − V
Ground Current − µ A
90
96
VO = 3.3 V
VI = 4.3 V
90
Vn − Output Spectral Noise Density − V/ Hz
POWER-SUPPLY RIPPLE
REJECTION
vs
FREQUENCY
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
20
40
60
80 100 120 140 160 180 200
t − Time − µs
Figure 16.
10
0
−10
0
20
40
60
80 100 120 140 160 180 200
t − Time − µs
Figure 17.
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TYPICAL CHARACTERISTICS (continued) (continued)
OUTPUT VOLTAGE
vs
TIME (AT STARTUP)
LOAD TRANSIENT RESPONSE
50
0
−50
−100
4
900
3
800
IO = 1A
VDO − Dropout Voltage − mV
VO− Output Voltage − V
VO = 3.3 V
CL =100 µF
TA = 25°C
2
1
0
1
Enable Pulse − V
I O − Output Current − A
∆ VO − Change in
Output Voltage − mV
100
DROPOUT VOLTAGE
vs
INPUT VOTAGE
0.5
0
0
20
40
60
80 100 120 140 160 180 200
t − Time − µs
0
600
500
TA = 25°C
400
TA = 125°C
300
200
TA = −40°C
100
0
0
20
40
Figure 18.
VI
700
60
80 100 120 140 160 180 200
t − Time − µs
2.5
Figure 19.
3
4
3.5
VI − Input Voltage − V
4.5
5
Figure 20.
To Load
IN
OUT
+
EN
CO
GND
RL
ESR
Figure 21. Test Circuit for Typical Regions of Stability
(Figure 22 Through Figure 25) (Fixed-Output Options)
10
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TYPICAL CHARACTERISTICS (continued) (1)
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
10
ESR − Equivalent Series Resistance − Ω
ESR − Equivalent Series Resistance − Ω
10
Region of Instability
1
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TA = 25°C
Region of Stability
0.1
Region of Instability
1
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TJ = 125°C
0.1
Region of Instability
Region of Instability
0.01
0.01
0
200
400
600
800
0
1000
200
600
800
Figure 22.
Figure 23.
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
1000
10
ESR − Equivalent Series Resistance − Ω
10
ESR − Equivalent Series Resistance − Ω
400
IO − Output Current − mA
IO − Output Current − mA
Region of Instability
1
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TA = 25°C
Region of Stability
0.1
Region of Instability
Region of Instability
1
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TJ = 125°C
Region of Stability
0.1
Region of Instability
0.01
0.01
0
200
400
600
800
1000
0
IO − Output Current − mA
Figure 24.
(1)
Region of Stability
200
400
600
800
1000
IO − Output Current − mA
Figure 25.
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to CO.
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TPS767D301-EP
SGLS327A – FEBRUARY 2006 – REVISED APRIL 2010
www.ti.com
APPLICATION INFORMATION
The features of the TPS767D301-EP (low-dropout voltage, ultra-low quiescent current, power-saving shutdown
mode, and a supply-voltage supervisor) and the power-dissipation properties of the TSSOP PowerPAD package
have enabled the integration of the dual LDO regulator with high output current for use in DSP and other
multiple-voltage applications.
Device Operation
The TPS767D301-EP features very low quiescent current, which remains virtually constant even with varying
loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to
the load current through the regulator (IB = IC/b). Close examination of the data sheets reveals that these devices
typically are specified under near no-load conditions; actual operating currents are much higher, as evidenced by
typical quiescent current versus load current curves. The TPS767D301-EP uses a PMOS transistor to pass
current; because the gate of the PMOS is voltage driven, operating current is low and invariable over the full load
range. The TPS767D301-EP specifications reflect actual performance under load conditions.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in b forces an increase in IB to maintain the load. During power up, this translates to
large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it
means rapid battery discharge when the voltage decays below the minimum required for regulation.
The TPS767D301-EP quiescent current remains low, even when the regulator drops out, eliminating both
problems. The TPS767D301-EP also features a shutdown mode that places the output in the high-impedance
state (essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 mA. If the
shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated
output voltage typically is reestablished in 120 ms.
Minimum Load Requirements
The TPS767D301-EP is stable, even at zero load. No minimum load is required for operation.
FB – Pin Connection (Adjustable Version Only)
The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option. The output
voltage is sensed through a resistor divider network to close the loop (see Figure 27). Normally, this connection
should be as short as possible; however, the connection can be made near a critical circuit to improve
performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier, and noise
pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup is
essential. In fixed-output options, this pin is a no connect.
External Capacitor Requirements
An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 mF) improves load
transient response and noise rejection when the TPS767D301-EP is located more than a few inches from the
power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load
transients with fast rise times are anticipated.
Like all low dropout regulators, the TPS767D301-EP requires an output capacitor connected between OUT and
GND to stabilize the internal control loop. The minimum recommended capacitance value is 10 mF and the
equivalent series resistance (ESR) must be between 60 mΩ and 1.5 Ω. Capacitor values of 10 mF or larger are
acceptable, provided the ESR is less than 1.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer
ceramic capacitors are all suitable, provided they meet the requirements previously described.
When it is necessary to achieve low height requirements along with high output current and/or high ceramic load
capacitance, several higher ESR capacitors can be used in parallel to meet the previous guidelines.
12
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TPS767D301-EP
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SGLS327A – FEBRUARY 2006 – REVISED APRIL 2010
TPS767D3xx
VI
5
IN
6
C1
0.1 µF
50 V
RESET
28
RESET
250 kΩ
IN
OUT
4
EN
OUT
24
VO
23
+
CO
10 µF
GND
3
Figure 26. Typical Application Circuit (Fixed Versions) for Single Channel
Programming the TPS767D301-EP Adjustable LDO Regulator
The output voltage of the TPS767D301-EP adjustable regulator is programmed using an external resistor divider
as shown in Figure 27. The output voltage is calculated using:
V
O
+V
ref
Ǔ
ǒ1 ) R1
R2
where:
Vref = 1.1834 V typ (the internal reference voltage)
(1)
Resistors R1 and R2 should be chosen for approximately 50-mA divider current. Lower-value resistors can be
used, but offer no inherent advantage and waste more power. Higher values should be avoided, as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ
to set the divider current at 50 mA and then calculate R1 using:
R1 +
ǒ
V
V
Ǔ
O *1
ref
R2
(2)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VI
0.1 µF
IN
RESET
RESET Output
EN
OUT
2.7 V
OUTPUT
VOLTAGE
+
10 µF
R2
Figure 27. TPS767D301-EP Adjustable LDO Regulator Programming
Reset Indicator
The TPS767D301-EP features a RESET output that can be used to monitor the status of the regulator. The
internal comparator monitors the output voltage. When the output drops to 95% (typical) of its regulated value,
the RESET output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If
not used, it can be left floating. RESET can be used to drive power-on reset circuitry or as a low-battery
indicator.
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13
TPS767D301-EP
SGLS327A – FEBRUARY 2006 – REVISED APRIL 2010
www.ti.com
Regulator Protection
The TPS767D301-EP PMOS-pass transistor has a built-in back-gate diode that safely conducts reverse currents
when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the
output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting
may be appropriate.
The TPS767D301-EP also features internal current limiting and thermal protection. During normal operation, the
TPS767D301-EP limits output current to approximately 1.7 A. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross
device failure, care should be taken not to exceed the power dissipation ratings of the package. If the
temperature of the device exceeds 150°C (typ), thermal-protection circuitry shuts it down. Once the device has
cooled below 130°C (typ), regulator operation resumes.
Power Dissipation and Junction Temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or
equal to PD(max).
The maximum power dissipation limit is determined using the following equation:
T max * T
A
P
+ J
D(max)
R
qJA
where:
TJmax is the maximum allowable junction temperature
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 27.9°C/W for the 28-terminal
PWP with no airflow.
TA is the ambient temperature.
(3)
The regulator dissipation is calculated using:
P
D
ǒ
+ V *V
I
O
Ǔ
I
O
(4)
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal
protection circuit.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS767D301MPWPREP
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
767D301EP
V62/06617-01XE
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
767D301EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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